Conformal plated vias in glass

Abstract

Devices and methods for conformally plated through-holes in glass. The device includes a through-hole or glass via (TGV) formed in a glass layer extending downward from a top surface, with an axis orthogonal to the top surface. The TGV is defined by a shape similar to an hourglass, with a first diameter at the top surface and the first diameter at the bottom surface, and a smaller second diameter therebetween. The periphery of the TGV is described as a sidewall. The sidewall is plated with a thin conformal conductive material from the top surface to the bottom surface, forming a cavity therein. The cavity may be bridged by the conductive material at the second diameter. An insulating material is located in the cavity.A conductive contact may extend across the TGV at the top surface and be electrically connected to the conductive material.

Description

BACKGROUND

[0001] A glass layer is often used to provide better mechanical / dimensional stability and stiffness compared to conventional epoxy glass fiber composite materials, and to improve the signal transmission density in a semiconductor package. To transmit signals from a top surface of the glass layer to a bottom surface, the glass layer is generally perforated with vias or "glass vias (TGVs)." However, the brittle nature of glass and the effective deposition of copper in the TGVs continue to pose technical challenges for manufacturing and operation. Accordingly, improved architectures and methods for transmitting signals through the glass layers are being sought. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 provides simplified cross-sectional illustrations of embodiments of conformally plated glass vias according to various embodiments. The Fig. 2-5 illustrate various exemplary manufacturing stages of conformally plated glass vias according to various embodiments. The Fig. 6-7 illustrate example use cases for conformally plated glass vias according to various embodiments. Fig. 8 illustrates an exemplary method for conformally plated glass vias according to various embodiments. Fig. 9 is a top view of a wafer and dies that may be included in a microelectronic assembly according to any of the embodiments disclosed herein. Fig. 10 is a simplified cross-sectional side view illustrating an implementation of an integrated circuit on a die that may be included in various embodiments, in accordance with any of the embodiments described herein. Fig. 11 is a cross-sectional side view of a microelectronic assembly that may include any of the embodiments disclosed herein. Fig. 12 is a block diagram of an exemplary electronic device that may incorporate any of the embodiments disclosed herein. DETAILED DESCRIPTION

[0002] A semiconductor package may include a multilayer substrate with a "glass core" or glass layer sandwiched between them. The glass layer has perforations (also called vias or glass vias (TGVs)) on its top and bottom surfaces to provide space for routing electrical signals between the silicon substrate. The glass layer provides mechanical / directional stability and rigidity in a semiconductor package and can increase routing density. However, the brittle nature of glass and difficulties with effective copper deposition in the TGVs continue to pose technical challenges for manufacturing and operation.

[0003] In some solutions, a buffer or lining layer is deposited on the sidewalls of the TGV to enhance copper deposition within the TGV. However, these solutions are susceptible to bending stress and temperature loading. Furthermore, although TGVs are often illustrated with vertical walls, in practice they are more likely to taper from the top surface to the center and from the bottom surface to the center, creating an hourglass shape. This taper, when filled with a conductive material, creates a "pinch point" at the center. This pinch point phenomenon can adversely limit power and energy density.

[0004] Embodiments described herein provide a technical solution to these technical challenges in the form of conformally plated glass vias. The practice of the architectures and methods described herein can be readily appreciated using SEM and / or TEM images, as described below. These concepts are elaborated upon below.

[0005] Example embodiments are described below in conjunction with the following drawing figures, wherein like reference numerals refer to like elements. Unless otherwise indicated, the figures are not necessarily to scale, but may be used for spatial orientation and relative positioning of features. As can be appreciated, certain terminology, such as "ceiling" and "floor," as well as "upper," "top," "lower," "above," "beneath," "bottom," and "top," refer to directions based on a review of the figures to which reference is made.Furthermore, terms such as "front," "rear," "back," "side," "vertical," and "horizontal" may describe the orientation and / or position of portions of the component within a consistent, yet arbitrary, frame of reference made clear by reference to the text and accompanying figures describing the component being discussed. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar meaning.

[0006] As used herein, the term "adjacent" refers to layers or components that are in direct physical contact with each other without any intervening layers or components. For example, a layer X adjacent to a layer Y refers to a layer that is in direct physical contact with layer Y.In contrast, as used herein, the phrase(s) “placed on” (alternatively, “placed under,” “placed above / over,” or “placed next to” in the context of a first layer or component placed on a second layer or component) includes (i) configurations where the first layer or component is directly physically attached to (i.e., adjacent to) the second layer, and (ii) components and configurations where the first layer or component is attached to (e.g., coupled to) the second layer or component via one or more intermediate layers or components.

[0007] The following detailed description is not intended to limit the application and uses of the disclosed technologies. It may be apparent that the novel embodiments may be practiced without each of the details described herein. For brevity, well-known structures and devices may be shown in block diagram form to facilitate description thereof.

[0008] The Fig. 1-7 contain many objects that are repeated. Unless otherwise stated, the same objects are intended to perform the same function or have the same feature across images, regardless of whether they are labeled or not. In addition, while the objects in the Fig. 1-7 are not to scale, various relationships and orientations shown in the images are intended as described herein.

[0009] Fig. 1 provides simplified cross-sectional illustrations of embodiments of conformally plated glass vias. Glass layer 102, or "glass core," may be structured with multiple through holes, also referred to as glass vias (TGVs). Embodiment 100 and embodiment 130 illustrate one of at least one TGV that may be located in glass layer 102. Glass layer 102 has top surface 101 and bottom surface 103. Glass layer 102 may have a thickness 126 (Z-height) in a range from about 20 micrometers to about 1.5 millimeters, + / -10%.

[0010] The glass layer 102 may be glass (as used herein, glass may be an alkali-free alkaline earth boro-aluminosilicate glass, such as glass comprising aluminum, oxygen, boron, silicon, and an alkaline earth metal (e.g., beryllium, magnesium, calcium, strontium, barium, radium, such as glass comprising SiO2, Al2O3, B2O3, and MgO) or a photosensitive glass (light-processable or light-structurable glass). In some embodiments, a light-sensitive glass may be a glass belonging to the lithium silicate family of glasses (e.g., a glass comprising lithium, silicon, and oxygen) that includes metallic particles, such as gold, silver, or other suitable metallic particles. In some embodiments, the glass layer 102 or the glass core may comprise multiple glass plates bonded together with an adhesion layer.In various embodiments, for example in a substrate (see for example the illustrations in . Fig. 6 and Fig. 7) with a Z-height (thickness) in a range of approximately 0.1 millimeters (mm) to 15 mm.

[0011] At least one through-hole or glass via (TGV) is formed in the glass layer 102. The through-holes extend from the top surface 101 to the bottom surface 103, with an axis orthogonal to the top surface, as shown. The TGVs are volumes in which glass is removed, and conductive materials are placed in the volumes sufficient to enable electrical communication from a top surface 101 to a bottom surface 103. Accordingly, the through-holes are characterized by a sidewall connected to a first diameter 110 at the top surface 101 and the first diameter 110 at the bottom surface 103. As illustrated in embodiments 100 and 130, the axis of the TGVs is substantially perpendicular to the top surface 101 of the glass layer 102.

[0012] The shape of the TGV reflects a technology used to create it. In embodiment 130, the sidewall has a slope (angle 120) measured from a plane of the top surface 101 in which the through-hole narrows toward the center point, where the center point has a second diameter 114 that is smaller than the first diameter. In one embodiment, the second diameter is at least 10% smaller than the first diameter, and in ideal cases, can grow to 100%. The slope at the sidewall in embodiment 130 can be a result of using a laser etch to create the TGV: in this approach, the top surface 101 is laser etched to approximately the center point, and the bottom surface is similarly laser etched to the center point.This results in a somewhat hourglass-shaped TGV, as illustrated, and provides a corresponding slope to the sidewall on the lower half of the TGV. The center point can be halfway between the top and bottom surfaces, plus or minus 15%. In contrast, in an idealized cylindrical TGV, as illustrated in embodiment 100, the through-hole has the first diameter 110 continuous from the top surface 101 to the bottom surface 103.

[0013] Conductive material 104 conforms to the sidewall within the cavity and is adjacent to non-conductive lining layer 252 between the copper (conductive material) and the glass. Conductive material 104 is continuous from the top surface to the bottom surface. The conductive material does not completely fill the TGV. In embodiment 100, the conductive material has a thickness that remains constant from the top surface to the bottom surface, this thickness being represented by first diameter 110 minus diameter 108, where diameter 108 is the diameter of cavity 106, which extends continuously from top surface 101 to bottom surface 103. The conductive material forms at least one cavity within the TGV.

[0014] In practice, technologies used to form the TGVs may more frequently produce the sidewall shape of embodiment 130. In embodiment 130, the sidewalls are tapered or inclined inward at an angle of 120, as shown. This may be achieved by using a laser to create the TGVs, and the laser tapers as it passes through a material. Also, in embodiment 130, thickness 118 of conductive material 112 varies from the top surface 101 to the midpoint to the bottom surface 103; this is illustrated with thickness 118-1 near the midpoint and thickness 118-2 at the top surface 101. The conductive material 112 forms bridge 116 at the midpoint, as shown. The bridge 116 forms a floor to cavity 122, and thereby also forms second cavity 124 in the TGV volume between the bridge 116 and the lower surface 103.

[0015] In practice, the TGVs and optional cavities similarly created in the glass layer may have an insulating material inside, and the TGVs may have a conductive contact or pad extending across them and electrically attached to the conductive material of the sidewall. An explanation of the fabrication of these features and further manufacturing steps follows in conjunction with the Fig. 1-8.

[0016] The practice of these embodiments can be identified by visually examining TEM or SEM images of cross-sectional views, as illustrated in embodiment 130, and observing the thickness change in the conductive material 112 (measured when moving up and down along the Z-axis, as illustrated and described) and the bridge 116 created by the conductive material 112, also as illustrated and described.

[0017] Additionally, different embodiments can be identified by visual inspection of TEM or SEM images of top or plan views. For example, comparing a planar disk fabricated horizontally at A, at B, and at C would reveal, in embodiment 130, rings of conductive material 112 with different outer diameters and either with an inner diameter or solid, as in bridge 116. Calculating the cross-sectional area of ​​each of these images (at A, B, and C) would result in the same number plus or minus 15%.

[0018] These visually observable features shown in embodiment 130 are advantageous because the presence of a conductive material at the surface of the glass is generally positively correlated with the mechanical stress experienced there. For example, the more copper at or near the surface of the glass, the more stress generally experienced. Embodiments advantageously reduce the amount of conductive material at the top surface (and at the bottom surface).

[0019] The Fig. 2-5 are simplified cross-sectional illustrations of various exemplary manufacturing stages of conformally plated glass vias according to various embodiments. Fig. 6-7 are simplified cross-sectional illustrations of various example use cases for conformally plated glass vias according to various embodiments. Fig. 8 illustrates exemplary method 800 for conformally plated glass vias.

[0020] Figure 200 illustrates glass layer 202 prior to the creation of the TGV and cavities. In embodiments that each produce a panel, the X-length of a glass layer and a corresponding Y-length (defining an area in a top or plan view) may range from a first length (e.g., X) in a range of 10 millimeters to 700 millimeters and a second length (e.g., Y) in a range of 10 millimeters to 700 millimeters, wherein the first length is perpendicular to the second length. The composition of the glass 202 is described above in connection with Fig. 1 described.

[0021] Image 230 illustrates (at 802) the through holes or TGVs created in glass layer 202. As mentioned above, the laser changes the chemistry of the glass, allowing the area to be preferentially etched away, resulting in a taper, as described in connection with embodiment 130. First TGVs 232-1 / 330-1 and second TGVs 232-2 / 330-2 are illustrated in image 230. In practice, TGVs 232-1 and 232-2 may be two of several TGVs. Optional cavity 234 may also be created during this phase. Optional cavity 234 may be large enough (e.g., minimum diameter 306) to accommodate an IC die or other component at a later manufacturing stage.

[0022] As shown in Figure 250, the liner layer 252 is added at 804. The liner layer is adjacent to and conformal to the glass material in the glass layer. The liner layer 252 can be anywhere between 15 nanometers and 10 micrometers thick. The thickness of the liner layer 252 depends on the method used to deposit this layer. By using a chemical vapor deposition (CVD) process, such as for silicon nitride, the liner layer 252 can be very thin, such as 20 nanometers + / - 5 nanometers. In other embodiments, the liner can be a slot-coated dielectric material or a polymer, such as polyethylene, and then it could be between 50 nanometers and 10 micrometers with + / - 10%.

[0023] Figure 300 illustrates seed 302 deposited at 806. The seed is an initial layer of a conductive material 112 that is deposited across the top surface and the bottom surface and conformally into the TGV and the cavities to assist in electroplating. In various embodiments, the seed is copper. In some embodiments, the seed 302 is a hybrid seed that includes layers such as ruthenium, then copper, then titanium, followed by copper. The hybrid seed may be deposited using CVD, and thickness 303 of the seed or hybrid seed layer may be 10 nanometers to 15 micrometers + / - 10%. At 806, the bridges (bridge 116) in the TGVs 330-1 and 330-2 are formed. The areas indicated by dashed circles 304 have the Fig. 1, Embodiment 130. In embodiments that include optional cavity 332, those skilled in the art will recognize that no bridge is formed across diameter 306 because it is too large; for example, cavity 332 may have a diameter in a range between 1 and 30 millimeters.

[0024] Figure 350 illustrates that the glass layer of 300 is laminated with insulating material 352 (at 808). In some embodiments, the insulating material is a dielectric material. As illustrated, the cavities formed in the conductive material or seed 302 are filled with the insulating material 352 at 808. The optional cavity 332 is also filled with the insulating material. The dielectric material may have a thickness of 100 nanometers to 20 micrometers + / - 10%.

[0025] In various embodiments, the dielectric material may be any insulating material, such as a suitable nitride or oxide, such as SiOx, silicon dioxide (SiO2), SiOxNy, carbon-doped silicon dioxide (C-doped SiO2, also known as CDO or organosilicate glass, which is a material comprising silicon, oxygen, and carbon), fluorine-doped silicon dioxide (F-doped SiO2, also known as fluorosilicate glass, which is a material comprising fluorine, silicon, and oxygen), hydrogen-doped silicon dioxide (H-doped SiO2, which is a material comprising silicon, oxygen, and hydrogen). In some embodiments, a dielectric layer comprises a photoimageable dielectric (PID).In some embodiments, the dielectric layer comprises an Ajinomoto build-up film (ABF), which is a material comprising an organic resin matrix with different types of fillers (e.g., silica fillers of different sizes, or hollow fillers of different sizes) to control the coefficient of thermal expansion (CTE) and / or the electrical properties (e.g., the dielectric constant (Dk) and / or the loss factor (insertion loss) (Df)).

[0026] In some embodiments, it is advantageous for the dielectric material to have a CTE that matches that of a component, such as an integrated circuit die, attached thereto (e.g., matching the CTE of silicon), or a CTE that matches that of a substrate or a PCB. In some embodiments, the dielectric material may have a CTE that is close (e.g., within 10%) to that of silicon. In other embodiments, the dielectric material may be any type of epoxy resin molding compound.

[0027] At 810, chemical mechanical polishing (CMP) may be performed to remove a portion of the insulating material to expose the conductive material 112 on the sidewall of the TGV, as well as to expose approximately 20 micrometers + / - 10% of the seed or conductive material 112 to facilitate electroplating in the next manufacturing stage. After completion of the CMP process, conductive plate 402 may be electrically attached over the planarized top surface, as illustrated in Figure 400. In some embodiments, conductive plate 402 comprises copper. Note that TGV 430-1 and TGV 430-2 now have the insulating material in the cavity, as does larger optional cavity 432.

[0028] At 812, the conductive plate 402 is then patterned and etched to create a conductive contact or pad for each TGV for a subsequent via to land on and attach to. After patterning and etching, the conductive plate 402 and seed 302 are removed accordingly, as illustrated in Figure 450. Note that conductive contact 452-1 is electrically attached to the sidewall of the TGV 430-1 at the top surface, covering a cavity filled with the insulating material; and conductive contact 452-3 is also attached to the sidewall of the TGV 430-1 at the bottom surface, covering a cavity filled with the insulating material.Similarly, conductive contact 452-2 is electrically attached to the sidewall of TGV 430-2 on the top surface, covering a cavity filled with the insulating material; and conductive contact 452-4 is also attached to the sidewall of TGV 430-2 on the bottom surface, covering a cavity filled with the insulating material. In some embodiments, the conductive contacts on the bottom surface are referred to as conductive pads to distinguish them from those on the top surface. Note that optional cavity 432 is a region filled with the insulating material and has sidewall 454 of the seed or hybrid seed.In practice, the insulating material may be removed from this optional cavity 432, such as by laser drilling or ablation, and an integrated circuit or component may be placed and electrically secured therein, for example, in the construction of a system or package assembly. This sidewall 454 (which may surround an integrated circuit or other component) is an identifiable feature that indicates the practice of the methods and apparatus described herein.

[0029] Some non-limiting examples of ICs and components that may be placed in the cavity 432 include a memory or high bandwidth storage, trench capacitors, a central processing unit, a photonic integrated circuit, a graphics processing unit, etc.

[0030] At 814, the glass layer with the conformally plated TGVs may undergo further fabrication and assembly. In a simplified example, as shown in Figure 500, the embodiment of Figure 450 may have a silicon substrate built on the top surface (e.g., at 504) or on the bottom surface (e.g., at 506). Continuing with this simplified example, in Figure 600 and Figure 700, the embodiment of Figure 450 is shown attached to or sandwiched between a substrate: substrate 604 / 704 includes one or more dielectric layers 608 / 708 with redistribution layers (RDL) or conductive traces 628 / 728 and vias 626 / 726 patterned therein on the top surface, and substrate 606 / 706 includes one or more dielectric layers 608 / 708 with redistribution layers (RDL) or conductive traces 628 and vias 626 patterned therein on the bottom surface.

[0031] The dielectric material may be one of the dielectric materials or insulating materials described above. The conductive material used for the RDL traces 628 and the vias 626 may comprise a metal (e.g., copper, aluminum, nickel, cobalt, iron, tin, gold, silver, or combinations thereof) or other suitable conductive material.

[0032] The optional cavity 432 was opened and filled with an IC, PIC, or other component, and electrically secured at 610 / 710 and at 612 / 712, as known in the art. As intended, the provided conformally plated vias in the glass layer provide landing and contact for vias, and provide an electrical path from the top surface 603 / 703 of the substrate to the bottom surface 605 / 705 of the substrate.

[0033] In Fig. 7, a first IC and a second IC were attached to the top surface 703, and solder was applied to the bottom surface 705 in the openings created for them. The dies IC1 and IC2 may be unpackaged integrated circuit dies and may alternatively be referred to as chips, chiplets, chip complexes, or chiplet complexes. While the terms die, chip, and chiplet can be used interchangeably, the term chiplet is sometimes used to refer to an integrated circuit that implements a subset of the functionality of a larger integrated circuit.Although the illustration shows chiplets with uniform dimensions, in practice, chiplet dimensions (lateral dimensions and thickness) and shape may vary depending on the chiplet; moreover, chiplets may vary depending on their type / functionality (e.g., computation, memory, I / O, power management, controlling power delivery, and / or providing power to components).

[0034] In further manufacturing steps, the IC1 and IC2 dies can be stabilized within an encapsulant, such as a potting compound, dielectric materials, metal, ceramic, plastic, or a combination thereof. Additionally, an underfill can be inserted beneath IC1 and IC2 to surround the solder bumps. A variety of underfill materials can be used; they are generally non-conductive (electrically) and reduce thermomechanical stress. Underfill materials can take the form of a liquid prepolymer with a filler, such as silicon dioxide, aluminum oxide, or boron nitride. The underfill can be cured to solidify it.

[0035] Additionally, as part of a thermal management solution, a thermal interface material (TIM) (not shown) may be disposed over the encapsulant and / or over the die. The TIM may be made of any suitable material, such as a silver particle-filled thermal compound, thermal grease, phase-change materials, indium foils, or graphite plates. The thermal management solution may be a conformal solution that accommodates height differences of the integrated circuit dies for which the thermal management solution provides cooling. For example, a thermal management solution may include a substantially planar cooling component with a TIM of varying thickness between the cooling component and the integrated circuit dies. In another example, the cooling component is non-planar, and the profile of the cooling component may vary with the thickness of the integrated circuit dies for which the cooling component provides cooling.In such embodiments, the TIM may be a substantially uniform thickness between the cooling component and the integrated circuit dies of varying thickness. Thermal management solutions may also include an integrated heat spreader.

[0036] Thus, various non-limiting embodiments of conformally plated vias in glass have been described. Embodiments exhibit different features in SEM images, including, but not limited to: cavities within TGVs having an insulating material therein, conductive material that varies in thickness along the TGV sidewall but maintains a consistent planar cross-sectional area, bridges of conductive material in the center of the TGV, and a wall of conductive seed material around the periphery of a cavity housing an IC or other component. The following description provides additional details and context for various dies and various package arrangements and device configurations that may be created based on or by using the provided embodiments.

[0037] Fig. 9 is a top view of wafer 900 and dies 902 that may be included in any of the embodiments disclosed herein. Wafer 900 may be formed from a semiconductor material and may include one or more dies 902 formed on a surface of wafer 900. After fabrication of the integrated circuit components on wafer 900 is complete, wafer 900 may undergo a singulation process in which dies 902 are separated from one another to provide discrete "chips" or are destined for a packaged integrated circuit component. The individual dies 902 comprising an integrated circuit component may include one or more transistors (for example, some of the transistors 1040 of Fig. 10, see below), support circuits for passing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, the wafer 900 or the die 902 may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive bridge RAM (CBRAM), etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. In addition, multiple devices may be combined on a single die 902. For example, a memory array formed by multiple memory devices may be implemented on the same die 902, such as a processor unit (e.g., processor unit 1202 of Fig. 12) or other logic configured to store information in the memory devices or execute instructions stored in the memory array. In some embodiments, a die 902 may be attached to a wafer 900 containing other dies, and the wafer 900 is subsequently singulated; this manufacturing process is referred to as a die-to-wafer assembly technique.

[0038] Fig. 10 is a cross-sectional side view of integrated circuit 1000 that may be included in any of the embodiments described herein. One or more of the integrated circuits 1000 may be incorporated into one or more dies 902 ( Fig. 9). The integrated circuit 1000 may be formed on die substrate 1002 (for example, wafer 900 of Fig. 9) and can be formed in a die (for example the Die 902 of Fig. 9) may be included.

[0039] The die substrate 1002 may be a semiconductor substrate formed from semiconductor material systems, including, for example, n-type or p-type material systems (or a combination of both). The die substrate 1002 may, for example, include a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 1002 may be formed using alternative materials that may or may not be combined with silicon, including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, III-V, or IV may also be used to form the die substrate 1002.Although a few examples of materials from which the die substrate 1002 may be formed are described herein, any material that can serve as a basis for an integrated circuit 1000 may be used. The die substrate 1002 may be part of a singulated die (for example, the die 902 of FIG. Fig. 9) or a wafer (for example, wafer 900 of Fig. 9).

[0040] The integrated circuit 1000 may include one or more device layers 1004 disposed on the die substrate 1002. The device layer 1004 may include features of one or more transistors 1040 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1002. The transistors 1040 may include, for example, one or more source and / or drain (S / D) regions 1020, gate 1022 for controlling current flow between the S / D regions 1020, and one or more S / D contacts 1024 for passing electrical signals to / from the S / D regions 1020.

[0041] The gate 1022 may be formed from at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one or more layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.In some embodiments, an annealing process may be performed on the gate dielectric to improve its quality when using a high-k material.

[0042] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or one n-type work function metal, depending on whether the transistor 1040 is to be a p-type metal-oxide-semiconductor (PMOS) transistor or an n-type metal-oxide-semiconductor (NMOS) transistor. In some implementations, the gate electrode may comprise a stack of two or more metal layers, where one or more metal layers are work function metal layers, and at least one metal layer is a fill metal layer. Additional metal layers may be included for other purposes, such as as a barrier layer.

[0043] For a PMOS transistor, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).

[0044] In some embodiments, when viewed as a cross-section of transistor 1040 along the source-channel-drain direction, the gate electrode may comprise a U-shaped structure including a bottom portion substantially parallel to the surface of die substrate 1002 and two sidewall portions substantially perpendicular to the top surface of die substrate 1002. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of die substrate 1002 and may not include sidewall portions substantially perpendicular to the top surface of die substrate 1002. In other embodiments, the gate electrode may comprise a combination of U-shaped structures and planar, non-U-shaped structures.For example, the gate electrode may comprise one or more U-shaped metal layers formed on top of one or more planar, non-U-shaped layers.

[0045] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and include deposition and etching processes. In some embodiments, multiple pairs of spacers may be used; for example, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0046] The S / D regions 1020 may be formed within the die substrate 1002 adjacent to the gate 1022 of individual transistors 1040. The S / D regions 1020 may be formed, for example, by using an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the die substrate 1002 to form the S / D regions 1020. An annealing process that activates the dopants and causes them to diffuse further into the die substrate 1002 may follow the ion implantation process. In the latter process, the die substrate 1002 may first be etched to form recesses at the locations of the S / D regions 1020. An epitaxial deposition process may then be performed to fill the recesses with a material used to fabricate the S / D regions 1020.In some implementations, the S / D regions 1020 may be fabricated using a silicon alloy, such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants, such as boron, arsenic, or phosphorus. In some embodiments, the S / D regions 1020 may be formed using one or more alternative semiconductor materials, such as germanium, or a Group III-V material or alloy. In further embodiments, one or more layers of metal and / or metal alloys may be used to form the S / D regions 1020.

[0047] Electrical signals, such as power and / or input / output (I / O) signals, may be transmitted to and / or from the devices (e.g., transistors 1040) of device layer 1004 through one or more interconnect layers disposed on device layer 1004 (illustrated in Fig. 10 as interconnect layers 1006-1010). For example, electrically conductive features of device layer 1004 (e.g., gate 1022 and S / D contacts 1024) may be electrically coupled to interconnect structures 1028 of interconnect layers 1006-1010. The one or more interconnect layers 1006-1010 may form metallization stacks (also referred to as "ILD stacks") 1019 of integrated circuit 1000.

[0048] The interconnect structures 1028 may be arranged within the interconnect layers 1006-1010 to transmit electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the Fig. 10 shown special configuration of interconnect structures 1028. Although a specific number of interconnect layers 1006-1010 in Fig. 10, embodiments of the present disclosure include integrated circuits with more or fewer interconnect layers than illustrated.

[0049] In some embodiments, the interconnect structures 1028 may include lines 1028a and / or vias 1028b filled with an electrically conductive material, such as a metal. The lines 1028a may be arranged to conduct electrical signals in a direction of a plane that is substantially parallel to a surface of the die substrate 1002 on which the device layer 1004 is formed. For example, the lines 1028a may conduct electrical signals in a direction into and out of the page and / or in a direction across the page. The vias 1028b may be arranged to conduct electrical signals in a direction of a plane that is substantially perpendicular to the surface of the die substrate 1002 on which the device layer 1004 is formed.In some embodiments, the vias 1028b may electrically couple lines 1028a of different interconnect layers 1006-1010.

[0050] The interconnect layers 1006-1010 may include dielectric material 1026 disposed between the interconnect structures 1028, as shown in Fig. 10. In some embodiments, the dielectric material 1026 disposed between the interconnect structures 1028 in different interconnect layers 1006-1010 may have different compositions; in other embodiments, the composition of the dielectric material 1026 may be the same between different interconnect layers 1006-1010. The device layer 1004 may also include a dielectric material 1026 disposed between the transistors 1040 and a lower layer of the metallization stack.The dielectric material 1026 included in device layer 1004 may have a different composition than the dielectric material 1026 included in interconnect layers 1006-1010; in other embodiments, the composition of the dielectric material 1026 in device layer 1004 may be the same as that of a dielectric material 1026 included in any of the interconnect layers 1006-1010.

[0051] A first interconnect layer 1006 (referred to as Metal 1 or "M1") may be formed directly on the device layer 1004. In some embodiments, the first interconnect layer 1006 may include lines 1028a and / or vias 1028b, as shown. The lines 1028a of the first interconnect layer 1006 may be coupled to contacts (e.g., S / D contacts 1024) of the device layer 1004. The vias 1028b of the first interconnect layer 1006 may be coupled to the lines 1028a of a second interconnect layer 1008.

[0052] The second interconnect layer 1008 (referred to as Metal 2 or "M2") may be formed directly on the first interconnect layer 1006. In some embodiments, the second interconnect layer 1008 may include a via 1028b to couple the interconnect structures 1028 of the second interconnect layer 1008 to the lines 1028a of a third interconnect layer 1010. Although the lines 1028a and the vias 1028b are structurally demarcated from each other by a line in individual interconnect layers for clarity, in some embodiments the lines 1028a and the vias 1028b may be structurally and / or materially contiguous (e.g., filled simultaneously during a dual damascene process).

[0053] The third interconnect layer 1010 (referred to as Metal 3 or "M3") (and additional interconnect layers if needed) may subsequently be formed on the second interconnect layer 1008 according to similar techniques and configurations described in connection with the second interconnect layer 1008 or the first interconnect layer 1006. In some embodiments, the interconnect layers located "higher up" in metallization stack 1019 in the integrated circuit 1000 (i.e., farther from the device layer 1004) may be thicker than the interconnect layers located lower in the metallization stack 1019, with the lines 1028a and the vias 1028b in the higher interconnect layers being thicker than those in the lower interconnect layers.

[0054] The integrated circuit 1000 may include solder stop material 1034 (e.g., polyimide or a similar material) and one or more conductive contacts 1036 formed on the interconnect layers 1006-1010. In Fig. 10, the conductive contacts 1036 are illustrated as taking the form of connection pads. The conductive contacts 1036 may be electrically coupled to the interconnect structures 1028 and configured to route the electrical signals of the one or more transistors 1040 to external devices. For example, solder connections may be formed on the one or more conductive contacts 1036 to mechanically and / or electrically couple an integrated circuit die including the integrated circuit 1000 to another component (e.g., a circuit board).The integrated circuit 1000 may include additional or alternative structures to route the electrical signals from the interconnect layers 1006-1010; for example, the conductive contacts 1036 may include other analog features (e.g., posts) that route the electrical signals to external components.

[0055] In some embodiments where the integrated circuit 1000 is a double-sided die, the integrated circuit 1000 may include another metallization stack (not shown) on the opposite side of the one or more device layers 1004. This metallization stack may include a plurality of interconnect layers, as discussed above with reference to the interconnect layers 1006-1010, to provide electrically conductive paths (e.g., including conductive lines and vias) between the one or more device layers 1004 and additional conductive contacts (not shown) on the opposite side of the integrated circuit 1000 from the conductive contacts 1036.

[0056] In other embodiments where the integrated circuit 1000 is a double-sided die, the integrated circuit 1000 may include one or more silicon vias (TSVs) through the die substrate 1002; these TSVs may provide contact with the one or more device layers 1004, and may provide electrically conductive paths between the one or more device layers 1004 and additional conductive contacts (not shown) on the opposite side of the integrated circuit 1000 from the conductive contacts 1036.In some embodiments, TSVs extending through the substrate may be used to route power and ground signals from conductive contacts on the opposite side of the integrated circuit 1000 from the conductive contacts 1036 to the transistors 1040 and any other components integrated into the integrated circuit 1000, and the metallization stack 1019 may be used to route I / O signals from the conductive contacts 1036 to the transistors 1040 and any other components integrated into the integrated circuit 1000.

[0057] Multiple integrated circuits 1000 may be stacked with one or more TSVs in each stacked device providing a connection between one of the devices to any of the other devices in the stack. For example, one or more high bandwidth memory (HBM) integrated circuit dies may be stacked on top of a base integrated circuit die, and the TSVs in the HBM dies may provide a connection between the single HBM die and the base integrated circuit die. Conductive contacts may provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts may be fine pitch solder bumps (microbumps).

[0058] Fig. 11 is a cross-sectional side view of microelectronic assembly 1100, which may include any of the embodiments disclosed herein. Microelectronic assembly 1100 includes multiple integrated circuit components disposed on circuit board 1102 (which may be a motherboard, a system board, a main board, etc.). Microelectronic assembly 1100 may include components disposed on first surface 1140 of circuit board 1102 and on opposite second surface 1142 of circuit board 1102; generally, components may be disposed on one or both surfaces 1140 and 1142.

[0059] In some embodiments, the circuit board 1102 may be a printed circuit board (PCB) that includes multiple metal (or interconnect) layers separated by layers of dielectric material and connected by electrically conductive vias. The individual metal layers comprise conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to carry electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1102. In other embodiments, the circuit board 1102 may be a non-PCB substrate. The Fig. 11 includes package-on-interposer structure 1136 coupled to first surface 1140 of circuit board 1102 by coupling components 1116. Coupling components 1116 may electrically and mechanically couple package-on-interposer structure 1136 to circuit board 1102 and may include solder balls (as shown in Fig. 11), pins (for example, as part of a pin grid array (PGA)), contacts (for example, as part of a contact pad array (LGA)), male and female portions of a socket, an adhesive, an underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0060] The package-on-interposer structure 1136 may include integrated circuit component 1120 coupled to interposer 1104 by coupling components 1118. The coupling components 1118 may take any form suitable for the application, such as the forms discussed above with reference to the coupling components 1116. Although a single integrated circuit component 1120 in Fig. As shown in Figure 11, multiple integrated circuit components may be coupled to interposer 1104; in fact, additional interposers may be coupled to interposer 1104. Interposer 1104 may provide an intermediate substrate used to bridge circuit board 1102 and integrated circuit component 1120.

[0061] The integrated circuit component 1120 may be a packaged or unpackaged integrated circuit component that includes one or more integrated circuit dies (for example, the die 902 of Fig. 9, the integrated circuit 1000 of Fig. 10) and / or one or more other suitable components.

[0062] The unpackaged integrated circuit component 1120 includes solder bumps that attach to the contacts on the die. The solder bumps enable the die to be attached directly to the interposer 1104. In embodiments where the integrated circuit component 1120 includes multiple integrated circuit dies, the dies may be of the same type (a homogeneous integrated circuit component across multiple dies) or of two or more different types (a heterogeneous integrated circuit component across multiple dies). In addition to including one or more processor units, the integrated circuit component 1120 may include additional components, such as embedded DRAM, high-bandwidth stacked memory (HBM), shared caches, input / output (I / O) controllers, or memory controllers.Any of these additional components may be arranged on the same integrated circuit die as a processor unit, or on one or more integrated circuit dies separate from the integrated circuit dies comprising the processor units. These separate integrated circuit dies may be referred to as "chiplets." In embodiments where an integrated circuit component comprises multiple integrated circuit dies, connections between the dies may be provided by the package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate, or combinations thereof. A packaged integrated circuit component on multiple dies may be referred to as a multi-chip package (MCP) or multi-chip module (MCM).

[0063] The interposer 1104 can spread connections to a larger pitch or redirect a connection to a different connection. For example, the interposer 1104 can couple the integrated circuit component 1120 to a set of conductive ball grid array (BGA) contacts of the coupling components 1116 for coupling to the circuit board 1102. In the Fig. In the embodiment illustrated in Figure 11, the integrated circuit component 1120 and the circuit board 1102 are mounted on opposite sides of the interposer 1104; in other embodiments, the integrated circuit component 1120 and the circuit board 1102 may be mounted on the same side of the interposer 1104. In some embodiments, three or more components may be interconnected using the interposer 1104.

[0064] In some embodiments, the interposer 1104 may be formed as a PCB including multiple metal layers separated by layers of dielectric material and connected by electrically conductive vias. In some embodiments, the interposer 1104 may be formed from an epoxy resin, a glass-fiber reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 1104 may be formed from alternating rigid or flexible materials, which may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other Group III-V and Group IV materials.The interposer 1104 may include metal interconnects 1108 and vias 1110, including, but not limited to, through-hole vias 1110-1 (extending from the first surface 1150 of the interposer 1104 to the second surface 1154 of the interposer 1104), blind vias 1110-2 (extending from the first or second surface 1150 or 1154 of the interposer 1104 to an internal metal layer), and buried vias 1110-3 (connecting internal metal layers).

[0065] In some embodiments, the interposer 1104 may comprise a silicon interposer. Silicon vias (TSVs) extending through the silicon interposer may connect connections on the first surface of a silicon interposer to an opposite second surface of the silicon interposer. In some embodiments, an interposer 1104 comprising a silicon interposer may further include one or more routing layers to route connections on a first surface of the interposer 1104 to an opposite second surface of the interposer 1104.

[0066] The interposer 1104 may further include embedded devices 1114, which may include both passive and active devices. Such devices may include, among others, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical system (MEMS) devices, may also be formed on the interposer 1104. The package-on-interposer structure 1136 may take the form of any of the package-on-interposer structures known in the art.

[0067] The integrated circuit assembly 1100 may include integrated circuit component 1124 coupled to the first surface 1140 of the circuit board 1102 by coupling components 1122. The coupling components 1122 may take the form of any of the embodiments discussed above with reference to the coupling components 1116, and the integrated circuit component 1124 may take the form of any of the embodiments discussed above with reference to the integrated circuit component 1120.

[0068] The Fig. Integrated circuit assembly 1100 illustrated in Figure 11 includes package-on-package structure 1134 coupled to second surface 1142 of circuit board 1102 by coupling components 1128. Package-on-package structure 1134 may include integrated circuit component 1126 and integrated circuit component 1132 coupled together by coupling components 1130 such that integrated circuit component 1126 is disposed between circuit board 1102 and integrated circuit component 1132. Coupling components 1128 and 1130 may take the form of any of the embodiments of coupling components 1116 discussed above, and integrated circuit components 1126 and 1132 may take the form of any of the embodiments of integrated circuit component 1120 discussed above.The package-on-package structure 1134 may be configured according to any of the package-on-package structures known in the art.

[0069] Fig. 12 is a block diagram of exemplary electrical device 1200 that may include one or more of the embodiments disclosed herein. For example, any suitable components of electrical device 1200 may include one or more of the microelectronic assemblies 1100, integrated circuit components 1120, integrated circuits 1000, or integrated circuit dies 902 or structures disclosed herein. A number of components are described in Fig. 12 as being included in the electrical device 1200, however, any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in the electrical device 1200 may be attached to one or more motherboards, main boards, printed circuit boards, or system boards. In some embodiments, one or more of these components may be fabricated on a single system-on-chip (SoC) die. In various embodiments, the electrical device 1200 is enclosed by or integrated within a package.

[0070] Additionally, in various embodiments, the electrical device 1200 may include one or more of the Fig.12, but the electrical device 1200 may include interface circuitry for coupling to the one or more components. For example, the electrical device 1200 may not include a display device 1206, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 1206 may be coupled. In another set of examples, the computing device 1200 may not include an audio input device 1224 or an audio output device 1208, but may include audio input or audio output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 1224 or an audio output device 1208 may be coupled.

[0071] The electrical device 1200 may include one or more processor units 1202 (e.g., one or more processor units). As used herein, the terms "processor unit," "processing unit," or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to convert that electronic data into other electronic data that may be stored in registers and / or memory.Processor unit 1202 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processing units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), control cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, controllers, or any other suitable type of processor units. Therefore, the processor unit may be referred to as an XPU (or xPU).

[0072] The electrical device 1200 may include memory 1204, which in turn may include one or more storage devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based stress-free phase-change memory), solid-state memory, and / or a hard disk drive. In some embodiments, the memory 1204 may include memory disposed on the same integrated circuit die as the processor unit 1202. This memory may be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last Level Cache (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0073] In some embodiments, the electrical device 1200 may include one or more processor units 1202 that are heterogeneous or asymmetric with another processor unit 1202 within the electrical device 1200. There may be a variety of differences between the processor units 1202 in a system with respect to a spectrum of performance metrics, including architectural, microarchitectural, thermal, power consumption characteristics, and the like. These differences may effectively manifest themselves as asymmetry and heterogeneity between the processor units 1202 within the electrical device 1200.

[0074] In some embodiments, electrical device 1200 may include communication component 1212 (e.g., one or more communication components). For example, communication component 1212 may manage wireless communications for the transfer of data to and from electrical device 1200. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that communicate data using modulated electromagnetic radiation through a non-solid medium. The term "wireless" does not imply that the associated devices do not contain any wires, although in some embodiments, they may not contain them.

[0075] The communication component 1212 may implement any of a number of wireless standards or protocols, including, but not limited to, Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Supplement), Long-Term Evolution (LTE) project along with any amendments, updates, and / or revisions (e.g., Advanced LTE project, Ultra-Mobile Broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compliant Broadband Wireless Access (BWA) networks are commonly referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformance and compatibility tests for the IEEE 802.16 standards.The communication component 1212 may operate according to a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 1212 may operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 1212 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols designated 3G, 4G, 5G, and beyond. The communication component 1212 may operate according to other wireless protocols in other embodiments.The electrical device 1200 may include antenna 1222 to facilitate wireless communications and / or to receive other wireless communications (such as AM or FM radio transmissions).

[0076] In some embodiments, the communication component 1212 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., IEEE 802.3 Ethernet standards). As mentioned above, the communication component 1212 may include multiple communication components. For example, a first communication component 1212 may be dedicated for shorter-range wireless communications, such as Wi-Fi or Bluetooth, and a second communication component 1212 may be dedicated for longer-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication component 1212 may be dedicated for wireless communications, and a second communication component 1212 may be dedicated for wired communications.

[0077] Electrical device 1200 may include battery / power circuitry 1214. Battery / power circuitry 1214 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of electrical device 1200 to a power source (e.g., AC power) separate from electrical device 1200.

[0078] The electrical device 1200 may include a display device 1206 (or corresponding interface circuitry, as discussed above). The display device 1206 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0079] The electrical device 1200 may include an audio output device 1208 (or corresponding interface circuitry, as discussed above). The audio output device 1208 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such as speakers, headphones, or earbuds.

[0080] The electrical device 1200 may include an audio input device 1224 (or corresponding interface circuitry, as discussed above). The audio input device 1224 may include any embedded, wired, or wirelessly connected device that generates a signal representing sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments with a Musical Instrument Digital Interface (MIDI) output). The electrical device 1200 may include a Global Navigation Satellite System (GNSS) device 1218 (or corresponding interface circuitry, as discussed above), such as a Global Positioning System (GPS) device. The GNSS device 1218 may be in communication with a satellite-based system and may determine a geographic location of the electrical device 1200 based on information received from one or more GNSS satellites, as known in the art.

[0081] The electrical device 1200 may include another output device 1210 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1210 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0082] The electrical device 1200 may include other input device 1220 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1220 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., a monoscopic or stereoscopic camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device such as a mouse, a stylus, a touchscreen, a proximity sensor, a microphone, a barcode reader, a quick response (QR) code reader, an electrocardiogram (ECG) sensor, a photoplethysmogram (PPG) sensor, a galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.

[0083] The electrical device 1200 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a mobile phone, a smartphone, a mobile internet device, a music player, a tablet computer, a laptop computer, a convertible 2-in-1 computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable game console, etc.), a desktop electrical appliance, a server, a rack-level computing solution (e.g., blade, tray, or sled computing systems), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary game console, a smart television, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device, or an embedded computing system (e.g., computing systems that are part of a vehicle, a smart home appliance, a consumer electronics product or equipment, or a piece of manufacturing equipment). In some embodiments, the electrical device 1200 may be any other electronic device that processes data. In some embodiments, the electrical device 1200 may include multiple discrete physical components.Given the variety of devices that electrical device 1200 may manifest as in various embodiments, electrical device 1200 may be referred to as a computing device or a computing system in some embodiments.

[0084] Although at least one embodiment has been presented in the foregoing detailed description, it should be appreciated that numerous variations exist. It should also be understood that the disclosed embodiments are only examples and are not intended to limit the scope, applicability, or configuration of the disclosure in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient roadmap for implementing the disclosed example embodiments. Various changes may be made in the function and arrangement of elements without departing from the scope of the disclosure as recited in the appended claims and their legal equivalents.

[0085] As used herein, the term “electronic component” may refer to an active electronic circuit (e.g., a processing unit, a memory, a storage device, FET) or a passive electronic circuit (e.g., a resistor, an inductor, a capacitor).

[0086] As used herein, the term "integrated circuit component" may refer to an electronic component configured on a semiconductive material to perform a function. An integrated circuit (IC) component may include one or more of any computing system components described or referenced herein or any other computing system component, such as a processor unit (e.g., system-on-a-chip (SoC), processor core, graphics processing unit (GPU), accelerator, chipset processor), I / O controller, memory, or network interface controller, and may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and storage devices.

[0087] A non-limiting example of an unpackaged integrated circuit component includes a single monolithic integrated circuit die; the die may include solder bumps attached to contacts on the die. The solder bumps or other conductive contacts, if present on the die, may enable direct attachment of the die to a printed circuit board (PCB) or other substrate.

[0088] A non-limiting example of a packaged integrated circuit component includes one or more integrated circuit dies mounted on a package substrate, where the integrated circuit dies and the package substrate are encapsulated in an encapsulating material, such as metal, plastic, glass, or ceramic. Often, the encapsulation includes an integrated heat spreader (IHS); the packaged integrated circuit component often has bumps, leads, or pins attached to the package substrate (either directly or through wires attaching the bumps, leads, or pins to the package substrate) to attach the packaged integrated circuit component to a printed circuit board (or motherboard or baseboard) or other component.

[0089] As used herein, phrases such as "one embodiment," "one embodiment," "various embodiments," "some embodiments," and the like indicate that some embodiments may have some, all, or none of the features described for other embodiments. "First," "second," "third," and the like describe a common object and indicate different instances of similar objects being referred to; unless explicitly stated, they do not imply a particular sequence, whether temporal or spatial, in terms of precedence, or in any other way. Consistent with the language of the patent application, "connected" indicates elements that are in direct physical or electrical contact with each other, and "coupled" indicates elements that cooperate or interact with each other; coupled elements may or may not be in direct physical or electrical contact.Furthermore, the terms “comprising,” “including,” “having,” and the like are used synonymously to denote non-exclusive inclusions.

[0090] As used in this application and the claims, a list of items joined by the phrase "at least one of" or the phrase "one or more of" may mean any combination of the listed terms. For example, the phrase "at least one of A, B, or C" may mean A; B; C; A and B; A and C; B and C; or A, B, and C. Similarly, the phrase "one or more of A, B, or C" may mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0091] As used in this application and the claims, the phrase "any one of" or "a respective one of" followed by a list of elements recited or stated as having a property, feature, etc. means that all elements in the list have the recited or stated property, feature, etc. For example, the phrase "any one of A, B, or C includes a sidewall" or "respective one of A, B, or C includes a sidewall" means that A includes a sidewall, B includes a sidewall, and C includes a sidewall.

[0092] Any operating theories, scientific principles, or other theoretical descriptions presented herein with reference to the devices or methods of this disclosure are provided for convenience of understanding and are not intended to limit the scope. The devices and methods in the appended claims are not limited to those devices and methods that function in the manner described by such operating theories.

[0093] The following examples relate to additional embodiments of technologies disclosed herein. EXAMPLES

[0094] Example 1 is a device comprising: a glass layer defined by a top surface and a bottom surface; a through-hole formed in the glass layer extending downward from the top surface to the bottom surface with an axis orthogonal to the top surface; the through-hole characterized by a sidewall having a first diameter at the top surface and the first diameter at the bottom surface; a conductive material conforming to the sidewall from the top surface to the bottom surface and defining a cavity therein; an insulating material in the cavity; and a conductive contact extending across the through-hole at the top surface and electrically connected to the conductive material.

[0095] Example 2 includes the subject matter of Example 1, wherein the cavity extends from the top surface to the bottom surface, and the insulation material is continuous from the top surface to the bottom surface.

[0096] Example 3 includes the subject matter of Example 1, wherein the through-hole is further characterized by a second diameter between the top surface and the bottom surface, the second diameter being at least 20% smaller than the first diameter.

[0097] Example 4 includes the subject matter of any of Examples 1-3, wherein the conductive material comprises a cross-sectional area measured perpendicular to the axis, and between the top surface and the bottom surface, the cross-sectional area varies by less than 10%.

[0098] Example 5 includes the subject matter of any of Examples 1, 3, or 4, wherein the conductive material comprises a thickness measured orthogonally from the sidewall, and wherein the thickness at the top surface and the bottom surface is at least 20% less than the thickness at a midpoint between the top surface and the bottom surface.

[0099] Example 6 includes the subject matter of Example 5, and further includes a bridge formed by the conductive material between the top surface and the bottom surface.

[0100] Example 7 includes the subject matter of Example 6, wherein the bridge forms a floor to the cavity and creates an additional cavity between the bridge and the bottom surface; and further comprises the insulating material in the additional cavity.

[0101] Example 8 includes the subject matter of Example 1 or Example 7, and further comprises a conductive pad extending across the through-hole on the bottom surface and electrically connected to the conductive material.

[0102] Example 9 includes the subject matter of any of Examples 1-8, wherein the conductive material comprises a layer of ruthenium, then a layer of copper, then a layer of titanium, followed by a layer of copper.

[0103] Example 10 includes the subject matter of any of Examples 1-8, wherein the conductive material and the conductive contact comprise copper.

[0104] Example 11 includes the subject matter of any of Examples 1-10, wherein the insulating material is a dielectric material.

[0105] Example 12 is a semiconductor package comprising: a semiconductor substrate including a plurality of dielectric layers and redistribution layers therein; a conductive via in the semiconductor substrate, the conductive via electrically connected to a redistribution layer and exposed at a bottom surface of the semiconductor substrate; a glass layer attached to the bottom surface of the semiconductor substrate, the glass layer comprising a plurality of glass vias; the glass vias comprising tapered sidewalls conformally plated with a conductive material; wherein in the tapered sidewalls, the conductive material forms a respective cavity with an insulating material therein; a conductive contact on the glass layer, the conductive contact extending across a glass via;and wherein the conductive via is electrically attached to the conductive contact;

[0106] Example 13 includes the subject matter of Example 12, wherein the conductive material in the tapered sidewalls forms a bridge in the glass via.

[0107] Example 14 includes the subject matter of Example 12 or Example 13, wherein in the tapered sidewalls, the conductive material has a first thickness at a top surface of the glass layer and a second thickness, greater than the first thickness, at a midpoint between the top surface and a bottom surface of the glass layer.

[0108] Example 15 includes the subject matter of Example 12 or Example 13, wherein the glass vias are formed about an axis orthogonal to a top surface of the glass layer; wherein in the tapered sidewalls, the conductive material comprises a cross-sectional area measured perpendicular to the axis; and between the top surface and the bottom surface, the cross-sectional area of ​​the conductive material in a TGV varies by less than 10%.

[0109] Example 16 includes the subject matter of any of Examples 12-15, and further comprises: an integrated circuit die mounted on a top surface of the semiconductor substrate; and an electrical path from the integrated circuit die through a glass via of the plurality of glass vias to a bottom surface of the glass layer.

[0110] Example 17 is a method comprising: creating glass vias (TGVs) in a glass layer; depositing a liner layer on the glass layer with the TGVs; depositing, over the liner layer, a hybrid layer comprising ruthenium, then copper, then titanium, followed by copper; causing the hybrid layer to form a cavity in the TGVs with a bridge therein; laminating a dielectric material on the hybrid layer; and causing the dielectric material in the TGVs to fill at least a portion of the cavity above the bridge.

[0111] Example 18 includes the subject matter of Example 17, and further comprises: removing the dielectric material to expose the hybrid layer; attaching a conductive plate to the hybrid layer; and etching the conductive plate to create a respective conductive contact for individual TGVs.

[0112] Example 19 includes the subject matter of Example 18, and further comprises attaching a first silicon substrate to a top surface of the glass layer, and a second silicon substrate to a bottom surface of the glass layer.

[0113] Example 20 includes the subject matter of Example 19, and further comprises attaching an integrated circuit (IC) die to the first silicon substrate and creating an electrical path from the IC die to a conductive contact on a bottom surface of the second silicon substrate.

Claims

[1] Device comprising: a glass layer defined by a top surface and a bottom surface; a through-hole formed in the glass layer extending downward from the upper surface to the lower surface, with an axis orthogonal to the upper surface; the through-hole characterized by a sidewall having a first diameter at the top surface and the first diameter at the bottom surface; a conductive material conforming to the sidewall from the top surface to the bottom surface and defining a cavity therein; an insulating material in the cavity; and a conductive contact extending across the through-hole on the top surface and electrically connected to the conductive material. [2] The device of claim 1, wherein the cavity extends from the upper surface to the lower surface, and the insulating material is continuous from the upper surface to the lower surface. [3] The device of claim 1, wherein the through-hole is further characterized by a second diameter between the upper surface and the lower surface, the second diameter being at least 20% smaller than the first diameter. [4] The device of any of claims 1-3, wherein the conductive material comprises a cross-sectional area measured perpendicular to the axis, and between the top surface and the bottom surface the cross-sectional area varies by less than 10%. [5] The device of any of claims 1-3, wherein the conductive material comprises a thickness measured orthogonally from the sidewall, and wherein the thickness at the top surface and the bottom surface is at least 20% less than the thickness at a midpoint between the top surface and the bottom surface. [6] The device of claim 4, wherein the conductive material comprises a thickness measured orthogonally from the sidewall, and wherein the thickness at the top surface and the bottom surface is at least 20% less than the thickness at a midpoint between the top surface and the bottom surface. [7] The device of claim 1, further comprising a bridge formed by the conductive material between the upper surface and the lower surface. [8] The device of claim 7, wherein the bridge forms a floor to the cavity, and creates an additional cavity between the bridge and the lower surface; and further comprising the insulating material in the additional cavity. [9] The device of claim 1, further comprising a conductive pad extending across the through-hole on the bottom surface and electrically connected to the conductive material. [10] The device of claim 8, further comprising a conductive pad extending across the through-hole on the bottom surface and electrically connected to the conductive material. [11] The device of claim 1, wherein the conductive material comprises a layer of ruthenium, then a layer of copper, then a layer of titanium, followed by a layer of copper. [12] The device of claim 8, wherein the conductive material comprises a layer of ruthenium, then a layer of copper, then a layer of titanium, followed by a layer of copper. [13] The device of claim 1 or claim 12, wherein the conductive material and the conductive contact comprise copper. [14] The device of claim 1, wherein the insulating material is a dielectric material. [15] Semiconductor package comprising: a semiconductor substrate including a plurality of dielectric layers and redistribution layers therein; a conductive via in the semiconductor substrate, the conductive via being electrically connected to a redistribution layer and exposed at a lower surface of the semiconductor substrate; a glass layer attached to the bottom surface of the semiconductor substrate, the glass layer comprising a plurality of glass vias; wherein the glass vias comprise tapered sidewalls conformally plated with a conductive material; wherein in the tapered side walls the conductive material forms a respective cavity with an insulating material therein; and a conductive contact on the glass layer, the conductive contact extending across a glass via; wherein the conductive via is electrically attached to the conductive contact. [16] The semiconductor package of claim 15, wherein the conductive material in the tapered sidewalls forms a bridge in the glass via. [17] The semiconductor package of claim 15, wherein in the tapered sidewalls the conductive material has a first thickness at a top surface of the glass layer and a second thickness, greater than the first thickness, at a midpoint between the top surface and a bottom surface of the glass layer. [18] The semiconductor package of claim 16, wherein in the tapered sidewalls the conductive material has a first thickness at a top surface of the glass layer and a second thickness, greater than the first thickness, at a midpoint between the top surface and a bottom surface of the glass layer. [19] The semiconductor package of claim 15, wherein the glass vias are formed around an axis orthogonal to a top surface of the glass layer; wherein in the tapered sidewalls the conductive material comprises a cross-sectional area measured perpendicular to the axis; and between the top surface and the bottom surface, the cross-sectional area of ​​the conductive material in a TGV varies by less than 10%. [20] The semiconductor package of claim 15, further comprising: an integrated circuit die mounted on a top surface of the semiconductor substrate; and an electrical path from the integrated circuit die through a glass via of the plurality of glass vias to a bottom surface of the glass layer. [21] The semiconductor package of claim 19, further comprising: an integrated circuit die mounted on a top surface of the semiconductor substrate; and an electrical path from the integrated circuit die through a glass via of the plurality of glass vias to a bottom surface of the glass layer. [22] Procedure comprising: Creating glass vias (TGV) in a glass layer; Depositing a lining layer on the glass layer with the TGV; Depositing, over the liner layer, a hybrid layer comprising ruthenium, then copper, then titanium, followed by copper; Cause the hybrid layer in the TGV to form a cavity with a bridge inside; Laminating a dielectric material on the hybrid layer; and Cause the dielectric material in the TGV to fill at least part of the cavity above the bridge. [23] The method of claim 22, further comprising: Removing the dielectric material to expose the hybrid layer; Attaching a conductive plate to the hybrid layer; and Etching the conductive plate to create a conductive contact for each TGV. [24] The method of claim 23, further comprising attaching a first silicon substrate to a top surface of the glass layer and a second silicon substrate to a bottom surface of the glass layer. [25] The method of claim 24, further comprising attaching an integrated circuit (IC) -Die on the first silicon substrate and creating an electrical path from the IC die to a conductive contact on a lower surface of the second silicon substrate.

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