Methods and systems for synchronizing an analog-to-digital converter

Abstract

A method for synchronizing an analog-to-digital converter, ADC, the method comprising: stopping, by a processor, a master clock signal to the ADC to pause sampling of the ADC, the master clock signal being provided to the ADC by an external master clock; detecting, by the ADC, that a synchronization event has occurred while the master clock is stopped; restarting, by the processor, the master clock signal to the ADC; resetting, by the ADC, an internal filter at a time synchronous with the master clock; and resuming, by the ADC, sampling in response to the ADC's internal filter being reset.

Description

priority

[0001] The present application claims priority over non-provisional US application No. 18 / 641803. Area

[0002] The present disclosure relates generally to methods and systems for synchronizing an analog-to-digital converter (ADC) and for synchronizing two or more ADCs. In particular, but not exclusively, the present disclosure relates to methods and systems for synchronizing an ADC or synchronizing two or more ADCs by stopping and starting a single master clock signal. background

[0003] Multichannel instruments typically require simultaneous sampling and use oversampling ADCs, which sample the input multiple times to generate a data output, resulting in an output with a lower frequency than the sampling frequency. Without output synchronization, decimation could cause the various channels of the multichannel instrument to produce outputs with significantly different phases. To achieve accurate and reliable data acquisition in multichannel, high-speed sampling applications, ADC synchronization at the output is used, and precise timing relationships between output signals are desirable. Furthermore, there are specific IEEE requirements and standards for synchronization schemes within some devices and instruments.

[0004] However, when multiple ADCs are involved, the ADC synchronization process is not straightforward and may require a complex hardware circuit arrangement. This hardware circuit arrangement can often include multiple input / output arrays and multiple system clocks.

[0005] Therefore, there is a need for an improved method and system for operating one ADC or two or more ADCs to ensure adequate synchronization. Summary of the Revelation

[0006] In ADC systems, the ADCs continuously perform sampling, i.e., sampling the input, and generating an output. Specifically, in oversampling ADC systems, the ADCs sample the input multiple times to generate a single data output. In many cases, several ADCs share the same master clock signal and therefore sample the input simultaneously. However, they may not generate the output simultaneously. This leads to a synchronization problem between the multiple ADCs in the system, which can result in phase errors in the measurement.

[0007] In the context of multi-channel instruments, for example, oversampling ADCs are used, which sample input values ​​multiple times to generate a single data output. This means that there is a risk of the multi-channel instruments experiencing an increased phase error between the outputs of the different instrument channels. This is also a particular problem in systems and devices where components requiring synchronized sampling are geographically separated. Therefore, there is a need to synchronize the sampling of individual ADCs within a system with respect to a time reference to ensure that the phase error is reduced. In turn, this enables the operation or synchronization of an ADC system with precise timing relationships between outputs.

[0008] This disclosure relates to a method for operating and synchronizing an ADC system. The ADC system can comprise a single ADC or multiple ADCs. This disclosure provides a method that involves stopping the master clock of the ADC system, causing the ADC to cease normal operation, such as sampling an input signal. The ADC system then receives or detects information indicating that the ADC should perform synchronization with a time reference. Upon restarting the master clock, the ADC's internal circuitry triggers the resumption of ADC sampling. Therefore, ADC sampling can be predictably restarted at a deterministic time after the master clock restart. This approach can be used to ensure the predictable restart of ADC sampling relative to a time reference for a single ADC or multiple ADCs.Accordingly, the present disclosure aims to provide methods and systems for enabling the operation or synchronization of an ADC system with precision timing relationships between outputs.

[0009] Furthermore, the present disclosure provides methods and systems for synchronizing one or more ADCs in such a way that they are robustly, reliably, and efficiently time-reference synchronized. In other words, the methods and systems aim to provide ADC time-reference synchronization with significantly reduced phase error in the output, reduced hardware and software complexity, minimal hardware footprint, and high predictability of the synchronization.

[0010] The present disclosure provides an ADC system and a multiple ADC system consisting of two or more ADCs. In both systems, the system may include at least one ADC, a processor, and a master clock. The master clock is a device located outside of the one or more ADCs. In the system with multiple ADCs, the ADCs are arranged such that all ADCs share a master clock. In conjunction with the ADC system, the present disclosure provides a method for operating the ADC system. The method involves stopping, by a processor, the master clock of the ADC(s) and pausing the sampling, then triggering or detecting a synchronization event at the ADC(s) while the master clock is stopped. Next, the method restarts the master clock of the ADC(s).When the master clock restarts, the internal filter of the ADC(s) is reset at a time synchronized with the restart of the master clock, so that sampling of the ADC(s) restarts in response to the internal filter reset. Sampling of one or more ADCs can be synchronized with respect to a time reference.

[0011] In a first aspect, a method for synchronizing an analog-to-digital converter (ADC) is provided, wherein the method comprises: stopping, by a processor, a master clock signal to the ADC to pause the sampling of the ADC, the master clock being supplied to the ADC by an external master clock; detecting, by the ADC, that a synchronization event has occurred while the master clock is stopped; restarting, by the processor, the master clock signal to the ADC; resetting, by the ADC, an internal filter at a time synchronous with the master clock; and resuming, by the ADC, sampling in response to the resetting of the ADC's internal filter.

[0012] The ADC synchronization method offers the advantage of robust and reliable ADC operation, as it allows the ADC to be used in conjunction with other ADCs without phase errors in their outputs. For example, the ADC is time-reference synchronized. This is achieved by enabling the synchronization of multiple ADCs without the need for separate synchronization signals or isolation components. This reduces system complexity, lowers hardware costs, and limits potential failure points, among other benefits.

[0013] In a second aspect, a method for synchronizing two or more analog-to-digital converters (ADCs) is provided, wherein the method comprises: stopping, by a processor, a shared master clock signal to two or more ADCs to pause the sampling of the two or more ADCs, the shared master clock being supplied to the two or more ADCs by an external master clock; detecting, by each of the two or more ADCs, that a synchronization event has occurred while the shared master clock is stopped; restarting, by the processor, the shared master clock signal to each of the two or more ADCs; resetting, by each of the two or more ADCs, an internal filter at a time synchronous with the master clock; and resuming, by the two or more ADCs, sampling in response to the resetting of their respective internal filters.

[0014] The method for synchronizing two or more ADCs offers the advantage of enabling the use of the ADCs without phase errors between their outputs. In some examples, the two or more ADCs may be oversampling ADCs, and thus the method ensures that the two or more ADCs sample the input signal synchronously with respect to a time reference. Removing phase errors improves system performance by ensuring robust and reliable operation of all ADCs within the system.

[0015] In a third aspect, an analog-to-digital converter (ADC) system is provided, the system comprising: an ADC including an internal filter; a master clock, wherein the master clock is located outside the ADC and coupled to it; a processor, wherein the processor is located outside the ADC and the master clock and coupled to them; and memory and computer program code stored therein, wherein, when executed by the processor, the computer program code does the following: stop, by a processor, a master clock signal to the ADC to pause the sampling of the ADC, wherein the master clock is supplied to the ADC by an external master clock; detect, by the ADC, that a synchronization event has occurred while the master clock is stopped; restart, by the processor, the master clock signal to the ADC;Resetting, by the ADC, an internal filter at a time synchronized with the master clock; and resuming, by the ADC, sampling in response to the resetting of the ADC's internal filter.

[0016] The ADC synchronization method offers the advantage of robust and reliable ADC operation, as it allows the ADC to be used in conjunction with other ADCs without phase errors in their outputs. For example, the ADC is time-reference synchronized. This is achieved by enabling the synchronization of multiple ADCs without the need for separate synchronization signals or isolation components. This reduces system complexity, lowers hardware costs, and limits potential failure points, among other benefits.

[0017] Further features and advantages are evident from the attached claims. Definitions

[0018] In this context, "synchronization" means ensuring that the sampling of each ADC is started at a specific, known time. Therefore, synchronization can be said to refer to time-related synchronization, where multiple ADCs do not necessarily have to sample at the same rate, as long as they can all be started at the required specific time.

[0019] "Master clock" refers to a clock signal supplied to an ADC from an external clock device or source. The master clock is distinct from the ADC's internal clock. In systems with multiple ADCs, the master clock is a shared master clock, as the same external clock device or source is coupled to all of the multiple ADCs within the system.

[0020] "Internal clock" refers to the clock signal present within any ADC. This clock signal is used to execute the instructions required for the general operation of the ADC.

[0021] "Synchronization event" refers to a stimulus received by or detected by the ADC that would indicate the ADC must attempt, or is instructed to attempt, to synchronize its sampling relative to a time reference. This stimulus could be in the form of receiving an instruction from a processor or detecting any environmental change within the ADC, such as the master clock stopping, etc.

[0022] "Internal filter" refers to a component of the ADC's internal circuitry. The internal filter is the device within the ADC that is triggered to reset upon detection or indication of a synchronization event. Indication of the synchronization event and subsequent reset of the internal filter allow the ADC to restart continuous sampling. The internal filter (or internal digital filter) is used during normal operation in an ADC or an oversampling ADC to process ADC samples and average them to digitally filter the samples. In oversampling ADCs, this process reduces the sampling rate. Figures

[0023] Further features and advantages of the present disclosure will become apparent from the following description, which is provided only as an example and with reference to the accompanying drawings, in which identical reference numerals refer to identical parts and in which: Fig. Figure 1 shows an exemplary schematic diagram of a synchronized multiple ADC system according to one approach; Fig. Figure 2 shows an example timing diagram for the synchronized multiple ADC system of Fig. 1 according to one approach; Fig. Figure 3 shows an exemplary schematic diagram of a channel-isolated DAQ system according to one approach; Fig. Figure 4a shows an exemplary schematic diagram of an ADC according to the present disclosure; Fig. Figure 4b shows an exemplary schematic diagram of an ADC according to the present disclosure; Fig. Figure 5 shows an exemplary schematic diagram of an FPGA system according to the present disclosure; Fig. Figure 6 shows an exemplary schematic diagram of an MCU system according to the present disclosure. Fig. Figure 7 shows an example timing diagram for use with the ADC system of Fig. 4a according to the present revelation; Fig. Figure 8 shows an example timing diagram for use with the ADC system of Fig. 4b according to the present revelation; Fig. Figure 9 shows an example timing diagram for use with the ADC system of Fig. 4a according to the present revelation; Fig. Figure 10 shows an example timing diagram for use with the ADC system of Fig. 4b according to the present revelation; Fig. Figure 11 shows an exemplary flowchart of the procedure for operating an ADC system, such as the ADC system 4a, according to the present disclosure; Fig. Figure 12 shows an exemplary flowchart of the procedure for operating an ADC system, such as the ADC system 4b, according to the present disclosure; Fig. Figure 13 shows an exemplary flowchart of the procedure for operating an ADC system, such as ADC system 4a, according to the present disclosure; and Fig. Figure 14 shows an exemplary flowchart of the procedure for operating an ADC system, such as the ADC system 4b, according to the present disclosure. Detailed description

[0024] The present disclosure provides methods and systems for synchronizing one or more ADCs such that the ADC(s) are robustly, reliably, and efficiently time-reference synchronized. Furthermore, the methods and systems aim to provide ADC time-reference synchronization without phase errors in the output, minimal hardware and software complexity, minimal hardware footprint, high predictability of the synchronization, low cost, etc.

[0025] In particular, the present disclosure utilizes an ADC system comprising one or more ADCs and a method for operating the system to provide simple yet robust and reliable time reference synchronization of the sampling of the one or more ADCs. The ADC(s) in the system use a master clock, which may be referred to as a shared master clock. In some examples, the ADC system comprises two or more ADCs, and all ADCs within the system use the same physical master clock. In other examples, the ADC system may comprise two or more ADCs that are geographically separated. In this example, the two or more ADCs do not physically share a master clock but share a synchronized version of the master clock.In both of the above examples, regardless of whether the master clock is physically the same master clock or the synchronized version of the master clock, the master clock is shared by every ADC in the ADC system.

[0026] The inventors have discovered that by stopping and starting the master clock, pausing the sampling of one or more ADCs in between, the resumption of sampling by one or more ADCs can be synchronized with respect to a time reference. The one or more ADCs are synchronized with a time reference because the internal ADC filter reset is synchronized with the restarted master clock. Thus, the resumption of sampling by one or more ADCs is time-reference synchronized. In particular, when sampling by one or more ADCs resumes in response to the reset of the internal filters of each ADC, not only is each ADC synchronized with the master clock, but they are also synchronized with each other.

[0027] In some cases, the ADC uses a synchronization output signal and a synchronization input signal. The synchronization output signal can be synchronous with the shared master clock. The system is then operated by stopping the master clock. When the master clock is stopped, the ADC detects a synchronization event. Detection of the synchronization event can occur either by receiving a command from the processor indicating that synchronization is requested, or by detecting, via an internal clock of the ADC, that the master clock has stopped. This does not result in a response from the ADC, as the master clock is stopped. The master clock is then restarted after the synchronization event is detected. This causes an internal filter (within the ADC) to reset.The internal filter can be reset by the ADC following the detection of a synchronization event. It should be noted that the ADC's internal filter can refer to an internal digital filter. Thus, the internal filter can process the ADC's samples or outputs. One could also say that the state of the internal filter can be reset, for example, the current count value of the internal filter is reset. In response to the filter being reset, the ADC restarts sampling. This enables time-based synchronization of the ADC using only a single master clock signal, no isolation components, and reduced additional signal connections. This means that the system described in this disclosure has reduced hardware requirements, a reduced footprint, reduced component and construction costs, and so on.The system of the present disclosure also exhibits improved reliability of the ADC sampling by providing a time-related synchronization capability by being robust against sample / edge timing ambiguity, thereby reducing the risk of phase error at the outputs of the ADC.

[0028] Furthermore, resetting the internal filter can be described as comprising a first state change of the internal filter at a time synchronized with the master clock, and a second state change of the internal filter at a time synchronized with the master clock, where the first state change can be opposite to the second state change, and where the second state change can occur after a fixed number of master clock cycles following the first state change. In this scenario, resuming ADC sampling can involve resuming sampling in response to the second state change of the ADC's internal filter.

[0029] In other cases, the present disclosure provides a multiple ADC system, wherein the multiple ADC system is arranged such that all ADCs of the system share a master clock. Again, time-related synchronization of the ADCs is achieved using only a single master clock signal by restarting the sampling of the ADCs in response to the reset of the internal filters of each of the ADCs.

[0030] The internal ADC filter can be a digital filter integrated within the ADC. It is used to remove / suppress unwanted signals from a specific frequency spectrum. The decimation process, similar to averaging multiple input samples to generate an output data element, is also achieved through the internal filter. The internal filter is an inherent part of the ADC and can be an oversampling ADC. For example, an ADC with an internal filter for performing decimation of 8 takes all 8 input samples, averages them, and produces a single output. If the ADC system includes two ADCs monitoring the same input signal without synchronization, the first ADC can average samples 1, 2, 3, 4, 5, 6, 7, and 8 to produce one sample, and the other ADC can average samples 5, 6, 7, 8, 9, 10, 11, and 12 to produce one sample.Both ADCs generate the output at the same rate, but the output differs due to a mismatch in the input signal phase. The synchronization process described in this disclosure essentially resets the internal ADC filters of the two ADCs. Thus, the internal ADC filters in both ADCs ensure that the resumption of sampling by each ADC is synchronized.

[0031] In conjunction with the ADC system and the multiple ADC system, this disclosure provides a method for operating the ADC systems. The method involves a processor stopping the master clock (MCLK) to the ADCs to halt sampling, and then detecting a synchronization event. Next, the method restarts the ADC's master clock. Upon restarting the master clock, the ADC(s) responds to the synchronization event by resetting an internal filter and, in response, restarting ADC sampling. Therefore, the sampling of the ADC or multiple ADCs is synchronized according to a time reference.

[0032] In some examples, the ADC system is connected to and controlled by a field-programmable gate array (FPGA). In the present disclosure, the method for operating the ADC system can use the FPGA to issue an instruction to stop the master clock. The FPGA then initiates the synchronization of the ADC(s) by providing a stimulus to the ADC(s), which the ADC(s) would detect as a synchronization event. The FPGA then issues an instruction to restart the master clock. In some scenarios, the FPGA can monitor the output of the ADC(s) to determine whether new output data is ready and, therefore, whether the sampling of the ADC(s) is synchronous with respect to a time reference.

[0033] In other examples, the ADC system is connected to and controlled by a microcontroller unit (MCU). In the present disclosure, the method for operating the ADC system can use the MCU to issue an instruction to stop the master clock. The MCU then initiates the synchronization of the ADC(s) by providing a stimulus to the ADC(s), which the ADC(s) would detect as a synchronization event. The MCU then issues an instruction to restart the master clock. In some scenarios, the MCU can then monitor the output of the synchronized ADCs to determine whether new output data is ready and, therefore, whether the sampling of the ADC(s) is synchronous with respect to a time reference.

[0034] The present revelation will now be discussed in more detail with regard to the associated figures.

[0035] Fig. Figure 1 shows an exemplary schematic diagram of a multiple ADC system 1. This system provides an example of a system for synchronizing multiple ADCs. The multiple ADC system 1 comprises a first ADC 10, a second ADC 12, and a master clock (MCLK) 14. The synchronization input signals of the first ADC 10 and the second ADC 12 are coupled to ensure that the first ADC 10 and the second ADC 12 have a shared synchronization signal (SYNC) 16. Based on Fig. It is also evident from Figure 1 that the multiple ADC system further comprises that each ADC includes an input pin and a data ready output (DRDY).

[0036] More precisely, it can be seen that the master clock 14 is coupled to an input of both the first ADC 10 and the second ADC 12. Thus, it is evident that the first ADC 10 and the second ADC 12 share a common master clock 14 signal. Furthermore, as discussed above, the synchronization input signals of the first ADC 10 and the second ADC 12 are coupled together, so they also share a common SYNC 16.

[0037] In this example, the first ADC 10 and the second ADC 12 sample the input pin multiple times to generate a data output at the DRDY output. Because of the shared master clock 14, the first ADC 10 and the second ADC 12 sample their respective input pins simultaneously, but they may not generate the DRDY output at the same time. This can lead to a synchronization problem between the two ADCs and result in a phase error in the measurement.

[0038] This can be seen in relation to the associated exemplary time diagram 2 of Fig. 2 will be described in more detail.

[0039] Fig. Figure 2 shows that the shared master clock 14 (as in Fig. (as seen in Figure 1) runs at a constant frequency. The figure further shows the DRDY output as a function of time for device 1 and device 2, i.e., the DRDY output of the first ADC 10 and the second ADC 12. Finally, the figure shows the shared SYNC 16 (as seen in Figure 1). Fig. (1 seen) as a function of time. It can be seen that SYNC 16 can be used to synchronize sampling between multiple ADCs. This is shown by the fact that SYNC 16 is initiated at initiation point 22, which in turn causes a synchronized DRDY output 24 at both the first ADC 10 and the second ADC 12 (i.e., device 1 and device 2).

[0040] For this to occur, SYNC 16 must be synchronized with the master clock 14; that is, the falling edge of SYNC 16 must be aligned with a falling edge of the master clock 14. In this respect, the master clock 14 drives on the falling edge and samples on the rising edge. Since the first ADC 10 and the second ADC 12 use the master clock 14 to sample the SYNC 16 signal, sampling SYNC 16, when synchronized with the master clock 14 signal, always yields the same result from a timing perspective.

[0041] This synchronization system encounters a problem, however, when SYNC 16 loses synchronization with master clock 14, i.e., when SYNC 16 becomes asynchronous to master clock 14. The edge timing of SYNC 16 can be ambiguous. This occurs because SYNC 16 cannot transition directly from high to low. Therefore, this creates an instance of ambiguity between SYNC 16 and the sampling timing of the master clock 14 signal. Consequently, one ADC might detect SYNC 16, while another ADC might not. As a result, the ADC that detected SYNC 16 would output at the DRDY output before the other ADC that did not. It would be expected that there would be a phase shift of one period of the master clock 14 between the ADCs. This can also be considered a phase error.

[0042] In other words, if SYNC 16 is asynchronous to the master clock 14, sampling SYNC 16 can lead to timing ambiguity between two ADCs. This occurs when the SYNC pulse edge lands close to the master clock sampling edge, for example, one ADC registers SYNC 16 while the other does not. This can result in a phase shift of one period of the master clock 14 between the two ADCs.

[0043] Therefore, there is a need to provide a system and a method for synchronizing one or more ADCs with a time reference in order to develop a more robust and reliable ADC system. Specifically, there is a need to provide a system and a method for synchronizing one or more ADCs with a time reference point so that it is more robust and reliable in providing synchronized outputs after ADC sampling by reducing or preventing phase errors at the ADC outputs.

[0044] Fig. Figure 3 shows an exemplary schematic diagram of a channel-isolated DAQ system 3 according to one approach. The channel-isolated DAQ system 3 comprises several ADCs 30a-30d, each of which has a corresponding isolator (ISO) 32 and an FPGA 34. The channel-isolated DAQ system 3 is arranged such that the ADCs 30a-30d are isolated from the FPGA 34 by their associated isolator 32.

[0045] In channel-isolated DAQ systems like that of Fig. Step 3 requires that the synchronization of the ADC on each channel necessitates both the master clock and the SYNC signal being transmitted across the isolation on high-speed isolation channels for each ADC channel. This results in increased power consumption, system complexity, the likelihood of failure points within the system, and higher costs associated with synchronization.

[0046] A similar example also uses network-distributed DAQ systems. In network-distributed DAQ systems, synchronizing ADCs requires the system to generate both the master clock and the SYNC with precise timing (this can be achieved using precision timing protocols such as IEC 1588). However, this increases the resource requirements for the network controller, as not all network controllers have two timers; for example, ADIN1110 MACPHY for 10baseT1L only has one TS_TIMER.

[0047] Therefore, there is a further need for a system and method for the time-related synchronization of one or more ADCs, which exhibit low system complexity, low system costs, low power consumption, etc., while ensuring robust and reliable synchronization of ADC outputs.

[0048] The present disclosure aims to provide solutions to the aforementioned problem. The solutions according to the present disclosure will now be discussed in relation to Fig. 4-14 discussed.

[0049] Fig. Figure 4a shows an exemplary schematic diagram of an ADC system 4a. The ADC system 4a comprises an ADC, a clock source 40, and a processor 47. The processor 47 is communicatively coupled to the clock source 40. The clock source 40 is coupled to the master clock (MCLK) 41 of the ADC. The processor 47 is coupled to the host interface 43 of the ADC. The ADC also includes a synchronization output signal (SYNC_OUT) 42 and a synchronization input signal (SYNC_IN) 44, which in this non-restrictive example are coupled such that the synchronization output signal supplies the signal to the synchronization input signal 44. In other examples, however, the synchronization output signal 42 may be coupled to the synchronization input signal 44 within the ADC circuit arrangement, as in relation to Fig. 4b is discussed.

[0050] In this example, the synchronization output signal 42 is a mechanism or pin present in many ADC systems 4a. In this respect, the ADC system 4a can generate a signal from the synchronization output signal 42 that is synchronous with the master clock 40. Due to the internal arrangement of the ADC 4a, the synchronization output signal 42 can be triggered in many ways, for example, by an asynchronous digital input or by an SPI instruction, etc. Therefore, the synchronization output signal 42 can be coupled to the synchronization input signal 44 via coupling 46 to synchronize the ADC 4a. This feature is typically used to synchronize multiple ADCs; that is, the multiple ADCs would have a shared master clock, and one ADC would generate the synchronization output signal, which is coupled to the synchronization input signal of all the other ADCs.This system ensures that the synchronization input signal and the master clock are synchronized, but it typically cannot achieve precision timing synchronized due to the lack of timing control of the triggering signal / command, especially when controlled by an MCU-based host device or the like.

[0051] Therefore, the present disclosure provides a method for operating an ADC system, which may include a single ADC or multiple ADCs, to achieve precision time synchronization. This operating method is discussed in more detail below.

[0052] Fig. Figure 4b shows another exemplary schematic diagram of an ADC system 4b. The ADC system 4b comprises an ADC, a clock source 40, and a processor 47. The processor 47 is communicatively coupled to the clock source 40. The clock source 40 is coupled to the master clock (MCLK) 41 of the ADC. The processor 47 is coupled to the host interface 43 of the ADC. The main difference between the ADC system 4b in Fig. 4b and the ADC system 4a in Fig. 4a is the absence of the synchronization output signal pin 42 and the synchronization input signal pin 43. This is the case, as discussed above, because in the ADC system 4b in Fig. 4b the corresponding synchronization output signal is internally coupled to the synchronization input signal within the ADC circuit arrangement. Therefore, despite the absence of external synchronization input / output signal pins, ADC system 4b has the same functionality with respect to the synchronization signals as ADC system 4a.

[0053] Fig. Figure 5 presents another exemplary schematic diagram of an ADC system 5 for synchronizing one or more ADCs using an FPGA 50. It can be seen that the system 5 comprises an FPGA 50, an isolator 52, and an ADC 54. The ADC 54 can be an oversampling (OS) ADC. The FPGA 50 includes a first IO pin 502, a second IO pin 504, and an SPI pin 506. The isolator 52 includes a first channel (CH0) 522, a second channel (CH1) 524, and a third channel (CH_SPI) 526. The ADC 54 includes a master clock 541, a synchronization input signal (SYNC_IN) 542, a synchronization output signal (SYNC_OUT) 543, a DRDY pin 544, and an SPI pin 545.

[0054] The first I / O pin 502 of FPGA 50 is connected to the first channel (CH0) 522 of isolator 52. The first channel (CH0) 522 of isolator 52 is, in turn, connected to the master clock 541 of ADC 54. Therefore, the first I / O pin 502 of FPGA 50 can send an instruction via the first channel (CH0) 522 of isolator 52 to the master clock 541 of ADC 54. The instruction from FPGA 50 can be to stop or restart the master clock 541 of ADC 54. FPGA 50 restarts the master clock 541 with precisely controlled timing.

[0055] The second I / O pin 504 of FPGA 50 is connected to the second channel (CH1) 524 of isolator 52. The second channel (CH1) 524 of isolator 52 is, in turn, connected to the DRDY pin 544 of ADC 54. Thus, an output signal from DRDY pin 544 of ADC 54 is fed into the second channel (CH1) 524 of isolator 52 and then to the second I / O pin 504 of FPGA 50. FPGA 50 uses the connection to DRDY pin 544 of ADC 54 to monitor the DRDY signal from ADC 54 in order to determine when new output data is ready.

[0056] SPI pin 506 of FPGA 50 is connected to the third channel (CH_SPI) 526 of isolator 52. The third channel (CH_SPI) 526 of isolator 52 is connected to SPI pin 545 of ADC 54. SPI pin 506 of FPGA 50, the third channel (CH_SPI) 526 of isolator 52, and SPI pin 545 of ADC all have bidirectional communication. Therefore, FPGA 50 can send SPI instructions or commands to ADC 54. This allows FPGA 50 to control the initiation of the synchronization process of ADC 54. Likewise, ADC 54 can send SPI data back to FPGA 50.

[0057] Therefore, one or more of the following steps (the numbered steps 1-4 refer to points 1-4 of Fig. 5) used to synchronize two or more ADCs 54 using the FPGA 50: 1. The first IO pin 502 of the FPGA 50 is used to send a signal to the master clock pin 541 of the ADC 54 (via the first channel (CHO) 522 of the isolator 52) to stop the output of the master clock 541; 2. The SPI pin 506 of the FPGA 50 is used to send an SPI instruction to the SPI pin 545 of the ADC 54 (via the third channel (CH_SPI) 526 of the isolator 52) to trigger the synchronization of the ADC 54; 3. The first IO pin 502 of the FPGA 50 is used to send a signal to the master clock pin 541 of the ADC 54 (via the first channel (CHO) 522 of the isolator 52) to restart the output of the master clock 541; 4. The second IO pin 504 of the FPGA 50 is used to monitor the signal DRDY 544 from the ADC 54 (via the second channel (CH1) 524 of the isolator 52) to determine when new output data is ready and that the ADCs are sampling synchronously.

[0058] Fig. Figure 6 presents an exemplary schematic diagram of a system 6 for synchronizing multiple ADCs using an MCU 60. It shows that the system 6 comprises an MCU 60, a MAC+PHY device 62, and an ADC 64. The ADC 64 can be an oversampling (OS) ADC. The MCU 60 includes software and hardware components. The software elements include an ADC driver 601, a PTP stack 602, a network stack 603, and a PHY driver 604. The hardware elements include an IO pin 605. The MAC+PHY device 62 contains hardware elements such as a timer (TS_TIMER) 622. The ADC 62 includes hardware elements such as a master clock 642, a synchronization input signal (SYNC_IN) 644, a synchronization output signal (SYNC_OUT) 646, and a DRDY pin 648.

[0059] In the example of Fig. The PHY driver 604 of MCU 60 is connected to the MAC+PHY device 62 in such a way that SPI instructions (or the like) can be communicated. The timer (TS_TIMER) 622 of the MAC+PHY device 62 is connected to the master clock 642 of ADC 64. The synchronization input signal 644 of ADC 64 is coupled to the synchronization output signal 646 of ADC 64, as mentioned previously. The DRDY pin 648 of ADC 64 is connected to the IO pin 605 of MCU 60. The ADC driver 601 of MCU 60 is also connected to ADC 64 in such a way that SPI instructions (or the like) can be communicated.

[0060] Therefore, one or more of the following steps (the numbered steps 1-4 refer to points 1-4 of Fig. 6) used to synchronize two or more ADCs 64 using the MCU 60: 1. The PHY driver 604 of the MCU 60 is used to instruct (via an SPI command or the like) the MAC+PHY device 62 to use the timer 622 to stop the master clock 642 of the ADC 64; 2. The ADC driver 601 of the MCU 60 is used to send an SPI instruction (or the like) to the ADC 64 to initiate a synchronization of the ADCs 64; 3. The PHY driver 604 of the MCU 60 is used to instruct (via an SPI instruction or the like) the MAC+PHY device 62 to use the timer 622 to restart the master clock 642 of the ADC 64 with precise timing. Precise timing can be achieved by using a standard or protocol, for example, the IEEE 1588 Precision Time Protocol. 4. The IO pin 605 of the MCU 60 is used to monitor a change in the DRDY pin 648 of the ADC 64 to determine when new output data is ready and that the ADCs are sampling synchronously.

[0061] Although Fig. While the operation described in Section 6 refers to a MAC+PHY device 62, it should be noted that the same operation could be achieved with alternative device arrangements. As another example, the operation can be achieved by integrating the MAC within the MCU with suitable timestamping and clock synchronization support. In yet another example, the operation can be achieved by using a multiport Ethernet switch (instead of the MAC+PHY device 62), where the multiport Ethernet switch includes the same timestamping and clock synchronization support. In both examples, the PHY(s) can be integrated into the MCU+MAC arrangement or into the multiport Ethernet switch.

[0062] Time diagram 7 of Fig. 7 corresponds to the ADC system 4a of Fig. 4a. The timing diagram 7 includes a master clock 70 signal, a synchronization output signal & synchronization input signal 71 (this corresponds to the synchronization output signal 42 and the synchronization input signal 44 of Fig. 4a), an interface between the processor and the ADC 72 (which is the host interface 43 in Fig. 4a / 4b corresponds), an internal ADC syn-latch or internal ADC latch 76 and an internal ADC filter reset 77.

[0063] Timing diagram 7 shows that the master clock 70 is switched off at point 73. Thus, the master clock 70 is switched off for the ADC or any associated ADCs. Switching off the master clock 70 does not cause any problems for standard ADC operation. During the time that the master clock 70 is switched off, a synchronization event, in this example a trigger command, is received at interface 72 (e.g., an SPI instruction command) to trigger the synchronization output signal 71 (and the synchronization input signal, since the synchronization output signal and the synchronization input signal are coupled). The signal at interface 72 to trigger the synchronization output signal 71 can be asynchronous to the master clock 70 and can be registered by the ADC even when the master clock 70 is not running.At the ADC(s), the synchronization output signal and the synchronization input signal 71 are both controlled by the ADC's internal logic, which in turn is controlled by the master clock 70. Therefore, the synchronization output signal 71 is not triggered when the synchronization event is received at interface 72 if the master clock 70 is off. Thus, at point 74, the master clock 70 is switched back on. During the off period of the master clock 70, the internal ADC latch 76 switches in response to the received synchronization event. When the master clock 70 resumes, the internal ADC latch 76 switches back, and the synchronization output signal 710 is then triggered. The triggering of the synchronization output signal 71 occurs at point 75.Since the ADC(s) within the system use the master clock 70 signal, the internal ADC filter reset is triggered synchronously with master clock 70 at a time after master clock 74 has restarted and after the synchronization output signal 75 has been triggered. In response to the reset of the internal ADC filter 77, the time-synchronized restart of the ADC(s) occurs at a deterministic time after the restart of master clock 70 and the reset of the internal ADC filter 77. By stopping and restarting master clock 70 with precise start timing in combination with the synchronization output signal / synchronization input signal mechanism, precise sampling synchronization relative to a reference time is achieved with only a single master clock 70 signal.

[0064] In this example, the accuracy of synchronizing one or more ADCs depends on restarting the master clock at a precisely controlled time. To ensure that the master clock 70 is restarted with precision start timing, a Precision Time Protocol (PTP) can be used. A PTP can be used to synchronize clocks in an electronic system, a computer network, or similar; particularly in networks and systems, PTP can be used to achieve highly reliable clock accuracy. This clock accuracy can, in many cases, be in the range of less than microseconds, making it suitable for a wide variety of applications. Numerous PTP standards have been published and continue to be developed. Furthermore, there are many methods for achieving precise controlled start timing of a master clock, such as IEEE 1588, which can be used.

[0065] In other words, one approach to precise timing involves ensuring that synchronous network systems align themselves around a repeating boundary. For example, ADC sampling can be initiated at a second boundary or at periods of any multiple of 32 microseconds since midnight on December 31, 1970, and so on. In this way, the ADCs all operate within a period smaller than specified (32 microseconds, or as applicable), effectively synchronizing them. Thus, a device can recover from a failure and then resume synchronous operation without shutting down the entire system.

[0066] The synchronization output signal and the synchronization input signal can be referenced to pins of the ADCs, or they can be referenced to the synchronization output / synchronization input signal from the ADCs. Since the ADCs can be arranged such that the synchronization output signal is coupled to the synchronization input signal pin, the synchronization signal generation logic can be implemented within the ADC. This ensures that the shared master clock guarantees that the output signal is synchronous with the shared master clock, thus creating synchronous ADCs. The generation logic behavior of the ADC is similar to that of a D flip-flop in that the input change is asynchronous to the master clock, while the output is synchronous with the master clock. As discussed previously, the synchronization output signal and the synchronization input signal can be coupled to external pins of the ADC or within the ADC's internal circuitry.

[0067] While the above description discusses the synchronization event, which is likely an SPI instruction on processor / ADC interface 72, other instruction types can be used. For example, the synchronization event could be an instruction transmitted to processor / ADC interface 72 via a pin switch. In this scenario, the instruction can be synchronous or asynchronous with the shared master clock and may not be required at a predetermined time.

[0068] It should be noted that the master clock (MCLK) 70 can be restarted at a predetermined time, and the predetermined time can correspond to the rising edge.

[0069] Furthermore, the procedure can, as in relation to Fig. As discussed in section 7, this also requires the system to monitor the synchronized restart of the ADC sampling. This may require monitoring of the synchronization output signal 71 or the DRDY pin (as discussed in relation to...). Fig. (discussed in sections 5-6) to ensure that all ADCs within the system sample synchronously with respect to a time reference.

[0070] The above-mentioned method for synchronizing one or more ADCs is performed by a computer-implemented system. The system may include at least one processor and at least one computer-readable storage medium that stores computer-readable instructions which, when executed by the processor, cause the processor to perform the procedures discussed in the examples explained in this disclosure.

[0071] The aforementioned procedure, as in relation to Fig. Disclosed in Section 7, this disclosure provides a method for synchronizing one or more ADCs using only a single master clock signal and optionally only one additional processor signal, which can be referred to as the synchronization signal. This differs from existing synchronization systems, which often require multiple clock signals and multiple additional synchronization signals and components. Thus, the systems and methods in this disclosure provide a time-reference synchronization system for ADCs with reduced complexity, reduced hardware components, reduced footprint, reduced hardware costs, and so on.

[0072] Fig. 8 refers to another example timing diagram 8 for operating an ADC system. Example timing diagram 8 refers to the ADC system 4b, as shown in Fig. 4b shown, since the synchronization output / input signals are coupled together in the internal circuit arrangement of the ADC.

[0073] The timing diagram 8 includes a master clock 80 signal, an interface between the processor and the ADC 82 (which is the host interface 43 in Fig. 4b), an internal ADC syn-latch or internal ADC latch 86 and an internal ADC filter reset 87.

[0074] Timing diagram 8 shows that the master clock 80 is switched off at point 83. Thus, the master clock 80 is switched off for the ADC or all associated ADCs. Switching off the master clock 80 does not cause any problems for standard ADC operation. During the time that the master clock 80 is switched off, a synchronization event, in this example a trigger command, is received at interface 82 (e.g., an SPI instruction). In timing diagram 7, this step triggered the output at the synchronization output signal (coupled with the synchronization input signal); however, in this example, the synchronization output / input signals are internally coupled. Nevertheless, because the master clock 80 is switched off, the ADC(s) do not respond to the synchronization event. B. the ADC does not respond to the trigger command, except that the internal ADC latch 86 switches.During the off-period of the master clock 80, the internal ADC latch 86 switches in response to the received synchronization event. Upon resumption of the master clock 80, the internal ADC latch 86 switches back, and the internal ADC filter 87 is reset at a deterministic time after the master clock restarts. In response to the reset of the internal ADC filter 87, the ADC(s) restart sampling at a deterministic time after the restart of the master clock 80 and the reset of the internal ADC filter 87. If the master clock 80 is stopped and restarted with precise start timing in combination with the internal synchronization output signal / synchronization input signal mechanism, precision sampling synchronization relative to a reference time is achieved with only a single master clock 80 signal.

[0075] As mentioned earlier, the accuracy of synchronizing one or more ADCs depends on restarting the master clock at a precisely controlled time. In practice, the MAC+PHY device (or an equivalent) can have an internal frequency- and value-matched clock that matches the timing of the master clock (IEEE 1588). It can then include logic to generate one or more external signals based on this clock, in this case, the master clock fed to the ADCs. A "start-time register" can then be installed, with the processor setting a value corresponding to an agreed-upon time in the future. When the synchronized clock in the MAC+PHY matches this start-time register value, it can begin driving the master clock output signal to the ADC.Thus, all synchronized ADCs use the same start time to begin master clock operation, resulting in synchronous generation of the ADC output.

[0076] Fig. 9 refers to another example timing diagram 9 for operating an ADC system. Example timing diagram 9 refers to the ADC system 4a, as shown in Fig. 4a shown, since the ADC system 4a includes coupled external synchronization input / output signal pins.

[0077] The timing diagram 9 includes a master clock 90 signal, a synchronization output signal & synchronization input signal 91 (this corresponds to the synchronization output signal 42 and the synchronization input signal 44 of Fig. 4a), an internal ADC synchro latch or internal ADC latch 96 and an internal ADC filter reset 97. Therefore, it can be seen that the main difference between the example timing diagram 9 and the example timing diagrams 7 / 8 is that the processor / host interface for receiving a synchronization event or instruction is not present. The ADC and the processor are still coupled via an ADC interface, but in this example, this interface is not used to receive the synchronization event or an instruction associated with the synchronization event.

[0078] Instead, the ADC automatically detects the synchronization event by detecting that the master clock has stopped. Thus, it can be said that in terms of Fig. Example 9 describes how automatic synchronization is performed every time the ADC (or multiple ADCs) detects a standstill in the master clock.

[0079] Therefore, in this example, the ADC system 4a operates as follows, according to the timing diagram 9.

[0080] Timing diagram 9 shows that the master clock 90 is switched off at point 93. Thus, the master clock 90 is switched off for the ADC or all associated ADCs. Switching off the master clock 90 does not cause any problems for standard ADC operation. The ADC continuously monitors its operation to ensure that the master clock 90 is still functioning in conjunction with the ADC. This is achieved by cyclically polling the master clock pin on the ADC. When the ADC detects that the master clock 90 has stopped, for example, at point 93, the ADC interprets this as an indication that a synchronization event has occurred. The ADC then triggers the synchronization output signal 91 (and the synchronization input signal, since the synchronization output and input signals are coupled).At the ADC(s), the synchronization output signal and the synchronization input signal 91 are both controlled by the ADC's internal logic, which in turn is controlled by the master clock 90. ​​Therefore, the synchronization output signal 91 does not trigger when the synchronization event is detected (by switching off the master clock 90), because the master clock 90 is switched off. During the off period of the master clock 90, the internal ADC latch 96 switches in response to the detection of the synchronization event. Thus, at point 94, the master clock 90 is switched back on. When the master clock 90 resumes operation, the internal ADC latch 96 switches back, and the synchronization output signal 91 is then triggered. The triggering of the synchronization output signal 91 occurs at point 95.Since the ADC(s) within the system use the master clock 90 signal, the internal ADC filter 97 is reset at a deterministic time after the restart of the master clock 90 and the triggering of the synchronization output signal 95. The synchronized restart of the sampling of the ADC(s) occurs at a deterministic time after the restart of the master clock 90, the reset of the synchronization output signal 95, and the reset of the internal ADC filter 97. If the master clock 90 is stopped and restarted with precise start timing in combination with the synchronization output signal / synchronization input signal mechanism, precision sampling synchronization relative to a reference time is achieved with only one master clock 90 signal.

[0081] Fig. 10 refers to another example timing diagram 10 for operating an ADC system. Example timing diagram 10 refers to the ADC system 4b, as shown in Fig. 4b shown, since the ADC system 4b includes synchronization input / output signals that are coupled internally within the ADC.

[0082] Timing diagram 10 includes a master clock 100 signal, an internal ADC sync latch or internal ADC latch 106, and an internal ADC filter reset 107. Therefore, it can be seen that the main difference between example timing diagram 10 and example timing diagrams 7 / 8 is that the processor / host interface for receiving a synchronization event or instruction is not present, similar to timing diagram 9. The ADC and the processor are still coupled via an ADC interface, but in this example, this interface is not used to receive the synchronization event or an instruction associated with the synchronization event. Instead, the ADC automatically detects the synchronization event by detecting that the master clock has stopped. Thus, it can be said that, with respect to Fig. The 10 described example performs an automatic synchronization every time the ADC (or multiple ADCs) detects a standstill in the master clock.

[0083] The exemplary timing diagram 10 differs from that of the exemplary timing diagram 9 in that there are no externally coupled synchronization input / output signal pins.

[0084] Therefore, in this example, the ADC system 4b operates as follows, according to the timing diagram 10.

[0085] Timing diagram 10 shows that master clock 100 is switched off at point 103. Thus, master clock 100 is switched off for the ADC or all associated ADCs. Switching off master clock 100 does not cause any problems for standard ADC operation. The ADC continuously monitors its operation to ensure that master clock 100 continues to function in conjunction with the ADC. This is achieved by cyclically polling the master clock pin on the ADC. When the ADC detects a stop of master clock 100, for example, at point 103, the ADC interprets this as an indication that a synchronization event has occurred. Therefore, the ADC does not restart sampling when the synchronization event is detected (by switching off master clock 100) because master clock 100 is switched off.During the off-period of master clock 100, the internal ADC latch 106 switches in response to the detection of the synchronization event. Thus, at point 104, master clock 100 is switched back on. When master clock 100 resumes, the internal ADC latch 106 switches back on, and at a deterministic time thereafter, the internal ADC filter 97 is reset. Since the ADC(s) within the system use the master clock 90 signal, the synchronized restart of the ADC(s) sampling occurs at a deterministic time after the restart of the master clock 100 and the reset of the internal ADC filter 107. If the master clock 100 is stopped and restarted with precise start timing in combination with the internal synchronization output signal / synchronization input signal mechanism, precision sampling synchronization relative to a reference time is achieved with only one master clock 100 signal.

[0086] Fig. Figure 11 shows an example flowchart 11 for operating an ADC system. In particular, flowchart 11 serves to operate an ADC system, such as ADC system 4a (in Fig. 4a), in conjunction with the time diagram 7 (in Fig. 7 shown). The flowchart 11 for operating an ADC system comprising one or more ADCs may consist of one or more of the following steps.

[0087] In s110, the ADC is continuously sampling; for example, the ADC is running normally and performing its usual operation. The master clock associated with the ADC is then switched off by a processor. Next, in s111, the ADC stops its normal operation; for example, the ADC stops sampling due to the master clock being switched off. During the master clock off time, s112 occurs, in which the ADC registers or detects a synchronization event or a synchronization command. For example, the synchronization event or synchronization event could be related to an SPI command from an external processor or a trigger by switching an ADC pin, such as the ADC / processor interface pin. Subsequently, the processor resumes sending the master clock signal to the ADC. The restart of the master clock occurs with precisely controlled start timing, as discussed previously.Next, at s113, the ADC generates a synchronization output signal that is synchronous with the master clock. This synchronization output signal is generated after a fixed number of master clock cycles following the restart of the master clock. At s114, the ADC registers the synchronization output signal against the synchronization input signal (since the synchronization output and input signals are coupled) in the next master clock cycle. At s115, the ADC resets its internal filter after a fixed number of master clock cycles following the receipt of the synchronization input signal. At s116, the ADC resumes continuous sampling, such as normal operation. The ADC sampling restart occurs at the same time as the restart of the master clock plus a fixed number of master clock cycles in response to the internal filter being reset in s115.

[0088] Fig. Figure 12 shows an example flowchart 12 for operating an ADC system. In particular, flowchart 12 serves to operate an ADC system, such as ADC system 4b (in Fig. 4b), in conjunction with the time diagram 8 (in Fig. (shown in Figure 8). The flowchart 12 for operating an ADC system comprising one or more ADCs may consist of one or more of the following steps.

[0089] In s120, the ADC is continuously sampling; for example, the ADC is running normally and performing its usual operation. The master clock connected to the ADC is then switched off by a processor. Next, in s122, the ADC stops its normal operation; for example, the ADC stops sampling due to the master clock being switched off. During the master clock off time, s124 occurs, in which the ADC registers or detects a synchronization event or a synchronization command. For example, the synchronization event or command could be an SPI command from an external processor or a trigger by switching an ADC pin, such as the ADC / processor interface pin. Subsequently, the processor resumes the master clock to the ADC. The restart of the master clock occurs with precisely controlled start timing, as discussed previously.In s126, the ADC resets its internal filter block after a fixed number of master clock cycles following the receipt of the synchronization event or synchronization. This occurs because the internally coupled synchronization output and input signals override the operations of s113-s114. Fig. 11. Internally, the ADC restarts continuous sampling, e.g., normal operation, on page 128. This restart of ADC sampling occurs at the same time as the restart of the master clock plus a fixed number of master clock cycles, in response to the internal filter being reset on page 126.

[0090] Fig. Figure 13 shows an example flowchart 13 for operating an ADC system. In particular, flowchart 13 serves to operate an ADC system, such as ADC system 4a (in Fig. 4a), in conjunction with the time diagram 9 (in Fig. (shown in Figure 9). Flowchart 13 is used to operate an ADC system comprising one or more ADCs and may include one or more of the following steps.

[0091] In s130, the ADC is continuously sampling; for example, the ADC is running normally and performing its normal operation. The master clock connected to the ADC is then switched off by a processor. Next, in s131, the ADC stops its normal operation; for example, the ADC stops sampling due to the master clock being switched off. During the master clock switch-off time, s132 occurs, in which the ADC detects a synchronization event or a synchronization instruction. For example, the synchronization event might be related to the ADC detecting the stop of the master clock and automatically interpreting this as a synchronization event. The ADC can achieve this by continuously polling the master clock pin to ensure that the external master clock signal is still being received. Once the ADC detects the stopped master clock, it confirms that a synchronization event has been detected by latching the ADC's internal latch.The processor then resumes the master clock signal at the ADC. The master clock restart is performed with precisely controlled start timing, as previously discussed. Next, at s133, the ADC generates a synchronization output signal that is synchronous with the master clock. This synchronization output signal is generated after a fixed number of master clock cycles following the master clock restart. At s134, the ADC registers the synchronization output signal against the synchronization input signal (since the synchronization output and input signals are coupled) in the next master clock cycle. At s135, the ADC resets its internal filter block after a fixed number of master clock cycles following the receipt of the synchronization input signal. At s136, the ADC resumes continuous sampling, such as normal operation.The ADC sampling restart occurs at the same time as the restart of the master clock plus a fixed number of master clock cycles in response to the internal filter being reset in s135.

[0092] Fig. Figure 14 shows an example flowchart 14 for operating an ADC system. In particular, flowchart 14 serves to operate an ADC system, such as ADC system 4b (in Fig. 4b), in conjunction with the time diagram 10 (in Fig. (shown in Figure 10). Flowchart 14 is used to operate an ADC system comprising one or more ADCs and may include one or more of the following steps.

[0093] In s140, the ADC is continuously sampling; for example, the ADC is running normally and performing its normal operation. The master clock connected to the ADC is then switched off by a processor. Next, in s142, the ADC stops its normal operation; for example, the ADC stops sampling due to the master clock being switched off. During the master clock switch-off time, s144 occurs, in which the ADC detects a synchronization event or a synchronization instruction. For example, the synchronization event might be related to the ADC detecting the stop of the master clock and automatically interpreting this as a synchronization event. The ADC can achieve this by continuously polling the master clock pin to ensure that the external master clock signal is still being received. Once the ADC detects the stopped master clock, it confirms that a synchronization event has been detected by latching the ADC's internal latch.The processor then resumes the master clock signal to the ADC. The master clock restart occurs with precisely controlled start timing, as discussed previously. In page 146, the ADC resets its internal filter block after a fixed number of master clock cycles following the receipt of the synchronization event or synchronization. This occurs because the internally coupled synchronization output and input signals override the operations of pages 133-134. Fig. 13. Internally, the ADC restarts continuous sampling, e.g., normal operation, in s148. This restart of ADC sampling occurs at the same time as the restart of the master clock plus a fixed number of master clock cycles, in response to the internal filter being reset in s146.

[0094] As previously mentioned in relation to the present disclosure, i.e., the above-mentioned methods for performing a synchronization of two or more ADCs are carried out by a computer-implemented system.The system may include at least one processor and at least one computer-readable storage medium that stores computer-readable instructions which, when executed by the processor, cause the processor to perform at least the following: stopping the shared master clock, wherein the shared master clock is the master clock for the two or more ADCs to be synchronized; receiving an instruction to trigger a synchronization output signal of a first ADC of the two or more ADCs while the shared master clock is stopped, wherein the synchronization output signal is synchronous with the shared master clock; and restarting the shared master clock to synchronize the sampling of the two or more ADCs.

[0095] The above-mentioned systems for synchronizing two or more ADCs consist of: one or more processors, two or more ADCs, wherein the ADCs are configured such that a synchronization output signal of a first ADC is coupled to the associated synchronization input signal of all other ADCs, and wherein the two or more ADCs have a shared master clock and memory device and computer program code designed to perform a method according to the present disclosure with the processor.

[0096] This has the advantage of providing a system and a method that can ensure robust and reliable sampling synchronization in a multi-ADC system. A further advantage is the reduction of the possibility of phase error between ADCs within the system. Moreover, this approach offers the benefit of providing a system and a method with reduced complexity, reduced hardware requirements, fewer failure points, reduced costs, reduced hardware needs, etc., compared to existing systems and methods for synchronizing multiple ADCs.

[0097] Furthermore, the system and method enable the synchronization of multiple ADCs without the need for separate synchronization signals or isolation components. This leads to the aforementioned advantages, such as reduced system complexity, lower hardware costs, and limited potential failure points.

[0098] Unless the context clearly requires otherwise, throughout the description and claims the words “comprise”, “comprehensive”, “include”, “containing”, and the like are to be understood in an inclusive sense, as opposed to an exclusive or exhaustive sense, that is to say, “including but not limited to”.

[0099] The words "coupled," "connected," or "tied," as used generally herein, refer to two or more elements or nodes, which may be directly connected or linked by one or more intermediate elements. Furthermore, the words "here," "foreground," "following," and words of similar meaning, when used in this application, are intended to refer to this application as a whole and not to any particular part thereof. Where the context permits, words in the detailed description that use the singular or plural may also include the plural or singular, respectively. The word "or," when referring to a list of two or more entries, is intended to cover all of the following interpretations of the word: any of the list entries, all of the list entries, and any combination thereof.

[0100] It is understood that the above list is not exhaustive and that the method and system described here are applicable to many technical problem areas to which machine learning models can be applied.

[0101] The target audience recognizes that various modifications, whether by addition, replacement or deletion, provide further examples of the present disclosure, any and all of which are intended to be included by the attached claims. Numbered aspects

[0102] As a non-restrictive example, some aspects of the revelation are set forth in the following numbered paragraphs.

[0103] Numbered paragraph 1: A method for synchronizing an analog-to-digital converter (ADC), wherein the method comprises: Stopping, by a processor, a master clock signal to the ADC to pause the sampling of the ADC, wherein the master clock is supplied to the ADC by an external master clock; Detect, via the ADC, that a synchronization event has occurred while the master clock is stopped; Restarting the master clock signal to the ADC by the processor; Resetting, via the ADC, an internal filter at a time synchronized with the master clock; and Resumption of sampling by the ADC in response to the resetting of the ADC's internal filter.

[0104] Numbered paragraph 2a: The method according to numbered paragraph 1, wherein resetting an internal filter comprises holding the internal filter in a reset state until sampling has resumed. Preferably, the internal filter is held for a fixed number of master clock cycles after the master clock has restarted. Preferably, the resetting of the internal filter is performed by the ADC following the detection by the ADC that the synchronization event has occurred.

[0105] Numbered paragraph 2b: The method according to numbered paragraph 1, wherein resetting an internal filter comprises a first state change of the internal filter at a time synchronized with the master clock, and a second state change of the internal filter at a time synchronized with the master clock, wherein the first state change is opposite to the second state change, and wherein the second state change occurs after a fixed number of master clock cycles following the first state change. Preferably, the resetting of the internal filter is performed by the ADC following the detection by the ADC that the synchronization event has occurred.

[0106] Numbered paragraph 3: The procedure according to numbered paragraph 2b, wherein resuming sampling of the ADC includes resuming sampling in response to the second state change of the internal filter of the ADC.

[0107] Numbered paragraph 4: The method according to any of the preceding numbered paragraphs, wherein resuming ADC sampling comprises resuming sampling after a fixed number of master clock cycles following the restart of the master clock. The fixed number of master clock cycles for resuming ADC sampling after the restart of the master clock may be equal to or different from the fixed number of master clock cycles for holding the internal filter in a reset state after the restart of the master clock. Preferably, the internal filter may be held in a reset state for a fewer number of clock cycles than the number of master clock cycles for resuming ADC sampling after the restart of the master clock.

[0108] Numbered paragraph 5: The method according to any of the numbered paragraphs 1 to 4, wherein the detection, by the ADC, of ​​the synchronization event comprises receiving an instruction from the processor indicating that synchronization is requested, and latching a synchronization event trigger of the ADC.

[0109] Numbered paragraph 6: The method according to any of the numbered paragraphs 1 to 4, comprising detecting, by the ADC, the synchronization event, detecting, by an internal clock of the ADC, that the master clock has stopped, and latching a synchronization event trigger of the ADC.

[0110] Numbered paragraph 7: The method according to any of the preceding numbered paragraphs, wherein the restart, by the processor, of the master clock signal to the ADC comprises restarting the master clock signal at a precisely controlled time.

[0111] Numbered paragraph 8: The procedure according to any of the preceding numbered paragraphs, the procedure further comprising the following: Generating, by the ADC, a synchronization output signal at a synchronization output of the ADC, wherein the synchronization output signal is synchronous with the master clock.

[0112] Numbered paragraph 9: The procedure according to numbered paragraph 8, the procedure further comprising the following: Register, by the ADC, the synchronization output signal at a synchronization input of the ADC after a fixed number of master clock cycles.

[0113] Numbered paragraph 10: The method according to numbered paragraph 9, wherein the synchronization output and the synchronization input of the ADC are coupled via external pins of the ADC and wherein the method further comprises: Resetting the internal filter of the ADC after a fixed number of master clock cycles of registering the synchronization output signal at a synchronization input of the ADC.

[0114] Numbered paragraph 11: The method according to numbered paragraph 9, wherein the synchronization output and the synchronization input of the ADC are coupled via an internal logic circuit arrangement of the ADC.

[0115] Numbered paragraph 12: The method according to any of the preceding numbered paragraphs, wherein the resetting, by the ADC, of ​​an internal filter at a time synchronous with the master clock comprises resetting with respect to a time reference from the master clock. Preferably, the resetting of the internal filter by the ADC is performed following the detection by the ADC that the synchronization event has occurred.

[0116] Numbered paragraph 13: The procedure according to numbered paragraph 12, wherein the resumption, by the ADC, of ​​sampling in response to the resetting of the ADC's internal filter includes resumption with respect to the time reference.

[0117] Numbered paragraph 14: The method according to any of the preceding numbered paragraphs, wherein the method further includes monitoring by the processor that the sampling of the ADC is restarted synchronously with the master clock.

[0118] Numbered paragraph 15: The method according to any of the preceding numbered paragraphs, wherein the method of stopping the master clock, restarting the master clock and / or restarting the sampling of the ADC is performed by a field-programmable gate array, FPGA, or a processor, such as a microcontroller unit, MCU.

[0119] Numbered paragraph 16: A method for synchronizing two or more analog-to-digital converters, ADCs, wherein the method comprises: Stopping, by a processor, a shared master clock signal to two or more ADCs to pause the sampling of the two or more ADCs, wherein the shared master clock is supplied to the two or more ADCs by an external master clock; Detect, through each of the two or more ADCs, that a synchronization event has occurred while the shared master clock is stopped; Restarting, by the processor, of the shared master clock signal to each of the two or more ADCs; Reset, by each of the two or more ADCs, of an internal filter at a time synchronized with the master clock; and Resuming sampling, through the two or more ADCs, in response to the resetting of their respective internal filters.

[0120] Numbered paragraph 17a: The method according to numbered paragraph 16, wherein resetting an internal filter comprises holding the internal filter in a reset state until sampling has resumed. Preferably, the resetting of the internal filter is performed by the ADC following the detection by the ADC that the synchronization event has occurred.

[0121] Numbered paragraph 17b: The method according to numbered paragraph 16, wherein resetting an internal filter comprises a first state change of the internal filter at a time synchronized with the master clock, and a second state change of the internal filter at a time synchronized with the master clock, wherein the first state change is opposite to the second state change, and wherein the second state change occurs after a fixed number of master clock cycles following the first state change. Preferably, the resetting of the internal filter is performed by the ADC following the detection by the ADC that the synchronization event has occurred.

[0122] Numbered paragraph 18: The procedure according to numbered paragraph 17b, wherein resuming sampling of the two or more ADCs includes resuming sampling in response to the second state change of the internal filter of the two or more ADCs.

[0123] Numbered paragraph 19: The method according to any of the numbered paragraphs 16 to 18, wherein resuming sampling of the two or more ADCs includes resuming sampling after a fixed number of master clock cycles following the restart of the master clock.

[0124] Numbered paragraph 20: The method according to any of the numbered paragraphs 16 to 19, wherein the detection, by each of the two or more ADCs, of the synchronization event comprises receiving an instruction from the processor indicating that synchronization is requested.

[0125] Numbered paragraph 21: The method according to one of the numbered paragraphs 16 or 19, comprising detecting, by each of the two or more ADCs, the synchronization event; detecting, by an internal clock of the two or more ADCs, that the master clock has stopped; and latching a synchronization event trigger of the two or more ADCs.

[0126] Numbered paragraph 22: The method according to any of the numbered paragraphs 16 to 21, wherein the restart, by the processor, of the master clock signal to each of the two or more ADCs comprises restarting the master clock signal at a precisely controlled time.

[0127] Numbered paragraph 23: The procedure according to one of the numbered paragraphs 16 to 22, the procedure further comprising the following: Generating, by each of the two or more ADCs, a synchronization output signal at a synchronization output of each of the two or more ADCs, wherein the synchronization output signal is synchronous with the master clock.

[0128] Numbered paragraph 24: The procedure according to numbered paragraph 23, the procedure further comprising the following: Register, through each of the two or more ADCs, the synchronization output signal at a synchronization input of each of the two or more ADCs after a fixed number of master clock cycles.

[0129] Numbered paragraph 25: The method according to numbered paragraph 24, wherein the synchronization output and the synchronization input of each of the two or more ADCs are coupled via external pins of each of the two or more ADCs, and wherein the method further comprises: Resetting the internal filter of each of the two or more ADCs after a fixed number of master clock cycles of registering the synchronization output signal at a synchronization input of the two or more ADCs.

[0130] Numbered paragraph 26: The method according to numbered paragraph 24, wherein the synchronization output and the synchronization input of each of the two or more ADCs are coupled via an internal logic circuit arrangement of the ADC.

[0131] Numbered paragraph 27: The method according to any of the numbered paragraphs 16 to 27, wherein the resetting, by each of the two or more ADCs, of an internal filter at a time synchronous with the master clock comprises resetting with respect to a time reference from the master clock. Preferably, the resetting of the internal filter by the ADC is performed following the detection by the ADC that the synchronization event has occurred.

[0132] Numbered paragraph 28: The procedure according to numbered paragraph 27, wherein the resumption, by each of the two or more ADCs, of sampling in response to the resetting of the internal filter of each of the two or more ADCs comprises resuming with respect to the time reference.

[0133] Numbered paragraph 29: The method according to any of the numbered paragraphs 16 to 28, wherein the method further includes monitoring by the processor that the sampling of the two or more ADCs is restarted synchronously with the master clock.

[0134] Numbered paragraph 30: The method according to any of the numbered paragraphs 16 to 29, wherein the method of stopping the master clock, restarting the master clock and resuming sampling of the two or more ADCs is performed by a field-programmable gate array, FPGA, or a processor, such as a microcontroller unit, MCU.

[0135] Numbered paragraph 31: An analog-to-digital converter or ADC system, wherein the system comprises the following: an ADC that includes an internal filter; a master clock, where the master clock is located outside the ADC and coupled to it, and a processor, wherein the processor is located outside the ADC and the master clock and is coupled to it; and a memory and computer program code stored therein, wherein the computer program code, when executed by the processor, does the following: Stopping, by a processor, a master clock signal to the ADC to pause the sampling of the ADC, wherein the master clock is supplied to the ADC by the external master clock; Detect, via the ADC, that a synchronization event has occurred while the master clock is stopped; Restarting the master clock signal to the ADC by the processor; Resetting, via the ADC, the internal filter at a time synchronized with the master clock; and Resumption of sampling by the ADC in response to the resetting of the ADC's internal filter.

[0136] Numbered paragraph 32: The system according to numbered paragraph 31, wherein the ADC includes an instruction trigger interface for receiving an instruction from the processor indicating that the master clock has been stopped, and latching a synchronization event trigger of the two or more ADCs.

[0137] Numbered paragraph 33: The system according to numbered paragraph 31, wherein the ADC includes an internal clock for detecting the synchronization event and for latching a synchronization event trigger of the ADC.

[0138] Numbered paragraph 34: The system according to any of the numbered paragraphs 31 to 33, wherein the ADC comprises an external synchronization output signal pin and an external synchronization input signal pin, and the synchronization output signal pin is coupled to the synchronization input signal pin.

[0139] Numbered paragraph 35: The system according to any of the numbered paragraphs 31 to 34, wherein the ADC comprises an internal logic circuit arrangement for coupling the synchronization output and the synchronization input of the ADC.

[0140] Numbered paragraph 36: The system according to any of the numbered paragraphs 31 to 35, wherein the processor is a field-programmable gate array, FPGA, or a microcontroller unit, MCU.

[0141] Numbered paragraph 37: The system according to any of the numbered paragraphs 31 to 36, wherein the system comprises two or more ADCs, wherein the two or more ADCs are arranged such that each of the two or more ADCs is coupled to the processor or the shared master clock. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 18 / 641803

[0001]

Claims

[1] Method for synchronizing an analog-to-digital converter, ADC, wherein the method comprises: Stopping, by a processor, a master clock signal to the ADC to pause the sampling of the ADC, wherein the master clock signal is supplied to the ADC by an external master clock; Detect, via the ADC, that a synchronization event has occurred while the master clock is stopped; Restarting the master clock signal to the ADC by the processor; Resetting, via the ADC, an internal filter at a time synchronized with the master clock; and Resumption of sampling by the ADC in response to the resetting of the ADC's internal filter. [2] Method according to claim 1, wherein resetting an internal filter comprises holding the internal filter in a reset state until sampling is resumed. [3] Method according to claim 1 or 2, wherein resuming sampling of the ADC comprises resuming sampling after a fixed number of master clock cycles after restarting the master clock. [4] A method according to any of the preceding claims, wherein the detection by the ADC of the synchronization event comprises one or more of the following: Receiving an instruction from the processor indicating that a synchronization is requested, and latching a synchronization event trigger of the ADC; and Detect, via an internal clock of the ADC, that the master clock has stopped, and latch a synchronization event trigger of the ADC. [5] Method according to any of the preceding claims, wherein the restart by the processor of the master clock signal to the ADC comprises restarting the master clock signal at a precisely controlled time. [6] The method according to any of the preceding claims, the method further comprising: Generating, by means of the ADC, a synchronization output signal at a synchronization output of the ADC, wherein the synchronization output signal is synchronous with the master clock; and Register, by the ADC, the synchronization output signal at a synchronization input of the ADC after a fixed number of master clock cycles. [7] Method according to claim 6, wherein the synchronization output and the synchronization input of the ADC are coupled via external pins of the ADC and wherein the method further comprises: Resetting the internal filter of the ADC after a fixed number of master clock cycles of registering the synchronization output signal at a synchronization input of the ADC. [8] Method according to claim 6 or 7, wherein the synchronization output and the synchronization input of the ADC are coupled via an internal logic circuit arrangement of the ADC. [9] Method according to any of the preceding claims, wherein the resetting by the ADC of an internal filter at a time synchronous with the master clock comprises resetting with respect to a time reference from the master clock. [10] Method for synchronizing two or more analog-to-digital converters, ADCs, wherein the method comprises: Stopping, by a processor, a shared master clock signal to two or more ADCs to pause the sampling of the two or more ADCs, wherein the shared master clock signal is supplied to the two or more ADCs by an external master clock; Detect, through each of the two or more ADCs, that a synchronization event has occurred while the shared master clock is stopped; Restarting, by the processor, of the shared master clock signal to each of the two or more ADCs; Reset, by each of the two or more ADCs, of an internal filter at a time synchronized with the master clock; and Resuming sampling, through the two or more ADCs, in response to the resetting of their respective internal filters. [11] Method according to claim 10, wherein resetting an internal filter comprises holding the internal filter in a reset state until sampling is resumed. [12] Method according to claim 10 or 11, wherein resuming sampling of the two or more ADCs comprises resuming sampling after a fixed number of master clock cycles after the master clock has been restarted. [13] Method according to any one of claims 10 to 12, wherein the detection, by each of the two or more ADCs, of the synchronization event comprises one or more of the following: Receiving an instruction from the processor indicating that a synchronization is requested, and latching a synchronization event trigger of the two or more ADCs; and Detect, through an internal clock of the two or more ADCs, that the master clock has stopped, and latch a synchronization event trigger of the two or more ADCs. [14] Method according to any one of claims 10 to 13, wherein the restart by the processor of the master clock signal to each of the two or more ADCs comprises restarting the master clock signal at a precisely controlled time. [15] The method according to any one of claims 10 to 14, wherein the method further comprises: Generating, through each of the two or more ADCs, a synchronization output signal at a synchronization output of each of the two or more ADCs, wherein the synchronization output signal is synchronous with the master clock; and Register, through each of the two or more ADCs, the synchronization output signal at a synchronization input of each of the two or more ADCs after a fixed number of master clock cycles. [16] The method of claim 15, wherein the synchronization output and the synchronization input of each of the two or more ADCs are coupled via external pins of each of the two or more ADCs, and wherein the method further comprises: Resetting the internal filter of each of the two or more ADCs after a fixed number of master clock cycles of registering the synchronization output signal at a synchronization input of the two or more ADCs. [17] Method according to claim 15 or 16, wherein the synchronization output and the synchronization input of each of the two or more ADCs are coupled via an internal logic circuit arrangement. [18] Method according to any one of claims 10 to 17, wherein the resetting by each of the two or more ADCs of an internal filter at a time synchronous with the master clock comprises resetting with respect to a time reference from the master clock. [19] Analog-to-digital converter or ADC system, the system comprising: an ADC that includes an internal filter; a master clock, where the master clock is located outside the ADC and coupled to it, and a processor, wherein the processor is located outside the ADC and the master clock and is coupled to it; and a memory and computer program code stored therein, wherein the computer program code, when executed by the processor, does the following: Stopping, by a processor, a master clock signal to the ADC to pause the sampling of the ADC, wherein the master clock signal is supplied to the ADC by the external master clock; Detect, via the ADC, that a synchronization event has occurred while the master clock is stopped; Restarting the master clock signal to the ADC by the processor; Resetting, via the ADC, the internal filter at a time synchronized with the master clock; and Resumption of sampling by the ADC in response to the resetting of the ADC's internal filter. [20] System according to claim 19, wherein the system comprises two or more ADCs, wherein the two or more ADCs are arranged such that each of the two or more ADCs is coupled to the processor or a shared master clock.

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