METHOD FOR MEASURING THE INTERNAL CAPACITY OF A TRANSISTOR COMPONENT

Abstract

A method and an evaluation circuit are disclosed. The method comprises applying a voltage with a predefined voltage level between a first load path node (11) and a second load path node (12) of a transistor device (1); measuring a voltage between a control node (13) and the second load path node (12) to obtain a voltage measurement; and determining at least one of an electrical charge stored in a first internal capacitor (21), or a capacitance value (C21) of the internal capacitor (21) effective between the first load path node (11) and the control node (13), based on the first voltage measurement and based on a capacitance value of a second internal capacitor (31) effective between the control node (13) and the second load path node (12).

Description

TECHNICAL AREA

[0001] The present disclosure relates to a method for measuring the internal capacitance of a transistor device. BACKGROUND

[0002] An isolated-gate transistor device, such as a MOSFET or an IGBT, inevitably exhibits internal capacitances between a load path node and a control node. A first internal capacitance, effective between the control node and a first load path node, is commonly referred to as the gate-drain capacitance in a MOSFET and the gate-collector capacitance in an IGBT. A second internal capacitance, effective between the control node and a second load path node, is commonly referred to as the gate-source capacitance in a MOSFET and the gate-emitter capacitance in an IGBT. Typically, an isolated-gate transistor device is driven by applying a voltage between the control node and the second load path node.

[0003] Both the first and second internal capacitances define the switching characteristics of the transistor devices. Furthermore, the first internal capacitance and the charge stored in it when a specific voltage is applied between the first and second load path nodes provide information about the parasitic turn-on tendency of the transistor device and the reliability of a gate dielectric in the off state of the transistor device.

[0004] Therefore, there is a need to measure the internal capacitances of a transistor device, and in particular to measure the first internal capacitance or an electrical charge stored in the first internal capacitance when a certain voltage is applied between the first and second load path nodes. SUMMARY

[0005] An example concerns a method. The method comprises applying a voltage with a predefined voltage level between a first load path node and a second load path node of a transistor device, measuring a voltage between a control node and the second load path node of the transistor device to obtain a voltage measurement, and determining at least one of the electrical charges stored in a first internal capacitance, or a capacitance value of a first internal capacitance effective between the first load path node and the control node, based on the first voltage measurement and based on a capacitance value of a second internal capacitance effective between the control node and the second load path node.

[0006] Another example involves an evaluation circuit that is configured to perform the procedure.

[0007] The expert will recognize additional features and advantages upon reading the following detailed description and upon examining the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure is illustrated by way of example and without limitation in the figures of the accompanying drawings, in which the same reference symbols refer to similar or identical elements. The elements of the drawings are not necessarily to scale relative to one another. The features of the various examples shown may be combined, provided they are not mutually exclusive. Fig. Figure 1 illustrates a transistor component that includes a first internal capacitance and a second internal capacitance according to an example; Fig. Figure 2 illustrates a transistor element that includes a first internal capacitance and a second internal capacitance according to another example; Fig. Figure 3 illustrates an example of a method for determining an electric charge stored in the first internal capacitance, wherein the method involves applying a voltage between a first load path node and a second load path node and measuring a voltage between a control node and the second load path node; Fig. Figure 4 illustrates an example of a procedure for applying the voltage between the first load path node and the second load path node and for measuring the voltage between the control node and the second load path node; Fig. 5 illustrates an example of a procedure for determining the second internal capacity; Fig. Figure 6 illustrates a modification of the procedure according to Fig. 4, which involves connecting an internal capacity between the control node and the second load path node; Fig. Figure 7 illustrates an example of an evaluation circuit designed to perform the procedure according to Fig. 3 to be carried out; Fig. Figure 8 illustrates an example of the evaluation circuit in detail; Fig. Figure 9 illustrates an example of an evaluation circuit that includes a first parasitic capacitance and a second parasitic capacitance; Fig. Figure 10 schematically illustrates a semiconductor body in which a vertical transistor device is integrated; Fig. Figure 11 illustrates a wafer comprising a plurality of semiconductor bodies and an evaluation circuit coupled to the transistor device integrated in one of the semiconductor bodies for determining the first internal capacitance; and Fig. Figure 12 illustrates one of the semiconductor bodies of the wafer according to Fig. 10 in detail. DETAILED DESCRIPTION

[0009] The examples described here provide a method for determining an electric charge stored in the internal capacitance of a transistor device and / or for determining the capacitance value of the transistor device's internal capacitance. The method can be performed at the wafer level; that is, the electric charge stored in the internal capacitances of a plurality of transistor devices arranged on the same wafer can be measured before the wafer is separated into the individual transistor devices.

[0010] Although specific examples have been illustrated and described here, the person skilled in the art will recognize that a multitude of alternative and / or equivalent implementations can replace the specific examples shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific examples discussed herein. Therefore, it is intended that this invention is limited only by the claims and their equivalents.

[0011] It should be noted that the methods and devices, including their preferred embodiments, as set forth in this document, can be used alone or in combination with the other methods and devices disclosed herein. Furthermore, the features set forth in connection with a device are also applicable to a corresponding method and vice versa. Moreover, all aspects of the methods and devices set forth in this document can be combined in any way. In particular, the features of the claims can be combined with one another in any manner.

[0012] It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. A person skilled in the art will be able to implement various arrangements which, although not explicitly described or shown here, embody the principles of the invention and are contained within its spirit and scope. Furthermore, all examples and embodiments set forth in this document are expressly intended primarily for illustrative purposes only, to assist the reader in understanding the principles of the proposed methods and systems. Moreover, all statements herein are intended to provide the principles, aspects, and embodiments of the invention, as well as specific examples thereof, including their equivalents.

[0013] With reference to the foregoing, an example disclosed herein relates to a method for determining an electric charge stored in an internal capacitance of a transistor device. Examples of transistor devices containing internal capacitances are given in the Fig. 1 and Fig. 2 illustrated.

[0014] With reference to the Fig. 1 and Fig. 2 Each of the transistor devices includes a first load path node 11, a second load path node 12, a control node 13, a first internal capacitance 21 and a second internal capacitance 31. The first internal capacitance 21 is effective between the first load path node 11 and the control node 13, and the second internal capacitance 31 is effective between the second load path node 12 and the control node 13.

[0015] Each of the in the Fig. 1 and Fig. The transistor device illustrated in Figure 2 is a voltage-controlled transistor device that is in an on-state or an off-state depending on the voltage level of a control voltage (drive voltage) applied between the control node 13 and the second load path node 12. The transistor device is in the on-state when the control voltage is higher than a threshold voltage of the transistor device, and the transistor device is in the off-state when the control voltage is lower than the threshold voltage of the transistor device. In the on-state, the transistor device is configured to conduct a current between the first and second load path nodes 11 and 12.In the off state, the transistor device is configured to block voltage levels of a load path voltage applied between the first and second load path nodes 11, 12 that are lower than the voltage blocking capability of the transistor device. The voltage blocking capability defines the maximum voltage level of the load path voltage that the transistor device can withstand. The voltage blocking capability depends on the specific implementation of the transistor device and is, for example, in a range between several tens of volts and several kilovolts.

[0016] According to the in Fig. In the illustrated example 1, the transistor device can be implemented as a MOSFET. In a MOSFET, the control node 13 is usually referred to as the gate node, the first load path node 11 is usually referred to as the drain node, and the second load path node is usually referred to as the source node. Accordingly, the first internal capacitance 21 is usually referred to as the gate-drain capacitance, the second internal capacitance 31 is usually referred to as the gate-source capacitance, and the control voltage is usually referred to as the gate-source voltage.

[0017] The transistor device in Fig. 1 is represented by its circuit symbol. The one in Fig. The circuit symbol shown represents an N-type enhancement MOSFET. However, this is only an example. Everything explained below applies equivalently to a P-type enhancement MOSFET.

[0018] According to the in Fig. In the illustrated example 2, the transistor device can be implemented as an IGBT. In an IGBT, the control node 13 is usually called the gate node, the first load path node 11 is usually called the collector node, and the second load path node is usually called the emitter node. Accordingly, the first internal capacitance 21 is usually called the gate-collector capacitance, the second internal capacitance 31 is usually called the gate-emitter capacitance, and the control voltage is usually called the gate-emitter voltage.

[0019] It should be noted that the first and second internal capacitances are 21 and 22 internal capacitances of the respective transistor device. However, to facilitate understanding of the procedure explained below, in the Fig. 1 and Fig. 2 the first and second internal capacitance 21, 22 are represented by capacitors, which are shown in addition to the circuit symbol of the respective transistor device.

[0020] In particular, the first internal capacitance 21 can have a significant influence on the electrical behavior of the transistor device. It is therefore desirable to determine the first internal capacitance and / or the electrical charge stored in the first internal capacitance when a specific load path voltage is applied between the first and second load path nodes 11, 12. An example of a method for determining the electrical charge stored in the first internal capacitance when a specific load path voltage is applied between the first and second load path nodes 11, 12 is given in Fig. 3 illustrated.

[0021] With reference to Fig. 3 comprises the method (1001) applying a load path voltage with a predefined voltage level between the first load path node 11 and the second load path node 12 of the transistor device 1; (1002) measuring a voltage between the control node 13 and the second load path node 12 to obtain a voltage measurement; and (1003) determining an electric charge stored in the first internal capacitance 21 based on the voltage measurement and based on a capacitance value of the second internal capacitance 31.

[0022] The procedure according to Fig. Equation 2 is based on the fact that the first and second internal capacitances 21, 31 form a capacitive voltage divider between the first and second load path nodes 11, 12. Thus, when a certain load path voltage is applied between the first and second load path nodes 11, 12, an electrical charge Q21 stored in the first internal capacitance 21 is equal to an electrical charge Q31 stored in the second internal capacitance 31. Q21=Q31

[0023] In the following, the electric charge Q21, which is stored in the first internal capacity 21, is referred to as the first electric charge, and the electric charge Q31, which is stored in the second internal capacity 31, is referred to as the second electric charge.

[0024] The second electric charge 31 is given by a capacitance value C31 of the second internal capacitance 31 multiplied by a voltage V31 across the second internal capacitor 31. Q31=Q21=V31⋅C31

[0025] Thus, by applying a load path voltage between the first and second load path nodes 11, 12, so that the first and second internal capacitances 21, 31 are charged, and measuring the resulting voltage V31 across the second internal capacitances 31, the electrical charge stored in the first internal capacitance 21 can be obtained using equation (2).

[0026] Determining the electric charge stored in the first internal capacitance using equation (2) requires knowledge of the capacitance value C31 of the second internal capacitance 31. An example of a procedure for determining the capacitance value C31 of the second internal capacitance 31 is explained below.

[0027] Fig. Figure 4 schematically illustrates an example of how to carry out the procedure according to Fig. 3. It should be noted that in Fig. Figures 4 and the following figures illustrate only the first and second internal capacitances 21 and 31 of the transistor device. The transistor device is a transistor device according to one of the examples previously explained herein.

[0028] As from Fig. As can be seen in Figure 4, the method involves applying a load path voltage with a predefined first voltage level V1 between the first and second load path nodes 11 and 12, and measuring the voltage level V31 across the second internal capacitor 31. Applying the load path voltage may involve using a voltage source V41 connected to the load path nodes 11 and 12. Measuring the voltage across the second internal capacitor 31 may involve using a voltage sensor V42 connected between the control node 13 and the second load path node 12. The voltage source V41 is a DC (direct current) voltage source, so the load path voltage applied across the load path of the transistor device is a DC voltage.

[0029] According to an example, based on the determined electrical charge Q21 stored in the first internal capacitance 21, a capacitance value C21 of the first internal capacitance 21 is determined using a difference between the voltage level of the load path voltage V1 and the measured voltage V31 across the second internal capacitance 31 as follows. C21=Q21V1−V31 where Q21 denotes the specific electrical charge stored in the first internal capacitance 21, V1 denotes the voltage level of the load path voltage applied between the first and second load path nodes 11, 12, and V31 denotes the voltage level of the measured voltage across the second internal capacitance 31.

[0030] There can be a delay between the point at which the voltage at the first voltage level V1 is applied to the load path and the point at which the first and second internal capacitors 21, 31 have been charged to such an extent that the voltages across them have stabilized at final values ​​that depend on the voltage (at voltage level V1) applied across the load path. This delay is due to the unavoidable resistance of a charging path between the voltage source V41 and the series capacitor circuit 21, 31. In general, for given capacitance values ​​of capacitors 21, 31, the higher the resistance, the longer it takes for the series capacitor circuit 21, 31 to be fully charged. This delay can range, for example, from several milliseconds to several seconds.

[0031] It is understood that the voltage across the second internal capacitor 31 is measured when the voltages across the first and second capacitors 21, 31 have stabilized at their final values. The same applies to each measurement process described below in which a voltage is applied to a capacitor or a series of capacitors. In each case, the applied voltage is a DC voltage, and the voltage measurement across a capacitor or series of capacitors is performed after the voltages across the capacitor or series of capacitors have stabilized at their respective final values. In other words, the voltage measurements are performed when the measurement setup and the device under test are in a steady state, i.e., neither the voltage level V1 nor the voltage across the capacitors is changing.One can also say that the dV / dt across the capacitances is essentially zero when the measurements are performed. This contrasts with dynamic measurements, where measurements are taken during rising or falling voltages, i.e., a non-zero dV / dt.

[0032] The voltage level V1 of the load path voltage applied during the process of determining the electrical charge stored in the first internal capacitance is lower than the breakdown voltage of the transistor device. For example, the voltage level V1 is selected from a range between 20% and 90%, specifically between 50% and 80% of the breakdown voltage of the transistor device. The voltage blocking capability depends on the specific type of transistor device and ranges from several tens of volts to several kilovolts, such as between 40 V and 10 kV.

[0033] Referring to equation (2), determining the electric charge Q31 stored in the second internal capacitance 31 involves using a previously determined capacitance value C31 of the second internal capacitance 31. Determining the capacitance value C31 of the second internal capacitance C31 can involve charging the second internal capacitance 31 with a predefined electric charge Q31 and measuring a voltage difference V31 resulting from charging the second internal capacitance 31 with the predefined electric charge Q31. The capacitance value C31 is then given by the quotient of the electric charge Q31 and the voltage difference V31. C31=ΔQ31ΔV31 where Q31 denotes the charge supplied to the second internal capacity 31, and V31 denotes the voltage difference between the voltage across the second internal capacity 31 after charging the second internal capacity 31 with Q31 and the voltage across the second internal capacity 32 before charging the second internal capacity 31 with Q31.

[0034] It should be noted that equation (4) holds equivalently if the second internal capacitance 31 is discharged by a certain amount Q31 of charge. In this case, the electrical charge stored in the second internal capacitance 31 is reduced by the predefined amount Q31, thus reducing the voltage by V31.

[0035] According to an example, charging the second internal capacity 31 with the predefined electric charge Q31 involves driving a current with a predefined current level I31 into the second internal capacity 31 for a predefined time interval t, such that the predefined electric charge Q31 is given by the current level I31 multiplied by the time interval t. ΔQ31=I31⋅Δt

[0036] Fig. Figure 5 schematically illustrates an example of a procedure for determining the capacity value C31 of the second internal capacity 31 according to the previously explained example. With reference to Fig. 5. The current with current level l31 for charging the second internal capacitance 31 is supplied by a current source 43, which is connected between the control node 13 and the second load path node 12. The voltage difference V31 resulting from charging the second internal capacitance 31 can be measured using the same voltage sensor 42 that is used to measure the voltage V31 across the second internal capacitance 31 in the Fig. The 4 illustrated procedures are used.

[0037] With reference to the above, the transistor device can be switched on during normal operation if a drive voltage (control voltage) higher than the threshold voltage is applied between the control node 13 and the second load path node 12. Furthermore, during normal operation, if it is desired to keep the transistor device in the off state, a drive voltage lower than the threshold voltage is applied between the control node 13 and the second load path node 12.

[0038] As an example, in the above-described procedure for determining the electric charge Q21 stored in the first internal capacitor 21, the load path voltage V1 applied between the first and second load path nodes 11, 12 is selected such that the resulting voltage V31 between the control node 13 and the second load path node 12 is lower than the threshold voltage of the transistor device, thus preventing the transistor device from switching on. A ratio between the capacitance values ​​C21, C31 of the first and second internal capacitors 21, 23 is at least roughly known before the measurement process, so that, based on this ratio of capacitance values, the voltage level V1 of the load path voltage applied during the measurement process can be appropriately adjusted to prevent the voltage level of the control voltage V31 from reaching the threshold voltage.

[0039] Typically, the capacitance value of the second internal capacitor 31 of the transistor device is much higher than the capacitance value of the first internal capacitor 21. Thus, according to the capacitive divider ratio of the capacitive voltage divider formed by the first and second internal capacitors 21 and 31, the voltage V31 between the control node 13 and the second load path node 52 is typically much lower than the voltage between the first load path node 51 and the control node 13 when the load path voltage V1 is applied between the first and second load path nodes 51 and 52. In one example, the transistor device is implemented such that the capacitance value of the first internal capacitor 21 is less than 10% or even less than 1% of the capacitance value of the second internal capacitor 31.

[0040] According to an example that was in Fig. As illustrated in Figure 6, a capacitor 33 is connected in parallel to the second internal capacitance 31 when determining the charge Q21 stored in the first internal capacitance 21. This capacitor 33 is also referred to as the additional capacitor or external capacitor. Connecting the additional capacitor 33 in parallel to the second internal capacitance 31 increases the total capacitance between the control node 13 and the second load path node 12 and, for a given voltage level V1 of the load path voltage, reduces the voltage V31 between the control node 13 and the second load path node 12 compared to the scenario in which only the second internal capacitance 31 is present between the control node 13 and the second load path node 12.This can either help to increase the safety margin between the voltage level V31 of the control voltage and the threshold voltage when a certain voltage level V1 of the load path voltage is applied, or it can make it possible to increase the voltage level V1 of the load path voltage at a given safety margin.

[0041] According to an example, the additional capacitor 33, which is connected in parallel to the second internal capacitance 31, is selected such that a total capacitance C3 between the control node 13 and the second load path node 12, which is given by the capacitance value of the second internal capacitance 32 plus the capacitance of the additional capacitor 33, C3=C31+C33 The capacitance value of the second internal capacitor 33 is high enough relative to the capacitance value of the first internal capacitor 22 that the voltage V31 between the control node 13 and the second load path node 12 is safely below the threshold voltage of the transistor device, so that the transistor device remains in the off state during the measurement. For example, the capacitance value of the second internal capacitor 33 lies in a range between the capacitance value of the second internal capacitor 31 and 10 times the capacitance value of the second internal capacitor 31.

[0042] In the procedure that took place in Fig. As illustrated in Figure 6, the charge stored in the first internal capacitance C21 is given by the charge stored in the parallel circuit which includes the second internal capacitance 31 and the capacitor 3. Q21=Q31=V31⋅C3=V31⋅(C31+C33) where C33 denotes the capacitance of the further capacitor 33.

[0043] According to an example, the above-described procedure is carried out by an evaluation circuit (evaluation equipment) 5 which is connected to the first and second load path nodes 11, 12 and the control node 13.

[0044] Fig. Figure 7 schematically illustrates a block diagram of an evaluation circuit 5 configured to perform the above-described procedure for determining the charge stored in the first internal capacity 21. Referring to Fig. The evaluation circuit 5 includes three connections (which can also be called pins): a first connection 51, which is connected to the first load path node 11; a second connection 52, which is connected to the second load path node 12; and a third connection 53, which is connected to the control node 13. A more detailed example of the evaluation circuit 5 is shown in Fig. 8 illustrates.

[0045] With reference to Fig. The evaluation circuit 5 includes a control circuit 8, which is configured to control the operation of the evaluation circuit 5. Specifically, the control circuit 8 is configured to receive measurement signals from voltage sensors of the evaluation circuit 5 and to control voltage and current sources of the evaluation circuit 5. This is explained in detail below.

[0046] In the Fig. In the illustrated example 8, the evaluation circuit 5 includes a controllable voltage source 41, which is connected between the first and second terminals 51, 52 and therefore between the first and second load path nodes 11, 12 of the transistor device. The voltage source 41 can be activated and deactivated by a control signal S41 received by the control circuit 8. When the voltage source 41 is activated, it applies a load path voltage with a predefined voltage level V1 between the first and second terminals 51, 52 and the first and second load path nodes 11, 12. When the voltage source 41 is deactivated, it provides a high electrical resistance between the first and second terminals 51, 52, so that the presence of the voltage source 41 does not affect the charge state of the first and second internal capacitances 21, 31.

[0047] With reference to Fig. The evaluation circuit 5 further includes a voltage sensor 71, which is connected between the third and second terminals 52, 53 and thus between the control node 13 and the second load path node 12. The voltage sensor 71 is configured to detect the voltage V31 between the control node 13 and the second load path node 12 and to provide a measured value V31', representing the measured voltage V31, to the control circuit 8.

[0048] Optionally, the evaluation circuit 5 also includes the additional capacitor 33. The additional capacitor 33 is connected between the third and the second terminals 53, 52 and therefore between the control node 13 and the second load path node 12.

[0049] Furthermore, the evaluation circuit 5 can include a first discharge switch 63 and a second discharge switch 64. The first discharge switch 63 is connected between the first and third terminals 51, 53, and therefore between the first load path node 11 and the control node 13. The second discharge switch 63 is connected between the third and second terminals 53, 52, and therefore between the control node 13 and the second load path node 12. Each of the first and second discharge switches 61, 64 receives a respective control signal S63, S64 from the control circuit 8 and is in an on state or an off state, depending on the respective control signal S63, S64. When the first discharge switch 63 is in the on state, it discharges the first internal capacitance 21. Equivalently, when the second discharge switch 64 is in the on state, it discharges the second internal capacitance 31.

[0050] According to one example, the first and second internal capacitances 21, 31 are discharged before the electrical charge stored in the first internal capacitance 21 is determined. For this purpose, the control circuit 8 can be configured to activate the first and second discharge switches 63, 64 to discharge the first and second internal capacitances 21, 31 before determining the electrical charge stored in the first internal capacitance 21. Determining the electrical charge stored in the first internal capacitance 21 can involve activating the voltage source 41 to apply the load path voltage with voltage level V1 between the first and second load path nodes 11, 12, and measuring the voltage V31 between the control node 13 and the second load path node 12 using the voltage sensor 71.The capacitance value C31 of the second internal capacitance 31 is stored in the control circuit 8 and the control circuit is configured to determine the charge stored in the first internal capacitance 21 according to equation (2) based on the stored capacitance value C31 and the voltage measurement value V31' received from the voltage sensor 71.

[0051] If the evaluation circuit 5 includes the additional capacitor 33, either the capacitance value C33 of the additional capacitor 33 is stored in the control circuit 8 in addition to the capacitance value C31 of the first internal capacitor, or the total capacitance C3 (=C31 + C33) is stored in the control circuit 8. In this example, the control circuit 8 is configured to calculate the charge stored in the first internal capacitor 21 according to equation (7) based on the stored capacitance values ​​C31, C33, or C3 and the voltage measurement V31' received from the voltage sensor 71.

[0052] According to one example, the control circuit 8 is configured to display the result of determining the charge Q21 stored in the first internal capacity 21 on a display device (not illustrated) or to communicate the result to another entity, such as another controller, via a suitable communication interface (also not illustrated).

[0053] With reference to the above, the capacitance value C21 of the first internal capacitance 21 can be determined based on the specific charge Q21 stored in the first internal capacitance 21. For example, the control circuit 8 is configured to determine the capacitance value C21 according to equation (3). In this example, in addition to the measurement V31', which represents the voltage V31 between the control node 13 and the second load path node 12, the control circuit 8 receives another voltage measurement V1', which represents the voltage level V1 of the load path voltage applied between the first and second load path nodes 11, 12, and is configured to calculate the capacitance value C21 based on the specific charge Q21 and the additional voltage measurement V1'.This additional voltage measurement V1' is provided, for example, by another voltage sensor 72, which is connected between the first and the second load path nodes 11, 12.

[0054] According to an example, the evaluation circuit 5 is further configured to determine the capacitance value C31 of the second internal capacitor 31. For this purpose, the evaluation circuit 5 includes a controllable current source 42, which is connected between the third and second terminals 53, 52 of the evaluation circuit 5 and thus between the control node 13 and the second load path node 12 of the transistor device 1. The current source 42 is configured to receive a control signal S42 from the control circuit 8 and is configured to be enabled or disabled based on the control signal S42. In the enabled state, the current source 42 provides a current with a predefined current level l31, which is other than zero. In the disabled state, the current source 42 provides no current (which is equivalent to providing a current with a current level of zero).

[0055] To determine the capacitance value C31 of the second internal capacitance 31, the control circuit 8 is configured to activate the current source 42 for a predefined time interval t, so that the second internal capacitance 31 is charged with a predefined amount of charge Q31. Furthermore, the control circuit 8 is configured, based on the voltage measurement V31' received from the first voltage sensor 71, to determine a voltage difference V31 between the control node 13 and the second load path node 12 before and after charging the second internal capacitance 31. Finally, the control circuit 8 is configured to determine the capacitance value C31 of the second internal capacitance 31 according to equation (4), based on the predefined amount of charge Q31 and the voltage difference V31.

[0056] With reference to Fig. 9 The evaluation circuit 5 can include a first parasitic capacitance 22 between the first terminal 51 and the third terminal 53 and a second parasitic capacitance 32 between the third terminal 53 and the second terminal 52. Such parasitic capacitances are present in the example shown in Fig. Figure 9 illustrates the capacitors connected between the respective terminals. The rest of the evaluation circuit is shown in Figure 9. Fig. Figure 9 is not illustrated in detail. The parasitic capacitances 22, 32 of the evaluation circuit 5 can distort the result of determining the charge Q21 stored in the first internal capacitance 21 and can distort the result of determining the capacitance value C31 of the second internal capacitance 31.

[0057] According to an example, before the transistor device is connected to the evaluation circuit 5 and the charge Q21 stored in the first internal capacitance 21 is determined, (a) a charge Q22 stored in the first parasitic capacitance 22 is determined, and (b) a capacitance value C30 of a capacitance between the third and second terminals 13, 12 of the evaluation circuit 5 is determined in an open-loop process in which the transistor device is not connected to the first, second, and third terminals 51, 52, 53 of the evaluation circuit 5. The capacitance value C30 of the capacitance between the third and second terminals 53, 52 of the evaluation circuit 5 is given either by a capacitance value C32 of the second parasitic capacitance 32 when the evaluation circuit is free of the further capacitance 33, C30=C32 or is given by the capacitance value C32 of the second parasitic capacitance 32 plus the capacitance value C33 of the further capacitor 33, C30=C32+C33

[0058] In the open-loop process, the capacitance value C30 of the total capacitance between the third and second terminals 53, 52 can be determined in the same way as explained above with reference to equations (4) and (5), i.e. based on charging / discharging the capacitance between the first and second terminals 52, 53 with a predefined charge and measuring the voltage increase / decrease resulting from the charging process.

[0059] In the open-loop measurement process, a voltage V2 is applied between the first and second terminals 51, 52 of the evaluation circuit 5 to determine the charge Q22 stored in the first parasitic capacitance 22. According to one example, the voltage level of this voltage V2 is essentially equal to the voltage level of the voltage V1 applied between the first and second terminals in the transistor measurement process, i.e., when the transistor device is connected to the evaluation circuit 5 and the charge stored in the first internal capacitance 21 of the transistor device is being measured. According to another example, "at least approximately equal" means that the voltage level of the voltage V2 applied in the open-loop measurement process lies within a range of 75% to 125% of the voltage level of the voltage V1 applied to the transistor device in the measurement process.

[0060] Determining the charge Q22 stored in the first internal capacitor 22 involves measuring a voltage V32 between the second and third terminals 52, 53 of the evaluation circuit 5. The charge Q22 stored in the first internal capacitor 22 depends on the voltage level V32 between the second and third terminals 52, 53 and is given by Q22=V32⋅C30 where C30 denotes the capacitance value of the capacitance between the third and second terminals 53, 52 in the open-loop process.

[0061] In the transistor measurement process, i.e., when the transistor device is connected to the evaluation circuit 5, a total charge Q2, stored by a total capacitance C2 between the first terminal 51 and the third terminal 53, is determined. This involves applying the load path voltage V1 between the first and second terminals 51, 52 of the evaluation circuit 5 (and between the first and second load path nodes 11, 12 of the transistor device), measuring the voltage V31 between the third and second terminals 53, 52 (and between the control node 13 and the second load path node 12 of the transistor device), and determining the total charge Q2 as a function of the measured voltage V31 and a capacitance value C3 of the total capacitance between the third and second terminals 53, 52. Q2=V31⋅C3 where Q2 denotes the total charge stored between the first and third terminals 51, 53, V31 denotes the measured voltage between the third and second terminals 53, 52, and C3 is the total capacitance between the third and second terminals 53, 52. This total capacitance C3 includes the capacitance value of the second internal capacitance 22 plus the capacitance value of the second parasitic capacitance 32 plus the capacitance value C33 of the optional additional capacitor 33. The procedure further involves determining the capacitance value C3 of the total capacitance between the third and second terminals 53, 52. This total capacitance can be determined in the same way as explained above with reference to equations (4) and (5), i.e., based on charging / discharging the capacitance between the first and second terminals 52, 53 with a predefined charge and measuring the voltage increase / decrease resulting from the charging process.

[0062] As explained above, the first internal capacitance 21 is typically much lower than the second internal capacitance 31, so that during the transistor measurement process, the voltage V31 between the control node 13 and the second load path node 12 is much lower than the voltage across the first internal capacitance 21 and may be less than 1% of the load path voltage. According to an example, in the evaluation circuit 5, Fig. 9 a capacitance value C22 of the first parasitic capacitance 22 between the first and third terminals 51, 53 is much lower than a capacitance value C30 of the capacitance between the third and second terminals 53, 52 of the evaluation circuit 5, so that a capacitive division ratio of the capacitive voltage divider with the first and second internal capacitances 21, 31 in the transistor device is essentially equal to a capacitive division ratio of the capacitor voltage divider with the first and second parasitic capacitances 22, 32 and the optional additional capacitor 33 of the evaluation circuit 5.In this case, if the voltage level V2 applied between the first and second terminals 51, 52 in the open-loop process is approximately equal to the voltage level V1 applied between the first and second terminals 51, 52 in the transistor measurement process, then the voltages between the first and third load terminals 51, 53 in the open-loop process and the transistor measurement process are approximately equal to or at least of the same order of magnitude. In this case, the charge Q21 stored in the first internal capacitor in the transistor measurement process is approximately given by... Q21=Q2−Q22=V31⋅C3−Q22 so that the charge Q21, which is stored in the first internal capacitance 21, can be easily determined based on the total charge Q2, which is determined in the transistor measurement process, and the charge Q22, which is determined in the open loop process.

[0063] If the voltage between the first and third terminals 51, 53 is not approximately equal in the open-loop process and the transistor measurement process, the procedure involves determining the capacitance value C21 of the first internal capacitance 21 based on the capacitance value C22 of the first parasitic capacitance 22 and the capacitance value C2 of the total capacitance between the third and second terminals 53, 52, when the transistor device is connected to the evaluation circuit 5. C21=C2−C22

[0064] According to an example, the capacitance value C22 of the first parasitic capacitance 22 is determined based on the determined charge Q22 in the open-loop process and the voltage between the first and third terminals 51, 53 in the open-loop process. C22=Q22V2−V32 where Q22 denotes the charge stored between the first and third terminals 51, 53 in the open-loop process, and V2-V32 is the difference between the voltage V2 between the first and second terminals 51, 52 and the voltage between the second and third terminals 53, 52 in the open-loop process. According to an example, the capacitance value C2 of the total capacitance between the first and third terminals in the device measurement process is determined based on the determined charge Q2 in the transistor measurement process and the voltage between the first and third terminals 51, 53 in the transistor measurement process. C2=Q2V1−V31 where Q2 denotes the charge stored between the first and third terminals 51, 53 in the transistor measurement process, and V1-V31, which is the difference between the load path voltage V1 and a voltage between the second and third terminals 53, 52, is the voltage between the first and third terminals 51, 53 in the transistor measurement process.

[0065] According to an example, the charge Q21, which is stored in the first internal capacitance 21, is determined in the transistor measurement process based on the determined capacitance C21 and based on the voltage between the first and third terminals 51, 53. Q21=C21⋅(V1−V31)

[0066] According to a Fig. In the illustrated example 10, the transistor device is a vertical transistor device. In this case, the first and second load path electrodes 91, 92 of the transistor device 1 are arranged over opposing surfaces 101, 102 of a semiconductor body 100 in which active device regions (such as source, body, and drain regions of a MOSFET) of the transistor device 1 are integrated. The transistor device 1 is identified by its circuit symbol in Fig. Figure 10 is shown. The circuit symbol is shown for illustrative purposes only. Fig. Figure 10 represents a MOSFET. However, this is only one example. The transistor device can be implemented according to any of the examples described above. The active device regions of the transistor device 1 can be integrated into the semiconductor body 100 in a conventional manner. Integrating active device regions of a transistor device into a semiconductor body is well known, so no further explanation is required in this respect.

[0067] In the Fig. In the illustrated example 10, a first load path electrode 91 is formed over a first surface 101 of the semiconductor body 100, and a second load path electrode 92 is formed over a second surface 102 of the semiconductor body 100. The first load path electrode 91 is connected to, or forms, the first load path node 11 of the transistor device, and the second load path electrode 92 is connected to, or forms, the second load path node 12 of the transistor device. In a MOSFET, for example, the first load path electrode 91 is a source electrode and the second load path electrode 92 is a drain electrode.

[0068] With reference to Fig. The transistor device further includes a control electrode 93. The control electrode 93 is connected to or forms the control node 13 of the transistor device. The control electrode 93 is formed over one of the first and second surfaces 101, 102. According to a Fig. In the illustrated example 10, the control electrode 91 is formed over the same surface as the first load path electrode 91, which is located in the Fig. The first surface, 101, is illustrated in the 10 example.

[0069] In a transistor device of the in Fig. In the type 10 illustrated, the load path voltage V1 is applied between the first and second load path electrodes 91, 92, which are formed over the opposite first and second surfaces 101, 102, to determine the charge Q21 stored in the first internal capacitance 21.

[0070] It is generally known that a multitude of transistor devices can be formed from the same semiconductor wafer, which is ultimately subdivided to form the multitude of devices. By way of example, the procedure described above for determining the charge Q21 stored in the first internal capacitance 21 of a transistor device is carried out at the wafer level. That is, the procedure is performed while the multitude of transistor devices are still part of a common wafer. This will be further explained below with reference to the Fig. 11 and Fig. 12 explained.

[0071] Fig. Figure 11 schematically illustrates a wafer 200 containing a plurality of semiconductor bodies 100, each of which integrates active device regions of a vertical transistor device. According to one example, each of the semiconductor bodies 100 is formed by a respective section of a continuous monocrystalline semiconductor layer of the wafer 200. Referring to Fig. 11. Scribble regions 110 are arranged between the semiconductor bodies 100 on the wafer 200. At the end of the manufacturing process, the wafer 200 is separated along the scribble regions 110, which are at least partially removed when the wafer 200 is separated.

[0072] The semiconductor bodies 100 are in Fig. Figure 11 is only schematically illustrated. For example, the control and load path electrodes of the transistor devices are not shown. Furthermore, the figure is illustrated Fig. 11 schematically an evaluation circuit (evaluation equipment) 5 which is configured to determine the electrical charge stored in each of the transistor devices when a respective voltage is applied between the first and second load path node of the respective transistor device.

[0073] Fig. Figure 12 schematically illustrates a section of the wafer 200 containing a semiconductor body 100 with active regions of a transistor device 1 integrated therein. This section includes the first load path electrode 92 and the control electrode 93 above the first surface 101, and the second load path electrode 91 above the second surface 102 opposite the first surface. By way of example, the first load path electrodes 91 of the transistor devices 1 formed on the same wafer 200 are a single, continuous electrode. This continuous electrode is separated to form the first load path electrodes 91 of the individual transistor devices 1 when the wafer 200 is cut.

[0074] With reference to the foregoing, the evaluation circuit (evaluation equipment) 5 includes a first, second, and third connection for connecting to the first load path electrode 91, the second load path electrode 92, and the control electrode 93. In the Fig. 11 and Fig. In the illustrated example 12, the first terminal 51 is formed by an electrically conductive carrier on which the wafer 200 is arranged such that the first load path electrodes 91 of the individual transistor devices 1 are in contact with the carrier. The electrically conductive carrier forming the first terminal 51 of the evaluation circuit 5 can also be referred to as a chuck.

[0075] The 200-gram wafer can be held in place on the support in various ways. In one example, the support includes through-holes (not illustrated) and is connected to a vacuum pump (also not illustrated). The vacuum pump is configured to create a vacuum between the 200-gram wafer and the support through the through-holes, thus holding the wafer in place on the support.

[0076] With reference to the Fig. 11 and Fig.In Figure 12, the second and third terminals 52 and 53 are implemented as probes (needles). The needle-shaped second terminal 52 is configured to be brought into electrical contact with the second load path electrode 92 of a transistor device 1, and the needle-shaped third terminal 53 is configured to be brought into electrical contact with the control electrode 93 of the respective transistor device 1 in order to measure the charge stored in the first internal capacitance 21 in the manner previously described herein.

[0077] According to an example, the several transistor devices 1 formed on wafer 200 are measured successively. That is, at each time, a load path voltage V1 is applied between the first and the second load path node 11, 12 of only one of the transistor devices 1 formed on wafer 200.

[0078] According to an example, the evaluation circuit 5 includes a plurality of second terminals 52 and a plurality of third terminals 53. In this example, the control electrodes 93 of a plurality of transistor devices 1 can be connected simultaneously to their respective third terminals 53, and the second load path electrodes 91 of the plurality of transistor devices can be connected simultaneously to their respective second terminals 52. Nevertheless, the individual transistor devices 1 of the plurality of transistor devices, whose control electrodes 93 and second load path electrodes 92 are simultaneously connected to the third and second terminals 53, 52 of the evaluation circuit 5, are measured successively.

[0079] It should be noted that the method is not limited to use with vertical transistor devices. The method can also be used to determine the charge stored in the first internal capacitance in a lateral transistor device where the control node and the first and second load path nodes are accessible on the same side of the semiconductor body containing the transistor device. For testing lateral transistor devices, the first terminal can be implemented as a needle instead of a disk.

[0080] Some aspects of the transistor device and the procedure described above are briefly summarized below.

[0081] An example relates to a method that involves applying a voltage with a predefined voltage level between a first load path node and a second load path node of a transistor device; measuring a voltage between a control node and the second load path node to obtain a voltage measurement; and determining at least one of an electric charge stored in a first internal capacitance, or a capacitance value of the internal capacitance effective between the first load path node and the control node, based on the first voltage measurement and based on a capacitance value of a second internal capacitance effective between the control node and the second load path node.

[0082] According to an example, the procedure further includes determining the capacity value of the second internal capacity. Determining the capacity value of the second internal capacity can involve charging the second internal capacity in a charging process; and determining the capacity value of the second internal capacity based on a charge supplied to the second internal capacity in the charging process, and based on a change in voltage between the control node and the second load path node in the charging process.

[0083] According to an example, the procedure further includes connecting an external capacitor between the control node and the second load path node when the voltage with the predefined voltage level is applied between the first load path node and the second load path node; and determining the electrical charge stored in the first internal capacitor, furthermore based on a capacitance value of the external capacitor.

[0084] According to one example, the transistor device is integrated into a semiconductor body, and the semiconductor body is one of a multitude of semiconductor bodies on a wafer.

[0085] The transistor device is a transistor device with an insulated gate, such as a MOSFET or an IGBT.

[0086] According to one example, applying a voltage at a predefined voltage level between the first load path node and the second load path node, and measuring the voltage between the control node and the second load path node, involves using an evaluation circuit. The evaluation circuit can include a first terminal configured to connect to the first load path node, a second terminal configured to connect to the second load path node, and a third terminal configured to connect to the control node.The evaluation circuit may further include a first parasitic capacitance between the first terminal and the third terminal and a second parasitic capacitance between the third terminal and the second terminal, and may further include determining the electric charge stored in the first internal capacitance and determining the capacitance value based on capacitance values ​​of the first parasitic capacitance and the second parasitic capacitance.

[0087] According to one example, the predefined voltage level of the voltage applied between the first load path node and the second load path node is selected such that a voltage between the control node and the second load path node, resulting from the voltage applied between the first load path node and the second load path node, is lower than a threshold voltage of the transistor device.

[0088] According to one example, the polarity of the voltage applied between the first load path node and the second load path node is such that an internal diode of the transistor device between the first load path node and the second load path node is reverse biased.

[0089] According to one example, the procedure further involves determining a capacity value of the first internal capacitance based on the determined electrical charge stored in the first internal capacitance and a difference between the voltage level of the load path voltage and the voltage level of the measured voltage between the control node and the second load path node.

[0090] According to another example, the method described above is used to determine at least one of the electric charges stored in a first internal capacitance, or the capacitance value of a first internal capacitance of each of several transistor devices integrated into a wafer. According to one example, this method involves successively determining the at least one of the electric charges stored in the first internal capacitance, or the capacitance value of each of the several transistor devices.

[0091] Another example relates to an evaluation circuit comprising a first terminal configured to be coupled to a first load path node of a transistor device; a second terminal configured to be coupled to a second load path node of the transistor device; and a third terminal configured to be coupled to a control node of the transistor device. The evaluation circuit is configured to determine a capacitance value of a first internal capacitor of the transistor device according to the procedure described above. According to one example, the evaluation circuit further includes an external capacitor between the third terminal and the second terminal. According to another example, each of the first and third terminals includes a contact probe, and the second terminal includes a contact plate or a contact probe.

Claims

[1] Procedure, encompassing: Applying a voltage with a predefined voltage level between a first load path node (11) and a second load path node (12) of a transistor device (1); Measuring a voltage between a control node (13) and the second load path node (12) to obtain a voltage reading; and Determine at least one of an electrical charge stored in a first internal capacitance (21), or of a capacitance value (C21) of the first internal capacitance (21) effective between the first load path node (11) and the control node (13), based on the voltage measurement and based on a capacitance value of a second internal capacitance (31) effective between the control node (13) and the second load path node (12). [2] Method according to claim 1, further comprising: Determining the capacity value of the second internal capacity (31). [3] Method according to claim 2, wherein determining the capacity value of the second internal capacity (31) comprises: Charging the second internal capacity (31) in one charging process; and Determining the capacity value of the second internal capacity (31) based on a charge supplied to the second internal capacity (31) in the charging process and based on a change in voltage between the control node (13) and the second load path node (12) in the charging process. [4] Method according to any one of claims 1 to 3, further comprising: Connecting an external capacitor (33) between the control node (13) and the second load path node (12) when the voltage with the predefined voltage level is applied between the first load path node (11) and the second load path node (12); and Determining the electric charge stored in the first internal capacitance (21), further based on a capacitance value of the external capacitance. [5] Method according to any one of claims 1 to 4, wherein the transistor device (1) is integrated into a semiconductor body (100), and wherein the semiconductor body (100) is one of a plurality of semiconductor bodies of a wafer (200). [6] Method according to any one of claims 1 to 5, wherein the transistor device (1) is a transistor device with an insulated gate. [7] Method according to claim 6, wherein the transistor device (1) is a MOSFET or an IGBT. [8] Method according to any one of claims 1 to 7, wherein applying the voltage at the predefined voltage level between the first load path node (11) and the second load path node (12) and wherein measuring the voltage between the control node (13) and the second load path node (12) includes using an evaluation circuit (5), wherein the evaluation circuit (5) comprises a first connection (51) configured to be coupled to the first load path node (11), a second connection (52) configured to be coupled to the second load path node (12), and a third connection (53) configured to be coupled to the control node (13). [9] Method according to claim 8, wherein the evaluation circuit (5) comprises a first parasitic capacitance (22) between the first terminal (51) and the third terminal (53) and a second parasitic capacitance (32) between the third terminal (53) and the second terminal (52), and wherein determining the electric charge stored in the first internal capacitance (21) further includes determining the capacitance value based on capacitance values ​​of the first parasitic capacitance (22) and the second parasitic capacitance (32). [10] Method according to any one of claims 1 to 9, wherein the predefined voltage level of the voltage applied between the first load path node (11) and the second load path node (12) is selected such that a voltage between the control node (13) and the second load path node (12), resulting from the voltage applied between the first load path node (11) and the second load path node (12), is lower than a threshold voltage of the transistor device. [11] Method according to any one of claims 1 to 10, wherein the polarity of the voltage applied between the first load path node (11) and the second load path node (12) is such that an internal diode of the transistor device between the first load path node (11) and the second load path node (12) is reverse biased. [12] Method according to any one of claims 1 to 11, further comprising: Determining a capacity value (C21) of the first internal capacity (21) based on the specific electrical charge (Q21) stored in the first internal capacitance (21), and a difference between the voltage level of the load path voltage and the voltage level of the measured voltage between the control node (31) and the second load path node (12). [13] Procedures, including: Determine at least one of an electric charge stored in a first internal capacitance (21) or of a capacitance value (C21) of a first internal capacitance (21) of each of several transistor devices integrated into a wafer (200) using a method according to any one of claims 1 to 12. [14] Method according to claim 13, wherein determining the at least one of the electric charge stored in the first internal capacitance (21) or the capacitance value of each of the multiple transistor devices (1) comprises successively determining the at least one of the electric charge or the capacitance value of the multiple transistor devices (1). [15] Evaluation circuit, comprising a first terminal (51) which is configured to be coupled to a first load path node (11) of a transistor device (1); a second terminal (52) which is configured to be coupled to a second load path node (12) of the transistor device (1); and a third terminal (53) which is configured to be coupled to a control node (13) of the transistor device (1), and set up to determine a capacitance value of a first internal capacitance (21) of the transistor device (1) according to the method of any one of claims 1 to 12. [16] Evaluation circuit according to claim 15, further comprising: an external capacity (33) between the third port (53) and the second port (52). [17] Evaluation circuit according to claim 15 or 16, wherein each of the first terminal (51) and the third terminal (53) comprises a contact needle, and wherein the second terminal (52) comprises a contact plate or a contact needle.

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