QUANTIZATION ERROR AND TRACK ATTENTION IN A DIGITAL PHASE CONTROL LOOP

Abstract

A digital phase-locked loop (DPLL) can include a dither source to provide a dither signal of up to one integer bit on a set of fractional bits of a modulation signal. The DPLL can include a digitally controlled oscillator (DCO) to generate a DPLL output signal. The DPLL can include a primary delta-sigma modulator (DSM) to drive a primary capacitor bank of the DCO based on the dither signal and the modulation signal; a first auxiliary DSM to drive a first auxiliary capacitor bank of the DCO based on the dither signal, thereby canceling any effect of the dither signal on the DPLL output signal; and a second auxiliary DSM to drive a second auxiliary capacitor bank of the DCO based on the modulation signal and the dither signal, thereby canceling any effect of a quantization error in the primary DSM.

Description

BACKGROUND

[0001] A phase-locked loop (PLL) is a device that generates a clock signal and synchronizes it with a reference signal. One application of a PLL is frequency synthesis. In a frequency synthesis application, a PLL can be used to generate a clock signal based on a reference clock (e.g., a reference signal provided by a reference oscillator). Specifically, the frequency of the clock generated by the PLL can be a multiple of the frequency of the original clock signal. A digital phase-locked loop (DPLL) is a type of PLL that uses digital control to synthesize a desired frequency. Components of a DPLL can include a phase detector (e.g., a time-to-digital converter (TDC)), a digital loop filter (DLF), a delta-sigma modulator (DSM), an oscillator, and a divider.In the case of a fully digital PLL (ADPLL), the oscillator is a digitally controlled oscillator (DCO) (instead of a voltage-controlled oscillator (VCO) as used in a conventional PLL). In the operation of a DPLL, the phase detector detects a phase difference between a reference signal and a feedback signal, the feedback signal being generated by splitting an output signal of the DCO. The phase detector converts the phase difference into a phase error signal in the digital domain, and the phase error signal is filtered by the DLF and then used in conjunction with controlling the DCO. SUMMARY

[0002] In some implementations, a DPLL comprises a dither source for providing a dither signal, wherein the dither signal is on the order of up to one integer bit on a set of fractional bits of a modulation signal; a DCO for generating a DPLL output signal at least partially based on the modulation signal, wherein the DCO has a primary capacitor bank, a first auxiliary capacitor bank, and a second auxiliary capacitor bank; a primary DSM for driving the primary capacitor bank based on the dither signal and the modulation signal; and a first auxiliary DSM for driving the first auxiliary capacitor bank based on the dither signal in connection with canceling any effect of the dither signal on the DPLL output signal.and a second auxiliary DSM for driving the second auxiliary capacitor bank based on the modulation signal and the dither signal in connection with canceling out the effect of a quantization error of the primary DSM on the DPLL output signal.

[0003] In some implementations, a DPLL includes a dither source to provide a dither signal that eliminates periodicity from a quantization error of a DSM of the DPLL; a primary signal path containing the DSM; a first auxiliary signal path containing a first auxiliary DSM associated with canceling any effect of the dither signal on an output signal of the DPLL; and a second auxiliary signal path containing a second auxiliary DSM associated with canceling any effect of the quantization error of the primary DSM on the output signal of the DPLL.

[0004] In some implementations, a DPLL comprises a dither source for providing a dither signal, wherein the dither signal is on the order of up to one integer bit on a set of fractional bits of a modulation signal; a DCO for generating a DPLL output signal at least partially based on the modulation signal; a primary DSM for driving a primary capacitor bank of the DCO based on the dither signal and the modulation signal; and a second auxiliary DSM for driving a second auxiliary capacitor bank of the DCO based on the modulation signal and the dither signal in connection with canceling out the effect of at least one quantization error of the primary DSM on the DPLL output signal. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Diagrams 1A-1B illustrate exemplary implementations of a DPLL that provides quantization error correction and trace reduction as described herein. Fig. Figures 2A-2B are diagrams illustrating the effect of a quantization error of a primary DSM provided by the use of a strong dithering signal, as described herein. Fig. Figure 3 is a diagram illustrating an effect on a noise shoulder of a primary DSM provided by the techniques and devices described herein. DETAILED DESCRIPTION

[0005] The following detailed description of example implementations refers to the accompanying drawings. The same reference symbols in different drawings may identify the same or similar elements.

[0006] A DPLL (e.g., an ADPLL) may need to meet a strict specification regarding point-phase noise (also known as emission masking) in a given application. For example, a DPLL used in a communications or radar application may need to meet a strict specification regarding point-phase noise. In particular, a given electromagnetic compatibility (EMC) regulation (e.g., a Federal Communications Commission (FCC) EMC regulation, a European Telecommunications Standards Institute (ETSI) EMC regulation, or similar) may impose a limit on radio frequency offset emissions with respect to both noise and spurs.

[0007] Traditionally, a DPLL includes a DSM (between a DLF and a DCO) to increase the equivalent frequency resolution of the DPLL. Specifically, while the DSM increases the frequency resolution, it also introduces a quantization error. The DSM can be configured to perform high-pass filtering of the quantization error. However, in some scenarios, the contribution of the quantization error introduced by the DSM to phase noise in the DPLL output signal can violate a desired emission mask and thus make compliance with applicable EMC emission control difficult or impossible.

[0008] One technique to address the quantization error introduced by the DSM involves converting a digital signal provided by the DSM into an analog signal using a digital-to-analog converter (DAC). The DAC output is fed to a low-pass filter (LPF) with a cutoff frequency set to filter out a peak in the DSM's quantization noise, thus reducing its impact at high offset frequencies. The LPF output is then used to drive a varactor of a voltage-controlled oscillator (VCO). The cascade of the DAC, LPF, and VCO can be considered an equivalent DCO with filtering of the DSM's quantization noise. However, this technique has several drawbacks, including increased analog design effort, greater layout complexity, and higher power consumption.

[0009] A second technique to correct the quantization error introduced by the DSM is to include an additional digitally controlled capacitor bank in the DCO in parallel with a primary capacitor bank of the DCO. The additional capacitor bank is characterized by a finer frequency gain compared to the primary capacitor bank (e.g., the frequency gain of the additional capacitor bank can be 1 / 8 of the frequency gain of the primary capacitor bank). The additional capacitor bank can be used to cancel the quantization error of the (primary) DSM driving the primary capacitor bank. In operation, the quantization error is extracted with the opposite sign, scaled by a gain equal to a ratio between the frequency gains of the primary capacitor bank and the additional capacitor bank (e.g., a gain of 8), and fed to an additional DSM.If the quantization error cancellation path is adjusted in both amplitude and phase, then the quantization error of the primary DSM is canceled, and the remaining quantization is that of the additional DSM, which is lower in power (phase noise) (e.g., 20 × log). 10 (8) = 18 decibels (dB) lower in the case where the frequency gain of the additional capacitor bank is 1 / 8 that of the primary capacitor bank). Thus, the effect of quantization error on the DPLL output is significantly reduced. This solution is advantageous in that it requires an analog design for the additional capacitor bank and a relatively low-complexity digital circuit for controlling the additional capacitor bank. However, this technique has a fundamental limitation when a ramp is used as a modulation signal (e.g., in a frequency-modulated continuous wave (FMCW) radar application). As in Fig. As shown in Figure 2A, which is discussed in more detail below, there is an inherent periodicity within the extracted quantization error from the primary DSM. Because the additional capacitor bank is inherently non-ideal (i.e., it does not have a perfectly linear frequency response with respect to the controller), this periodicity is converted into spurs by the nonlinearity of the capacitor bank, which can dramatically affect system performance. For example, in an FMCW radar application, the spurs caused by the periodicity of the quantization error can lead to false target detection.

[0010] Some implementations described herein provide a DPLL that attenuates quantization error and spurs. In some implementations, the DPLL may include a dither source to provide a dither signal. The dither signal may be on the order of one integer bit on a set of fractional bits of a modulation signal. The DPLL may further include a DCO to generate a DPLL output signal based at least partially on the modulation signal. The DCO may include a primary capacitor bank, a first auxiliary capacitor bank, and a second auxiliary capacitor bank. The DPLL may also include a primary DSM to drive the primary capacitor bank based on the dither signal and the modulation signal.The DPLL may further include a first auxiliary DSM for driving the first auxiliary capacitor bank based on the dither signal, thereby canceling any effect of the dither signal on the DPLL output signal. The DPLL may further include a second auxiliary DSM for driving the second auxiliary capacitor bank based on the modulation signal and the dither signal, thereby canceling any effect of a quantization error of the primary DSM on the DPLL output signal.

[0011] The DPLL described here avoids the limitations of the technique described above, which uses an additional DSM to cancel the quantization error of the primary DSM. For example, the DPLL described here can disrupt the periodicity of the primary DSM's quantization error by means of a strong dither source placed before the primary DSM. Typically, dithering is a technique used to prevent trace generation from a DSM (e.g., pattern noise), where a dither signal is relatively small. Conversely, in the DPLL described here, the dither source is strong enough to scramble the generation of the primary DSM's quantization error, thereby removing any periodicity in the quantization error. Of course, this strong dither signal is undesirable from a phase noise perspective, as the dither signal would compromise the noise performance.For this reason, the DPLL described here has a signal path that cancels out the dither signal. Additional details are provided below.

[0012] Fig. Diagrams 1A-1B illustrate exemplary implementations of a DPLL 100, which provides quantization error correction and trace reduction. As shown in Fig. As shown in Figures 1A-1B, the DPLL 100 can include a reference oscillator (REF) 102, a TDC 104, a DLF 106, a group of DSMs 108 (e.g., a DSM 108a, a DSM 108b, and a DSM 108c), a DCO 110 comprising a group of capacitor banks 112 (e.g., a capacitor bank 112a, a capacitor bank 112b, and a capacitor bank 112c), a frequency divider 114, and a dither source 116.

[0013] The REF 102 is a component configured to provide a reference signal. That is, the REF 102 is a component that provides a reference signal upon which an output signal (identified as in Fig. 1A-1B) of the DPLL 100 is to be generated and with which the output signal is to be synchronized. The reference signal is in Fig. 1A-1B are marked as r.

[0014] The TDC 104 is a component configured to provide a phase error signal that indicates a phase difference between the reference signal and a feedback signal. That is, the TDC 104 can detect a phase difference between the reference signal and the feedback signal generated by the DPLL 100. The phase error signal and the feedback signal are in Fig. 1A-1B are labeled e and fb, respectively. As shown, in some implementations the feedback signal is an output value of the DIV 114. Thus, in some implementations the feedback signal is the frequency-divided output signal that is output by the DIV 114.

[0015] The DLF 106 is a component configured to control the DSM 108 or the DCO 110 based on the phase error signal provided by the TDC 104. That is, the DLF 106 can be configured to receive the phase error signal and adjust the control of the DSM 108 or the DCO 110 based on the phase error signal (e.g., to improve the synchronization between the reference signal and the output signal of the DPLL 100). In some implementations, an output value of the DLF 106 is a modulation signal. The modulation signal is in Fig. 1A-1B are marked as m.

[0016] The DSM 108a (also referred to as the primary DSM 108a) is a component configured to increase the equivalent frequency resolution of the DPLL 100. In some implementations, the primary DSM 108a may be configured to drive the primary capacitor bank 112a based on the dither signal and the modulation signal. In some implementations, as in Fig. Figures 1A-1B illustrate an input signal of the primary DSM 108a, a signal resulting from the summation of a dither signal provided by the dither source and the modulation signal provided by the DLF 106.

[0017] The DSM 108b (also referred to as the first auxiliary DSM 108b) is a component configured to drive the first auxiliary capacitor bank 112b based on the dither signal. In some implementations, the first auxiliary DSM 108b drives the first auxiliary capacitor bank 112b in connection with canceling the effect of the dither signal on the output signal of the DPLL 100, as described below. In some implementations, an input signal to the first auxiliary DSM 108b is a signal resulting from inversion and scaling (e.g., by gaining g). b ) of the dither signal provided by the dither source 116.

[0018] The DSM 108c (also referred to as the second auxiliary DSM 108c) is a component configured to drive the second auxiliary capacitor bank 112c based on the modulation signal and the dither signal. In some implementations, the second auxiliary DSM 108c drives the second auxiliary capacitor bank 112c in connection with canceling the effect of a quantization error of the primary DSM 108a on the output signal of the DPLL 100, as described below. In some implementations, as in Fig. 1A shows an input signal of the second auxiliary DSM 108c, a signal resulting from scaling (e.g., by amplification g). c ) of a differential signal associated with the primary DSM 108a. The differential signal associated with the primary DSM 108a is in Fig. 1A-1B as -q aThis is indicated. Here, the difference signal associated with the primary DSM 108a corresponds to a quantization error of the primary DSM 108a. That is, in some implementations, the input signal of the second auxiliary DSM 108c is a difference between the input value of the primary DSM 108a and an output value of the primary DSM 108a, scaled by g. c .

[0019] Additionally, in some implementations, the second auxiliary DSM 108c can drive the second auxiliary capacitor bank 112c in connection with canceling the effect of a quantization error of the first auxiliary DSM 108b on the output signal of the DPLL 100, as described below. In some such implementations, as in Fig. Figure 1B shows an input signal of the second auxiliary DSM 108c, a signal resulting from the summation of the scaled difference signal associated with the primary DSM 108a (e.g., the signal -q). a , scaled by the amplification g c), and a scaled difference signal associated with the first auxiliary DSM 108b. The scaled difference signal associated with the first auxiliary DSM 108b is in Fig. 1B as -q b This is indicated. Here, the scaled difference signal assigned to the first auxiliary DSM 108b corresponds to a quantization error of the first auxiliary DSM 108b. Thus, in some implementations, the input signal of the second auxiliary DSM 108c is a difference between the input value of the primary DSM 108a and an output value of the primary DSM 108a, scaled by g. c , plus a difference between an input value of the first Auxiliary DSM 108b and an output value of the first Auxiliary DSM 108b.

[0020] In some implementations, the amplification g b , which is applied to the dither signal (e.g., the gain applied to a signal path of the first auxiliary DSM 108b), differs from the gain g c, which is applied to the differential signal associated with the primary DSM 108a (e.g., the gain applied to a signal path of the second auxiliary DSM 108c). Alternatively, in some implementations, the gain g b , which is applied to the dither signal, should be the same as the gain g c , which is applied to the differential signal associated with the primary DSM 108a. In some implementations, the gain g is based on b , which is applied to the dither signal, on a gain factor of the first auxiliary capacitor bank 112b. Likewise, the gain g can be c , which is applied to the differential signal associated with the primary DSM 108a, in some implementations are based on a gain factor of the second auxiliary capacitor bank 112c.

[0021] The DCO 110 is a component configured to generate the output signal of the DPLL 100. In some implementations, the DCO 110 comprises capacitor bank 112a (also referred to as the primary capacitor bank 112a), capacitor bank 112b (referred to as the first auxiliary capacitor bank 112), and capacitor bank 112c (referred to as the second auxiliary capacitor bank 112). In some implementations, the DCO 110 generates the output signal of the DPLL 100 based on the outputs of the primary capacitor bank 112a, the first auxiliary capacitor bank 112b, and the second auxiliary capacitor bank 112c. In some implementations, a frequency or other characteristic of the output signal generated by the DCO 110 is controlled by the DLF 106, as described above. In some implementations, such as in Fig. As shown in Figures 1A-1B, the DCO 110 can be configured to provide the output signal to the DIV 114 (in addition to providing the output signal as an output value of the DPLL 100). In some implementations, the first auxiliary capacitor bank 112b has a first gain factor (in Fig. 1A-1B (labeled 1 / b) and the second auxiliary capacitor bank 112c has a second gain factor (in Fig. (1A-1B are labelled as 1 / c). In some implementations, the first gain factor differs from the second gain factor. Alternatively, the first gain factor of the first auxiliary capacitor bank 112b can be the same as the second gain factor of the second auxiliary capacitor bank 112c. In one example, the gain factor of the first auxiliary capacitor bank 112 and the gain factor of the second auxiliary capacitor bank 112c can be 1 / 8 (e.g., 1 / b = 1 / c = 1 / 8), so that the frequency gains of the first auxiliary capacitor bank 112b and the second auxiliary capacitor bank 112c are scaled by a factor of 1 / 8 compared to the LSB (Less Significant Bit) gain of the primary capacitor bank 112a.

[0022] The DIV 114 is a component configured to perform frequency division on the output signal of the DPLL 100 to generate the frequency-split output signal. In some implementations, the frequency-split output signal has a frequency matching the frequency of the reference signal and a phase matching the phase of the output signal. In some implementations, the DIV 114 provides the feedback signal to the TDC 104.

[0023] The dither source 116 is a component configured to provide a dither signal. In some implementations, the dither signal is used to scramble the generation of the primary DSM 108a's quantization error, thereby removing periodicity from the primary DSM 108a's quantization error. In some implementations, the dither signal is a strong dither signal. For example, the dither signal may be on the order of up to one integer bit of the modulation signal (e.g., almost an entire fraction of an integer bit, such as ±0.9999). In some implementations, the dither signal is a zero-average signal (e.g., to prevent the dither signal from corrupting the output signal of the DPLL 100). In some implementations, the dither signal is a random signal, meaning that the values ​​of the dither signal are generated randomly.The effect of this randomization is to scramble the quantization error of the primary DSM 108a, as mentioned above.

[0024] In an exemplary company in Fig. In the DPLL 100 shown in Figure 1A, the dither signal d, provided by the dither source 116, is summed with the modulation signal m, provided by the DLF 106, on a primary signal path. This result is provided as an input value for the primary DSM 108a. An output value of the primary DSM 108a, which is displayed in Fig. 1A as s a The primary capacitor bank 112a of the DCO 110 is controlled by the signal marked as such. On a first auxiliary signal path, the dither signal d is inverted and amplified by the gain g. b The scaled result is provided as an input value for the first auxiliary DSM 108b. An output value of the first auxiliary DSM 108b, which is in Fig. 1A as s bThe first auxiliary capacitor bank 112b of the DCO 110 is controlled by the signal. On a second auxiliary signal path, the input value of the primary DSM 108a (i.e., a result of summing the dither signal d and the modulation signal m) and the output value of the primary DSM 108a are used to generate a differential signal -q. a to generate a value corresponding to the quantization error of the primary DSM 108a. The difference signal -q a is increased by g c scaled, and a resulting signal is provided as an input value for the second auxiliary DSM 108c. An output value of the second auxiliary DSM 108c, which is in Fig. 1A as s cThe second auxiliary capacitor bank 112c of the DCO is controlled by the label. The DCO 110 generates the output signal out based on the output values ​​of the primary capacitor bank 112a, the first auxiliary capacitor bank 112b, and the second auxiliary capacitor bank 112c. In this example, the first auxiliary capacitor bank 112b serves to cancel the effect of the dither signal d on the output signal out of the DPLL 100, and the second auxiliary capacitor bank 112c serves to cancel the effect of the quantization error of the primary DSM 108a on the output signal out of the DPLL 100.

[0025] In an exemplary company in Fig. In the DPLL 100 shown in Figure 1B, the dither signal d, provided by the dither source 116, is summed with the modulation signal m, provided by the DLF 106, on a primary signal path. This result is provided as an input value for the primary DSM 108a. An output value of the primary DSM 108a, which is displayed in Figure 1B, is then used to calculate the output value of the modulation signal m. Fig. 1B as s a The primary capacitor bank 112a of the DCO 110 is controlled by the signal marked as such. On a first auxiliary signal path, the dither signal d is inverted and amplified by the gain g. b The scaled result is provided as an input value for the first auxiliary DSM 108b. An output value of the first auxiliary DSM 108b, which is in Fig. 1B as s bThe first auxiliary capacitor bank 112b of the DCO 110 is controlled by the signal. On a second auxiliary signal path, the input value of the primary DSM 108a (i.e., a result of summing the dither signal d and the modulation signal m) and the output value of the primary DSM 108a are used to generate a differential signal -q. a to generate a value corresponding to the quantization error of the primary DSM 108a. The difference signal -q a is increased by g c scaled. Furthermore, the input value of the first auxiliary DSM 108b (i.e., a result of inverting and scaling the dither signal d by the gain g) is scaled. b ) and the output value of the first auxiliary DSM 108b is used to generate a differential signal -q b to generate a value corresponding to the quantization error of the first auxiliary DSM 108b. The scaled difference signal -q a is used with the difference signal -q bThe results are summed, and one of these is provided as an input value for the second auxiliary DSM 108c. An output value of the second auxiliary DSM 108c, which is in Fig. 1B as s c The second auxiliary capacitor bank 112c of the DCO is controlled by the capacitor bank 110. The DCO 110 generates the output signal out based on the output values ​​of the primary capacitor bank 112a, the first auxiliary capacitor bank 112b, and the second auxiliary capacitor bank 112c. In this example, the first auxiliary capacitor bank 112b serves to cancel the effect of the dither signal d on the output signal out of the DPLL 100, and the second auxiliary capacitor bank 112c serves to cancel the effect of the quantization error of the primary DSM 108a and the effect of the quantization error of the first auxiliary DSM 108b on the output signal out of the DPLL 100.

[0026] In this way, the DPLL 100 can be used to interrupt the periodicity of the quantization error of the primary DSM 108a by means of the dither signal d, which is sufficiently strong to scramble the generation of the quantization error of the primary DSM 108a, thereby removing the periodicity in the quantization error of the DSM 108a. Furthermore, the DPLL 100 cancels out the effect of the dither signal d such that the dither signal d has no effect on an output signal of the DPLL 100. As a result, the primary DSM 108a can perform intended high-pass shaping, while reducing or eliminating the effect of the quantization error introduced by the primary DSM 108a on phase noise in the output signal of the DPLL 100, thereby preventing emission mask violation and enabling compliance with applicable EMC emission control.

[0027] As stated above, Fig. Examples 1A-1B are provided. Other examples may differ from what is described in relation to Fig. 1A-1B is described. The number and arrangement of components that are in Fig. Figures 1A-1B are provided as an example. In practice, there may be additional components, fewer components, different components, or components arranged differently than those shown. Fig. shown in 1A-1B. Furthermore, two or more components shown in Fig. 1A-1B are shown, being implemented within a single component, or a single component that is in Fig. As shown in 1A-1B, it can be implemented as multiple, distributed components. Additionally or alternatively, a set of in Fig. The components shown in 1A1B (e.g., one or more components) perform one or more functions that are defined by another set of components in Fig. The components shown in 1A-1B are described.

[0028] Fig. 2A-2B are diagrams illustrating an effect on the quantization error of the primary DSM 108a provided by the use of the strong dither signal d. Fig. Figure 2A illustrates an example of a quantization error of a primary DSM in a DPLL, which provides quantization error cancellation using an additional DSM in a conventional manner (i.e., without using a strong dither signal as described herein). Fig. Figure 2B illustrates an example of a quantization error of the primary DSM 108a in the DPLL 100 described herein. As in Fig. As can be seen in Figure 2A, the quantization error of the primary DSM in the conventional DPLL exhibits a periodic pattern. Comparatively, as in Fig. 2B shows the periodicity removed from the quantization error of the primary DSM 108a due to the use of the strong dither signal.

[0029] As stated above, Fig. 2A-2B are provided as examples. Other examples may differ from what is provided in relation to Fig. 2A-2B is described.

[0030] Fig. Figure 3 is a diagram illustrating the effect on a noise shoulder of the primary DSM 108a provided by the techniques and devices described herein. The dark curve in Fig. Figure 3 represents the phase noise in an output value of a conventional DPLL, while the lighter gray curve in Fig. 3 represents the phase noise in an output value of the DPLL 100 (e.g., in terms of decibels referenced to a carrier in a hertz bandwidth (dBc / Hz) over the frequency (f)). In some scenarios, the phase noise in the DPLL 100, as in Fig. 3 illustrates that it must be sufficiently low so that an emission mask is not violated in a given frequency range, and can therefore enable compliance with an applicable EMC emission control.

[0031] As stated above, Fig. 3 is provided as an example. Other examples may differ from what is provided in relation to Fig. 3 is described.

[0032] According to an example, the reinforcement g c and the reinforcement g b The gains described in the examples above can be implemented as a constant gain. According to another example, one or both of the gains g can be implemented as a constant gain. c and the reinforcement g bThe gain described in the examples above can be implemented as a dynamically varying gain. The dynamically varying gain can be determined, for example, based on the frequency to be generated by the DPLL 100. The use of a dynamically varying gain g b enables the correction of variations across the frequency band of the ratio between the frequency gains of the primary capacitor bank 112a and the first auxiliary capacitor bank 112b and a dynamically varying gain g. c This enables the correction of variations across the frequency band in the ratio between the frequency gains of the primary capacitor bank 112a and the second auxiliary capacitor bank 112c. The dynamically varying gains g b and g ccan be implemented using a lookup table, where the gain is selected based on the frequency to be generated by the DPLL 100. In other examples, the dynamically varying gains g b and g c during operation, they can be dynamically calculated or estimated using, for example, interpolation circuits or least-mean-squares machines.

[0033] The foregoing disclosure provides illustration and description but is not intended to be exhaustive or to restrict implementations to the exact forms disclosed. Modifications and variations may be made in light of the foregoing disclosure or may be derived from practical implementation experience.

[0034] As used herein, the term "component" shall be understood generally to mean hardware, firmware, and / or a combination of hardware and software. It is evident that systems and / or procedures described herein may be implemented in various forms of hardware, firmware, or a combination of hardware and software. The actual specialized control hardware or software code used to implement these systems and / or procedures does not restrict the implementations. Thus, the operation and behavior of the systems and / or procedures are described herein without reference to specific software code—it is understood that software and hardware may be designed to implement the systems and / or procedures based on the description herein.

[0035] As used herein, meeting a threshold may, depending on the context, refer to a value that is greater than the threshold, greater than or equal to the threshold, less than the threshold, less than or equal to the threshold, equal to the threshold, not equal to the threshold, or the like.

[0036] Even if certain combinations of features are specified in the claims and / or disclosed in the description, these combinations are not intended to limit the disclosure of different implementations. In fact, many of these features can be combined in ways not specifically specified in the claims and / or disclosed in the description. Although each dependent claim listed below may depend directly on only one claim, the disclosure of different implementations includes each dependent claim in combination with every other claim in the claim set. As used herein, an expression referring to "at least one of" a list of elements refers to any combination of those elements, including single elements. As an example, "at least one of: a, b, or c" is intended to cover a, b, c, ab, ac, bc, and abc, as well as any combination with multiples of the same element.

[0037] When "a component" or "one or more components" (or another element, such as "a controller" or "one or more controllers") are described or claimed (within a single claim or across multiple claims) to perform or be configured to perform multiple operations, this language is intended to generally cover a wide variety of architectures and environments. Unless expressly claimed otherwise (e.g.,(via the use of "first component" and "second component" or any other language that distinguishes components in the claims), this language shall, for example, cover a single component that performs all operations or is configured to perform all operations, a group of components that perform all operations together or are configured to perform all operations, a first component that performs a first operation or is configured to perform a first operation, and a second component that performs a second operation or is configured to perform a second operation, or any combination of components that perform the operations or are configured to perform the operations.For example, if a claim takes the form "one or more components configured to: perform X; perform Y; and perform Z", then that claim should be interpreted as meaning "one or more components configured to perform X; one or more (possibly different) components configured to perform Y; and one or more (also possibly different) components configured to perform Z".

[0038] No element, action, or instruction used herein should be construed as critical or essential unless expressly described as such. Furthermore, the article "the," as used herein, shall encompass one or more elements referred to in conjunction with the article "the," and may be used interchangeably with "the one or the several." Furthermore, the terms "has," "have," "have," or the like, as used herein, shall be open terms. Furthermore, the phrase "based on" shall mean "at least partly based on" unless expressly stated otherwise. Furthermore, the term "or," as used herein, shall be inclusive when used in a series and may be used interchangeably with "and / or" unless expressly stated otherwise (e.g., when used in combination with "either" or "only one of").

Claims

[1] Digital phase-locked loop, which has the following features: a dither source for providing a dither signal, wherein the dither signal is on the order of up to one integer bit on a set of fractional bits of a modulation signal; a digitally controlled oscillator for generating a digital phase-locked loop output signal based at least partially on the modulation signal, wherein the digitally controlled oscillator comprises a primary capacitor bank, a first auxiliary capacitor bank and a second auxiliary capacitor bank; a primary delta-sigma modulator for driving the primary capacitor bank based on the dither signal and the modulation signal; a first auxiliary delta-sigma modulator for driving the first auxiliary capacitor bank based on the dither signal in connection with canceling the effect of the dither signal on the digital phase-locked loop output signal; and a second auxiliary delta-sigma modulator for driving the second auxiliary capacitor bank based on the modulation signal and the dither signal in connection with canceling out the effect of a quantization error of the primary delta-sigma modulator on the digital phase-locked loop output signal. [2] Digital phase-locked loop according to claim 1, wherein the second auxiliary delta-sigma modulator is provided to control the second auxiliary capacitor bank in connection with canceling an effect of a quantization error of the first auxiliary delta-sigma modulator on the digital phase-locked loop output signal. [3] Digital phase-locked loop according to claim 1 or 2, wherein the dither signal is provided to scramble the generation of the quantization error of the primary delta-sigma modulator in order to remove the periodicity from the quantization error of the primary delta-sigma modulator. [4] Digital phase-locked loop according to any one of claims 1 to 3, wherein the dither signal is a zero-average signal. [5] Digital phase-locked loop according to any one of claims 1 to 4, wherein an input signal of the primary delta-sigma modulator is a signal resulting from the summation of the dither signal and the modulation signal. [6] Digital phase-locked loop according to any one of claims 1 to 5, wherein an input signal of the first auxiliary delta-sigma modulator is a signal resulting from inverting and scaling the dither signal. [7] Digital phase-locked loop according to any one of claims 1 to 6, wherein an input signal of the second auxiliary delta-sigma modulator is a signal resulting from the summation of a scaled differential signal associated with the primary delta-sigma modulator and a scaled differential signal associated with the first auxiliary delta-sigma modulator. [8] Digital phase-locked loop according to any one of claims 1 to 7, wherein the first auxiliary capacitor bank has a first gain factor and the second auxiliary capacitor bank has a second gain factor. [9] Digital phase-locked loop according to any one of claims 1 to 8, wherein a first gain is applied to a signal path of the first auxiliary delta-sigma modulator and a second gain is applied to a signal path of the second auxiliary delta-sigma modulator. [10] Digital phase-locked loop, which has the following features: a dither source for providing a dither signal that eliminates the periodicity from a quantization error of a primary delta-sigma modulator of the digital phase-locked loop; a primary signal path that features the primary delta-sigma modulator; a first auxiliary signal path that includes a first auxiliary delta-sigma modulator associated with canceling the effect of the dither signal on an output signal of the digital phase-locked loop; and a second auxiliary signal path which includes a second auxiliary delta-sigma modulator in connection with canceling the effect of the quantization error of the primary delta-sigma modulator on the output signal of the digital phase-locked loop. [11] Digital phase-locked loop according to claim 10, wherein the second auxiliary delta-sigma modulator is associated with canceling the effect of a quantization error of the first auxiliary delta-sigma modulator on the output signal of the digital phase-locked loop. [12] Digital phase-locked loop according to claim 10 or 11, wherein the dither signal is on the order of up to one integer bit on a set of fractional bits of a modulation signal. [13] Digital phase-locked loop according to one of claims 10 to 12, wherein the dither signal is provided to scramble the generation of the quantization error of the primary delta-sigma modulator. [14] Digital phase-locked loop according to any one of claims 10 to 13, wherein the dither signal is a zero-average signal. [15] Digital phase-locked loop according to any one of claims 10 to 14, wherein an input signal of the primary delta-sigma modulator is a signal resulting from the summation of the dither signal and a modulation signal. [16] Digital phase-locked loop according to any one of claims 10 to 15, wherein an input signal of the first auxiliary delta-sigma modulator is a signal resulting from inverting and scaling the dither signal. [17] Digital phase-locked loop according to any one of claims 10 to 16, wherein an input signal of the second auxiliary delta-sigma modulator is a signal resulting from the summation of a scaled differential signal associated with the primary delta-sigma modulator and a scaled differential signal associated with the first auxiliary delta-sigma modulator. [18] Digital phase-locked loop according to any one of claims 10 to 17, wherein a first gain is applied to a signal path of the first auxiliary delta-sigma modulator and a second gain is applied to a signal path of the second auxiliary delta-sigma modulator, wherein the second gain differs from the first gain. [19] Digital phase-locked loop according to any one of claims 10 to 18, further comprising a digitally controlled oscillator comprising a primary capacitor bank on the primary signal path, a first auxiliary capacitor bank on the first auxiliary signal path and a second auxiliary capacitor bank on the second auxiliary signal path. [20] Digital phase-locked loop, which has the following features: a dither source for providing a dither signal, wherein the dither signal is on the order of up to one integer bit on a set of fractional bits of a modulation signal; a digitally controlled oscillator for generating a digital phase-locked loop output signal based at least partially on the modulation signal; a primary delta-sigma modulator for driving a primary capacitor bank of the digitally controlled oscillator based on the dither signal and the modulation signal; and a second auxiliary delta-sigma modulator for driving a second auxiliary capacitor bank of the digitally controlled oscillator based on the modulation signal and the dither signal in connection with canceling out the effect of at least one quantization error of the primary delta-sigma modulator on the digital phase-locked loop output signal. [21] Digital phase-locked loop according to claim 20, which further comprises a first auxiliary delta-sigma modulator for driving a first auxiliary capacitor bank of the digitally controlled oscillator based on the dither signal in connection with canceling an effect of the dither signal on the digital phase-locked loop output signal. [22] Digital phase-locked loop according to claim 21, wherein the second auxiliary delta-sigma modulator is provided to control the second auxiliary capacitor bank in connection with canceling an effect of a quantization error of the first auxiliary delta-sigma modulator on the digital phase-locked loop output signal.

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