Stacked dies enclosure with electrical shielding plate

Abstract

A semiconductor package structure comprises a substrate with a substrate surface, a processing device electrically coupled to the substrate surface, one or more radio frequency integrated circuits (RFICs) electrically coupled to the substrate surface, and a shielding plate. The shielding plate is positioned between the one or more RFICs and the processing device and is configured to couple the one or more RFICs to a package ground via one or more conductors. The package ground has a ground voltage associated with the semiconductor package structure.

Description

RELATED REGISTRATIONS

[0001] This application claims priority over provisional application No. 63 / 672,660, filed on 17 July 2024, which is incorporated by reference in its entirety. TECHNICAL AREA

[0002] Aspects and implementations of the present disclosure relate to die packages and, in particular, to a stacked die package with an electrical shielding plate. BACKGROUND

[0003] A die package (e.g., a semiconductor package structure) is an assembled form of an integrated circuit (IC). The die package can provide mechanical protection, electrical connections, and other features for the IC. It enables the secure integration of the IC into electronic systems, such as printed circuit boards (PCBs). The die package can contain one or more ICs in the final configuration. BRIEF DESCRIPTION OF THE FIGURES

[0004] The present disclosure is illustrated by way of example and without limitation in the figures of the accompanying drawings, in which the same reference numerals denote similar elements. It should be noted that different references to “a” or “a single” embodiment in this disclosure do not necessarily refer to the same embodiment and such references signify at least one. Fig. Figure 1A is a schematic block diagram of an exemplary semiconductor package structure comprising a spacer and a leadframe, according to some embodiments. Fig. Figure 1B is a schematic block diagram of an exemplary semiconductor package structure comprising a spacer and a laminate substrate, according to some embodiments. Fig. Figure 1C is a schematic block diagram of a top-down perspective of an exemplary semiconductor package structure according to some embodiments. Fig. Figure 2A is a schematic block diagram of an exemplary semiconductor package structure comprising a spacer and a leadframe, according to some embodiments. Fig. Figure 2B is a schematic block diagram of an exemplary semiconductor package structure comprising a spacer and a laminate substrate, according to some embodiments. Fig. Figure 3A is a schematic block diagram of an exemplary semiconductor package structure comprising a memory device and a leadframe, according to some embodiments. Fig. Figure 3B is a schematic block diagram of an exemplary semiconductor package structure comprising a storage device and a laminate substrate, according to some embodiments. Fig. Figure 4 is a schematic block diagram of an exemplary semiconductor package structure comprising a double-sided substrate, according to some embodiments. Fig. Figure 5A is a schematic block diagram of a single-sided shielding plate with a single ground plane according to one embodiment. Fig. Figure 5B is a schematic block diagram of a double-sided shielding plate with two ground planes according to some embodiments. Fig. Figure 6 presents a flowchart of an exemplary process for manufacturing a semiconductor package structure according to some embodiments. DETAILED DESCRIPTION

[0005] In the context of microcontroller chip applications, such as those found in wearable devices, healthcare products, and home or industrial automation systems, there is a growing need for Bluetooth® and Wi-Fi® connectivity. However, integrating Bluetooth® and Wi-Fi® intellectual property (IP) blocks into a microcontroller unit (MCU) system-on-chip (SoC) can be a resource-intensive and time-consuming process, potentially increasing development costs. To accelerate time to market, an approach that integrates a dedicated, standalone Bluetooth® and Wi-Fi® connectivity chip with the MCU in the same package is recommended. This approach not only simplifies development but also facilitates faster product launches.

[0006] With the growing demand for smaller and smaller portable devices and other microcontroller chip applications, there is a parallel increase in demand for smaller and smaller die packages (e.g., semiconductor package structures). To efficiently utilize the available surface area of ​​a microcontroller chip's substrate, integrated circuits (ICs) can be stacked to form a stacked-die package. Stacking a high-frequency (HF) chip implementing Bluetooth® and Wi-Fi® technologies on a single MCU chip provides the shortest die-to-die connections and a smaller package footprint, enabling the design of miniaturized products.

[0007] However, this stacking arrangement can introduce challenges related to electrical noise coupling, especially when high-frequency RF chips are involved, which are sensitive to electromagnetic (EM) interference. For example, a radio frequency integrated circuit (RFIC) is a type of IC designed to generate and transmit EM waves (e.g., radio waves) for wireless communication. RFICs are sensitive to EM radiation and can experience performance problems when exposed to external EM fields (e.g., from EM fields, waves, or radiation from another IC). Since other ICs, such as microcontrollers (MCUs), emit EM fields through their operations, stacking an EM-sensitive IC (e.g., an RFIC) on top of an EM-emitting IC (e.g., an MCU) would cause the EM-sensitive IC to experience performance problems related to electrical noise coupling.Such noise coupling can lead to reduced signal quality and potential malfunctions in the RFIC chip.

[0008] To avoid EM-sensitive ICs experiencing such problems, they are conventionally placed in a side-by-side configuration with EM-emitting ICs. While this can reduce the performance issues experienced by the EM-sensitive IC, such a configuration often uses up to twice the available surface area of ​​the substrate, resulting in larger die packages and wasted substrate surface area.

[0009] Aspects and embodiments of the present disclosure address these and other limitations of existing technology by providing a stacked die package with an electrical shielding plate. In some embodiments, the die package (e.g., the semiconductor package structure) comprises a substrate, a processing device, one or more RFICs, and a shielding plate. The processing device (e.g., an EM-emitting IC, such as an MCU) and the RFIC(s) (e.g., EM-sensitive ICs) may be electrically coupled to the surface of the substrate. In some embodiments, the shielding plate is positioned between the processing device and the RFIC(s) and configured to couple the RFIC(s) to the semiconductor package ground via conductors.

[0010] The systems, devices, and methods disclosed herein offer advantages over conventional solutions. By placing the shielding plate between the processing device and the RFIC(s), the EM-sensitive IC(s) are shielded from the EM emitted by the EM-emitting IC(s), thereby reducing power problems, signal integrity issues, and / or instances of device failure. Furthermore, placing the shielding plate between the processing device and the RFIC(s) allows the RFIC(s) to be stacked on the processing device, reducing the amount of substrate surface area utilized by the die package. This reduces the overall size of the die package and minimizes wasted substrate surface area.

[0011] Technologies directed towards a stacked-dies package with an electrical shielding plate are described in this disclosure. The following description presents numerous specific details, such as examples of specific systems, components, methods, and so on, to provide a good understanding of several embodiments of this disclosure. However, it will be obvious to a person skilled in the art that at least some embodiments of this disclosure can be carried out without these specific details. In other cases, well-known components or methods are not described in detail or are presented in a simple block diagram format to avoid unnecessary obfuscation of this disclosure. Thus, the specific details presented are merely exemplary.Certain implementations may differ from these exemplary details and still be considered to be within the scope of protection of the present disclosure.

[0012] Fig. Figures 1A-B are schematic block diagrams of an exemplary semiconductor package structure according to some embodiments. Fig. Figure 1A is a schematic block diagram of an exemplary semiconductor package structure 100A comprising a leadframe 116, according to one embodiment. Fig. Figure 1B is a schematic block diagram of an exemplary semiconductor package structure 100B comprising a laminate substrate 126, according to one embodiment. Both Fig. 1A as well Fig. 1B shows essentially similar components, but with a different housing substrate.

[0013] In some embodiments, the semiconductor package structure 100A is mounted on a leadframe 116 and comprises one or more RFICs 102, a shielding plate 108, and a processing device 122. The components of the semiconductor package structure 100A can be attached to a package mass 120 of the leadframe 116 by a first die-bonding layer 124. A die-bonding layer can be used to physically bond the other components of the semiconductor package structure 100A to the leadframe 116 and can comprise materials such as adhesives (e.g., film adhesive, epoxy, etc.), solder, die-bonding films (DAFs), etc. In some embodiments, the die-bonding layer can be an epoxy that cures to form a hard layer (e.g., puncture-resistant) to create a permanent bond. In other embodiments, the die attachment layer can be a protective film (e.g.,The protective film is applied using a film-over-wire (FOW) technique over the bond wires that connect the components of the semiconductor package structure 100A to the substrate (e.g., the leadframe 116). The protective film can shield the bond wires from mechanical stress, contamination, and / or moisture while maintaining the electrical integrity of the connections. The protective film can also act as a spacer to physically separate different components of the semiconductor package structure 100A from the bond wires of those components.

[0014] The semiconductor package structure 100A can configure the various components (e.g., dies, ICs, etc.) in a stacked arrangement, allowing one or more ICs to be stacked on top of another IC. In some embodiments, the first IC in such a stacked configuration can be the processing device 122. The processing device 122 can be a microcontroller unit (MCU), an application-specific integrated circuit (ASIC), a microprocessor unit (MPU), a field-programmable gate array (FGPA), etc. In some embodiments, the processing device 122 is an MCU secured to the package ground 120 by the first die mounting layer 124. The MCU can be electrically coupled to the package ground 120 and to one or more package leads 118 of the leadframe 116.In some embodiments, the MCU is electrically coupled to the chassis ground 120 via one or more ground connectors 110 and to one or more chassis leads 118 via one or more signal and / or power connectors 114. The ground connectors 110 and / or the signal and / or power connectors 114 can be conductors (e.g., materials that allow an electric current to flow).

[0015] In some embodiments, the shielding plate 108 is connected to and positioned above the processing device 122 via a second die mounting layer 112. The second die mounting layer 112 can be a protective film to protect the bond wires of the processing device 122 and to allow the ground connectors 110 and / or the signal and / or power connectors 114 from the processing device 122 to pass through the second die mounting layer 112. In some embodiments, the shielding plate 108 includes a ground plane 106, which can be a metal layer, electrically coupled to the housing ground 120 via one or more ground connectors 110. The ground plane 106, when connected to the chassis ground 120, can act as a conductive path between the one or more RFICs 102 and the chassis ground 120 to help reduce EM interference from the processing device 122.In some embodiments, the shielding plate 108 is a silicon material (e.g., a silicon wafer) and the ground plane 106 is a metal layer of aluminum (Al) and / or copper (Cu). In some embodiments, the shielding plate 108 may have more than one ground plane 106. A shielding plate 108 with a single ground plane 106 may be referred to as a single-sided shielding plate, and a shielding plate 108 with more than one ground plane 106 may be referred to as a double-sided shielding plate.

[0016] The semiconductor package structure 100A can include one or more RFICs 102 stacked on the top surface of the shielding plate 108. The shielding plate 108 can be larger than the RFIC(s) 102 (e.g., having a larger surface area than a single RFIC and / or multiple RFICs in a side-by-side configuration). In some embodiments, the one or more RFICs 102 are attached to the ground plane 106 of the shielding plate 108 via a third die mounting layer 104, which can be made of a material substantially similar to the first die mounting layer 124 and / or the second die mounting layer 112. In some embodiments, the third die mounting layer 104 is a different material than the first die mounting layer 124 and / or the second die mounting layer 112.

[0017] The RFIC(s) 102 can be electrically coupled to the ground plane 106 of the shielding plate 108 via one or more ground connectors 110. Since the ground plane 106 is electrically connected (e.g., electrically coupled) to the chassis ground 120, the RFIC(s) 102 are, according to some embodiments, also electrically coupled to the chassis ground 120 via ground connectors 110. The RFIC(s) 102 can be electrically coupled to the chassis ground 120 and one or more chassis leads 118 of the leadframe 116. In some embodiments, the RFIC(s) 102 are electrically coupled to the chassis ground 120 via one or more ground connectors 110 and to one or more chassis leads 118 via one or more signal and / or power connectors 114.

[0018] The RFIC(s) 102 can be a short-range wireless communication IC (e.g., a Bluetooth® IC), a short-range low-power wireless communication IC (e.g., a Bluetooth® Low Energy (BLE) IC), a wireless local area network (WLAN) communication IC (e.g., a Wi-Fi® IC), a radio frequency IC (e.g., a millimeter-wave IC), a photonic IC (e.g., an optical IC), or various other electromagnetically sensitive ICs. In some embodiments, the RFIC(s) 102 is a single RFIC 102. In other embodiments, the RFIC(s) 102 is / are multiple RFICs. In embodiments with more than one RFIC 102 (e.g., a first RFIC and a second RFIC), the first RFIC and the second RFIC can be of the same type or they can be different types of RFICs. The RFIC(s) 102 can be combined with other passive components, such as antennas, filters, etc.In some embodiments, the RFIC(s) 102 may include an integrated antenna structure. In other embodiments, the antenna may be separate from the RFIC(s) 102 and may be included in the semiconductor package structure 100A as an antenna module and antenna-in-package (AiP), etc. If the antenna is separate from the RFIC(s) 102, the antenna may be mounted on the RFIC(s) 102 and / or stacked in a side-by-side configuration with the RFIC(s) 102.

[0019] While the semiconductor package structure 100A includes the components described above in some embodiments, other components may be included in the semiconductor package structure 100A, such as resistors, capacitors, inductors, transformers, crystal oscillators, filters, antennas, varactor diodes, symmetrical / unsymmetrical transformers, etc.

[0020] Fig. Figure 1B is a schematic block diagram of an exemplary semiconductor package structure 100B comprising a laminate substrate 126, according to some embodiments. The semiconductor package structure 100B is essentially similar to the semiconductor package structure 100A, with two exceptions.

[0021] First, the shielding plate 108 is a double-sided shielding plate and, in some embodiments, comprises a first ground plane 106A and a second ground plane 106B. The shielding plate 108 can be an organic material, such as bismaleimide triazine (BT) resin, polyimide, liquid crystal polymer (LCP), polyethylene terephthalate (PET), etc. The first and / or the second ground plane 106A and 106B can be a copper metal layer. In some embodiments, the metal layer can be a metal that shares similar properties to copper, such as silver or gold. The first ground plane 106A and the second ground plane 106B can be connected through the shielding plate 108 by one or more vias (e.g., a conductive path connecting different layers), as described in conjunction with Fig. 5B is described.

[0022] Secondly, the substrate on which the semiconductor package structure 100B is built is a laminate substrate 126. A laminate substrate can be a multilayer structure consisting of alternating layers of insulating and conductive materials, as used in ball-grid array (BGA) packages. BGA packages are surface-mount IC packages with an array of solder balls on the underside of the package (e.g., opposite the semiconductor package structure 100B, which is mounted on the top side of the laminate substrate 126) that provide electrical and mechanical connections to the PCB. The conductive materials (e.g., traces) can extend from the top side of the laminate substrate 126 to the solder balls to create a package ground 120. The one or more ground connectors 110 of the semiconductor housing structure 100B can be connected to the housing ground 120 via these conductor tracks on the top of the laminate substrate 126.Other conductor tracks on the laminate substrate 126 can provide signal and / or power to the semiconductor package structure 100B via one or more signal and / or power connectors 114.

[0023] Fig. Figure 1C is a schematic block diagram of a top-down perspective of an exemplary semiconductor package structure 100C according to some embodiments. Fig. 1C shows essentially similar components to those in Fig. 1A illustrated, but from a different perspective (e.g. a top-down perspective or top view).

[0024] In some embodiments, the semiconductor package structure 100C is mounted on a leadframe 116 and comprises one or more RFICs 102, a shielding plate 108, and a processing device 122. The processing device 122 can be attached to the package ground 120 of the leadframe 116 by a first die mounting layer and electrically connected to the package ground 120 and one or more package leads 118. The processing device 122 can be electrically connected to the package ground 120 by one or more ground connectors 110 and to the package leads 118 by one or more signal and / or power connectors 114. In some embodiments, the shielding plate 108 is stacked on top of the processing device 122 and attached to it by a second die mounting layer. The shielding plate 108 can be a single-sided or double-sided shielding plate.

[0025] The RFIC(s) 102 can be stacked on the shielding plate 108 and secured to the shielding plate 108 by a third die mounting layer. The RFIC(s) 102 can be electrically connected to the shielding plate 108 and / or the chassis ground 120 by one or more ground connectors 110. In some embodiments, the one or more ground connectors 110 are bond wires, wherein a first bond wire connects the one or more RFIC(s) 102 to the shielding plate 108 and a second bond wire connects the shielding plate 108 to the chassis ground 120. The RFIC(s) 102 can also be electrically connected to the one or more chassis leads 118 by one or more signal and / or power connectors 114. In some embodiments, more than one RFIC 102 can be attached to the shielding plate 108 either in a stacked or side-by-side configuration.

[0026] Fig. Figures 2A-B are schematic block diagrams of an exemplary semiconductor package structure according to some embodiments. Fig. Figure 2A is a schematic block diagram of an exemplary semiconductor package structure 200A comprising a spacer 202 and a leadframe 116, according to one embodiment. Fig. Figure 2B is a schematic block diagram of an exemplary semiconductor package structure 200B comprising a spacer 202 and a laminate substrate 126, according to one embodiment. Both Fig. 2A as well Fig. 2B shows essentially similar components to those in Fig. 1A-B is illustrated, but with a different configuration.

[0027] In some embodiments, the semiconductor package structure 200A is mounted on a leadframe 116 and comprises one or more RFICs 102, a single-sided shielding plate 108, a processing device 122, and a spacer 202. In some embodiments, the semiconductor package structure 200B is mounted on a laminate substrate 126 and comprises one or more RFICs 102, a double-sided shielding plate 108, a processing device 122, and a spacer 202. The RFIC(s) 102 can be mounted through the first die attachment layer 124 to the package substrate (e.g., the leadframe 116, as shown in [reference]). Fig. 2A illustrates, or the laminate substrate 126, as shown in Fig. The shielding plate 108 can be stacked on the RFIC(s) 102 and attached to the RFIC(s) 102 by the second die mounting layer 112. The shielding plate 108 can be a single-sided shielding plate (as shown in Figure 2B). Fig. 2A illustrated) or a double-sided shielding plate (as shown in Fig. (2B illustrated). The processing device 122 can be stacked on the shielding plate 108 and fastened to the shielding plate 108 by the third die fastening layer 104.

[0028] In some embodiments, the spacer 202 is positioned below the processing device 122 to provide structural support for the processing device 122. The spacer 202 can be made of a dielectric material (e.g., an electrically insulating material), such as polyimide, silicon dioxide (SiO2), epoxy resin, glass, silicon nitride (Si3N4), etc. The spacer 202 can be used to support the processing device 122 if the processing device 122 is larger than the RFIC(s) 102. In some embodiments, more than one spacer 202 can be used to support the processing device 122. In other embodiments, no spacer 202 can be used to support the processing device 122 (e.g., if the processing device 122 is smaller than the RFIC(s) 102).

[0029] Fig. Figures 3A-B are schematic block diagrams of an exemplary semiconductor package structure comprising a storage device, according to some embodiments. Fig. Figure 3A is a schematic block diagram of an exemplary semiconductor package structure 300A comprising a storage device 314 and a leadframe 116, according to one embodiment. Fig. Figure 3B is a schematic block diagram of an exemplary semiconductor package structure 300B comprising a storage device 314 and a laminate substrate 126, according to one embodiment. Both Fig. 3A as well Fig. 3B shows essentially similar components to those in Fig. 1A-B and Fig. 2A-B is illustrated, but with a different configuration and additional component (e.g., the storage device 314).

[0030] In some embodiments, the semiconductor package structure 300A is mounted on a leadframe 116 and comprises one or more RFICs 102, a shielding plate 108, a processing device 122, a storage device 314, and a storage device shielding plate 308. In some embodiments, the semiconductor package structure 300B is mounted on a laminate substrate 126.

[0031] The processing device 122 can be attached to the housing substrate (e.g. the 116, as in) by the first die attachment layer 124. Fig. 3A illustrates, or the laminate substrate 126, as in Fig. (Figure 3B illustrated). The storage device shielding plate 308 can be stacked on the processing device 122 and attached to the processing device 122 by the first storage device shielding plate die mounting layer 312. In some embodiments, the storage device shielding plate 308 has a storage device ground plane 306 and is a single-sided shielding plate. In other embodiments, the storage device shielding plate 308 is a double-sided shielding plate. The storage device 314 can be attached to the storage device ground plane 306 of the storage device shielding plate 308 by a second storage device shielding plate die mounting layer 310.Both the first storage device shielding plate die mounting layer 312 and the second storage device shielding plate die mounting layer 310 can be attached to the first die mounting layer 124, the second die mounting layer 112 and / or the third die mounting layer 104, which are related to . Fig. The descriptions in 1A are essentially similar.

[0032] In some embodiments, the storage device 314 is a storage die that stores data. The storage device 314 can be a volatile memory die (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), a non-volatile memory die (e.g., NAND flash memory), or another type of memory die (e.g., high-bandwidth memory (HBM), general-purpose flash memory (UFS)). In some embodiments, a spacer 202 can also be stacked on the storage device mass area 306 to provide support for the RFIC(s) 102 stacked above the storage device 314. The spacer 202 can be used to support the RFIC(s) 102 if the RFIC(s) 102 is / are larger than the storage device 314. In some embodiments, more than one spacer 202 can be used to support the RFIC(s) 102.In other embodiments, no spacer 202 can be used to support the RFIC(s) 102 (e.g., if the combined surface area of ​​side-by-side RFIC(s) 102 is smaller than the surface area of ​​the storage device 314, or if the surface area of ​​a single RFIC 102 is smaller than the surface area of ​​the storage device 314).

[0033] The shielding plate 108 can be attached to the storage device 314 and / or the spacer 202 by the second die mounting layer 112. The shielding plate 108 can further be attached to the RFIC(s) 102 by the third die mounting layer 104. In some embodiments, more than one RFIC is arranged in a side-by-side configuration (e.g., a first RFIC 302A is coplanar with and adjacent to a second RFIC 302B). The first RFIC 302A can be attached to the ground plane 106 of the shielding plate 108 by a first RFIC die mounting layer 304A, and the second RFIC 302B can be attached to the ground plane 106 by a second RFIC die mounting layer 304B. In some embodiments, the first RFIC 302A and the second RFIC 302B are both RFICs, such as a short-range wireless communication IC (e.g., a Bluetooth® IC), a short-range low-power wireless communication IC (e.g., a Bluetooth® IC), or a Bluetooth® IC.a Bluetooth® Low Energy (BLE) IC), an IC for communication over a wireless local area network (WLAN) (e.g., a Wi-Fi® IC), a radio frequency IC (e.g., a millimeter wave IC), a photonic IC (e.g., an optical IC), or various other EM-sensitive ICs. In some embodiments, either the first RFIC 302A or the second RFIC 302B is another component, such as an antenna module.

[0034] Fig. Figure 4 is a schematic block diagram of an exemplary semiconductor package structure 400 comprising a double-sided substrate 402, according to some embodiments. The semiconductor package structure 400 is mounted on a double-sided substrate 402 and comprises one or more RFICs 102, a processing device 122, and a ground plane 106. The double-sided substrate 402 can provide a similar shielding effect to the shielding plate 108 (e.g., of a shielding plate 108). Fig. 1A), and the mass surface 106 can be integrated into the double-sided substrate 402 (e.g. integral with it).

[0035] In some embodiments, the processing device 122 is attached to a top side of the double-sided substrate 402 by the first die mounting layer 124. The RFIC(s) 102 may be attached to a bottom side of the double-sided substrate 402 by the second die mounting layer 112. In some embodiments, the semiconductor package structure 400 includes an RFIC 102 attached to the bottom side of the double-sided substrate 402. In other embodiments, more than one RFIC 102 is attached to the bottom side of the double-sided substrate 402, either in a stacked or side-by-side configuration.

[0036] The RFIC(s) 102 can further be attached to the underside of the double-sided substrate 402 by an encapsulating agent 404. The encapsulating agent 404 can be a material such as an epoxy resin that both attaches the RFIC(s) 102 to the underside of the double-sided substrate 402 and also encapsulates the wires and / or bond wires to improve electrical connectivity.

[0037] Fig. Figures 5A-B are schematic block diagrams of a shielding plate according to some embodiments. Fig. Figure 5A is a schematic block diagram of a single-sided shielding plate 500A with a single ground plane 106 according to one embodiment. Fig. Figure 5B is a schematic block diagram of a double-sided shielding plate 500B with two ground planes 106A-B according to one embodiment. Both Fig. 5A as well Fig. 5B exhibits essentially similar components to those in Fig. 1A and Fig. 1B illustrated, however from a cross-sectional perspective.

[0038] In some embodiments, the shielding plate 108 is a single-sided shielding plate 500A, as in Fig. Figure 5A illustrates this with a single ground plane 106 arranged on a first side of the shielding plate 108. The shielding plate 108 can be made of a silicon material. In other embodiments, the shielding plate 108 is a double-sided shielding plate 500B, as shown in Fig. Figure 5B illustrates this. The double-sided shielding plate 500B can have a first ground plane 106A arranged on a first side of the shielding plate 108 and a second ground plane 106B arranged on a second side of the shielding plate 108. In some embodiments, the shielding plate 108 can include an insulating layer made of an organic material. The first ground plane 106A and the second ground plane 106B can be connected to each other by one or more vias 502. In some embodiments, the vias 502 are silicon vias (TSVs).

[0039] Fig.Figure 6 presents a flowchart of an exemplary process 600 for manufacturing a semiconductor package structure according to some embodiments. Process 600 can be carried out using a variety of semiconductor package manufacturing equipment, such as a wafer singulation saw, a die mounting machine, a bond wire, a ball placement machine, an encapsulation molding machine, a wafer bonding machine, a plasma cleaner, a TSV etching machine, etc. Although shown in a particular sequence or order, the process sequence can be modified unless otherwise specified. Thus, the illustrated embodiments should be understood as examples, and the illustrated process can be carried out in a different order, and some processes can be performed in parallel. Other process sequences are possible.

[0040] In process 602, a substrate with a first surface and a second surface is provided. The substrate can be a leadframe package, a laminate substrate, a double-sided substrate, or another type of substrate. The first surface can be the top side of the substrate, and the second surface can be the bottom side. In some embodiments, the substrate includes a set of conductive traces for electrical routing (e.g., connecting various components within the semiconductor package structure).

[0041] In process 604, a first die bonding layer is applied to the first surface of the substrate. In some embodiments, the first die bonding layer is applied to a first side of a first IC (e.g., a processing die, a processing device).

[0042] In step 606, the first side of the first IC is placed on the first die mounting layer. The first IC may have a first set of electrical contacts. In some embodiments, the first IC is a processing device (e.g., an MCU). In some embodiments, the first IC includes one or more RFICs.

[0043] In process 608, a first set of electrical contacts of the first IC is electrically connected to the substrate.

[0044] In process 610, a second die mounting layer is applied to a second side of the first IC. In some embodiments, the second die mounting layer is applied to a first side of a shielding plate. The second die mounting layer may cover one or more wires of the first IC. In some embodiments, the one or more wires are bond wires. In some embodiments, the one or more wires may extend through the second die mounting layer (e.g., to be bonded to the substrate).

[0045] In process 612, the first side of the shielding plate is positioned on the second die mounting layer. In some embodiments, the shielding plate has a first ground plane and a second ground plane, and the second ground plane is positioned on the second die mounting layer. The shielding plate may include an insulating layer made of an organic material, with the first ground plane located on a first side of the insulating layer and the second ground plane on a second side of the insulating layer. The first ground plane may be connected (e.g., electrically connected, electrically coupled) to the second ground plane by one or more vias extending through the insulating layer. In some embodiments, the first and second ground planes are a copper metal layer.

[0046] In process 614, the shielding plate is electrically connected to the substrate.

[0047] In process 616, a third die mounting layer is applied to a second side of the shielding plate. In some embodiments, the third die mounting layer is applied to a first side of a second IC. In some embodiments, the shielding plate has a single ground plane, and the third die mounting layer is applied to the ground plane. The shielding plate can be made of silicon, and the ground plane can be a metal layer of aluminum or copper.

[0048] In process 618, the first side of the second IC is positioned on the third die mounting layer. The second IC may have a second set of electrical contacts. In some embodiments, the second IC comprises one or more RFICs. In some embodiments, the second IC is a processing device. In some embodiments, the second IC is a storage device. In some embodiments, the one or more RFICs comprise a first RFIC and a second RFIC. The first RFIC may be coplanar and adjacent to the second RFIC. In some embodiments, the first RFIC and the second RFIC are in a stacked configuration.

[0049] In process 620, the second set of electrical contacts of the second IC is electrically connected to the substrate and to the shielding plate.

[0050] In some embodiments, the methods, components, and features described herein are implemented by discrete hardware components or are integrated into the functionality of other hardware components such as ASICs, FPGAs, DSPs, or similar devices. In some embodiments, the methods, components, and features are implemented by firmware modules or functional circuits within hardware devices. In some embodiments, the methods, components, and features are implemented in any combination of hardware devices and computer program components or in computer programs.

[0051] Insofar as the terms “includes”, “containing”, “comprises”, “comprehensive”, “exhibits”, “contains”, variants thereof and other similar words are used either in the detailed description or in the claims, these terms shall be used in a similar manner to the term “containing” as an open transitional word, without excluding any additional or other elements.

[0052] As used in this application, the terms "block," "layer," "component," "module," "system," or the like are generally intended to refer to a computer-related entity, either hardware (e.g., a circuit), software, a combination of hardware and software, or an entity relating to an operating machine with one or more specific functionalities. For example, a component may be, but is not limited to, a process running on a processor (e.g., a digital signal processor), a processor, an object, an executable file, an execution stream, a program, and / or a computer. For illustration, both an application running on a controller and the controller itself can be a component.One or more components can reside within a process and / or execution flow, and a component can be located on one computer and / or distributed between two or more computers. Furthermore, a "device" can take the form of purpose-built hardware; generalized hardware specialized by running software that enables the hardware to perform specific functions (e.g., generating points of interest and / or descriptors); software on a non-volatile, computer-readable medium; or a combination thereof.

[0053] The systems, circuits, modules, and so on mentioned above have been described in terms of the interaction between multiple components and / or blocks. It is understood that such systems, circuits, components, blocks, and so on may include these components or specified subcomponents, some of the specified components or subcomponents, and / or additional components, according to various permutations and combinations of the foregoing. Subcomponents may also be implemented as components that are communicatively coupled to other components, rather than being contained within higher-level components (hierarchically).Additionally, it should be noted that one or more components can be combined into a single component that provides aggregated functionality, or they can be divided into several separate subcomponents, and one or more intermediate layers, such as an administration layer, can be provided to communicatively couple to such subcomponents in order to provide integrated functionality. Any components described herein can also interact with one or more other components not specifically described here, but which are known to those skilled in the art.

[0054] Unless specifically stated otherwise, terms such as "identify," "receive," "cause," "train," "generate," "provide," "retain," "interrupt," "determine," "transmit," or the like refer to actions and processes performed or implemented by computer systems that manipulate and convert data represented as physical (electronic) quantities within the computer system's registers and memory into other data similarly represented as physical quantities within the computer system's memory or registers, or other such information storage, transmission, or display devices. In some embodiments, the terms "first," "second," "third," "fourth," etc., as used herein, are intended as designations to distinguish between different elements and, by virtue of their numerical designation, do not have an ordinal meaning.

[0055] The examples described here also refer to a device for carrying out the procedures described herein. In some embodiments, this device is specifically designed for carrying out the procedures described herein or comprises a general-purpose computer system that is selectively programmed by a computer program stored in the computer system. Such a computer program is stored in a computer-readable, tangible storage medium.

[0056] Some of the procedures and illustrative examples described herein do not inherently relate to a particular computer or other device. In some embodiments, various general-purpose systems are used according to the teachings described herein. In some embodiments, a more specialized device is constructed to perform the procedures described herein and / or each of their individual functions, routines, subroutines, or operations. Examples of the structure for a multitude of these systems are set forth in the preceding description.

[0057] The foregoing description is intended to be illustrative and not limiting. Although the present disclosure has been described with reference to specific illustrative examples and implementations, it is understood that the present disclosure is not limited to the examples and implementations described. The scope of protection of the disclosure should be determined with reference to the following claims, together with the full scope of protection of equivalents to which the claims refer.

[0058] The foregoing description sets forth numerous specific details, such as examples of specific systems, components, methods, and so forth, to provide a good understanding of several embodiments of the present disclosure. However, it will be obvious to a person skilled in the art that at least some embodiments of the present disclosure can be carried out without these specific details. In other cases, well-known components or methods are not described in detail or are presented in a simple block diagram format to avoid unnecessary obfuscation of the present disclosure. Thus, the specific details set forth are merely exemplary. Certain implementations may deviate from these exemplary details and still be considered to be within the scope of protection of the present disclosure.

[0059] The terms “above,” “below,” “between,” “arranged on,” and “on,” as used herein, refer to the relative position of a material layer or component with respect to other layers or components. For example, a layer arranged on, above, or below another layer may be in direct contact with the other layer or may have one or more intervening layers. Furthermore, a layer arranged between two layers may be in direct contact with the two layers or may have one or more intervening layers. Likewise, unless expressly stated otherwise, a feature arranged between two features may be in direct contact with the adjacent features or may have one or more intervening layers.

[0060] The words “example” or “exemplary” are used herein to mean that they serve as an example, case, or illustration. Any aspect or design described herein as an “example” or “exemplary” is not necessarily to be interpreted as preferential or advantageous over other aspects or designs. Rather, the use of the words “example” or “exemplary” is intended to represent concepts in a concrete way.

[0061] References in this description to "a single embodiment," "an embodiment," or "some embodiments" mean that a particular feature, structure, or property described in connection with the embodiment is included in at least one embodiment. Thus, the appearance of the phrase "in a single embodiment," "in an embodiment," or "in some embodiments" at various points in this description does not necessarily all refer to the same embodiment. Additionally, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise specified or clear from the context, "X includes A or B" means any of the natural inclusive permutations. That is, if X includes A; X includes B; or X includes both A and B, then "X includes A or B" is satisfied in any of the foregoing cases.In addition, the articles "a" and "an," as used in this application and the attached claims, should generally be interpreted as meaning "one or more," unless otherwise specified or it is clear from the context that they refer to a singular form. Furthermore, the terms "first," "second," "third," "fourth," etc., as used herein, are intended as designations to distinguish between different elements and, by virtue of their numerical designation, cannot necessarily have an ordinal meaning. When the term "about," "essentially," or "approximately" is used herein, it is intended to indicate that the stated nominal value is accurate to within ±10%.

[0062] Although the processes are shown and described here in a specific order, the sequence of operations of each process can be changed so that certain operations can be performed in reverse order, or so that certain operations can be performed at least partially concurrently with other operations. In another embodiment, instructions or sub-operations of different processes can be carried out intermittently and / or alternately.

[0063] It is understood that the foregoing description is intended to be illustrative and not limiting. Many other embodiments will be apparent to the person skilled in the art upon reading and understanding the foregoing description. The scope of protection of the disclosure should therefore be determined with reference to the attached claims, together with the full scope of protection of equivalents to which such claims entitle. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] WO 63 / 672,660

[0001]

Claims

[1] A semiconductor package structure that includes the following: a substrate that includes a substrate surface; a processing device that is electrically coupled to the substrate surface; one or more integrated radio frequency integrated circuits (RFICs) that are electrically coupled to the substrate surface; and a shielding plate, wherein the shielding plate is arranged between the one or more RFICs and the processing device, and wherein the shielding plate is configured to couple the one or more RFICs via one or more conductors to a housing ground having a ground voltage associated with the semiconductor housing structure. [2] Semiconductor housing structure according to claim 1, wherein the processing device is a microcontroller unit (MCU). [3] Semiconductor housing structure according to claim 1, wherein the one or more RFICs are positioned above the processing device. [4] Semiconductor package structure according to claim 1, wherein the one or more RFICs are a short-range wireless communication integrated circuit (IC), a low-power short-range wireless communication IC, a wireless local area network (WLAN) communication IC, a radio frequency IC or a photonic IC. [5] Semiconductor housing structure according to claim 1, wherein the shielding plate is a silicon wafer further comprising: a first surface that is coupled to the processing device via an epoxy resin; and a second surface coupled to a ground plane, where the ground plane is of aluminum or copper. [6] Semiconductor housing structure according to claim 1, wherein the shielding plate further comprises: an insulating layer containing an organic material, wherein the insulating layer has a first surface and a second surface; a first mass surface that is arranged on the first surface of the insulating layer; a second mass surface arranged on the second surface of the insulating layer; and one or more vias extending through the insulating layer and electrically coupling the first ground plane and the second ground plane, wherein the first ground plane and the second ground plane are copper. [7] Semiconductor housing structure according to claim 1, wherein a first RFIC of one or more RFICs is configured to be coplanar and adjacent to a second RFIC of one or more RFICs, and wherein the first RFIC and the second RFIC are positioned above the processing device. [8] Semiconductor housing structure according to claim 1, further comprising a storage device arranged between the one or more RFICs and the processing device, wherein the shielding plate is arranged between the storage device and the processing device and wherein a second shielding plate is arranged between the storage device and the one or more RFICs. [9] Semiconductor housing structure according to claim 1, wherein an antenna module is arranged on the one or more RFICs and wherein there is no shielding plate between the one or more RFICs and the antenna module. [10] Semiconductor housing structure according to claim 1, wherein the shielding plate is configured as follows: Coupling to the package ground of the semiconductor package structure via one or more first bond wires; and Coupling to one or more RFICs via one or more second bond wires, wherein the shielding plate is configured to electrically couple the one or more RFICs and the chassis ground via the one or more first bond wires and the one or more second bond wires. [11] A semiconductor package structure that includes the following: a double-sided substrate comprising a first surface and a second surface; a processing device that is electrically coupled to the first surface of the substrate; one or more RFICs electrically coupled to the second surface of the substrate, positioned beneath the processing device; and a shielding plate, wherein the shielding plate is arranged between the one or more RFICs and the processing device, and wherein the shielding plate is configured to couple the one or more RFICs to a ground voltage associated with the semiconductor package structure via one or more conductors. [12] Semiconductor package structure according to claim 11, wherein the one or more RFICs are a short-range wireless communication IC, a low-power short-range wireless communication IC, a wireless local area network (WLAN) communication IC, a radio frequency IC or a photonic IC. [13] Semiconductor housing structure according to claim 11, wherein the shielding plate is integral with the double-sided substrate. [14] Semiconductor package structure according to claim 11, wherein a first RFIC of the one or more RFICs is configured to be coplanar and adjacent to a second RFIC of the one or more RFICs. [15] Semiconductor package structure according to claim 11, wherein a first RFIC of the one or more RFICs is configured to be arranged above a second RFIC of the one or more RFICs. [16] A method for manufacturing a semiconductor package structure comprising the following: Providing a substrate having a first surface and a second surface, wherein the substrate includes a plurality of conductive traces for electrical routing; Application to the first surface of the substrate, a first die attachment layer; Arranging a first side of a first IC on the first die mounting layer, wherein the first IC has a first set of electrical contacts; electrical connection of the first set of electrical contacts of the first IC to the substrate; Applying a second die attachment layer to a second side of the first IC, configured to cover one or more bond wires of the first IC; Arrange on the second die mounting layer, a first side of a shielding plate; electrical connection of the shielding plate to the substrate; Apply, on a second side of the shielding plate, a third die mounting layer; Arranging a first side of a second IC on the third die mounting layer, wherein the second IC has a second set of electrical contacts; and Electrical connection of the second set of electrical contacts of the second IC to the substrate and to the shielding plate. [17] Method according to claim 16, wherein the first IC is an MCU. [18] Method according to claim 16, wherein the second IC is one or more RFICs. [19] Method according to claim 18, wherein a first RFIC of one or more RFICs is configured to be coplanar and adjacent to a second RFIC of one or more RFICs, and wherein the first RFIC and the second RFIC are positioned above the first IC. [20] Method according to claim 16, wherein the shielding plate further comprises: an insulating layer containing an organic material, wherein the insulating layer has a first surface and a second surface; a first mass surface that is arranged on the first surface of the insulating layer; a second mass surface arranged on the second surface of the insulating layer; and one or more vias extending through the insulating layer and electrically coupling the first ground plane and the second ground plane, wherein the first ground plane and the second ground plane are copper.

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