Filtering with tensor structures

Abstract

Integrated circuit devices, methods, and circuit arrangements for implementing filters based on multipliers in tensor circuits are provided. An integrated circuit arrangement can include a first tensor circuit with a first set of multipliers of first accuracy and a first summation circuit arrangement, and a second tensor circuit with a second set of multipliers of second accuracy and a second summation circuit arrangement. The first and second tensor circuits can jointly perform a multiplication operation with a third accuracy higher than the first and second accuracy.

Description

BACKGROUND

[0001] This disclosure relates to filtering using tensor circuits of an integrated circuit, such as tensor circuits of embedded digital signal blocks (DSP blocks) of an integrated circuit.

[0002] This section aims to familiarize the reader with various aspects of the prior art that may be related to different aspects of the present disclosure described and / or claimed below. This discussion is intended to provide the reader with background information that will enable a better understanding of the various aspects of the present disclosure. Accordingly, these statements are to be read in this sense, and not as incorporations into the prior art.

[0003] Integrated circuits are found in numerous electronic devices and provide a wide variety of functionality. Many integrated circuits include arithmetic circuit blocks for performing arithmetic operations, such as addition and multiplication. For example, a digital signal processing (DSP) block can complement a programmable logic circuit array in a programmable logic device, such as a field-programmable gate array (FPGA). Programmable logic circuit arrays and DSP blocks can be used to perform numerous different arithmetic functions. Many programmable logic devices include DSP blocks with a small number of larger multipliers (e.g., multiplication, addition, multiplication ...One or two 18x18-bit multipliers per DSP block are needed to implement certain types of filters, such as finite impulse response (FIR) filters, along with some supporting circuitry, such as delay chains and accumulators. Therefore, implementing a large filter can consume a large number of DSP blocks. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Various aspects of this revelation can be better understood by reading the following detailed description and referring to the drawings, in which the following applies: Fig. Figure 1 is a block diagram of a system used to program an integrated circuit device; Fig. 2 is a block diagram of the integrated circuit device made up of Fig. 1; Fig. Figure 3 is a block diagram of a finite impulse response (FIR) filter that can be formed using multipliers formed using tensor resources from digital signal processor (DSP) blocks of the integrated circuit device; Fig. Figure 4 is a diagram of two tensor blocks within a DSP block of the integrated circuit device; Fig. Figure 5 is a diagram of multiplication using a larger multiplier, which is formed using multiple tensor blocks from multiple DSP blocks; Fig. Figure 6 is a diagram of an equivalent result of the multiplication of Fig. 5; Fig. Figure 7 is a block diagram of tensor blocks consisting of two DSP blocks with additional circuitry in soft logic to perform multiplication. Fig. 5 and Fig. 6 to be carried out; Fig. Figure 8 is a block diagram of tensor blocks consisting of two DSP blocks with a hardened logic circuit arrangement in the DSP blocks to handle the multiplication of Fig. 5 and Fig. 6 to enable; Fig. Figure 9 is a diagram of a tensor block within a DSP block of the integrated circuit device with a closer view of an arrangement of coefficient registers; Fig. Figure 10 is a diagram of a tensor block within a DSP block of the IC device with a chained arrangement of coefficient registers to support decimation filtering; Fig. 11 Diagram of a tensor block within a DSP block of the integrated circuit device with multiplexers to represent the chained arrangement of Fig. 10 to support; Fig. Figure 12 is a diagram of the multiplication of asymmetric vectors when different tensor blocks support different levels of accuracy; Fig. Figure 13 is a diagram of an equivalent result of the multiplication of Fig. 12; and Fig. Figure 14 is a diagram of an asymmetric multiplication that can be performed using several tensor blocks; Fig. 15 Diagram of an equivalent result of asymmetric multiplication from Fig. 14; Fig. Figure 16 is a block diagram of tensor blocks from a DSP block, which is used to perform the asymmetric multiplications from Fig. 14 and Fig. 15 to be carried out; Fig. Figure 17 is a block diagram of tensor blocks consisting of three DSP blocks, which are used to perform a larger asymmetric multiplication; and Fig. Figure 18 is a block diagram of a data processing system that can incorporate the integrated circuit. DETAILED DESCRIPTION OF CERTAIN VERSIONS

[0005] One or more specific embodiments are described below. In an effort to provide a concise description of these embodiments, the specifications do not describe all features of an actual implementation. It should be clear that, as with any engineering or design project, developing such an actual implementation will require numerous implementation-specific decisions to achieve the developers' specific objectives, such as adhering to system and business constraints, which may vary from one implementation to another. Furthermore, it is understood that such a development effort could be complex and time-consuming, but would nevertheless constitute a routine design, manufacturing, and production undertaking for average professionals who benefit from this disclosure.

[0006] When introducing elements of different embodiments of the present disclosure, the articles "a," "an," and "the" are to be understood as meaning that there is one or more of the elements. The terms "consisting of," "including," and "with" are to be understood as comprehensive and mean that, in addition to the listed elements, further elements may be present. Furthermore, references to "a particular embodiment" or "an embodiment" of the present disclosure are not to be understood as excluding the existence of additional embodiments that also have the listed features.

[0007] Many integrated circuits, such as programmable logic devices, incorporate DSP blocks with a hardened circuit arrangement to perform artificial intelligence (AI) operations. These DSP blocks contain "hardened" circuitry specialized to efficiently perform specific mathematical operations. This contrasts with "soft" circuitry, which can be formed by programmable logic but may not be as efficient. The AI ​​circuit arrangement of the DSP blocks may include a large number of smaller multipliers with lower precision than are typically found in many DSP applications. These multipliers can form large tensors that compute scalar products, implemented in the hardware of the DSP blocks.Instead of allowing the AI-related circuitry of DSP blocks to simply remain unused when a programmable logic device is used in filtering operations, this disclosure provides systems and methods for utilizing the AI-related circuitry to provide additional regular DSP functionality. For example, AI tensor cores of DSP blocks can be used to perform FIR filtering, which is one of the most common applications performed on programmable logic devices. This can double (or more) the arithmetic density of FIR filters, largely by repurposing a hardened resource typically used for AI operations in digital signal processing.

[0008] Fig. Figure 1 illustrates a block diagram of a system 10 that can be used to implement the filtering systems and procedures of this disclosure on an integrated circuit system 12 (e.g., a single monolithic integrated circuit or a multi-die system of integrated circuits). A developer might want to implement a system design to perform filtering operations on the integrated circuit system 12 (e.g., a programmable logic device, such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC) that includes a programmable logic circuit arrangement). The integrated circuit system 12 may include a single integrated circuit, multiple integrated circuits in one package, or multiple integrated circuits in multiple packages that communicate remotely (e.g., via wires or traces).In some cases, the designer can specify a high-level program to be implemented, such as an OPENCL® program, which can enable the designer to provide programming instructions more efficiently and easily to configure a set of programmable logic cells for the integrated circuit system 12 without specific knowledge of low-level hardware description languages ​​(e.g., Verilog, VHDL (Very High-Speed ​​Integrated Circuit Hardware Description Language)). Since OPENCL® is quite similar to other high-level programming languages, such as C++, programmable logic designers familiar with such programming languages ​​may experience a reduced learning curve compared to designers who have to learn unfamiliar low-level hardware description languages ​​to implement new functionalities in the integrated circuit system 12.

[0009] In a configuration mode of the integrated circuit system 12, a developer can use an electronic device 13 (e.g., a computer) to implement high-level concepts (e.g., a system user concept) using development software 14, such as a version of INTEL® QUARTUS® from INTEL CORPORATION. The electronic device 13 can use the design software 14 and a compiler 16 to convert the high-level program into a lower-level description (e.g., a configuration program, a bitstream). The compiler 16 can provide machine-readable instructions representing the high-level program to a host 18 and the integrated circuit system 12. The host 18 can receive a host program 22, which can be controlled or implemented by the kernel programs 20.To implement the host program 22, the host 18 can communicate instructions from the host program 22 to the integrated circuit system 12 via a communication link 24, which may include, for example, direct memory access (DMA communications) or peripheral component interconnect express (PCIe) communications. In some embodiments, the kernel programs 20 and the host 18 can configure programmable logic blocks (e.g., LABs 110) on the integrated circuit system 12. The programmable logic blocks (e.g., LABs 110) may include circuit arrangements and / or other logic elements and may be configurable to implement a variety of functions in combination with digital signal processing (DSP) blocks 120.

[0010] The designer can use the design software 14 to create and / or specify a low-level program, such as the low-level hardware description languages ​​described above. In some embodiments, the system 10 can also be implemented without a separate host program 22. Thus, the embodiments described herein are intended to be illustrative and not limiting.

[0011] An illustrative embodiment of a programmable integrated circuit system 12, such as a programmable logic device (PLD) (e.g., a field-programmable gate array device (FPGA) that can be configured to implement a circuit design), is shown in Fig. 2 shown. As in Fig. As shown in Figure 2, the integrated circuit system 12 (e.g., an integrated circuit device of a field-programmable gate array (FPGA)) can have a two-dimensional array of functional blocks, sometimes called arithmetic logic modules (ALMs), including programmable logic blocks (e.g., also called logic array blocks (LABs) 110 or configurable logic blocks (CLBs)) and other functional blocks, such as embedded digital signal processing blocks (DSP blocks) 120 and embedded random access memory blocks (RAM blocks) 130. Functional blocks, such as LABs 110, can include smaller programmable areas (e.g., logic elements, configurable logic blocks, or adaptive logic modules) that receive input signals and perform user-defined functions on the input signals to generate output signals.The LABs 110 can also be grouped into larger programmable areas, sometimes referred to as logic sectors, which are individually managed and configured by corresponding logic sector managers. The grouping of programmable logic resources on the integrated circuit system 12 into logic sectors, logic array blocks, logic elements, or adaptive logic modules is for illustrative purposes only. In general, the integrated circuit system 12 can include functional logic blocks of any suitable size and type, which can be organized according to any suitable logic resource hierarchy.

[0012] The programmable logic of the integrated circuit system 12 can be controlled by programmable memory elements, sometimes referred to as configurable random-access memory (CRAM). Memory elements can be loaded with configuration data (also called programming data or configuration bitstream) using input-output elements (IOEs) 102. Once loaded, each memory element provides a corresponding static control signal that controls the operation of an associated functional block (e.g., LABs 110, DSP, BLOCK 120, RAM 130, or input-output elements 102).

[0013] In one scenario, the outputs of the loaded memory elements are applied to the gates of metal-oxide-semiconductor transistors in a functional block to switch specific transistors on or off, thereby configuring the logic in the functional block, including the routing paths. The programmable logic circuit elements that can be controlled in this way include parts of multiplexers (e.g., multiplexers used to create routing paths in interconnect circuits), lookup tables, logic arrays, AND, OR, NAND, and NOR logic gates, pass gates, etc.

[0014] The memory elements can use any suitable volatile and / or non-volatile memory structures, such as random-access memory (RAM) cells, fuses, antifuses, programmable read-only memory cells, mask-programmed and laser-programmed structures, combinations of these structures, etc. Because the memory elements are loaded with configuration data during programming, they are sometimes referred to as configuration memory, configuration random-access memory (CRAM), or programmable memory elements. The integrated circuit system 12 (e.g., as a programmable logic device (PLD)) can be configured to implement a customer-specific circuit design. For example, the configuration RAM can be programmed to control LABs 110, DSP BLOCK 120, and RAM 130, programmable interconnect circuits (i.e.,vertical channels 140 and horizontal channels 150) and the input / output elements 102 form the circuit design implementation.

[0015] Additionally, the programmable logic device can include input-output elements (IOEs) 102 for driving signals from the integrated circuit system 12 and for receiving signals from other devices. The input-output elements 102 can include a parallel input-output circuit arrangement, a serial data transceiver circuit arrangement, a differential transceiver and receiver circuit arrangement, or any other circuit arrangement used to connect one integrated circuit to another.

[0016] The integrated circuit system 12 can also include a programmable interconnect circuit arrangement in the form of vertical routing channels 140 (i.e., interconnects formed along a vertical axis of the integrated circuit system 12) and horizontal routing channels 150 (i.e., interconnects formed along a horizontal axis of the integrated circuit system 12), each routing channel containing at least one track for guiding at least one wire. If desired, the interconnect circuit arrangement can include pipeline elements, and the contents stored in these pipeline elements can be accessed during operation. For example, a programming circuit can allow read and write access to a pipeline element.

[0017] It should be noted that other routing topologies besides the topology in Fig. The interconnect circuit arrangement shown in Figure 2 is to be included in the scope of protection of this disclosure. For example, the routing topology may include wires running diagonally or horizontally and vertically along various parts of its circumference, as well as wires that are perpendicular to the device plane in the case of three-dimensional integrated circuits, and the driver of a wire may be located at a point other than the end of a wire. The routing topology may include global wires spanning substantially the entire integrated circuit system 12, fractional global wires, such as wires spanning a portion of the integrated circuit system 12, staggered wires of a certain length, smaller local wires, or any other suitable interconnect resource arrangement.

[0018] The integrated circuit 12 can be programmed to perform a variety of operations. One in Fig. The third example shown is a finite impulse response (FIR) filter. For example, an FIR filter can be an asymmetric FIR filter, where weights applied to different taps can be different, or, as in the example of Fig. 3. A symmetrical FIR filter 180, where the weights around a defined point are of the same magnitude. In the example of Fig. 3. The symmetrical FIR filter 180 receives an input signal x(n). The in Fig. Figure 3 illustrates FIR filter 180, which has nine taps symmetrically arranged around a point x(4) of the signal x(n), where the first point in the x(n) signals is x(0). The x(n) signal passes through registers 182, which provide the tap points to a pre-adder 184 before the results enter a multiplier 186 to be multiplied by a weight value (here, coefficients C1, C2, C3, C4, or C5). The partial results are summed in adders 188 to obtain the result of filter 180. The adders 184 and the multipliers 186 can, in some cases, be effectively grouped into a single operation 190. In some cases, the weights may have the same magnitude but a different sign. In such cases, the pre-adder 184 can be configured as a pre-subtractor. The 188 adders can be separate addition circuits or a single large summing circuit.

[0019] A wide variety of filters, such as the FIR filter 180 from Fig. 3, can be formed using a circuit arrangement of the integrated circuit system 12. The filter multiplication can be performed using AI-related circuits on the DSP blocks 120 and / or large multipliers (e.g., 18x18 multipliers, 27x27 multipliers) of the DSP blocks 120. The DSP blocks 120 can include a tensor circuit arrangement 200, as shown in Fig. Figure 4 shows that the tensor circuit arrangement 200 can include several separate tensor circuits 202, 204. In the example of Fig. Figure 4 of the tensor circuit arrangement 200 includes a first tensor circuit 202 and a second tensor circuit 204. Each tensor circuit 202, 204 includes a set of multipliers 206 that multiply a first input vector (consisting, for example, of values ​​A0, A1, ..., A9) by a second input vector (composed, for example, of values ​​B0, B1, ..., B9 or values ​​D0, D1, ..., D9). The products of the multipliers 206 can be summed in the summing circuit arrangement 208 to produce an overall scalar product. Registers 210 can be shifted to coefficients (e.g., filter weights, a vector) to be multiplied. Here there are ten registers 210. Therefore, it may take ten cycles to load the tensor circuits 202, 204 with the coefficients, but once loaded, the coefficients can be used in any suitable number of multiplication operations with different inputs (e.g.The same value of B0 can be used in multiplication operations with different values ​​of A0 without having to reload register 210).

[0020] It can be seen that the structure of the tensor circuits 202, 204 provides multiplication of inputs and summation of the resulting products, operations which also take place in many filters, such as the FIR filter 180 of Fig. 3. However, the multipliers 206 can have lower precision than those used in many filters. For example, the multipliers 206 can be a range of 6-bit, 7-bit, 8-bit, 9-bit, 10-bit, 11-bit, or 12-bit multipliers. In contrast, many filter operations can have a precision of 16 bits or more.

[0021] To achieve multiplication with a precision more commonly used in filter operations, tensor circuits 202, 204 can be used jointly by several different DSP blocks 120. For example, in Fig. As shown in Figure 5, a filter operation can employ a multiplication 212, which involves two 16-bit numbers, including a multiplicand 214 and a multiplier 216. The multiplicand 214 can be partitioned into two 8-bit blocks A and C, and the multiplier 216 can be partitioned into two 8-bit blocks B and D. It should be noted that the values ​​given are examples and may vary depending on the specific application and the size of the multipliers in the tensor circuits 202 and 204. When calculating the sum of all multipliers 206, it is possible to sum all lower chunks in the summing circuit arrangement 208 of one of the tensor circuits 202 or 204 and separately all higher chunks in the summing circuit arrangement 208 of the other of the tensor circuits 202 or 204, before adding the sum of the lower chunks to the sum of the upper chunks to form the result.

[0022] For example, an equivalent multiplication operation is 218, which is in Fig. Figure 6 shows the addition of the values ​​219, 220, and 221. The value 219 is a 32-bit value consisting of the product AB and the product CD. The value 220 is a 16-bit value consisting of the product AD. The value 221 is a 16-bit value consisting of the product BC. It should be noted that the product AB is a 16-bit value resulting from the product of an 8x8-bit multiplication of the values ​​A and B. Fig. 5 corresponds to the product CD being a 16-bit value, which is the product of an 8x8-bit multiplication of the values ​​C and D of Fig. 5 corresponds to the product AD being a 16-bit value, which is the product of an 8x8-bit multiplication of the values ​​A and D of Fig. 5 corresponds, and the product BC is a 16-bit value that is the product of an 8x8-bit multiplication of the values ​​B and C from Fig. 5 corresponds to...

[0023] As in Fig. As shown in 7, the multiplication operation 218 can be performed by Fig. 6 using four tensor circuits 202A, 204A, 202B, 204B of two DSP blocks 120A and 120B. Each DSP block 120A and 120B can include a respective addition circuit arrangement 222A and 222B and a bit shift circuit arrangement 224A and 224B. Another bit shift circuit arrangement 226 and 228 outside the DSP blocks 120A and 120B can be formed in soft logic by programming the programmable logic circuit arrangement (e.g., LABs 110) of the integrated circuit system 12.

[0024] To perform the multiplication operation 218 of Fig. 6 using the circuit arrangement of Fig. To perform step 7, the value A (e.g., A0 in) can be used. Fig. 4) fed to a multiplier of the first tensor circuit 202A of the DSP block 120A and assigned the value D (e.g. D0 in Fig. 4) are multiplied to create the product AD. At the same time, the value A (e.g., A0 in) can be... Fig. 4) fed to a multiplier of the second tensor circuit 204A of the DSP block 120A and assigned the value B (e.g. B0 in Fig. 4) be multiplied to generate the product AB. The result of the first tensor circuit 202A (the product AD) can be shifted 8 bits to the right by the bit-shift circuit 224A and added in the addition circuit 222A. In parallel, the value C can be fed to a multiplier of the first tensor circuit 202B of the DSP block 120B and multiplied by the value D to generate the product CD. Simultaneously, the value C can be fed to a multiplier of the second tensor circuit 204B of the DSP block 120B and multiplied by the value B to generate the product CB. The result of the first tensor circuit 202B (the product CD) can be shifted 8 bits to the right by the bit-shift circuit arrangement 224B and added in the addition circuit arrangement 222B. To the in Fig. To achieve the final alignment shown in Figure 6, the sum of the result of the addition 222A can be shifted 8 bits to the left by the bit-shifting circuit arrangement 226 and added in the addition circuit arrangement 228. As a result, the 8x8-bit multipliers of the tensor circuits 202A, 202B, 204A, and 204B can thus effectively operate together as a 16x16-bit multiplier.

[0025] As is understood, the operation discussed above refers to a single multiplication operation, but there can be many multiplication operations that are grouped together in filtering operations. Since the tensor circuits 202A, 202B, 204A, and 204B contain many multiplier and summing circuit arrangements for summing the results, the tensor circuits 202A, 202B, 204A, and 204B can be used to form many higher-precision multipliers for filtering purposes. For example, if the tensor circuits 202A, 202B, 204A, and 204B each contain ten 8x8-bit multipliers, they can collectively act as ten 16x16-bit multipliers for filtering, using the technique discussed above.

[0026] Although the bit-shifting circuits within the DSP blocks above are described as shifting by 8 bits to create a 16-bit multiplier, the bit-shifting circuits can shift by a different number of bits in different situations. While shifting by 8 bits is sufficient for unsigned multipliers, signed multipliers constructed from signed 8-bit tensor circuits 202, 204 may only be able to perform a signed 15-bit multiplication. The shifting offsets in Fig. Therefore, 6 represents either 7 bits or 8 bits. The bit-shift circuit arrangements 224 and 226 can be configured to support several different numbers of bit shifts and / or directions to the right or left. It should be noted that the other bit-shift circuit arrangement, which is discussed elsewhere in the same way, can also be configured to shift different numbers of bits (e.g., 7 or 8 bits) and / or different directions (e.g., left or right).

[0027] In the example of Fig. 7 The bit-shifting circuit arrangement 226 and the addition circuit arrangement 228 are formed in soft logic using a programmable logic circuit arrangement (e.g., LABs 110) of the integrated circuit system 12. In another example, which is described in Fig. As shown in Figure 8, the bit-shifting circuit arrangement 226 and the addition circuit arrangement 228 can form a hardened circuit arrangement within the DSP blocks 120. The balancing registers 240 and 242 can align the two asymmetric scalar products of the tensor circuits 202A and 202B, respectively, which are shifted relative to each other and summed. A dedicated hardened inter-DSP communication channel 244 can relay the results from the second DSP block 120B to the first DSP block 120A. Thus, for example, the addition circuit arrangement 228 can be implemented as a cascading adder used for the second tensor circuit 204A, which is typically used to add multiple tensors together when operating in AI mode.The addition circuit arrangement 228 for summing the results of the tensor circuits 202A, 202B, 204A and 204B in each block can also be implemented using the cascade adder for the first tensor circuit arrangement 202A. In other words, in some cases the addition circuit arrangement 228 may not be an additional adder, but may be an existing adder (e.g., cascade adder, summing circuit arrangement) that is reused by inserting additional multiplexers to select the appropriate inputs.

[0028] As mentioned above, there can be many multiplication operations that are grouped into filter operations. In fact, with reference to the in Fig. In the exemplary tensor circuits 202 and 204 shown, an FIR filter can be implemented by inputting data into any number of the ten parallel inputs (e.g., A0, A1, ..., A9) and loading the coefficients (e.g., B0, B1, ..., B9) into the register chain formed using registers 210. The data input can be connected via a delay line implemented in soft logic (e.g., LABs 110) of the integrated circuit system 12.

[0029] Additional sets of registers 210 can allow multiple sets of coefficients to be loaded, so that new coefficients can be loaded simultaneously when previously loaded coefficients are used in multiplication operations. Fig. Figure 9 illustrates an example of a tensor circuit 202, 204 with two sets of registers 210A, 210B, which can be loaded with two separate sets of coefficients. The multiplexers 260 can select between the coefficients to be multiplied. Here, there are two coefficient chains. In this way, one chain can be loaded while the other is used for operation, so there may be less or no dead time in the system. In other examples, there may be additional sets of registers 210 to provide additional coefficient chains.

[0030] Another arrangement of the coefficient chains formed by registers 210A and 210B for a tensor circuit 202 is shown in Fig. Figure 10 shows that this structure can be used for a variety of purposes, including forming a decimation filter. Instead of loading coefficients, the coefficient chains formed by registers 210A and 210B can act as the delay chains for the data. The coefficients are then loaded in parallel with the ten inputs. Multiple channels or coefficient banks can be implemented using the soft logic (e.g., LABs 110) of the integrated circuit system 12. The structure of the tensor circuit 202 is shown in Figure 10. Fig. 10 can be used to form a filter with a decimation factor of 2 for a data stream, alternately filtering even data samples of one register clock cycle, then odd data samples of the next clock cycle, and so on, as the samples are shifted by registers 210A and 210B. Although two sets of registers 210A and 210B are shown, additional sets of registers 210 can provide additional delays to allow other types of decimation filters (e.g., decimation filter by three, decimation filter by four) depending on the number of sets of registers used.

[0031] The tensor circuits 202, 204 can include an additional circuit arrangement to modify the filter arrangement. Fig. 10 and to enable the filter techniques described above. For example, by means of an exemplary tensor circuit 202, 204 in Fig. As shown in Figure 11, additional multiplexers 280 allow data from registers 210A and 210B to be routed in a variety of ways. For example, in one configuration, the multiplexers 280 allow the tensor circuit 202, 204 to load registers 210B while the values ​​in registers 210A are used for operation. At a later time, the values ​​stored in registers 210B can be moved to registers 210A, and the process can be repeated. In another configuration, the multiplexers 280 allow the tensor circuit 202, 204 to act as a decimation filter in the manner of Fig. 10 works.

[0032] In some cases, the tensor circuits 202 and 204 can support different respective accuracies. For example, the first tensor circuit 202 can have 10x10-bit multipliers, while the second tensor circuit 204 can have 8x8-bit multipliers. Many filter operations have historically used INT18 multiplication (e.g., 18x18-bit multiplication). However, it is difficult to generate INT18 multiplier vectors from INT10 and INT8 vectors because one or two of the inputs of each vector are unsigned (resulting in 9x8 and 7x7 multipliers). Nevertheless, multiple DSP blocks 120 with tensor circuits 202 and 204, respectively, with 10-bit and 8-bit accuracies, can be used to effectively perform 18x18-bit filtering. The products of the multipliers of the tensor circuits 202, 204 can be aligned in the manner discussed above to achieve an 18x18 multiplier with some least significant bit errors (LSB errors).In fact, the upper 17 bits will always be correct.

[0033] This is illustrated by an example multiplication operation 300, which is shown in Fig. 12 is shown. Fig. The multiplication operation 300 involves two 18-bit values, including a multiplicand 302 and a multiplier 304. The multiplicand 304 can be partitioned into a signed 8-bit block A and an unsigned 10-bit block B. The multiplier 304 can be partitioned into a signed 8-bit block C and an unsigned 10-bit block D. Fig. 13 represents an essentially equivalent multiplication operation 306, which involves adding the values ​​308, 310, and 312. The value 308 is a value consisting of the 8x8-bit product AC (signed x signed) and the 9x9-bit product BD (unsigned x unsigned). The value 310 is a value consisting of the 9x8-bit product AD (signed x unsigned). The value 312 is a value consisting of the 9x8-bit product BC (signed x unsigned).

[0034] The resulting 18×18 multiplication from the use of tensor circuits 202, 204 with 10x10-bit and 8x8-bit multiplier accuracies, respectively, is nearly equivalent to the use of 18x18 multipliers. An explanation follows. Consider that the inputs to the multiplier X and the multiplicand Y are split into two parts: an upper part of 8 bits and a lower part of 10 bits. X=A210210+B Y=C210210+D

[0035] With A and C as signed 8-bit values ​​and B and D as unsigned 10-bit values, the product XY can be written as: P=XY=AC210220+AD210 210+BC210 210+BD.

[0036] The resulting products can be described as follows using two DSP blocks 120, each comprising a tensor circuit 202 with 10-bit multipliers and a tensor circuit 204 with 8-bit multipliers: • AC => 8x8 multiplications, mapped to the narrow 8-bit mode of one of the DSP blocks 120. • AD => 8x10-bit multiplication, mapped to the wide 10-bit mode of one of the DSP blocks 120. It is noted that D is an unsigned value, so this is not actually a full multiplication. Instead, D is reduced to 9 bits and sign-expanded (0-expanded), with its lower bit being discarded. • BC => 10x8-bit multiplication, which is a similar mapping to AD. B is reduced to 9 bits before multiplication. This multiplication is mapped to the wide 10-bit mode of one of the DSP blocks 120. • BD => 10x10-bit unsigned multiplication, mapped to the narrow 8-bit mode.

[0037] The approximate value using this approach can be written as follows: P˜=AC220+AD˜210+B˜C210+B˜'D˜'

[0038] The error introduced in this approach can therefore be calculated as follows: P−P˜=AD210−AD˜210+BC210−B˜C210+BD−B˜'D'˜=(D−D˜)A210+(B−B˜)C210 +BD−BD'˜+BD'˜−B˜'D'˜=(D−D˜)A210+(B−B˜)C210+B(D−D'˜)+D'˜(B−B˜') (D−D˜)(A210)+(B−B˜)(C210)+B(D−D'˜)+D'˜(B−B˜')

[0039] Since D - D̃ corresponds to the error introduced when a bit is truncated (similarly for B - B̃), the maximum generated error is "1". The maximum error occurs when: • A and C are maximum positive values ​​signed on 8 bits (127) • B is the largest unsigned 10-bit integer (1023) and C is the largest positive value.

[0040] In this case, P - P̃ = 274.369, which is 1.000010111111000001.2 * 2^(18). This means that of the 36 bits of the product, the upper 17 bits are guaranteed to be correct. In fact, the upper 17 bits will always be correct. If errors exceed 2 20 (That is, 1.04M) different possible values ​​are calculated, the maximum error obtained is 267521, whereas the average error is 55416. In other words, the average error is equivalent to averaging 20 bits, where the result is correct, whereas the maximum error is such that the top 17 bits will always be correct.

[0041] In addition to performing larger symmetric multiplications, the tensor circuits 202 and 204 of the DSP blocks 120 can also be used to perform asymmetric multiplications. To perform an asymmetric multiplication with an accuracy higher than that of any single multiplier from the tensor circuits 202 and 204, multiple tensor circuits 202 and 204 from several different DSP blocks 120 can be used together. For example, in Fig. As shown in Figure 14, an asymmetric multiplication 320 can involve a 16-bit number (e.g., a multiplicand 322) and an 8-bit number (e.g., a multiplier 324). The multiplicand 322 can be split into two 8-bit blocks A and B, and the multiplier 216 can remain as a single 8-bit block C. It should be noted that the values ​​given are examples and may vary depending on the specific application and the size of the multipliers in the tensor circuits 202 and 204.

[0042] An equivalent multiplication operation 330, which in Fig. Figure 15 shows the addition of the values ​​332 and 334. The value 332 is a 16-bit value consisting of the product AC. The value 334 is a 16-bit value consisting of the product BC. It should be noted that the product AC is a 16-bit value resulting from the product of an 8x8-bit multiplication of the values ​​A and C. Fig. 14 corresponds, and that the product AC is a 16-bit value, which is a product of an 8x8-bit multiplication of the values ​​B and C of Fig. 14 corresponds to this.

[0043] As in Fig. As shown in 16, the multiplication operation can be 330 of Fig. 15 are executed using two tensor circuits 202, 204 by a DSP block 120. To perform the multiplication operation 330 of Fig. 15 using the circuit arrangement of Fig. To perform 16, the value C (e.g. A0 in Fig. 4) fed to a multiplier of the first tensor circuit 202 and assigned the value A (e.g. D0 in Fig. 4) are multiplied to produce the product AC. At the same time, the value C (e.g., A0 in) can be Fig. 4) fed to a multiplier of the second tensor circuit 204 and assigned the value B (e.g. B0 in Fig. 4) are multiplied to generate the product BC. The result of the first tensor circuit 202 (of the product AC) can be shifted 8 bits to the left by the bit-shifting circuit 224 and added in the addition circuit 222.

[0044] Other suitable multiplication operations can be performed using a variety of combinations of tensor circuits 202, 204 of different DSP blocks 120. In fact, in some cases a filter may contain coefficient values, where one group of coefficients has a lower precision (e.g., a maximum precision of 8 bits) and another group has a higher precision (e.g., a larger range, such as 16 bits). Fig. Figure 17 shows how this filter type can be efficiently constructed from a set of DSP blocks 120, arranged in both asymmetric and symmetrical forms. For example, a first DSP block 120A can perform a 16x8-bit multiplication using the tensor blocks 202A and 204A, the displacement circuit arrangement 224A, and the addition circuit arrangement 222A, as described above. Fig. 16. The second and third DSP blocks 120B and 120C can jointly perform a larger multiplication 340 (e.g., 16x16-bit multiplication), which the tensor blocks 202B, 204B, 202C and 204C, the shift circuit arrangement 224B and 224C and the addition circuit arrangement 222B and 222C, as well as the shift circuit arrangement 226 and the addition circuit arrangement 228, can perform as discussed above. Fig. 7 or Fig. The final result from the smaller multiplication of the first DSP block 120A can be shifted using the shift circuit arrangement 342 and added to the final result from the larger multiplication 340 of the second and third DSP blocks 120B and 120C (as output by the adder 228) using the addition circuit arrangement 344. The shift circuit arrangement 226 and 342 and the addition circuit arrangement 228 and 344 can be a hardened circuit arrangement within the DSP blocks 120A, 120B and / or 120C, or they can be soft logic implemented in a programmable logic circuit arrangement (e.g., LABs 110).For example, the 16-bit scalar products can be constructed using two adjacent DSP blocks 120B and 120C using fully internal shifts and additions from a circuit arrangement within the DSP blocks 120B and 120C, and the asymmetric 8-bit scalar products can be added using shifts and additions of soft logic implemented in programmable logic circuits.

[0045] The circuits discussed above can be implemented on the integrated circuit system 12, which can include a component of a data processing system, such as a data processing system 500, which is in Fig. Figure 18 shows that the data processing system 500 can include the integrated circuit system 12 (e.g., a programmable logic device), a host processor 502, a memory and / or storage circuit arrangement 504, and a network interface 506. The data processing system 500 can contain more or fewer components (e.g., an electronic display, user interface structures, application-specific integrated circuits (ASICs)). In addition, each of the components shown in Figure 12 can be used in the data processing system 500. Fig.The integrated circuit system 12 comprises the circuit components shown in Figure 18. The host processor 502 can include any of the aforementioned processors capable of managing a data processing request for the data processing system 500 (e.g., to perform encryption, decryption, machine learning, video processing, speech recognition, image recognition, data compression, database search ranking, bioinformatics, network security pattern identification, spatial navigation, cryptocurrency operations, or the like). The memory and / or storage circuit 504 can include random-access memory (RAM), read-only memory (ROM), one or more hard disks, flash memory, or the like. The memory and / or storage circuit arrangements 504 can hold data to be processed by the data processing system 500.In some cases, the memory and / or storage circuit arrangement 504 can also store configuration programs (bitstreams) for programming the integrated circuit device 12. The network interface 506 can enable the data processing system 500 to communicate with other electronic devices. The data processing system 500 can comprise several different packages or can be contained in a single package on a single package substrate. For example, components of the data processing system 500 can be located on several different packages at one location (e.g., a data center) or at multiple locations. For example, the components of the data processing system 500 can be located in different geographic locations or areas, such as cities, states, or countries.

[0046] The 500 data processing system can be part of a data center that handles a variety of different requirements. For example, the 500 data processing system can receive a data processing request via the 506 network interface to perform encryption, decryption, machine learning, video processing, speech recognition, image recognition, data compression, database search ranking, bioinformatics, network security pattern identification, spatial navigation, digital signal processing, or other specialized tasks.

[0047] The techniques and methods described here can be applied to other types of integrated circuit systems. For example, the hybrid modular multiplier can be used with central processing units (CPUs), graphics cards, hard drives, or other components.

[0048] While the embodiments set forth in this disclosure may take various modifications and alternative forms, certain embodiments are illustrated by way of example in the drawings and are described in detail herein. However, the disclosure is not intended to be limited to the specific forms disclosed. The disclosure is intended to cover all modifications, equivalents, and alternatives that fall within the scope and protection of the disclosure, as defined by the following appended claims.

[0049] The techniques presented and claimed herein relate to and are applied to material objects and concrete examples of a practical nature that demonstrably improve the current technical field and are therefore not abstract, intangible, or purely theoretical. Furthermore, if a claim contains one or more elements at the end of this description that are designated as "means for [performing] [a function]..." or "steps for [performing] [a function]...", it is intended that these elements are to be configured in accordance with 35 USC 112(f). However, for all claims that contain elements designated in any other way, these elements are not to be configured in accordance with 35 USC 112(f). Exemplary embodiments

[0050] Exemplary embodiments of the disclosure may include, among other things, the following:

[0051] EXAMPLE EXECUTION 1. Integrated circuit device comprising: a first tensor circuit comprising a first set of multipliers of a first accuracy and first summation circuit arrangement; and a second tensor circuit comprising a second set of multipliers of a second accuracy and second summation circuit arrangement;

[0052] where the first tensor circuit and the second tensor circuit are configurable to jointly perform a multiplication operation with a third accuracy that is higher than the first accuracy and the second accuracy.

[0053] EXAMPLE EXECUTION 2. Integrated circuit device according to exemplary embodiment 1, comprising: a first bit-shifting circuit arrangement that is configurable to bit-shift a result from the first tensor circuit with respect to a result from the second tensor circuit; and a first addition circuit arrangement that is configurable to add the bit-shifted result from the first tensor circuit and the result from the second tensor circuit.

[0054] EXAMPLE EXECUTION 3. Integrated circuit device according to exemplary embodiment 1, comprising: a third tensor circuit comprising a third set of multipliers of the first accuracy and third summation circuit arrangement; and a fourth tensor circuit comprising a fourth set of multipliers of the second accuracy and second summation circuit arrangement; wherein the first tensor circuit, the second tensor circuit, the third tensor circuit and the fourth tensor circuit are configurable to jointly perform a multiplication operation with a fourth accuracy that is higher than the first accuracy and the second accuracy.

[0055] EXAMPLE EXECUTION 3. Integrated circuit device according to exemplary embodiment 3, wherein: the first tensor circuit and the second tensor circuit lie within a first digital signal processing block; and The third tensor circuit and the fourth tensor circuit are located within a second digital signal processing block: the integrated circuit device comprises the following: a dedicated connection between the first digital signal processing block and the second digital signal processing block; a bit-shifting circuit arrangement that is configurable to bit-shift a result from the first digital signal processing block with respect to a result from the second digital signal processing block; and an addition circuit arrangement that is configurable to sum the bit-shifted result from the first digital signal processing block and the result from the second digital signal processing block.

[0056] EXAMPLE EXECUTION 4. Integrated circuit device according to embodiment 3, wherein the multiplication operation comprises obtaining a product equal to multiplying a first value by a second value, wherein: The first tensor circuit can be configured to multiply a first part of the first value with a first part of the second value; The second tensor circuit can be configured to multiply the first part of the first value by a second part of the second value; The third tensor circuit can be configured to multiply a second part of the first value by the first part of the second value; and The fourth tensor circuit can be configured to multiply the second part of the first value with the second part of the second value.

[0057] EXAMPLE EXECUTION 5. Integrated circuit device according to exemplary embodiment 4, comprising: a first bit-shifting circuit arrangement that is configurable to bit-shift a first result from the first tensor circuit relative to a second result from the second tensor circuit; a second bit-shifting circuit arrangement that is configurable to bit-shift a third result from the third tensor circuit relative to a fourth result from the fourth tensor circuit; a first addition circuit arrangement that is configurable to add the first shifted result and the second result to obtain a fifth result; a second addition circuit arrangement that is configurable to add the third shifted result and the fourth result to obtain a sixth result; a third bit-shifting circuit arrangement that is configurable to shift the fifth result bitwise relative to the sixth result; and a third addition circuit arrangement that is configurable to add the fifth shifted result and the sixth result to obtain the product equal to multiplying the first value by the second value.

[0058] EXAMPLE EXECUTION 6. Integrated circuit device according to embodiment 3, wherein the first tensor circuit, the second tensor circuit, the third tensor circuit, the fourth tensor circuit, the first bit shift circuit, the second bit shift circuit, the first addition circuit, the second addition circuit, the third bit shift circuit and the third addition circuit are formed in a hardened circuit.

[0059] EXAMPLE EXECUTION 7. Integrated circuit device according to embodiment 3, wherein the first accuracy is 8 bits, the second accuracy is 8 bits and the fourth accuracy is 16x16 bits.

[0060] EXAMPLE EXECUTION 8. Integrated circuit device according to exemplary embodiment 1, wherein the first accuracy is equal to the second accuracy.

[0061] EXAMPLE EXECUTION 10. Integrated circuit device according to example embodiment 1, wherein the first accuracy differs from the second accuracy.

[0062] EXAMPLE EXECUTION 11. Filter circuit arrangement comprising the following: multiple tensor circuits that are configurable to multiply sets of components of input data with sets of components of weights; a bit-shifting circuit arrangement that is configurable to shift a portion of the results output by the tensor circuits in order to produce shifted results; and an addition circuit arrangement that is configurable to sum the shifted part of the results with the unshifted results to produce an output signal.

[0063] EXAMPLE IDEAL FORM 12. Filter circuit arrangement of exemplary embodiment 11, wherein a first section of the filter circuit arrangement comprises a first accuracy and a second section of the filter circuit arrangement comprises a second accuracy.

[0064] EXEMPLARY EMBODY 13. Filter circuit arrangement of exemplary embodiment 11, wherein a first set of the plurality of tensor circuits each comprises multipliers with inputs of first accuracy and second accuracy, wherein the first accuracy differs from the second accuracy.

[0065] EXAMPLE EXECUTION 14. Filter circuit arrangement of exemplary embodiment 11, wherein: The sets of components of the input data include the following: a first data component that holds a first set of the most significant bits of a first input data value; and a second data component that holds a second set of least significant bits of the first input data value; and The sets of components of the weightings include the following: a first weighting component that holds a first set of the most significant bits of a first weight value; and a second weighting component that holds a second set of least significant bits of the first weighting value.

[0066] EXAMPLE EMBODY FORM 15. Filter circuit arrangement according to embodiment 11, wherein the tensor circuits comprise a first set of registers and a second set of registers, wherein the first set of registers is configurable to store a first part of the sets of components of the input data or the sets of components of the weights to be used for performing multiplication operations, while a second part of the sets of components of the input data or the sets of components of the weights are loaded via the second set of registers.

[0067] EXAMPLE EMBODY FORM 16. The filter circuit arrangement according to embodiment 11, wherein the tensor circuits comprise a first set of registers and a second set of registers and are configurable to implement a decimation filter, wherein the first set of registers is configurable to store a first part of the sets of components of the input data that represent either even data samples or odd data samples, and wherein the second set of registers is configurable to store a second part of the sets of components of the input data that represent the other even and odd data samples, wherein the tensor circuits are configurable to perform multiplication operations based on the storage from the first set of registers, and wherein the first set of registers is configurable to shift data to the second set of registers.and the second set of registers is configurable to shift data to the first set of registers between multiplication operations.

[0068] EXAMPLE EXECUTION 17. Programmable logic device, comprising: programmable logic circuit arrangement that is configurable to implement soft logic circuits; and embedded digital signal processing blocks that are configurable to perform mathematical operations based on a hardened logic circuit arrangement, wherein at least some of the digital signal processing blocks include: a tensor circuit that includes the following: a set of multiplier circuits that are configurable to multiply respective multiplicand values ​​with multiplier values; a first set of registers that are configurable to store a first set of multiplier values; a second set of registers that are configurable to store a second set of multiplier values a first set of multiplexers, wherein each multiplexer of the first set of multiplexers receives inputs from one of the first set of registers and one of the second set of registers and selectively outputs to one of the set of multiplier circuits; a second set of multiplexers, wherein each multiplexer of the second set of multiplexers receives inputs from one of the first set of registers and one of the second set of registers and selectively outputs to an adjacent one of the first set of registers; and a third set of multiplexers, wherein each multiplexer of the first set of multiplexers receives inputs from one of the first set of registers and one of the second set of registers and selectively outputs to an next of the second set of registers.

[0069] EXAMPLE EXECUTION 18. Programmable logic device according to embodiment 17, wherein the tensor circuit is configurable to be used in a decimation filter, wherein the first set of multiplier values ​​corresponds to even or odd data samples and the second set of multiplier values ​​corresponds to the other even or odd data samples.

[0070] EXAMPLE EXECUTION 19. Programmable logic device according to embodiment 17, wherein the tensor circuit is configurable to be used in a finite impulse response filter that operates on the first set of multiplier values ​​while the second set of multiplier values ​​is being loaded.

[0071] EXAMPLE EMBODY 20. Programmable logic device according to embodiment 17, wherein the tensor circuit has a first accuracy or a second accuracy and wherein several digital signal processing blocks are configurable to jointly perform a multiplication operation with a third accuracy that is higher than the first accuracy and the second accuracy.

Claims

[1] Integrated circuit device comprising: a first tensor circuit comprising a first set of multipliers of a first accuracy and first summation circuit arrangement; and a second tensor circuit comprising a second set of multipliers of a second accuracy and second summation circuit arrangement; where the first tensor circuit and the second tensor circuit are configurable to jointly perform a multiplication operation with a third accuracy that is higher than the first accuracy and the second accuracy. [2] Integrated circuit device according to claim 1, comprising: a first bit-shifting circuit arrangement that is configurable to bit-shift a result from the first tensor circuit with respect to a result from the second tensor circuit; and a first addition circuit arrangement that is configurable to add the bit-shifted result from the first tensor circuit and the result from the second tensor circuit. [3] Integrated circuit device according to claim 1, comprising: a third tensor circuit comprising a third set of multipliers of the first accuracy and third summation circuit arrangement; and a fourth tensor circuit comprising a fourth set of multipliers of the second accuracy and second summation circuit arrangement; wherein the first tensor circuit, the second tensor circuit, the third tensor circuit and the fourth tensor circuit are configurable to jointly perform a multiplication operation with a fourth accuracy that is higher than the first accuracy and the second accuracy. [4] Integrated circuit device according to claim 3, wherein: the first tensor circuit and the second tensor circuit lie within a first digital signal processing block; and The third tensor circuit and the fourth tensor circuit are located within a second digital signal processing block: the integrated circuit device comprises the following: a dedicated connection between the first digital signal processing block and the second digital signal processing block; a bit-shifting circuit arrangement that is configurable to bit-shift a result from the first digital signal processing block with respect to a result from the second digital signal processing block; and an addition circuit arrangement that is configurable to sum the bit-shifted result from the first digital signal processing block and the result from the second digital signal processing block. [5] Integrated circuit device according to claim 3, wherein the multiplication operation comprises obtaining a product which is equal to the multiplication of a first value by a second value, wherein: The first tensor circuit can be configured to multiply a first part of the first value with a first part of the second value; The second tensor circuit can be configured to multiply the first part of the first value by a second part of the second value; The third tensor circuit can be configured to multiply a second part of the first value by the first part of the second value; and The fourth tensor circuit can be configured to multiply the second part of the first value with the second part of the second value. [6] Integrated circuit device according to claim 4, comprising: a first bit-shifting circuit arrangement that is configurable to bit-shift a first result from the first tensor circuit relative to a second result from the second tensor circuit; a second bit-shifting circuit arrangement that is configurable to bit-shift a third result from the third tensor circuit relative to a fourth result from the fourth tensor circuit; a first addition circuit arrangement that is configurable to add the first shifted result and the second result to obtain a fifth result; a second addition circuit arrangement that is configurable to add the third shifted result and the fourth result to obtain a sixth result; a third bit-shifting circuit arrangement that is configurable to shift the fifth result bitwise relative to the sixth result; and a third addition circuit arrangement that is configurable to add the fifth shifted result and the sixth result to obtain the product equal to multiplying the first value by the second value. [7] Integrated circuit device according to claim 3, wherein the first tensor circuit, the second tensor circuit, the third tensor circuit, the fourth tensor circuit, the first bit shift circuit, the second bit shift circuit, the first addition circuit, the second addition circuit, the third bit shift circuit and the third addition circuit are formed in a hardened circuit. [8] Integrated circuit device according to claim 3, wherein the first accuracy is 8 bits, the second accuracy is 8 bits and the fourth accuracy is 16 x 16 bits. [9] Integrated circuit device according to any one of claims 1 to 8, wherein the first accuracy is equal to the second accuracy. [10] Integrated circuit device according to any one of claims 1 to 8, wherein the first accuracy differs from the second accuracy. [11] Filter circuit arrangement comprising the following: multiple tensor circuits that are configurable to multiply sets of components of input data with sets of components of weights; a bit-shifting circuit arrangement that is configurable to shift a portion of the results output by the tensor circuits in order to produce shifted results; and an addition circuit arrangement that is configurable to sum the shifted part of the results with the unshifted results to produce an output signal. [12] Filter circuit arrangement according to claim 11, wherein a first section of the filter circuit arrangement comprises a first accuracy and a second section of the filter circuit arrangement comprises a second accuracy. [13] Filter circuit arrangement according to claim 11, wherein a first set of the multiple tensor circuits each comprises multipliers with inputs of first accuracy and second accuracy, wherein the first accuracy differs from the second accuracy. [14] Filter circuit arrangement according to claim 11, wherein: The sets of components of the input data include the following: a first data component that holds a first set of the most significant bits of a first input data value; and a second data component that holds a second set of least significant bits of the first input data value; and The sets of components of the weightings include the following: a first weighting component that holds a first set of the most significant bits of a first weight value; and a second weighting component that holds a second set of least significant bits of the first weighting value. [15] Filter circuit arrangement according to one of claims 11 to 14, wherein the tensor circuits comprise a first set of registers and a second set of registers, wherein the first set of registers is configurable to store a first part of the sets of components of the input data or the sets of components of the weights to be used to perform multiplication operations, while a second part of the sets of components of the input data or the sets of components of the weights are loaded via the second set of registers. [16] Filter circuit arrangement according to any one of claims 11 to 14, wherein the tensor circuits comprise a first set of registers and a second set of registers and are configurable to implement a decimation filter, wherein the first set of registers is configurable to store a first part of the sets of components of the input data that represent either even data samples or odd data samples, and wherein the second set of registers is configurable to store a second part of the sets of components of the input data that represent the other even and odd data samples, wherein the tensor circuits are configurable to perform multiplication operations based on the storage from the first set of registers, and wherein the first set of registers is configurable to shift data to the second set of registers.and the second set of registers is configurable to shift data to the first set of registers between multiplication operations. [17] Programmable logic device comprising: programmable logic circuit arrangement that is configurable to implement soft logic circuits; and embedded digital signal processing blocks that are configurable to perform mathematical operations based on a hardened logic circuit arrangement, wherein at least some of the digital signal processing blocks include: a tensor circuit that includes the following: a set of multiplier circuits that are configurable to multiply respective multiplicand values ​​with multiplier values; a first set of registers that are configurable to store a first set of multiplier values; a second set of registers that are configurable to store a second set of multiplier values a first set of multiplexers, wherein each multiplexer of the first set of multiplexers receives inputs from one of the first set of registers and one of the second set of registers and selectively outputs to one of the set of multiplier circuits; a second set of multiplexers, wherein each multiplexer of the second set of multiplexers receives inputs from one of the first set of registers and one of the second set of registers and selectively outputs to an adjacent one of the first set of registers; and a third set of multiplexers, wherein each multiplexer of the first set of multiplexers receives inputs from one of the first set of registers and one of the second set of registers and selectively outputs to an next of the second set of registers. [18] Programmable logic device according to claim 17, wherein the tensor circuit is configurable to be used in a decimation filter, wherein the first set of multiplier values ​​corresponds to even or odd data samples and the second set of multiplier values ​​corresponds to the other even or odd data samples. [19] Programmable logic device according to claim 17 or 18, wherein the tensor circuit is configurable to be used in a finite impulse response filter that operates on the first set of multiplier values ​​while the second set of multiplier values ​​is being loaded. [20] Programmable logic device according to claim 17 or 18, wherein the tensor circuit has a first accuracy or a second accuracy and wherein several digital signal processing blocks are configurable to jointly perform a multiplication operation with a third accuracy that is higher than the first accuracy and the second accuracy. [21] Integrated circuit device comprising: a programmable logic circuit, and embedded hardened arithmetic circuit arrangement; wherein the programmable logic circuit arrangement and the embedded hardened arithmetic circuit arrangement are configurable to form a filter circuit arrangement comprising the following: multiple tensor circuits that are configurable to multiply sets of components of input data with sets of components of weights; a bit-shifting circuit arrangement that is configurable to shift a portion of the results output by the tensor circuits in order to produce shifted results; and an addition circuit arrangement that is configurable to sum the shifted part of the results with the unshifted results to produce an output signal. [22] Integrated circuit device according to claim 21, wherein: The sets of components of the input data include the following: a first data component that holds a first set of the most significant bits of a first input data value; and a second data component that holds a second set of least significant bits of the first input data value; and The sets of components of the weightings include the following: a first weighting component that holds a first set of the most significant bits of a first weight value; and a second weighting component that holds a second set of least significant bits of the first weighting value. [23] Integrated circuit device according to claim 21 or 22, wherein the tensor circuits comprise a first set of registers and a second set of registers and are configurable to implement a decimation filter, wherein the first set of registers is configurable to store a first part of the sets of components of the input data representing one of the even data samples and one of the odd data samples, and wherein the second set of registers is configurable to store a second part of the sets of components of the input data representing the other of the even data samples and one of the odd data samples, wherein the tensor circuits are configurable to perform multiplication operations based on the storage from the first set of registers, wherein the first set of registers is configured to move data to the second set of registers,and wherein the second set of registers is configurable to shift data to the first set of registers between multiplication operations. [24] Integrated circuit device comprising: Means for performing a first multitude of multiplication operations with a first degree of accuracy; and Means for performing a second plurality of multiplication operations with a second degree of accuracy; wherein the means for performing the first plurality of multiplication operations and the means for performing the second plurality of multiplication operations are configurable to jointly perform a third multiplication operation with a third accuracy that is higher than the first accuracy and the second accuracy. [25] Integrated circuit device according to claim 24, wherein the first accuracy is identical to the second accuracy.

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