Semiconductor storage device

Abstract

A non-volatile semiconductor storage device includes a first semiconductor layer enclosing a first memory cell transistor enclosing a first channel, a second semiconductor layer enclosing a second memory cell transistor enclosing a second channel, a third semiconductor layer enclosing a third memory cell transistor enclosing a third channel, and a control circuit that controls the first memory cell transistor up to the third memory cell transistor so that a write operation can be performed.When performing a write operation on the second memory cell transistor, the control circuit applies a first voltage, which is a reference voltage, to the second channel, applies a second voltage, which is greater than the first voltage, to the first channel, and then applies the second voltage to the third channel, thereby driving the voltage applied to the first channel up to a third voltage, which is greater than the second voltage.

Description

AREA

[0001] The embodiments described herein generally relate to a non-volatile semiconductor storage device. GENERAL STATE OF THE ART

[0002] NAND flash memory is a type of non-volatile semiconductor storage device. To increase the capacity of NAND flash memory, three-dimensional NAND flash memory, in which multiple cells are arranged three-dimensionally, has been put into practical use. For example, three-dimensional NAND flash memory designs can be categorized into those where memory strings are arranged vertically and those where memory strings are arranged horizontally. BRIEF DESCRIPTION OF THE DRAWINGS Fig. is a block diagram of a non-volatile semiconductor storage device according to one embodiment. Fig. is a circuit diagram of a memory cell arrangement enclosed in a non-volatile semiconductor memory device according to one embodiment. Fig. is a top view showing a configuration of a memory cell area, part of an SGD area and part of an SGS area of ​​a non-volatile semiconductor memory device according to one embodiment. Fig. is a top view showing a planar configuration of part of a memory cell area and an SGS area of ​​a non-volatile semiconductor memory device according to one embodiment. Fig. is a circuit diagram showing an example of a circuit configuration of a reading amplifier section according to one embodiment. Fig. is a threshold distribution diagram showing an example of a threshold distribution of a memory cell transistor according to one embodiment. Fig. is a diagram showing an example of a program loop in a non-volatile semiconductor storage device according to one embodiment. Fig. is a flowchart that shows an example of a write operation in a non-volatile semiconductor memory device according to a comparative example. Fig. is a perspective view showing an example of a channel in a non-volatile semiconductor storage device according to one embodiment. Fig. is a perspective view showing an example of a channel state in the non-volatile semiconductor storage device according to the comparison example. Fig. is a perspective view showing an example of a channel in the non-volatile semiconductor storage device according to the comparison example. Fig. is a flowchart showing a write operation in a non-volatile semiconductor memory device according to one embodiment. Fig. is a threshold distribution diagram showing an example of a threshold distribution of a memory cell transistor according to one embodiment. Fig. is a flowchart showing a write operation in a non-volatile semiconductor memory device according to one embodiment. Fig. is a flowchart showing a write operation in a non-volatile semiconductor memory device according to one embodiment. DETAILED DESCRIPTION

[0003] One objective of the present disclosure is to provide a non-volatile semiconductor storage device capable of suppressing degradation in the distribution width of a threshold value.

[0004] A non-volatile semiconductor storage device according to this embodiment comprises a plurality of first memory cell transistors, a plurality of second memory cell transistors, and a plurality of third memory cell transistors, each of which is set to a threshold voltage of 2 n(n is an integer equal to 2 or greater) or several different levels can be set, a first bit line extending in a first direction, a second bit line and a third bit line parallel to the first bit line, a source line located on one side opposite to the first bit line with respect to the first direction and extending along a second direction intersecting the first direction, a first semiconductor layer extending in the first direction and enclosing the plurality of first memory cell transistors electrically connected between the first bit line and the source line, a second semiconductor layer enclosing the plurality of second memory cell transistors electrically connected between the second bit line and the source line and stacked with the first semiconductor layer along a third direction,which intersects both the first direction and the second direction, a third semiconductor layer enclosing the plurality of third memory cell transistors, electrically connected between the third bit line and the source line and stacked on one side of the first semiconductor layer, opposite to a side on which the second semiconductor layer is stacked, along the third direction, and a control circuit configured to control each of the plurality of first memory cell transistors, each of the plurality of second memory cell transistors, and each of the plurality of third memory cell transistors to perform a write operation comprising a first operation and a second operation,wherein, during the execution of the write operation to write data to a second memory cell transistor among the plurality of second memory cell transistors, the control circuit performs a control operation such that it is possible to carry out the first operation of supplying a first voltage as a reference voltage to the second bit line and a second channel of the plurality of second memory cell transistors, of supplying a second voltage, greater than the first voltage, to the first bit line and a first channel of the plurality of first memory cell transistors, and then of supplying the second voltage to the third bit line and a third channel of the plurality of third memory cell transistors, and of raising the voltage supplied to the first channel to a third voltage, greater than the second voltage.

[0005] The following describes a non-volatile semiconductor storage device according to one embodiment with reference to the drawings. Furthermore, in the following description, components with the same functions and configurations are designated by common reference numerals. Additionally, if a plurality of components with common reference numerals need to be distinguished from one another, subscripts are appended to the same reference numerals to differentiate the components. Conversely, if a plurality of components does not need to be distinguished from one another, only one common reference numeral is appended to the plurality of components, and no subscript is appended to it.

[0006] In the description, drawings and claims of the present application (hereinafter also referred to as "the present description and the like"), a non-volatile semiconductor storage device, which is one of the embodiments, is described, for example, a three-dimensional NAND-type flash memory and in particular a three-dimensional NAND-type flash memory in which a memory string extends horizontally. [FIRST VERSION]

[0007] With reference to Fig. until Fig. A non-volatile semiconductor storage device 1 and a method for controlling the non-volatile semiconductor storage device 1 will be described. [1. STORAGE SYSTEM CONFIGURATION]

[0008] A storage system configuration is described with reference to Fig. be described. Fig. Figure 1 is a block diagram showing an example configuration of a memory system 3 that includes a non-volatile semiconductor memory device 1. As shown in Figure 2 Fig. As shown, the storage system 3 includes the non-volatile semiconductor storage device 1 and a storage controller 2. For example, the storage system 3 is a memory card, such as an SSD (solid-state drive) or an SDTM card. The storage system 3 may include a host device (not shown). For example, the storage controller 2 controls a write operation, a read operation, and an erase operation of the non-volatile semiconductor storage device 1. [2. CONFIGURATION OF THE NON-VOID SEMICONDUCTOR STORAGE DEVICE]

[0009] A configuration of the non-volatile semiconductor storage device 1 is described with reference to Fig. The non-volatile semiconductor storage device 1 includes an input / output circuit 10, a logic control circuit 11, a status register 12, an address register 13, an instruction register 14, a sequence control 15, a ready / busy circuit 16, a voltage generation circuit 17, a memory cell array 18, a line decoder 19, a read amplifier module 20, a data register 21, and a column decoder 22.

[0010] The input / output circuit 10 controls the input (receiving) of a signal DQ from the memory controller 2 and the output (sending) of the signal DQ to the memory controller 2. For example, the signal DQ includes data DAT, an address ADD, and a command CMD. Specifically, the input / output circuit 10 sends the data DAT received from the memory controller 2 to data register 21, sends the address ADD received from the memory controller 2 to address register 13, and sends the command CMD received from the memory controller 2 to command register 14. Furthermore, the input / output circuit 10 sends status information STS received from status register 12, the data DAT received from data register 21, the address ADD received from address register 13, and so on to the memory controller 2.

[0011] The logic control circuit 11 receives various types of control signals from the memory controller 2. The logic control circuit 11 controls the input / output circuit 10 and the sequence control 15 according to the received control signal.

[0012] For example, status register 12 temporarily holds the status data STS during the write operation, the read operation and the erase operation and notifies the storage controller 2 whether the operations have been completed normally or not.

[0013] Address register 13 temporarily holds the received address ADD. Address register 13 transmits a row address RADD to the row decoder 19 and transmits the column address CADD to the column decoder 22.

[0014] The command register 14 temporarily stores the received command CMD and transmits the command CMD to the sequence control 15.

[0015] The sequence control unit 15 controls the operation of the non-volatile semiconductor storage device 1. For example, the sequence control unit 15 controls the status register 12, the ready-busy circuit 16, the voltage generation circuit 17, the line decoder 19, the read amplifier module 20, the data register 21, the column decoder 22, and the like, according to the received CMD instruction, and executes the write operation, the read operation, the erase operation, and the like. The sequence control unit 15 in the non-volatile semiconductor storage device 1 can be referred to as a "controller".

[0016] The Ready-Busy circuit 16 sends a Ready-Busy signal RBn to the storage controller 2 according to an operating status of the sequence control 15.

[0017] The voltage generation circuit 17 generates voltages necessary for the write, read, and erase operations under the control of the sequence controller 15. For example, the voltage generation circuit 17 supplies the generated voltage to the memory cell array 18, the line decoder 19, the read amplifier module 20, and the like. The line decoder 19 and the read amplifier module 20 apply the voltage supplied by the voltage generation circuit 17 to memory cell transistors in the memory cell array 18.

[0018] The memory cell arrangement 18 comprises a plurality of blocks BLK (BLK0 to BLK3, ...), each containing a plurality of non-volatile memory cell transistors MC, which are linked to rows and columns. Each block BLK comprises a plurality of string parts SU (SU0 to SU3, ...). Each string part SU comprises a plurality of memory groups MG (memory string pairs). The number of blocks BLK in the memory cell arrangement 18, the number of string parts SU in the blocks BLK, and the number of memory groups MG in the string parts are arbitrarily determined. Details of the memory cell arrangement 18 will be described later.

[0019] The line decoder 19 decodes the line address RADD. Based on a decoding result, the line decoder 19 applies a necessary voltage to the memory cell array 18.

[0020] For example, the read amplification module 20 reads the data read from the memory cell arrangement 18 and sends the read data to the data register 21. Furthermore, the read amplification module 20 also sends write data to the memory cell arrangement 18, for example, during the write operation.

[0021] Data register 21 includes a variety of latch circuits. The latch circuit temporarily holds the write or read data.

[0022] For example, the column decoder 22 decodes the column address CADD during the write operation, the read operation and the erase operation and selects the latching circuit in the data register 21 according to the decoding result. [3. STORAGE CELL ARRANGEMENT CONFIGURATION]

[0023] A configuration of the memory cell arrangement 18 is described with reference to Fig. be described. Fig. This is a circuit diagram showing an example of the memory cell arrangement 18. A circuit configuration of the memory cell arrangement 18, which is shown in Fig. The circuit configuration and a semiconductor layer (channel layer) of the memory cell arrangement 18 in the non-volatile semiconductor memory device 1 are not limited to the configuration shown in Fig. configurations shown are the same as those in Fig. or similar to them, are described as necessary, and descriptions of configurations that are the same as the configurations in Fig. or similar to them, can be omitted.

[0024] As described in "2. Configuration of the Non-Volatile Semiconductor Memory Device", the memory cell arrangement 18 includes a plurality of blocks BLK. Each block BLK includes a plurality of string parts SU. Each string part SU includes a plurality of memory groups MG (memory string pairs).

[0025] As in Fig. As shown, the plurality of memory groups MG is stacked in a Z-direction and corresponds to a plurality of semiconducting layers electrically connected by bit line contacts (not shown). For example, the plurality of memory groups MG that are in Fig. shown are areas that are traversed by storage trenches MT (see Fig. and Fig. ) are separated. Each of the semiconductor layers in the non-volatile semiconductor memory device 1 corresponds to the string part SU. For example, among select gate lines corresponding to semiconductor layer 31 (memory group MG), a drain side is designated by "SDG" and a source side is designated by "SGS". A channel layer (a channel) is referred to as a "semiconductor layer".

[0026] Furthermore, the memory cell arrangement 18 includes a plurality of memory groups MG. Specifically, each of the semiconductor layers 31 (the string parts SU) stacked in the Z direction includes a plurality of memory groups MG separated in a Y direction. Each memory group MG includes two memory strings MSa and MSb and selection transistors ST1 and ST2. In the case where the memory strings MSa and MSb are not distinguished from each other in the non-volatile semiconductor memory device 1, the memory strings can be referred to as "memory strings MS". A selection transistor ST1 in the non-volatile semiconductor memory device 1 can be referred to as a "drain-side selection transistor", and the selection transistor ST2 in the non-volatile semiconductor memory device 1 can be referred to as a "source-side selection transistor".

[0027] For example, the memory string MSa can include four memory cell transistors MCa0, MCa1, MCa2, and MCa3. Similarly, the memory string MSb can include four memory cell transistors MCb0, MCb1, MCb2, and MCb3. In the case where the memory cell transistors MCa0 to MCa3 and MCb0 to MCb3 are not distinguished in the non-volatile semiconductor memory device 1, the memory cell transistors can be referred to as "memory cell transistors MC".

[0028] The memory cell transistor MC includes a control gate and a charge storage layer and holds data in a non-volatile manner. The memory cell transistor MC can be of the MONOS type, in which an insulating layer is used for the charge storage layer, or it can be of the FG type, in which a conductive layer is used for the charge storage layer. In one example, the memory cell transistor MC in the non-volatile semiconductor memory device 1 is of the FG type. Furthermore, the number of memory cell transistors MC included in each memory string MS can be 8, 16, 32, 48, 64, 96, or 128, and the number of memory strings MS is not limited to that shown in the example. Fig. is shown. A single memory cell transistor MC can be configured for 2 n(n is a positive integer) or more ways to set a threshold voltage. In this case, a plurality of memory cells, which are units of a read operation and a write operation, can hold n pages of data.

[0029] The memory cell transistors MCa0 to MCa3, contained in the memory string MSa, are connected in series such that their current paths are in series. Similarly, the memory cell transistors MCb0 to MCb3, contained in the memory string MSb, are connected in series such that their current paths are in series. The drains of memory cell transistors MCa0 and MCb0 are both connected to a source of selector transistor ST1. The sources of memory cell transistors MCa3 and MCb3 are both connected to a drain of selector transistor ST2. The number of selector transistors ST1 and ST2 included in the memory group MG is optional and can be one or more.Furthermore, the memory cell transistors MCa0 to MCa3 and MCb0 to MCb3 can, for example, function as a memory string, according to the dimensions of semiconductor layer 31, which functions as a channel layer (a channel) that will be described later. That is, the memory cell transistors MCb0, MCa0, MCb1, MCa1, MCb2, MCa2, MCb3, and MCa3 can function as a memory string connected in series.

[0030] The gates of the memory cell transistors MC in the multitude of memory groups MG, which are arranged along the Z-direction, are connected via a contact plug CWL (see Fig. ) are connected together to a word line WL. For example, the gates (gate electrodes) of the plurality of memory cell transistors MCa0, which are arranged along the Z-direction, are connected to a common word line WLa0. Similarly, the gates (gate electrodes) of the plurality of memory cell transistors MCa1, MCa2, and MCa3 are each connected to common word lines WLa1, WLa2, and WLa3, respectively. Similarly, the gates (gate electrodes) of the plurality of memory cell transistors MCb0 to MCb3 are each connected to common word lines WLb0 to WLb3. One side consists of a plurality of memory cell transistors MC, which are connected to the common word line WL.A multitude of data (threshold voltages) stored in the multitude of memory cell transistors MC enclosed in one page corresponds to the data of one page that will be written to later.

[0031] The drains of the selection transistors ST1 of the multiple memory groups MG, arranged along the Z-direction, are connected to distinct bit lines BL. Furthermore, the gates (gate electrodes) of the selection transistors ST1 of the multiple memory groups MG, arranged along the Z-direction, are connected to a selection gate line SGD (for example, SGD1). The drains of the selection transistors ST1 of the multiple memory groups MG, arranged along the Z-direction, are connected via the distinct bit line contacts (not shown) to the bit lines BL, which correspond to different bit line contacts. The selection gate line SGD can be referred to as a "drain-side selection gate line."

[0032] Specifically, in the selection transistor ST1, which corresponds to the memory group MG located in the top layer, the drain is connected to a bit line BLk-1, and the gate electrode is connected to a selection gate line SGD1. In the selection transistor ST1, which corresponds to the memory group MG located in the bottom layer, the drain is connected to a bit line BLk+1, and the gate electrode is connected to the selection gate line SGD1. In the selection transistors ST1, which correspond to the memory groups MG stacked one layer along the Z-direction with respect to the memory group MG located in the bottom layer, the drain is connected to the bit line BLk, and the gate electrode is connected to the selection gate line SGD1.

[0033] The source of each selection transistor ST2 of the plurality of memory groups MG, which are arranged along the Z direction, is connected via a contact plug (a source line contact plug CSL, a conductive layer 45, see Fig. ) is connected to a source line SL1. Furthermore, the gates (gate electrodes) of the selection transistors ST2 of the plurality of memory groups MG, which are arranged along the Z-direction, are connected to a selection gate line SGS (for example, SGS1). The selection gate line SGS can be referred to as a "source-side selection gate line".

[0034] Furthermore, although not shown, the plurality of memory groups MG arranged along the Z-direction in the non-volatile semiconductor memory device 1 is also arranged along the Y-direction. For example, the non-volatile semiconductor memory device 1 includes a configuration in which a plurality of memory groups MG arranged along the Z-direction are arranged as a memory configuration, and a plurality of memory configurations are arranged such that they are adjacent to each other along the Y-direction.

[0035] A multitude of semiconductor layers 31 (see Fig. and Fig. The semiconductor layers 31 are arranged in a layer in the Z-direction. The semiconductor layers 31, which are arranged in layers, are separated in the Y-direction by storage trenches MT extending in the X-direction. The semiconductor layers 31, separated in the Y-direction within each layer, extend in the Z-direction and the X-direction to form storage groups MG. As a result, the semiconductor layers 31, which are arranged in a layer, form a plurality of storage groups MG arranged in the Y-direction. For example, the plurality of semiconductor layers 31, which are arranged in a layered manner in the non-volatile semiconductor storage device 1, includes semiconductor layers 31 from the first layer to the nth layer, such as the first layer, the second layer, ..., the k-1th layer, the k-th layer, the k+1th layer, ..., the n-1th layer and the nth layer, from the top along the Z-direction. Here, the numerical value k is a natural number greater than 2, and the numerical value n is a natural number greater than k+1. For example, the plurality of semiconductor layers is 31, which are in . Fig. Semiconductor layers of the k-1th layer, the k-th layer and the k+1th layer are shown from the top along the Z-direction.

[0036] For example, the non-volatile semiconductor storage device 1 includes a substrate (not shown) that encloses a main surface extending in the X direction (first direction) and the Y direction (second direction), which intersects the X direction. As shown in Fig. As shown, the non-volatile semiconductor memory device 1 has a semiconductor layer 31 (a first channel) of the k-th layer, which includes the bit line BLk (first bit line), which is arranged on one side of the substrate in the Z direction (third direction), intersecting the X and Y directions, and extends in the X direction; the source line SL1, which is arranged on one side of the substrate in the Z direction and extends in the Y and Z directions; a selector transistor ST1-k (first drain-side selector transistor), which is arranged on one side of the substrate in the Z direction and extends in the X direction and is connected to the bit line BLk; a selector transistor ST2-k (first source-side selector transistor), which is connected to the source line SL1; and a memory cell transistor MCb1(BLk) (first memory cell transistor).which is connected between the selection transistor ST1-k and the selection transistor ST2-k, a semiconductor layer 31 (a second channel) of the k-1-th layer with a selection transistor ST1-k-1 (second drain-side selection transistor) connected to the bit line BLk-1 (second bit line), arranged on one side (top) of the k-th semiconductor layer 31 in the Z-direction, extending in the X-direction and different from the bit line BLk, a selection transistor ST2-k-1 (second source-side selection transistor) connected to the source line SL1, and a memory cell transistor MCb1 (BLk-1) (second memory cell transistor) connected between the selection transistor ST1-k-1 and the selection transistor ST2-k-1, a semiconductor layer 31 (a third channel) of the k+1-th layer, which includes a selection transistor ST1-k+1 (third drain-side selection transistor),arranged on the opposite side of the k-1th semiconductor layer 31 in the Z direction with respect to the k-th semiconductor layer 31, which extends in the X direction and is connected to the bit line BLk+1 (third bit line), which is different from the bit line BLk-1 and the bit line BLk-1, a selection transistor ST2-k+1 (third source-side selection transistor) which is connected to the source line SL1, and a memory cell transistor MCb1 (BLk+1) (third memory cell transistor) which is connected between the selection transistor ST1-k+1 and the selection transistor ST2-k+1, and a word line WLb1 which serves as a gate (gate electrode) of the memory cell transistor MCb1 (BLk+1), a gate (gate electrode) of the memory cell transistor MCb1 (BLk), and a gate (gate electrode) of the memory cell transistor MCb1 (BLk-1). functions, exhibits. [4. STRUCTURE OF STORAGE CELL AREA, PART OF THE SGD AREA, SGS AREA AND STAIRCASE CONTACT AREA]

[0037] With reference to Fig. and Fig. An exemplary planar configuration of a part of a memory cell area MCA, an SGD area SGDA and an SGS area SGSA will be described. Fig. is a top view showing part of the memory cell area MCA, the SGD area SGDA and part of the SGS area SGSA of memory cell arrangement 18. Fig. is a top view showing an exemplary stair contact area SCSA corresponding to the memory cell area MCA, the SGS area SGSA, and the select gate line SGS of the memory cell assembly 18. The planar configuration of each area of ​​the memory cell assembly 18 in the non-volatile semiconductor memory device 1, which is in Fig. and Fig. The example shown is an example, and the planar configuration of each region of the memory cell arrangement 18 in the non-volatile semiconductor memory device 1 is not limited to the example shown in Fig. and Fig. configurations shown are the same as those in Fig. and Fig. or similar to them, are described as necessary, and descriptions of configurations that are the same as those in Fig. and Fig. or similar to them, can be omitted.

[0038] As in Fig. As shown, the storage trench MT is provided between the semiconductor layers 31, which are arranged adjacent to each other along the Y direction. Insulating layers (not shown) are embedded in the storage trench MT.

[0039] An insulating layer 32 is provided on a side face of the semiconductor layer 31 in the memory cell region MCA. The insulating layer 32 acts as an etch stop when an insulating layer 36 (a tunnel insulation film) and a charge storage layer 35 are formed, which will be described later.

[0040] Furthermore, a multitude of word line pillars (WLP) are provided in the memory cell area (MCA) to separate the memory trenches (MT). The word line pillar (WLP) comprises a conductive layer 33 extending in the Z-direction and an insulating layer 34 that contacts one side face of the conductive layer 33. The conductive layer 33 acts as a contact plug (CWL). The insulating layer 34 acts as a blocking insulating film for the memory cell transistor (MC).

[0041] The charge storage layer 35 and the insulating layer 36 are provided between the word line pillar WLP and the semiconductor layer 31 to separate the insulating layer 32 along the Y-direction. The insulating layer 36 acts as a tunnel insulation film. Specifically, one side face of the charge storage layer 35 along the X-direction is in contact with the insulating layer 34 of the word line pillar WLP, and the other side faces are in contact with the insulating layer 36 in an XY plane. The other side faces are the other side face along the X-direction and the two side faces along the Y-direction. A portion of the side faces of the insulating layer 36 is in contact with the semiconductor layer 31 and the insulating layer 32.

[0042] Therefore, the insulating layer 34, the charge storage layer 35, and the insulating layer 36 are formed in that order from the conductive layer 33 to the semiconductor layer 31, between the conductive layer 33 and the semiconductor layer 31. A region encompassing a portion of the semiconductor layer 31, a portion of the conductive layer 33, a portion of the insulating layer 34, the charge storage layer 35, and the insulating layer 36 functions as the memory cell transistor MC. A region encompassing a portion of the semiconductor layer 31, a portion of the conductive layer 33, a portion of the insulating layer 34, the charge storage layer 35, and the insulating layer 36 is also referred to as an "intersection region between the semiconductor layer 31 and the word line pillar WLP." In the embodiment described in Fig. As shown, in a semiconductor layer 31, an overlap region between the semiconductor layer 31 and the word line pillar WLP, which is located on a lower side of a paper surface, functions Fig. is provided as the memory string MSa (memory cell transistor MCa), and an overlap area between semiconductor layer 31 and the word line pillar WLP, which is located on a top side of the paper surface of Fig. The memory string provided functions as the memory string MSb (memory cell transistor MCb). Furthermore, for example, the multitude of memory cell transistors MCa, corresponding to semiconductor layer 31, are arranged in the sequence MCa0, MCa1, ... from the SGD region SGDA to the SGS region SGSA. Similarly to the memory cell transistor MCa, the memory cell transistors MCb are arranged in the sequence MCb0, MCb1, ... from the SGD region SGDA to the SGS region SGSA.

[0043] Furthermore, for example, as in Fig. As shown, the memory cell area MCA and the SGS area SGSA of the memory cell arrangement 18 have a configuration in which the four semiconductor layers 31 are independently connected near the SGS area SGSA, and the conductive layer 45, which penetrates the semiconductor layer 31, can be provided in the SGS area SGSA. The conductive layer 45 functions as a source lead contact plug CSL. The semiconductor layer 31 has a circular shape in a connection area with the conductive layer 45. Furthermore, the shape of the semiconductor layer 31 in the connection area with the conductive layer 45 is freely selectable. For example, the shape of the connection area can be a polygon.The connection areas can be shaped in such a way that, when defects of the source lead contact plug CSL, which penetrates the semiconductor layer 31, are processed, sufficient clearances can be ensured to prevent the defects of the source lead contact plug CSL from protruding from the semiconductor layer 31 in the XY plane due to manufacturing variations or the like.

[0044] Similar to the insulating layer 32 in the memory cell region MCA, an insulating layer 46 is provided such that it surrounds the side face of the semiconductor layer 31 in the SGS region SGSA. That is, the insulating layer 46 is provided so that it is in contact with the side face of the semiconductor layer 31. The insulating layers 46 function as a gate insulating film for the selection transistors ST2-k-1 to ST2-k+1. In the insulating layer 46, one side face, opposite the side face in contact with the semiconductor layer 31, is in contact with a conductive layer 47. Furthermore, SiO₂, for example, is used for the insulating layers 46. The insulating layers 46 are preferably formed from a SiO₂ film.For example, in the case where an adjustment of threshold values ​​of the selection transistors ST2-k-1 to ST2-k+1 is required, the insulating layer 46 is preferably formed from a three-layer ONO film in which SiO2, SiN and SiO2 are stacked, instead of the SiON film.

[0045] The conductive layer 47 functions as the select-gate conductor (SGS). Specifically, the conductive layer 47 includes a first section extending in the Y direction and a plurality of second sections within the SGS region (SGSA), in which one side face is in contact with the insulating layer 46 and one end face is in contact with the first section of the conductive layer 47. A conductive material is used for the conductive layer 47. The conductive material can be, for example, a metallic material or a semiconductor, such as impurity-doped silicon or phosphorus-doped polysilicon.

[0046] In the SGS region SGSA, an area encompassing semiconductor layer 31, insulating layer 46, and the second sections of conductive layer 47 from the memory cell region MCA to conductive layer 45 functions as the selection transistor ST2. Specifically, the second sections of conductive layer 47 act as a gate electrode of the selection transistor ST2, insulating layer 46 acts as a gate insulating film of the selection transistor ST2, and channels of the selection transistor ST2 are formed in semiconductor layer 31.

[0047] A conductive layer 49 and an insulating layer 44, which penetrate the first section of the conductive layer 47, are arranged in the stair-step contact region SCSA. The conductive layer 49 acts as a contact plug CSGS. The insulating layer 44 acts as a blind pier HR. For example, the conductive layer 49 is connected to each of the first sections of the conductive layer 47, which are stacked in the Z direction. An insulating layer 40i is formed between the conductive layer 47 and the conductive layer 49, which are not connected. The insulating layer 40i includes insulating layers 41, 42, and 43. The insulating layer 41 is arranged to be in contact with a side face of the conductive layer 49. The side face of the conductive layer 49 is also referred to as an "outer face".The insulating layer 42 is arranged to be in contact with part of an outer surface of the conductive layer 41. The insulating layer 43 is arranged to be in contact with the outer surface of the insulating layer 42. A conductive material is used for the conductive layer 49. The conductive material can be, for example, a metallic material, and in particular, tungsten and titanium nitride (TiN) can be used. For example, the staircase contact region SCSA is a region in which a plurality of select gate leads (SGS) (a plurality of select gate leads including select gate leads SGS0, SGS1, SGS2, SGS3, ...) are arranged in a staircase configuration.

[0048] Furthermore, for example, as in Fig. An insulating layer 38 is shown in the SGD region SDGA arranged to surround the side face of the semiconductor layer 31, similar to the insulating layer 46 in the SGS region SGSA. The insulating layer 38 acts as a gate insulating film for the selection transistors ST1. The insulating layer 38 can be made of the same insulating material as the insulating layer 46.

[0049] In the insulating layer 38, one side face, opposite the side face in contact with the semiconductor layer 31, is in contact with a conductive layer 39. The conductive layer 39 functions as the select-gate conductor SGD. Specifically, the conductive layer 39 includes a first section (not shown) extending in the Y direction and a plurality of second sections in the SGD region SGDA, in which a side face contacts the insulating layer 38 and a tail section contacts the first section of the conductive layer 39. The conductive layer 39 can be made of the same conductive material as the conductive layer 47.

[0050] Furthermore, similar to the selection transistor ST2 in the SGS region SGSA, in the SGD region SGDA, a region encompassing semiconductor layer 31, insulating layer 38, and the second sections of conductive layer 39 from memory cell region MCA to conductive layer 39 functions as the selection transistor ST1. Specifically, the second sections of conductive layer 39 act as a gate electrode of the selection transistor ST1, insulating layer 38 acts as a gate insulating film of the selection transistor ST1, and channels of the selection transistor ST1 are formed in semiconductor layer 31.

[0051] Furthermore, for example, although not shown, similar to the SGS region SGSA, conductive layers independently connected to each of the four semiconductor layers 31 in the SGD region SGDA can penetrate the semiconductor layers 31 that are not connected beneath the four semiconductor layers 31 and act as a contact plug provided in the SGD region SGDA. The semiconductor layers 31 in the SGD region SGDA can have a circular shape in the junction area with the conductive layers acting as the contact plug. Furthermore, the conductive layer acting as the contact plug can be made of the same material as the conductive layer 45 (the source lead contact plug CSL). Also, although not shown, a stepped contact region corresponding to the SGD region SGDA can be provided on the side of the SGD region SGDA, similar to the stepped contact region on the side of the SGS region SGSA.The stair contact area corresponding to the SGD area SGDA is a stair contact area corresponding to the selection gate line SGD and is, for example, an area in which a multitude of selection gate lines SGD (a multitude of selection gate lines SGD, which includes the selection gate lines SGD0, SGD1, SGD2, SGD3, ...) are provided in a stair form. [5. CIRCUIT CONFIGURATION OF THE READER AMPLIFIER SECTION]

[0052] With reference to Fig. An exemplary circuit configuration of a reading amplifier section SAU is shown. Fig. This is an exemplary circuit configuration of the reading amplifier section SAU. Furthermore, the circuit configuration of the reading amplifier section SAU, which is shown in Fig. An example is shown, and the circuit configuration of the read amplifier section SAU of the non-volatile semiconductor storage device 1 is not limited to the example shown in Fig. is shown. Descriptions of the same or similar configurations as those in Fig. until Fig. are described as necessary, and descriptions of the same or similar configurations as those in Fig. until Fig. can be omitted.

[0053] The read amplifier module 20 includes a multitude of read amplifier parts SAU, each linked by bit lines BL1 to BLm (m is a natural number, equal to 2 or greater). Fig. shows a circuit configuration of a reading amplifier section SAU.

[0054] For example, the read amplifier section SAU can temporarily hold data that is read out on the corresponding bit line BL. Furthermore, the read amplifier section SAU can perform a logical operation using temporarily stored data and can temporarily hold data that is subject to the logical operation. For example, the non-volatile semiconductor storage device 1 can perform a read operation and a write operation using the read amplifier module 20 (read amplifier section SAU).

[0055] As in Fig. As shown, the read amplifier section SAU includes a read amplifier section SA and latch circuits SDL, ADL, BDL, CDL, and XDL. The read amplifier section SA and the latch circuits SDL, ADL, BDL, CDL, and XDL are connected by a bus LBUS in such a way that they are able to send and receive data to and from each other.

[0056] For example, during the read operation, the read amplifier section SA reads the data read from the corresponding bit line BL and determines whether the read data is "0" or "1". For example, the read amplifier section SA includes a p-channel MOS transistor 120, n-channel MOS transistors 121 to 128, and a capacitor 129.

[0057] One end of transistor 120 is connected to a power supply line, and one gate of transistor 120 is connected to a node INV in the latch circuit SDL. One end of transistor 121 is connected to the other end of transistor 120, the other end of transistor 121 is connected to a node COM, and a control signal BLX is input to a gate of transistor 121. One end of transistor 122 is connected to the node COM, and a control signal BLC is input to a gate of transistor 122. Transistor 123 is a high breakdown voltage MOS transistor, and one end of transistor 123 is connected to the other end of transistor 122, the other end of transistor 123 is connected to a corresponding bit line BL, and a gate of transistor 123 receives a control signal BLS.

[0058] One end of transistor 124 is connected to node COM, the other end of transistor 124 is connected to node SRC, and one gate of transistor 124 is connected to node INV. One end of transistor 125 is connected to the other end of transistor 120, the other end of transistor 125 is connected to node SEN, and a control signal HLL is input to a gate of transistor 125. One end of transistor 126 is connected to node SEN, the other end of transistor 126 is connected to node COM, and a control signal XXL is input to a gate of transistor 126.

[0059] One end of transistor 127 is grounded, and one gate of transistor 127 is connected to node SEN. One end of transistor 128 is connected to the other end of transistor 127, the other end of transistor 128 is connected to the bus LBUS, and a control signal STB is input to a gate of transistor 128. One end of capacitor 129 is connected to node SEN, and the other end of capacitor 129 receives the clock signal CLK.

[0060] For example, the control signals BLX, BLC, BLS, HLL, XXL, and STB are generated by the sequence controller 15. Furthermore, for example, a voltage VDD (second voltage), which is an internal power supply voltage of the non-volatile semiconductor memory device 1, is applied to the power supply line connected to one end of transistor 120. Furthermore, for example, a voltage VSS (first voltage) of the non-volatile semiconductor memory device 1 is applied to node SRC. For example, the voltage VSS is a voltage capable of defining another voltage with respect to the voltage VSS, and the voltage VSS can be a reference voltage, 0 V, or ground potential.

[0061] The latch circuits SDL, ADL, BDL, CDL, and XDL temporarily hold the read data. For example, the latch circuit XDL is connected to data register 21 and is used to input and output data between the read amplifier section SAU and the input / output circuit 10.

[0062] For example, the SDL latch circuit includes inverters 130 and 131 and n-channel MOS transistors 132 and 133. An input node of inverter 130 is connected to node LAT, and an output node of inverter 130 is connected to node INV. An input node of inverter 131 is connected to node INV, and an output node of inverter 131 is connected to node LAT. One end of transistor 132 is connected to node INV, the other end of transistor 132 is connected to bus LBUS, and a control signal STI is input to a gate of transistor 132. One end of transistor 133 is connected to node LAT, the other end of transistor 133 is connected to bus LBUS, and a control signal STL is input to a gate of transistor 133.For example, the data held in the LAT node corresponds to the data held in the SDL latch circuit, and the data held in the INV node corresponds to the inverted data of the data held in the LAT node. The circuit configurations of the ADL, BDL, CDL, and XDL latch circuits, for example, are the same as the circuit configuration of the SDL latch circuit and will therefore not be described.

[0063] The point in time at which each of the read amplifier sections SAU in the read amplifier module 20 determines the data to be read on the bit line BL is based on the point in time at which the control signal STB is applied. In this description and the like, "the sequence control 15 applies the control signal STB" corresponds to the sequence control 15 changing the control signal STB from a "L" level to a "H" level.

[0064] Furthermore, the configuration of the read amplifier module 20 in the non-volatile semiconductor storage device 1 is not limited to the configuration described in Fig. This is shown. For example, in the read amplifier section SAU, transistor 128, into which the control signal STB is input, can be a p-channel MOS transistor. Here, "the control unit 15 applies the control signal STB" corresponds to the control unit 15 changing the control signal STB from the "H" level to the "L" level.

[0065] Furthermore, the number of latching circuits included in the read amplifier section (SAU) can be set to any desired number. For example, in this case, the number of latching circuits is based on the number of data bits held by a memory cell transistor (MC). Additionally, a variety of bit lines (BL) can be connected to a read amplifier section (SAU) via selectors. [6. THRESHOLD VALUE DISTRIBUTION OF THE STORAGE CELL TRANSISTOR]

[0066] With reference to Fig. An exemplary threshold distribution of the memory cell transistor MC is described. Fig. This is a threshold distribution diagram showing an exemplary threshold distribution of the memory cell transistor MC. It should be noted that the threshold distribution of the memory cell transistor MC of the non-volatile semiconductor memory device 1 is not limited to the example shown in Fig. configurations shown are the same as those in Fig. until Fig. or similar to them, are described as necessary, and descriptions of configurations that are the same as those in Fig. until Fig. or similar to them, can be omitted.

[0067] For example, the non-volatile semiconductor storage device 1 uses a TLC (Triple-Level Cell) method in which three-bit data is stored in a memory cell transistor MC as a writing method of the memory cell transistor MC.

[0068] Fig. This is a diagram showing an example data mapping, a read voltage, and a test voltage of the MC memory cell transistor in the TLC method. A vertical axis represents the threshold value, which is... Fig. The line shown corresponds to the number of memory cell transistors MC (number of MC), and a horizontal axis corresponds to a threshold value Vth of the memory cell transistor MC.

[0069] As in Fig. As shown, the multitude of memory cell transistors MC in the TLC method forms eight threshold distributions. These eight threshold distributions (write level and program target level) are designated as "Er" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level, in order from the lowest threshold voltage. Different three-bit data, for example, are assigned to the "Er" level, the "A" level, the "B" level, the "C" level, the "D" level, the "E" level, the "F" level, and the "G" level, as shown below. "Er" level: "111" ("low-bit / medium-bit / high-bit") data “A” level: “011” data "B" level: "001" data "C" level: "000" data “D” level: “010” data “E” level: “110” data “F” level: “100” data "G" level: "101" data

[0070] That is, the TLC corresponds to a case where a value n is 3, under 2 n(n is a positive integer) or more threshold voltages that can be set for a memory cell transistor MC.

[0071] A test voltage, used in every write operation, is defined between adjacent threshold distributions. Specifically, test voltages AV, BV, CV, DV, EV, FV, and GV are defined, corresponding to the "A" level, the "B" level, the "C" level, the "D" level, the "E" level, the "F" level, and the "G" level, respectively.

[0072] For example, the test voltage AV is set between a maximum threshold voltage at the "Er" level and a minimum threshold voltage at the "A" level. When the test voltage AV is applied to the memory cell transistor MC, the memory cell transistor MC that includes the threshold voltage at the "Er" level is switched to an on state, and the memory cell transistor MC that includes the threshold voltage at the "A" level or higher is switched to an off state.

[0073] Furthermore, the other test voltages BV, CV, DV, EV, FV, and GV are set in the same way as the test voltage AV. The test voltage BV is set between the "A" level and the "B" level, the test voltage CV is set between the "B" level and the "C" level, the test voltage DV is set between the "C" level and the "D" level, the test voltage EV is set between the "D" level and the "E" level, the test voltage FV is set between the "E" level and the "F" level, and the test voltage GV is set between the "F" level and the "G" level.

[0074] For example, the test voltage AV can be set to 0.8 V, the test voltage BV can be set to 1.6 V, the test voltage CV can be set to 2.4 V, the test voltage DV can be set to 3.1 V, the test voltage EV can be set to 4.6 V, and the test voltage GV can be set to 5.6 V. Furthermore, the test voltages AV, BV, CV, DV, EV, FV, and GV are not limited to the examples shown here. For example, the test voltages AV, BV, CV, DV, EV, FV, and GV can be set in steps, as applicable, within a range of 0 V to 7.0 V.

[0075] Furthermore, a read voltage used in each read operation can be set between adjacent threshold distributions. For example, a read voltage AR is set between the maximum threshold voltage at the "Er" level and the minimum threshold voltage at the "A" level to determine whether the threshold voltage of the memory cell transistor MC is contained within the "Er" level, or within the "A" level or higher.

[0076] The other read voltages BR, CR, DR, ER, FR, and GR can be set in the same way as the read voltage AR. For example, the read voltage BR is set between the "A" level and the "B" level, the read voltage CR is set between the "B" level and the "C" level, the read voltage DR is set between the "C" level and the "D" level, the read voltage ER is set between the "D" level and the "E" level, the read voltage FR is set between the "E" level and the "F" level, and the read voltage GR is set between the "F" level and the "G" level.

[0077] Furthermore, a read read voltage VREAD is set to a voltage higher than the maximum threshold voltage of the highest threshold distribution (for example, the "G" level). The memory cell transistor MC, to which the read read voltage VREAD is applied, is switched to an on state regardless of the data to be stored.

[0078] Furthermore, the test voltages AV, BV, CV, DV, EV, FV, and GV are set to voltages higher than the read voltages AR, BR, CR, DR, ER, FR, and GR, respectively. This means that the test voltages AV, BV, CV, DV, EV, FV, and GV are each set closer to the lower end of the threshold distributions of the "A" level, the "B" level, the "C" level, the "D" level, the "E" level, the "F" level, and the "G" level, respectively.

[0079] For example, when the data mapping described above is applied, low-bit single-page data (lower page data) is determined in the read operation based on the read data using the AR and ER read voltages. Medium-bit single-page data (middle page data) is determined by read results using the BR, DR, and FR read voltages. High-bit single-page data (higher page data) is determined by the read data using the CR and GR read voltages. As described above, because the lower-page data, middle-page data, and higher-page data are determined by two, three, and two read operations, respectively, this data mapping is referred to as the "2-3-2 code."

[0080] Furthermore, the number of bits of data to be stored in a memory cell transistor MC, and the mapping of data to the threshold distribution of the memory cell transistor MC, which are determined with reference to Fig. The examples described are not limited to those in Fig. This will be demonstrated. For example, 2 bits, 4 bits, or more of data can be stored in a memory cell transistor (MC). Furthermore, the read voltage and the read read throughput voltage can be set to the same voltage value in each method, or they can be set to different voltage values. [7. OVERVIEW OF WRITING AND READING OPERATIONS]

[0081] A method for operating the memory cell arrangement located in Fig. is shown with reference to Fig. be described. Fig. Figure 1 is a diagram showing an example of a program loop in the non-volatile semiconductor memory device 1. Furthermore, the program loop of the non-volatile semiconductor memory device 1 is not limited to the example shown in Figure 2. Fig. configurations shown are the same as those in Fig. until Fig. or similar to them, are described as necessary, and descriptions of configurations that are the same as those in Fig. until Fig. or similar to them, can be omitted.

[0082] For example, as described in "3. Configurations of Memory Cell Arrangement," if the number of layers of the multitude of semiconductor layers is n, the areas separated by the memory trench MT enclose n memory groups MG stacked in the Z direction. The string parts SU represent a block BLK, which operates simultaneously. The write operation, the read operation, and the erase operation are performed in block units BLK.

[0083] The non-volatile semiconductor storage device 1 repeatedly executes a program loop during the write operation. The program loop includes a program operation and a check operation. The program operation is an operation to inject electrons into a charge storage layer in the selected memory cell transistor MC to increase the threshold voltage of the selected memory cell transistor MC. Alternatively, the program operation is an operation to maintain the threshold voltage of the selected memory cell transistor MC by preventing the injection of electrons into the charge storage layer. The check operation is an operation to verify whether the threshold voltage of the selected memory cell transistor MC has reached a target level by performing a read operation using the check voltage following the program operation.The selected memory cell transistor MC, whose threshold voltage has reached the target level, is then write-protected.

[0084] The non-volatile semiconductor storage device 1 repeatedly executes the program loop, which includes the program operation and the check operation described above, so that the threshold voltage of the selected memory cell transistor MC rises to the target level.

[0085] Electrons accumulated in the charge storage layer can be in an unstable state. Therefore, the electrons accumulated in the charge storage layer of the memory cell transistor MC can escape from the charge storage layer as time passes from the moment the program operation described above is completed. As the electrons escape from the charge storage layer, the threshold voltage of the memory cell transistor MC decreases. Therefore, in the read operation, which is performed after the write operation is complete, the non-volatile semiconductor memory device 1 performs the read operation using a read voltage lower than the test voltage to compensate for such a decrease in the threshold voltage of the memory cell transistor that can occur over time. Furthermore, the read operation can include the test operation.Furthermore, in this description and the like, every operation of the non-volatile semiconductor storage device 1 is included in every operating procedure. Specifically, the write operation of the non-volatile semiconductor storage device 1 is included in a write operating procedure, the read operation of the non-volatile semiconductor storage device 1 is included in a read operating procedure, the erase operation of the non-volatile semiconductor storage device 1 is included in an erase operating procedure, and the test operation of the non-volatile semiconductor storage device 1 is included in a test operating procedure.

[0086] For example, there is an example program loop in Fig. a program target level (“Er” level to “G” level) in a vertical direction and indicates the number of times the program loop is executed in the non-volatile semiconductor memory device 1 (the number of loops) in a lateral direction. Additionally, “O”, which is in Fig. The program target level, up to which a program operation should be performed in each loop, is shown, and “-”, which is in Fig. The value shown indicates a program target level below which a program operation should not be performed in each loop.

[0087] For example, as in Fig. The number of loops in the non-volatile semiconductor memory device 1 is seven. Furthermore, with reference to Fig. The memory cell transistor MC, which is set to the "A" level, is subject to the program operation in the first loop and is not subject to the program operation in the second and subsequent loops. Similarly, the memory cell transistor MC, which is set to the "B" level, is subject to a program operation in the first and second loops and is not subject to a program operation in the third and subsequent loops. The memory cell transistors MC, which are set to the "C" level through the "G" level, are subject to program operations according to the number of loops, similar to the memory cell transistor MC, which is set to the "A" level, and the memory cell transistor MC, which is set to the "B" level. [7-1. EXAMPLE OF A WRITING SURGERY]

[0088] With reference to Fig. , Fig. until Fig. An example of a write operation to a non-volatile semiconductor memory device will be described in a comparative example. With reference to Fig. , Fig. , Fig. and Fig. An example of a write operation in the memory cell arrangement 18 of the non-volatile semiconductor memory device 1 will be described.

[0089] Fig. is a flowchart showing an example of the write operation in the non-volatile semiconductor memory device according to the comparison example, and is a flowchart showing an example of a time-dependent change in voltages applied to different circuit components. Fig. Figure 1 is a perspective view showing an exemplary channel layer in the non-volatile semiconductor memory device 1, and Figure 2 is a schematic view focusing on the memory string MSb among the memory strings of the semiconductor layers 31, which are in Fig. be shown. Fig. and Fig. These are schematic illustrations showing an example of a channel layer state in the non-volatile semiconductor storage device according to the comparison example. Fig. Figure 1 shows the flowchart of the write operation in the memory cell arrangement 18 of the non-volatile semiconductor memory device 1, and shows a flowchart that illustrates an example of a time change in voltages applied to different circuit components. Fig. is a threshold distribution diagram showing an exemplary threshold distribution of the memory cell transistor MC.

[0090] Furthermore, the flowcharts that are in Fig. and Fig. Only flowcharts are shown, illustrating exemplary changes over time in voltages applied to various circuit components. They do not necessarily depict exact changes in voltages applied to the word line WL, the potential of the select gate lines SGD and SGS, and the like. Furthermore, a perspective view showing a channel layer and a view showing the state of the channel layer are shown. Fig. until Fig. shown, and a threshold distribution of the memory cell transistor MC of the non-volatile semiconductor memory device 1, which is in Fig. The schematic representations shown, a perspective view of the channel layer, a view showing the state of the channel layer, and a threshold distribution of the memory cell transistor MC of the non-volatile semiconductor memory device 1 are not limited to the examples shown in Fig. until Fig. will be shown. Furthermore, the same or similar configurations as those in Fig. until Fig. are described as necessary, and a description of the same or similar configurations as those in Fig. until Fig. can be omitted. Furthermore, when describing the write operation of the non-volatile semiconductor memory device in the comparison example, in the case where the non-volatile semiconductor memory device in the comparison example has the same configuration as that of non-volatile semiconductor memory device 1, the description will be performed using the same components as that of non-volatile semiconductor memory device 1.

[0091] The following explanation will focus on the memory string MSb among the memory strings of the respective semiconductor layer 31. The selection gate lines SGD connected to the memory cell transistors MC to operate in the respective memory strings MS are designated as selection gate lines SEL-SGD, and the selection gate lines SGD connected to the other memory cell transistors MC are designated as non-selection gate lines USEL-SGD. The word lines WL connected to the memory cell transistors MC to operate in each memory string MS are designated as selection word lines SEL-WL, and the other word lines WL connected to the memory cell transistors MC are designated as non-selection word lines USEL-WL.Among the memory strings of semiconductor layer 31, the bit lines BL connected to the memory strings containing the memory cell transistors MC to be operated are called Program BL. Bit lines BL connected to memory strings containing memory cell transistors MC other than those to be operated are called Inhibit BL. Furthermore, during the write operation, the voltage applied to the Select Gate Line SGS, which is connected to the memory cell transistor MC in each memory string MS, is the voltage VSS. The Select Gate Line SGS is not differentiated by the memory cell transistor MC in each memory string MS and is referred to as the "Select Gate Line SGS".

[0092] For example, the memory cell transistors MC that are to be operated are memory cell transistors MC into which data (threshold voltage) is written, and the other memory cell transistors MC besides those that are to be operated are memory cell transistors MC into which data (threshold voltage) is not written. For example, memory cell transistors MC other than those that are to be operated are referred to as "memory cell transistors MC that are not to be operated".

[0093] Furthermore, each of the multiple bit lines BL (for example, BLk-1, BLk, BLk+1) is connected to a read amplifier section SAU, corresponding to each of the multiple bit lines BL. Furthermore, for example, as in Fig. The transistor 122, enclosed in the read amplifier section SAU, is shown to be controlled based on the voltage supplied to the control signal BLC, such that it is in the on state and the off state, and the transistor 123, enclosed in the read amplifier section SAU, is shown to be controlled based on the voltage supplied to the control signal BLS, such that it is in the on state and the off state, and if the transistor 123 is in the on state, the read amplifier section SAU supplies data (threshold voltage) stored in the voltage VDD and the latch circuits SDL, ADL, BDL, CDL or XDL to the bit line BL.Furthermore, the operation of transistor 123 in the write operation in the memory cell arrangement 18 of the non-volatile semiconductor storage device 1 is the same as the operation of transistor 122, and in the description of the write operation in the memory cell arrangement 18 of the non-volatile semiconductor storage device 1, the operation of transistor 122 is described, and the description of the operation of transistor 123 is omitted.

[0094] Furthermore, for example, as in the memory string MSb of Fig. shown, semiconductor layer 31 of the k+1-th layer is designated as the channel layer (k+1) (channel(k+1)), semiconductor layer 31 of the k-th layer is designated as the channel layer (k) (channel(k)), and semiconductor layer 31 of the k-1-th layer is designated as the channel layer (k-1) (channel(k-1)). Here, with reference to Fig. and Fig. The bit line BL and the selection gate lines SGD and SGS connected to channel (k+1), the bit line BLk+1 and the selection gate lines SGD1 and SGS1, the bit line BL and the selection gate lines SGD and SGS connected to channel (k) are the bit line BLk and the selection gate lines SGD1 and SGS1, and the bit line BL and the selection gate lines SGD and SGS connected to channel (k-1) are the bit line BLk-1 and the selection gate lines SGD1 and SGS1. Furthermore, each of the selection gate lines SGD and SGS is supplied with the voltage that is in Fig. is shown.

[0095] With reference to Fig. and Fig. The memory cell transistors MCb1 (BLk-1), MCb1 (BLk), and MCb1 (BLk+1) are memory cell transistors MC on the same side (page), connected to the same select word line SEL-WLb1, and controlled by the same select word line SEL-WLb1 and select gate lines SGD1 and SGS1. As described above, Fig. a schematic diagram focusing on the memory string MSb and showing a plurality of memory cell transistors MC (MCb1 (BLk-1), MCb1 (BLk), MCb1 (BLk+1) connected to the same selection word line SEL-WLb1 in the memory string Msb, and a schematic diagram showing one memory cell transistor MC among the plurality of memory cell transistors MC connected to the same selection word line SEL-WLb1.

[0096] Furthermore, a program target level of the memory cell transistor MCb1 (BLk-1) is a "G" level (program target "G"). A program target level of the memory cell transistor MCb1 (BLk) is an "Er" level (program target "Er"), and a program target level of the memory cell transistor MCb1 (BLk+1) is a "D" level (program target "D").

[0097] Furthermore, the memory controller 2 sends a signal (write operation signal) instructing a data write operation to the non-volatile semiconductor storage device. For example, when the non-volatile semiconductor storage device receives the write operation signal, the sequence control 15 controls the read amplifier module 20, the line decoder 19, the voltage generator circuit 17, and the like, based on the write operation signal, via the logic control circuit 11, the input / output circuit 10, and the instruction register 14, to execute the write operation. For example, under the control of the voltage generator 17, the read amplifier module 20, and the line decoder 19, a voltage is applied to the word line WL, the select gate line SGD, the select gate line SGS, the source line SL, the bit line BL, the control signal BLS, the control signal BLC, and the like, using the sequence control 15. [7-1-1. EXAMPLE OF A WRITING OPERATION OF A NON-VOID SEMICONDUCTOR STORAGE DEVICE IN A COMPARISON EXAMPLE]

[0098] First, an example of a write operation of the non-volatile semiconductor storage device is presented in the comparative example with reference to Fig. until Fig. be described. [7-1-1-1. EXAMPLE OF A WRITING OPERATION UP TO TIME T0]

[0099] The write operation up to time T0 includes putting the non-volatile semiconductor storage device 1 into a ready state. For example, the ready state is a state in which the non-volatile semiconductor storage device 1 is waiting to be written to data.

[0100] As in Fig. As shown, the voltage VSS is supplied to the selection gate line SEL-SGD (SGD1), the non-selection gate lines USEL-SGD (SGD0, SGD2, SGD3, ...), the selection gate lines SGS (SGS0, SGS1, SGS2, SGS3, ...), the selection word line SEL-WLb1, the other non-selection word lines USEL-WL besides the selection word line SEL-WLb1, the bit line Program BL, the bit line Inhibit BL, the channels of the memory cell transistors that are to be operated, the channels of the memory cell transistors that are not to be operated, and the control signals BLC until time T0.

[0101] As in Fig. As shown, since the voltage VSS is supplied to each control line, each memory cell transistor MC is in the off state. [7-1-1-2. EXAMPLE OF WRITING OPERATIONS FROM TIME T0 TO TIME T1]

[0102] Next, write operations from time T0 to time T1 will be described. For example, the write operations from time T0 to time T1 include applying a voltage VSGPCH to the select gate line SEL-SGD and the non-select gate line USEL-SGD, and applying a voltage VCHPCH to the select word line SEL-WLb1 and the non-select word line USEL-WL.

[0103] As in Fig. As shown, between time T0 and T1, the voltage VSGPCH is applied to the select gate line SEL-SGD and the non-select gate line USEL-SGD, and the voltage VSGPCH is applied to the select word line SEL-WLb1 and the non-select word line USEL-WL. Furthermore, the voltage applied to the control signal BLC gradually increases to a voltage VDD+VTH. The select gate line SGS, the program bit line BL, the inhibit bit line BL, the channel of the memory cell transistor to be operated, and the channel of the memory cell transistor to be de-energized are supplied with the voltage VSS, the same voltage as up to time T0.

[0104] Based on the voltages applied to the control lines at time T1, the selection transistors ST1-k-1, ST1-k and ST1-k+1, the memory cell transistors MCb0 to MCb3 and the memory cell transistors MCa to MCa3 are switched to the ON state, and the selection transistors ST2-k-1, ST2-k and ST2-k+1 are kept in the OFF state.

[0105] Accordingly, at time T1, the voltage VSS supplied to the bit line BLk-1 is supplied to channel (k-1) each from the selection transistor ST1-k-1 and the memory cell transistors MCb0 to MCb3, which are connected to the selection transistor ST1-k-1; the voltage VSS supplied to the bit line BLk1 is supplied to channel (k) each from the selection transistor ST1-k and the memory cell transistors MCb0 to MCb3, which are connected to the selection transistor ST1-k; and the voltage VSS supplied to the bit line BLk+1 is supplied to channel (k+1) each from the selection transistor ST1-k+1 and the memory cell transistors MCb0 to MCb3, which are connected to the selection transistor ST1-k+1. [7-1-1-3. EXAMPLE OF WRITING OPERATIONS FROM TIME T1 TO TIME T2]

[0106] Next, write operations from time T1 to time T2 will be described. These write operations involve precharging the bit line inhibit BL and the channel of the memory cell transistor that is not to be operated. For example, the write operations from time T1 to time T2 include applying a voltage VDD to the bit line inhibit BL and applying the voltage VDD to the channel of the memory cell transistor that is not to be operated and is connected to the bit line inhibit BL.

[0107] As in Fig. As shown, from time T1 to T2 the control signal BLC is supplied with the voltage VDD+VTH. Similar to time T1, the voltage VSGPCH is supplied to the select gate line SEL-SGD and the non-select gate line USEL-SGD, the voltage VSGPCH is supplied to the select word line SEL-WLb1 and the non-select word line USEL-WL, and the voltage VSS is supplied to the select gate line SGS.

[0108] Based on the voltages applied to the control lines at time T2, the selection transistors ST1-k-1, ST1-k, and ST1-k+1, the memory cell transistors MCb0 to MCb3, and the memory cell transistors MCa0 to MCa3 are held in the ON state, and the selection transistors ST2-k-1, ST2-k, and ST2-k+1 are held in the OFF state. Furthermore, when the voltage VDD+VTH is applied to the control signal BLC, transistor 122 of the read amplifier section SAU, which is connected to the Program BL bit line, is switched to the ON state, the voltage VSS is applied to the Program BL bit line, and the voltage VSS is applied to the memory cell transistor to be operated.Furthermore, when the voltage VDD+VTH is applied to the control signal BLC, transistor 122 of the read amplifier section SAU, which is connected to the bit line Inhibit BL, is switched to the on state, the voltage VDD is applied to the bit line Inhibit BL, and the voltage VDD is applied to the channel of the memory cell transistor that is not to be operated. The multiple bit lines Inhibit BL are supplied with the voltage VDD simultaneously. [7-1-1-4. EXAMPLE OF WRITING OPERATIONS FROM TIME T2 TO TIME T3]

[0109] Next, write operations from time T2 to time T3 will be described. As in Fig. As shown, from time T2 to time T3, the voltage applied to the select gate line SEL-SGD and the non-select gate line USEL-SGD changes from voltage VSGPCH to voltage VSS, and the voltage applied to the select word line SEL-WLb1 and the non-select word line USEL-WL changes from voltage VSGPCH to voltage VSS. Furthermore, similar to time T2, voltage VSS is applied to the select gate line SGS, the bit line Program BL, the channel of the memory cell transistor to be activated, and the control signal BLC. Voltage VDD is applied to the bit line Inhibit BL and the memory cell transistor that is not to be activated. Therefore, since voltage VSS is applied to each control line, each memory cell transistor MC is in the off state. [7-1-1-5. EXAMPLE OF WRITING OPERATIONS FROM TIME T3 TO TIME T4]

[0110] Next, write operations from time T3 to time T4 will be described. These write operations involve driving the channel of the memory cell transistor that is not to be operated from a state where voltage VDD is applied to a state where voltage VCHA is applied.

[0111] As in Fig. As shown, from time T3 to T4, the select gate line SEL-SGD changes from a state where the voltage VSS is applied to a state where the voltage VSG is applied, the non-select gate line USEL-SGD is supplied with the voltage VSS, the select word line SEL-WLb1 and the non-select word line USEL-WL change from a state where the voltage VSS is applied to a state where the voltage VPASS is applied, and the control signal BLC changes from a state where the voltage VSS is applied to a state where the voltage VBLC is applied. Furthermore, similar to time T3, the voltage VSS is applied to the select gate line SGS, the bit line Program BL, and the channel of the memory cell transistor that is to be operated, and the voltage VDD is applied to the bit line Inhibit BL and the channel of the memory cell transistor that is not to be operated.

[0112] The voltage VSS applied to the Program BL bit line is sufficiently lower than the voltage VSG applied to the Select Gate line SEL-SGD. Therefore, the Select transistor ST1, connected to the Program BL bit line, is switched to the ON state, and the voltage VSS is applied to the channel of the memory cell transistor to be operated. The voltage VDD applied to the Inhibit BL bit line is sufficiently higher than the voltage VSG applied to the Select Gate line SEL-SGD. Therefore, since the voltage VSG applied to the gate of the Select transistor ST1, connected to the Inhibit BL bit line, is relatively low, the Select transistor ST1 is switched to the OFF state. Additionally, the Select Word line WLb1 and the Non-Select Word line WL are supplied with the voltage VPASS, and the memory cell transistors MC of the respective layers are in the ON state.

[0113] Therefore, the bit line inhibit BL and the non-selective channel of the memory cell transistor are electrically isolated. Consequently, capacitive coupling between the non-selective channel of the memory cell transistor and the non-selective word line USEL-WL drives the non-selective channel of the memory cell transistor from a state where voltage VDD is applied to a state where voltage VCHA is applied. [7-1-1-6. EXAMPLE OF WRITING OPERATIONS FROM TIME T4 TO TIME T5]

[0114] Next, write operations from time T4 to T5 will be described. These write operations involve writing threshold voltages, corresponding to the program target level, to the memory cell transistor to be operated. As described in Fig. As shown, from time T4 to time T5, the select gate line SEL-SGD (SGD1) is supplied with voltage VSG, the bit line Program BL is supplied with voltage VSS, and the select transistor ST1, which is connected to the bit line Program BL, is held in the ON state. Furthermore, the bit line Inhibit BL is supplied with voltage VDD, and the select transistor ST1, which is connected to the bit line Inhibit BL, changes to the OFF state. The select word line SEL-WLb1 changes from a state in which voltage VPASS is applied to a state in which voltage VPGM is applied, and the memory cell transistor MC, which is electrically connected to the select word line SEL-WLb1, changes to the ON state.Similar to time T4, the voltage supplied to the channel of the memory cell transistor that is to be operated maintains the voltage VSS, the voltage supplied to the channel of the memory cell transistor that is not to be operated maintains the voltage VCHA, the select gate line SGS is supplied with the voltage VSS, the select transistor ST2 is kept in the off state, and the control signal BLC maintains a state in which the voltage VBLC is supplied.

[0115] For example, the select word line SEL-WLb1 is supplied with the voltage VPGM, the memory cell transistor to be operated is switched to the on state, and the program line BL is supplied from a state where the voltage VSS is applied to the voltage corresponding to the program target level. For example, the voltage VPGM is a voltage sufficiently higher than the voltage corresponding to the program target level. Therefore, an electric field is applied to the memory cell transistor to be operated due to a potential difference between the channel voltage VSS and the select word line SEL-WLb1 voltage VPGM, and electrons are injected into the charge storage layer of the memory cell transistor. As a result, a program corresponding to the program target level is executed on the memory cell transistor to be operated, and the threshold voltage of the memory cell transistor rises.Furthermore, the voltage VPGM can be described as a "writing voltage".

[0116] The channel of the memory cell transistor that is not to be operated and is connected to the bit line Inhibit BL maintains a state in which the voltage VCHA is applied. Therefore, an electric field is applied to the memory cell transistor that is not to be operated due to a potential difference between the voltage VCHA of the channel and the voltage VPGM of the select word line SEL-WLb1. If the potential difference between the voltage VCHA and the voltage VPGM is sufficiently small, no electrons are injected (or only a small amount of electrons are injected) into the charge storage layer of the memory cell transistor that is not to be operated. As a result, the memory cell transistor that is not to be operated is not programmed, and the threshold voltage of the memory cell transistor does not increase (or increases only slightly). [7-1-1-7. SPECIFIC EXAMPLE OF A WRITING OPERATION OF A NON-VOID SEMICONDUCTOR STORAGE DEVICE IN A COMPARISON EXAMPLE]

[0117] First, with reference to Fig. and Fig. , a specific example in a first loop to fourth loop in the program loop, which is in Fig. is shown, is described.

[0118] When the voltage VPGM is applied to the selection word line SEL-WLb1, which is in Fig. As shown, the voltage VSS is supplied from the bit line BLk-1 via the selection transistor ST1-k-1 to the channel (k-1), and the voltage VSS is supplied from the bit line BLk+1 via the selection transistor ST1-k+1 to the channel (k+1). Consequently, the threshold voltages of the memory cell transistor MCb1 (BLk-1) of the k-1 layer and the memory cell transistor MCb1 (BLk+1) of the k+1 layer increase.

[0119] On the other hand, since the bit line BLk is supplied with the voltage VDD, and the selection transistor ST1-k, which is connected to the bit line BLk, is switched off, the channel (k) is in a floating state.

[0120] Consequently, for example, in a state where the voltage VPASS is applied to the select word line SEL-WLb1, channel (k) is driven from a state where the voltage VDD is applied to a state where the voltage VCH1 is applied. Therefore, even if the voltage applied to the select word line SEL-WLb1 increases from the voltage VPASS to the voltage VPGM, the potential difference between the voltage applied to the select word line SEL-WLb1 and the voltage applied to channel (k) does not increase. Therefore, the threshold voltage of the memory cell transistor MCb1 (BLk), which encloses part of channel (k), does not increase.

[0121] Next, with reference to Fig. and Fig. , a specific example of a fifth to seventh loop in the program loop, which is in Fig. As shown, it will be described. In the fifth to seventh program loops, although the memory cell transistor exhibiting the "D" level as the program target level is not subject to the operation, the memory cell transistor exhibiting the "G" level as the program target level is subject to the operation. Therefore, the select word line SEL-WLb1 is supplied with the voltage VPGM.

[0122] That is, as in the bit line Inhibit BL of Fig. and the channel of the memory cell transistor that is not to be operated, the bit line BLk+1 and the channel (k+1) connected to the bit line BLk+1 are supplied with the voltage VDD in the same way as the bit line BLk and the channel (k) connected to the bit line BLk. Consequently, since the select transistor ST1-k+1 is switched off, the channel (k+1) is in a floating state. Therefore, similar to the channel (k), the channel (k+1) is driven high. Consequently, when the voltage VPGM is applied to the select word line SEL-WLb1, the channel (k+1) is driven from a state in which the voltage VDD is applied (see the channel of the memory cell transistor that is not to be operated). Fig. ), driven up to a state in which a voltage VCH2 is applied (see channel (k+1) of Fig. ).

[0123] Here, channel (k) is driven from a state where voltage VDD is applied to a state where voltage VCH1 is applied by the program target of memory cell transistor MCb1 (BLk), which includes a portion of channel (k), being at the "Er" level and the voltage VPGM being applied to the select word line SEL-WLb1. Furthermore, since the threshold voltage of memory cell transistor MCb1 (BLk+1), which includes a portion of channel (k+1), is raised to the "D" level, higher than the "Er" level, as described above, the voltage applied to channel (k+1), a state where voltage VCH2 is applied, is driven from a state where voltage VDD is applied, due to the voltage VPGM being applied to the select word line SEL-WLb1.At this point, since channel (k) is in the state of equilibrium, channel (k) is driven, for example, further from the state in which the voltage VCH1 is applied to a state in which a voltage VCH3, higher than the voltage VCH1, is applied, due to an effect of the voltage VCH2, which is applied to channel (k+1).

[0124] Here, the greater the potential difference between the voltage applied to the select word line SEL-WLb1 and the voltage applied to channel (k), the more likely an unintended increase in the threshold voltage will occur in the memory cell transistor MCb1 (BLk). Although the state of channel (k) described above is one in which the voltage VCH3 is applied, a potential difference between the voltage VPGM applied to the select word line SEL-WLb1 and the voltage VCH3 is still large and is a potential difference at which an unintended increase in the threshold voltage in the memory cell transistor MCb1 (BLk) can occur.Therefore, for example, it is likely that a memory cell transistor in which a threshold voltage is written that has a low program target level will exhibit an unintended increase in the threshold voltage in the second half of a program loop, such as from the fifth loop to the seventh loop. For example, the fact that an unintended increase in the threshold voltage is likely to occur is expressed as "a program perturbation is likely to occur."

[0125] Therefore, the write operation of the non-volatile semiconductor storage device in the comparison example tends to cause an unintended increase in the threshold voltage (a program error tends to occur). [7-1-2. EXAMPLE OF A WRITING OPERATION IN STORAGE CELL ARRANGEMENT 18 OF NON-VOID SEMICONDUCTOR STORAGE DEVICE 1]

[0126] Next, an example of a write operation in the memory cell arrangement 18 of the non-volatile semiconductor memory device 1 is given with reference to Fig. , Fig. and Fig. be described. A flowchart that is in Fig. The flowchart shown corresponds to the flowchart of the fifth to seventh loops in the program loop, which is shown in Fig. is shown.

[0127] In an example of the write operation in the memory cell arrangement 18 of the non-volatile semiconductor memory device 1, a selected memory cell transistor MC, which is to be subjected to the write operation, is a memory cell transistor MC connected to the bit line BLk-1, the source line SL1, and the select word line SEL-WLb1. The memory cell transistor MC is the memory cell transistor MCb1 (BLk-1), which is in Fig. or Fig. As shown, the memory cell transistor MCb1 (BLk-1) encloses part of the k-1 layer semiconductor layer 31 (of channel (k-1)). The bit line BLk-1 is the bit line Program BL.

[0128] Furthermore, in an example of the write operation in the memory cell arrangement 18 of the non-volatile semiconductor memory device 1, the unselected memory cell transistors MC, which are not subjected to the write operation, are the bit line BLk, the source line SL1, and the memory cell transistors MCb1 (BLk) connected to the select word line SEL-WLb1, and the memory cell transistors MCb1 (BLk+1) connected to the bit line BLk+1, the source line SL1, and the select word line SEL-WLb1. As in Fig. or Fig. As shown, the memory cell transistor MCb1 (BLk) encloses a portion of the k-layer semiconductor layer 31 (of channel (k)), and the memory cell transistor Mcb1 (BLk+1) encloses a portion of the k+1-layer semiconductor layer 31 (of channel (k+1)). Furthermore, the bit line BLk is a bit line inhibit BL (BLk) and the bit line BLk+1 is a bit line inhibit BL (BLk+1).

[0129] In the write operation in the memory cell arrangement 18 of the non-volatile semiconductor memory device 1, a time change of the voltage at any time point of the select gate line SEL-SGD (SGD1), the non-select gate lines USEL-SGD (SGD0, SGD2, SGD3, ...), the select gate lines SGS (SGS0, SGS1, SGS2, SGS3, ...), the select word line SEL-WLb1, the non-select word lines USEL-WL other than the select word line SEL-WLb1 and the control signal BLC is the same as a time change of the voltage at any time point of the non-select word line SEL-SGD (SGD1), the non-select gate lines USEL-SGD (SGD0, SGD2, SGD3, ...), the select word line SEL-WLb1 and the non-select word lines USEL-WL other than the select word line SEL-WLb1 and of the BLC control signal.Therefore, in the description of the write operation in the memory cell arrangement 18 of the non-volatile semiconductor storage device 1, the description of the time change of the voltages at the respective times of the selection gate line SEL-SGD, the non-selection gate line USEL-SGD, the selection gate line SGS and the other non-selection word lines USEL-WL as the selection word line SEL-WLb1 and the selection word line SEL-WLb1 is omitted. [7-1-2-1. EXAMPLE OF A WRITING OPERATION UP TO TIME T0]

[0130] First, a write operation will be described up to time T0.

[0131] As in Fig. As shown, up to time T0, a bit line ProgramBLk-1, a bit line Inhibit BLk, and a bit line BLk+1 are supplied with the voltage VSS. The bit line ProgramBLk-1 can be referred to as a "second bit line," the bit line Inhibit BLk can be referred to as a "first bit line," and the bit line Inhibit BLk+1 can be referred to as a "third bit line."

[0132] Furthermore, as described above, the channel layer of the memory cell transistor MC that is the target of the write operation is channel (k-1), and the channel layer of the memory cell transistor MC that is not the target of the write operation is channel (k) or channel (k+1). Channel (k-1), channel (k), and channel (k+1) are supplied with the voltage VSS. In a data latch DL, which is in Fig. The data shown (a threshold voltage) is logically calculated in the read amplifier section SAU using the latch circuit SDL, ADL, BDL, CDL, or XDL. For example, the logically managed data can be stored in a latch circuit SDL, ADL, BDL, CDL, or XDL. For example, no data is stored in the data latch DL at time T0.

[0133] As in Fig. As shown, since the voltage VSS is supplied to each control line, each memory cell transistor MC is in the off state. [7-1-2-2. EXAMPLE OF WRITING OPERATIONS FROM TIME T0 TO TIME T1]

[0134] Next, write operations from time T0 to time T1 will be described.

[0135] As in Fig. As shown, the voltage supplied to the control signal BLC gradually increases from time T0 to time T1, reaching the voltage VDD+VTH (eighth voltage). The selection gate line SGS (SGS1), the bit line ProgramBLk-1, the bit line Inhibit BLk, the bit line Inhibit BLk+1, channel (k-1), channel (k), and channel (k+1) are supplied with the voltage VSS, the same as up to time T0. As at time T0, no data is stored in the data latch DL.

[0136] Here, the voltage VSGPCH can be greater than the voltage VCHPCH and can be the same magnitude as the voltage VCHPCH. Furthermore, for example, the voltage VCHPCH is greater than the voltage VSS. Additionally, the voltage VDD is greater than the voltage VSS and can be the same or substantially the same as the voltage VCHPCH.

[0137] Based on the voltages applied to each control line at time T1, the selection transistors ST1-k-1, ST1-k and ST1-k+1, the memory cell transistors MCb0 to MCb3 and the memory cell transistors MCa0 to MCa3 are switched to the ON state, and the selection transistors ST2-k-1, ST2-k and ST2-k+1 are kept in the OFF state.

[0138] Accordingly, at time T1, the voltage VSS supplied to the bit line BLk-1 is supplied to the selection transistor ST1-k-1 and to channel (k-1) (second channel) of each of the memory cell transistors MCb0 to MCb3 (second memory cell) connected to the selection transistor ST1-k-1; the voltage VSS supplied to the bit line BLk is supplied to the selection transistor ST1-k and to channel (k) (first channel) of each of the memory cell transistors MCb0 to MCb3 (first memory cell) connected to the selection transistor ST1-k; and the voltage VSS supplied to the bit line BLk+1 is supplied to the selection transistor ST1-k+1 and to channel (k+1) (third channel) of each of the memory cell transistors MCb0 to MCb3 (third memory cell) connected to the selection transistor ST1-k+1. [7-1-2-3. EXAMPLE OF WRITING OPERATIONS FROM TIME T1 TO TIME T2]

[0139] Next, the write operations from time T1 to time T2 will be described. These write operations are pre-charging the bit line Inhibit BL (BLk), the bit line Inhibit BL (BLk+1), channel (k), and channel (k+1). For example, the write operations from time T1 to time T2 include applying voltage VDD to the bit line Inhibit BL (BLk), then applying voltage VDD to the bit line Inhibit BL (BLk+1), and finally increasing the voltage applied to the bit line Inhibit BL (BLk) from voltage VDD to a voltage VDD+dv (third voltage).Furthermore, the write operations from time T1 to time T2 include supplying the voltage VDD to the bit line Inhibit BL (BLk) and supplying the voltage VDD to the channel (k) of the memory cell transistor MCb1 (BLk) which is connected to the bit line Inhibit BL (BLk), then supplying the voltage VDD to the bit line Inhibit BL (BLk+1) and raising the voltage supplied to the channel (k) from the voltage VDD to the voltage VDD+dv.

[0140] As in Fig. As shown, from time T1 to T2 the control signal BLC is supplied with the voltage VDD+VTH. Similar to time T1, the selection gate line SGS (SGS1), the bit line ProgramBLk-1 and the channel (k-1) are supplied with the voltage VSS.

[0141] Based on the voltages supplied to the respective control lines at time T2, the selection transistors ST1-k-1, ST1-k and ST1-k+1, the memory cell transistors MCb0 to MCb3 and the memory cell transistors MCa0 to MCa3 are kept in the ON state, and the selection transistors ST2-k-1, ST2-k and ST2-k+1 are kept in the OFF state. Furthermore, when the voltage VDD+VTH is supplied to the control signal BLC, transistor 122 of the read amplifier section SAU, which is connected to the bit line Inhibit BLk-1, is switched to the on state, the voltage VSS is supplied to the bit line ProgramBLk-1, the voltage VSS is supplied to the selection transistor ST1-k-1 and to the channel (k-1) (first channel) of each of the memory cell transistors MCb0 to MCb3 (first memory cell) that are connected to the selection transistor ST1-k-1.Furthermore, when the voltage VDD+VTH is supplied to the control signal BLC, transistor 122 of the read amplifier section Inhibit BL (Blk), which is connected to the bit line SAU, is switched to the on state, the voltage VDD is supplied to the bit line Inhibit BL (BLk), and the voltage VDD is supplied to the selection transistor ST1-k and the channel (k) of each of the memory cell transistors MCb0 to MCb3, which are connected to the selection transistor ST1-k. Furthermore, when the voltage VDD+VTH is supplied to the control signal BLC, transistor 122 of the read amplifier section SAU, which is connected to the bit line Inhibit BL (BLk+1), is switched to the on state, the voltage VDD is supplied to the bit line Inhibit (BLk+1), and the voltage VDD is supplied to the selection transistor ST1-k+1 and to the channel (k+1) (third channel) of each of the memory cell transistors MCb0 to MCb3 (third memory cell) that are connected to the selection transistor ST1-k+1.

[0142] When voltage VDD is applied to the bit line inhibit BL (BLk) and channel (k), the memory cell transistor MCb1 (BLk) is in a floating state. In this state, when voltage VDD is applied to the bit line BL (BLk+1) and channel (k+1), capacitive coupling between the bit line inhibit BL (BLk+1) (channel (k+1)) and the bit line inhibit BL (BLk) (channel (k)) causes the voltage applied to the bit line inhibit BL (BLk) and the voltage applied to channel (k) to increase from voltage VDD to voltage VDD+dv. Furthermore, at the time when the voltage VDD is supplied to channel (k), the data latch DL indicates a threshold voltage at which the program target level logically calculated using the latch circuit SDL, ADL, BDL, CDL or XDL in the read amplifier section SAU is at the "Er" level.The threshold voltage with the program target level of "ER" can be stored in a latch circuit SDL, ADL, BDL, CDL, or XDL. Furthermore, when the voltage VDD is applied to channel (k+1), the data latch DL displays a threshold voltage at a level between the "A" level and the "F" level, which, using the latch circuit SDL, ADL, BDL, CDL, or XDL, represents logically calculated program target levels in the read amplifier section SAU. The threshold voltage with program target levels from the "A" level to the "F" level can be stored in a latch circuit SDL, ADL, BDL, CDL, or XDL.

[0143] Furthermore, after the voltage VDD is supplied to channel (k), and the voltage VDD is supplied to channel (k+1), the voltage VSS is supplied to the control signal BLC. [7-1-2-4. EXAMPLE OF WRITING OPERATIONS FROM TIME T2 TO TIME T3]

[0144] Next, write operations from time T2 to time T3 will be described. As in Fig. As shown, from time T2 to time T3, similar to time T2, the selection gate line SGS (SGS1), the bit line ProgramBLk-1, channel (k-1), and the control signal BLC are supplied with the voltage VSS, the bit line Inhibit BLk and channel (k) are supplied with the voltage VDD+dv, and the bit line Inhibit BLk+1 and channel (k+1) are supplied with the voltage VDD. Furthermore, similar to time T2, in the data latch DL, the threshold voltages from the "A" level to the "F" level are displayed as the program target levels logically calculated using the latch circuit SDL, ADL, BDL, CDL, or XDL in the read amplifier section SAU. For example, the threshold voltages from the "A" level to the "F" level are stored in a latch circuit SDL, ADL, BDL, CDL, or XDL. Therefore, since the voltage VSS is supplied to each control line, each memory cell transistor MC is in the off state. [7-1-2-5. EXAMPLE OF WRITING OPERATIONS FROM TIME T3 TO TIME T4]

[0145] Next, write operations from time T3 to time T4 will be described. The write operations from time T3 to time T4 include driving the channel (k+1) of the unselected memory cell transistor MC (Mcb1 (BLk+1)) from a state where voltage VDD is applied to a state where voltage VCHB (fifth voltage) is applied, and driving the channel (k) of the unselected memory cell transistor MC (MCb1 (BLk)) from a state where voltage VDD+dV is applied to a state where voltage VCHC (sixth voltage) is applied.

[0146] As in Fig. As shown, from time T3 to time T4, the selection gate line SEL-SGD (SGD1) changes from a state in which the voltage VSS is applied to a state in which the voltage VSG is applied, the non-selection gate line USEL-SGD (SHD1) is supplied with the voltage VSS, the selection word line SEL-WLb1 and the non-selection word line USEL-WL are changed from a state in which the voltage VSS is applied to a state in which the voltage VPASS (fourth voltage) is applied, and the control signal BCL is changed from a state in which the voltage VSS is applied to a state in which the voltage VBLC is applied. Furthermore, similar to time T3, the voltage VSS is supplied to the selection gate line SGS (SGS1), the bit line ProgramBLk-1, the channel (k-1) and the control signal BLC, the voltage VDD+dv is supplied to the bit line Inhibit BLk, and the voltage VDD is supplied to the bit line Inhibit BLk+1.Furthermore, similar to time T2, the bit line ProgramBLk-1 is supplied with the voltage VSS. In the data latch DL, the threshold voltages from the "A" level to the "F" level are displayed as the program target levels logically calculated using the latch circuit SDL, ADL, BDL, CDL, or XDL in the read amplifier section SAU. For example, the threshold voltages that represent program target levels from the "A" level to the "F" level are stored in a latch circuit SDL, ADL, BDL, CDL, or XDL.

[0147] The voltage VSS applied to the bit line ProgramBLk-1 is sufficiently lower than the voltage VSG applied to the select gate line SEL-SGD. Therefore, the select transistor ST1-k-1, connected to the bit line ProgramBLk-1, is switched to the on state, and the voltage VSS is applied to channel (k-1). The non-select gate line SGD (SGD1) is supplied with the voltage VSS, and the bit line Inhibit BLk+1 is supplied with the voltage VDD. The non-select gate line SGD (SGD1) is supplied with the voltage VSS, and the bit line Inhibit BLk is supplied with the voltage VDD+dV. The voltages VDD applied to the bit line Inhibit BLk+1 and VDD+dV applied to the bit line Inhibit BLk are sufficiently higher than the voltage VSG applied to the select gate line SEL-SGD.Therefore, since the voltage VDD applied to the gate of the selector transistor ST1-k+1, which is connected to the bit line inhibit BLk+1, and the voltage VSG applied to the gate of the selector transistor ST1-k, which is connected to the bit line inhibit BLk, are relatively low, the selector transistor ST1-k+1 and the selector transistor ST1-k are switched to the off state. Furthermore, the select word line WLb1 and the non-select word line WL are supplied with the voltage VPASS, and the memory cell transistors MC of the respective layers are in the on state.

[0148] Therefore, the bit line Inhibit BLk+1 and channel (k+1) are electrically isolated, and the bit line Inhibit BLk and channel (k) are electrically isolated. Consequently, capacitive coupling between channel (k+1) and the non-selection word line USEL-WL drives channel (k+1) from a state where voltage VDD is applied to a state where voltage VCHB is applied, and capacitive coupling between channel (k) and channel (k+1) and the non-selection word line USEL-WL drives channel (k) from a state where voltage VDD+dV is applied to a state where voltage VCHC is applied.

[0149] For example, the voltage VSG is lower than the voltage VSGPCH, the voltage VPASS (fourth voltage) is higher than the voltage VCHPCH, the voltage VCHC is higher than the voltage VCHB, and the voltage VCHB and the voltage VCHC are higher than the voltage VDD and the voltage VDD+dV.

[0150] As with reference to Fig. , Fig. and Fig. As described in “7-1-1. Example of a write operation of a non-volatile semiconductor memory device in a comparative example”, from time T1 to T4 the non-volatile semiconductor memory device in the comparative example includes the voltage VDD of the plurality of bit lines Inhibit BL (BLk, BLk+1 in Fig. ) is supplied at the same time, and implies that the voltage supplied to channel (k) changes from voltage VCH1 to voltage VCH3 when the voltage supplied to channel (k+1) becomes voltage VCH2. Consequently, a potential difference between voltage VPGM and voltage VCH3 supplied to the select word line SEL-WLb1 is still large, and the non-volatile semiconductor memory device in the comparison example tends to exhibit an unintended increase in the threshold voltage (a program fault tends to occur). Therefore, for example, in the case of using the non-volatile semiconductor memory device in the comparison example, one threshold distribution width becomes wider, and one adjacent level distribution width becomes narrower, so that the threshold voltage distribution, which in Fig. as shown, it worsens.

[0151] On the other hand, in the non-volatile semiconductor memory device 1, the voltage VDD is applied to the bit line inhibit BLk, the memory cell transistor MC (memory cell transistor MCb1 (BLk)), which encloses a portion of the channel (k) connected to the bit line inhibit BLk, is in a floating state, and the voltage VDD is applied to the bit line inhibit BLk+1. As a result, the non-volatile semiconductor memory device 1 can increase the voltage applied to channel (k) to the voltage VDD+dV by utilizing the capacitive coupling between channel (k) and channel (k+1).

[0152] Therefore, in the subsequent operation, the non-volatile semiconductor memory device 1 can drive the channel (k) of the memory cell transistor MCb1 (BLk) up to the voltage VCHC, which is greater than the voltage VCH1 up to the voltage VCH3 in the comparative example. As a result, the non-volatile semiconductor memory device 1 is able to suppress interference between channel (k) and channel (k+1), suppress rewriting of the threshold voltage stored in the memory cell transistor MCb1 (BLk), and suppress degradation of the threshold voltage distribution. [7-1-2-6. EXAMPLE OF WRITING OPERATIONS FROM TIME T4 TO TIME T5]

[0153] Next, write operations from time T4 to time T5 will be described. These write operations involve writing a threshold voltage, representing the program target level of the "G" level, to the selected memory cell transistor MCb1 (BLk-1). As described in Fig. As shown, the bit line ProgramBLk-1 is supplied with the voltage VSS, and the selector transistor ST1-k-1 remains in the on state. The non-selection gate line USEL-SGD (SGD1) is supplied with the voltage VSS, the bit line Inhibit BLk is supplied with the voltage VDD+dV, and the selector transistor ST1-k is switched to the off state. The non-selection gate line USEL-SGD (SGD1) is supplied with the voltage VSS, the bit line Inhibit BLk+1 is supplied with the voltage VDD, and the selector transistor ST1-k+1 is switched to the off state. The selection word line SEL-WLb1 is changed from a state in which the voltage VPASS is applied to a state in which the voltage VPGM (the seventh voltage) is applied, and the memory cell transistors MCb1 (BLk-1), MCb1 (BLk) and MCb1 (BLk+1) are changed to the ON state.Similar to time T4, the voltage supplied to channel (k-1) maintains the voltage VSS, the voltage supplied to channel (k) maintains the voltage VCHC, the voltage supplied to channel (k+1) maintains the voltage VCHB, the select gate line SGS (SGS1) maintains the voltage VSS, the select transistors ST2-k-1, ST2-k and ST2-k+1 maintain the off state, and the control signal BLC maintains a state in which the voltage VBLC is supplied. Furthermore, similar to time T4, at which the data latch DL displays the threshold voltages from the "A" level to the "F" level as the program target levels logically calculated using the latch circuit SDL, ADL, BDL, CDL or XDL in the read amplifier section SAU, and, for example, the threshold voltages from the "A" level to the "F" level are stored in a latch circuit SDL, ADL, BDL, CDL or XDL.

[0154] For example, the voltage VPGM is greater than the voltage VPASS, the voltage VCHB, and the voltage VCHC. Furthermore, the voltages VCHB and VCHC are less than the voltage VPAAS and greater than the voltages VSGPCH and VCHPCH.

[0155] In a state where the voltage VPGM is applied to the select word line SEL-WLb1 and the memory cell transistor MCb1 is switched to the on state, the voltage applied to the bit line ProgramBLk-1 becomes a threshold voltage, corresponding to the program target level of the "G" level, and is lower than the voltage VSS. The voltage VPGM is a voltage at which a program target level is sufficiently higher than the threshold voltage at the "G" level. Furthermore, the voltage VPGM is sometimes referred to as a write voltage.

[0156] Channel (k) of memory cell transistor MCb1 (k), which is connected to the bit line Inhibit BLk, maintains a state in which the voltage VCHC is applied. Therefore, the write operation of the non-volatile semiconductor memory device 1 can prevent the threshold voltage stored in memory cell transistor MCb1 (k) (in this case, the threshold voltage that has the program target level of the "Er" level) from being rewritten.

[0157] Furthermore, the potential difference between the voltage VCHC (drive-up voltage) applied to channel (k+1) of memory cell transistor MCb1 (BLk+1), which is connected to the bit line inhibit BLk+1, and the voltage VPGM (write voltage) applied to the select word line WLb1, which is connected to memory cell transistor MCb1 (BLk+1), is smaller than the potential difference between the voltage VCH3 and the voltage VPGM in the non-volatile semiconductor memory device of the comparison example. Therefore, during the write operation of the non-volatile semiconductor memory device 1, the potential difference between the drive-up voltage and the write voltage can be reduced. In the case where the drive-up voltage is small, the threshold voltage stored in the memory cell transistor MC can be rewritten because the potential difference between the drive-up voltage and the write voltage becomes large.In this case, for example, as in . Fig. This is shown because the threshold voltage distribution width of the "Er" level is broadened like a broken line, the distance between the threshold voltage distribution width of the "Er" level and the threshold voltage distribution width of the adjacent "A" level is narrowed, or the threshold voltage distribution width of the "Er" level can overlap the threshold voltage distribution width of the adjacent "A" level. On the other hand, during the write operation of the non-volatile semiconductor memory device 1, the drive voltage increases, and the potential difference between the drive voltage and the write voltage can decrease. Therefore, as shown in Fig. As shown, a distribution width of the threshold voltage of the "Er" level, which is broadened like a broken line, can be narrowed, as shown by a thick solid line, and a distribution width of adjacent threshold voltages can be moved away (a threshold window is enlarged). Furthermore, as in the case where the program target level is the "Er" level, even if the program target level is the "A" level, a distribution width of the threshold voltage of the "A" level can be narrowed such that the distribution width of the threshold voltage of the "A" level, which is broadened like a broken line, is shown by a thick solid line, and a distribution width of adjacent threshold voltages can be moved away (a threshold window is enlarged).Furthermore, as in the case where the program target level, broadened like a broken line, is the "Er" level, even if the program target level is the "B" level, the distribution width of the threshold voltage of the program target level, which is the "B" level, can be narrowed, as indicated by a thick solid line, and the distribution width of adjacent threshold voltages can be shifted (a threshold window is widened). That is, the write operation of the non-volatile semiconductor memory device 1 can be applied to the entire page and can suppress a deterioration of the threshold voltage distribution when viewed across the entire page.

[0158] Furthermore, it is assumed that the non-volatile semiconductor storage device 1 exhibits a certain degree of error tolerance. For example, to correct the error, the memory controller 2 of the storage system 3 incorporates ECC (error checking and correction). In general, the higher the error rate, the more ECC resources are required. The non-volatile semiconductor storage device 1 can reduce the error rate in the page and improve the error-free operation. Furthermore, the non-volatile storage device 1 can reduce the error rate in the page and can reduce the ECC resources accordingly. As a result, the storage system 3, which uses the non-volatile semiconductor storage device 1, is able to reduce costs.

[0159] Furthermore, in the write operation of the non-volatile semiconductor storage device 1, the operations up to time T2 can be referred to as a "first operation", and the operations from time T3 to time T5 can be referred to as a "second operation". [SECOND VERSION]

[0160] An example of a write operation in the memory cell arrangement 18 of the non-volatile semiconductor memory device 1 according to a second embodiment is given with reference to Fig. be described. Fig. is a flowchart showing the write operation in the memory cell arrangement 18 of the non-volatile semiconductor memory device 1 according to the second embodiment.

[0161] A flowchart according to the second embodiment includes the following configurations 1 to 3. Configurations 1 to 3 differ from the example of the write operation in the memory cell arrangement 18 of the non-volatile semiconductor memory device 1 according to the first embodiment.

[0162] Configuration 1: From time T0 to time T1, the control signal BLC is changed from a state in which the voltage VSS is applied to a state in which a voltage VBLDR (ninth voltage) is applied.

[0163] Configuration 2: From time T1 to time T2, the control signal BLC is changed from a state in which the voltage VBLDR is applied to a state in which a voltage VDD+VTH is applied.

[0164] Configuration 3: The voltage VBLDR is a voltage greater than the voltage VDD+VTH.

[0165] Configurations other than configurations 1 to 3 are the same as the example of the write operation in memory cell arrangement 18 of the non-volatile semiconductor memory device 1 according to the first embodiment. Therefore, a description of the same configuration and function as the example of the write operation in memory cell arrangement 18 of the non-volatile semiconductor memory device 1 according to the first embodiment will be omitted.

[0166] The write operation in the memory cell arrangement 18 of the non-volatile semiconductor memory device 1 according to the second embodiment has the same effects as the write operation in the memory cell arrangement 18 of the non-volatile semiconductor memory device 1 according to the first embodiment. [THIRD VERSION]

[0167] An example of a write operation in the memory cell arrangement 18 of the non-volatile semiconductor memory device 1 according to a third embodiment is given with reference to Fig. be described. Fig. is a flowchart showing the write operation in the memory cell arrangement 18 of the non-volatile semiconductor memory device 1 according to the third embodiment.

[0168] The flowchart according to the third embodiment includes configuration 4 and configuration 5, which are shown below. Configuration 4 and configuration 5 differ from an example of a write operation in the memory cell arrangement 18 of the non-volatile semiconductor memory device 1 according to the first embodiment.

[0169] Configuration 4: The voltage VDD is applied to the bit line Inhibit BLk+1 and the channel (k+1) at times corresponding to a time of the data (threshold voltage) to be calculated by the data latch DL.

[0170] Configuration 5: The bit line Inhibit BLk and the channel (k) are changed from a state in which the voltage VDD is applied to a state in which the voltage VDD+dV is applied at a time when the voltage VDD is applied to the bit line Inhibit BLk+1 and the channel (k+1).

[0171] The configurations other than configuration 4 and configuration 5 are the same as the example of the write operation in the memory cell arrangement 18 of the non-volatile semiconductor memory device 1 according to the first embodiment. Therefore, a description of the same configuration and function as an example of the write operation in the memory cell arrangement 18 of the non-volatile semiconductor memory device 1 according to the first embodiment will be omitted.

[0172] For example, as seen through a continuous waveform in Fig. The bit line Inhibit BLk+1 and channel (k+1) are changed from a state where voltage VDD is applied to a state where voltage VDD+dV is applied, at a time when the threshold voltage, which has the program target level of the "A" level, is calculated and processed in the data latch DL at time T11. Furthermore, at the time when voltage VDD is applied to the bit line Inhibit BLk+1 and channel (k+1), the bit line Inhibit BLk and channel (k) are changed from the state where voltage VDD is applied to the state where voltage VDD+dV is applied.

[0173] Furthermore, for example, the waveform in a broken line in Fig. The bit lines Inhibit BLk+1 and channel (k+1) are changed from a state where voltage VDD is applied to a state where voltage VDD+dV is applied, at a time when the threshold voltage, which has the program target level of "B", is calculated and processed in the data latch DL at time T12 following time T11. Furthermore, at the time when voltage VDD is applied to the bit line Inhibit BLk+1 and channel (k+1), the bit line Inhibit BLk and channel (k) are changed from the state where voltage VDD is applied to the state where voltage VDD+dV is applied.

[0174] Furthermore, for example, the waveform in a broken line in Fig.At a time when the threshold voltages at the program target level from the "C" level to the "F" level in the data latch DL are calculated and processed at time T13 following time T12, the bit line Inhibit BLk+1 and the channel (k+1) are changed from a state in which the voltage VDD is applied to a state in which the voltage VDD+dV is applied. Furthermore, at the time when the voltage VDD is applied to the bit line Inhibit BL (BLk+1) and the channel (k+1), the bit line Inhibit BL (BLk) and the channel (k) are changed from the state in which the voltage VDD is applied to the state in which the voltage VDD+dV is applied.

[0175] In the non-volatile semiconductor memory device 1, the threshold voltage is written to the memory cell transistor MC at a different rate depending on the level of the threshold voltage (from the "Er" level to the "G" level). The non-volatile semiconductor memory device 1 according to the third embodiment can change the time at which the channel (for example, channel (k)) one layer below the channel (for example, channel (k-1) enclosed along the Z direction in the memory cell transistor to be written to) changes from the state in which the voltage VDD is applied to the state in which the voltage VDD+dV is applied, according to the level of the threshold voltage (from the "Er" level to the "G" level).As a consequence, the non-volatile semiconductor memory device 1 according to the third embodiment can optimize a time of driving up the lower channel along the Z direction with respect to the channel enclosed in the memory cell transistor MC to be written, according to the level of the threshold voltage (“Er” level to “G” level). [OTHER VERSIONS]

[0176] Each part described as a configuration, which is included in the storage system 3 in the first to third embodiments described above, can be implemented either by hardware or by software, or can be implemented by a combination of hardware and software.

[0177] In the above embodiments, where the terms "identical" and "corresponding" are used, "identical" and "corresponding" may include cases where there is a margin of error within the design domain.

[0178] Furthermore, in cases where it is expressed that a certain voltage is applied or supplied, the present disclosure includes both the control of applying or supplying the voltage and the actual application or supply of the voltage. Moreover, applying or supplying the certain voltage may, for example, include applying or supplying a voltage of 0 V.

[0179] As used herein, “connection” refers to an electrical connection and does not, for example, exclude the insertion of another element between it.

[0180] Various embodiments are in accordance with the following numbered clauses. Clause 1. Non-volatile semiconductor storage device comprising the following: a plurality of first memory cell transistors (Mcb1(BLk)), a plurality of second memory cell transistors (Mcb1(BLk-1)) and a plurality of third memory cell transistors (Mcb1(BLk)+1), each of which is set to a threshold voltage of 2 n (n is an integer, equal to 2 or greater) or more different levels can be set, a first bit line (BLk) that extends in a first direction (X-direction), a second bit line (BLk-1) and a third bit line, parallel to the first bit line (BLk+1), a source line (SL) that is located on one side, opposite to the first bit line, with respect to the first direction and extends along a second direction (Y-direction) which intersects the first direction, a first semiconductor layer (channel(k)) extending in the first direction and enclosing the plurality of first memory cell transistors electrically connected between the first bit line and the source line, a second semiconductor layer (channel(k-1)), which encloses the multitude of second memory cell transistors, connected between the second bit line and the source line and stacked with the first semiconductor layer along a third direction that intersects both the first direction and the second direction, a third semiconductor layer (channel(k+1), which includes the plurality of third memory cell transistors, connected between the third bit line and the source line and stacked on one side of the first semiconductor layer, opposite to a side on which the second semiconductor layer is stacked, along the third direction, and a control circuit (15) configured to control each of the plurality of first memory cell transistors, each of the plurality of second memory cell transistors, and each of the plurality of third memory cell transistors to perform a write operation that includes a first operation and a second operation, where When performing the write operation to write data to a second memory cell transistor among the multitude of second memory cell transistors, the control circuit performs controls in such a way that it is possible to carry out the first operation of supplying a first voltage (VSS) as a reference voltage to the second bit line and a second channel of the multitude of second memory cell transistors, supplying a second voltage (VDD), greater than the first voltage, to the first bit line and a first channel of the multitude of first memory cell transistors, and then supplying the second voltage to the third bit line and a third channel of the multitude of third memory cell transistors and driving up the voltage supplied to the first channel to a third voltage (VDD+dV), greater than the second voltage. Clause 2. Non-volatile semiconductor storage device according to Clause 1, further comprising a word line (WLb1), parallel to the source line, along the second direction, where the word line is connected to a second memory cell transistor, a first memory cell transistor among the multitude of first memory cell transistors, and a third memory cell transistor among the multitude of third memory cell transistors, and a first memory cell transistor is connected to a threshold voltage of the lowest level ("Er" level) among the 2 n or is programmed with more different levels. Clause 3. Non-volatile semiconductor storage device according to Clause 2, further comprising the following: a drain-side selection gate line (SGD) that cuts the first bit line, the second bit line, and the third bit line, a source-side selection gate line (SGS), parallel to the source line, a first drain-side selection transistor (ST1-K-1) that is electrically connected between the first bit line and the plurality of first memory cell transistors, a first source-side selection transistor (ST2-K-1) that is electrically connected between the plurality of first memory cell transistors and the source line, a second drain-side selection transistor (ST1-K) that is electrically connected between the second bit line and the plurality of second memory cell transistors, a second source-side selection transistor (ST2-K) that is electrically connected between the multitude of second memory cell transistors and the source line, a third drain-side selection transistor (ST1-K+1) that is electrically connected between the third bit line and the plurality of third memory cell transistors, and a third source-side selection transistor (ST2-K+1) that is electrically connected between the multitude of third memory cell transistors and the source line, where the drain-side selection gate line is connected to the first drain-side selection transistor, the second drain-side selection transistor, and the third drain-side selection transistor. the source-side selection gate line is connected to the first source-side selection transistor, the second source-side selection transistor, and the third source-side selection transistor. Clause 4. Semiconductor storage device according to Clause 3, where The control circuit performs controls to execute the first operation, wherein the first operation includes supplying a voltage (VCHPCH) equal to the second voltage to the word line, supplying a voltage (VSGPCH) equal to or greater than the second voltage and equal to or less than the third voltage to the drain-side select gate line, and supplying the first voltage to the source-side select gate line. Clause 5. Semiconductor storage device according to Clause 4, where The control circuit performs controls to execute the second operation, wherein the second operation, after the first operation, includes applying the first voltage to the word line, the drain-side select gate line, and the source-side select gate line; applying a voltage (VSG) greater than the first voltage and less than the second voltage to the drain-side select gate line after applying the first voltage; applying a fourth voltage (VPASS) greater than the third voltage to the word line after applying the first voltage; boosting a voltage applied to the third channel to a fifth voltage (VCHB) greater than the second voltage; and boosting a voltage applied to the first channel to a sixth voltage (VCHC) greater than the third voltage. the sixth voltage is greater than the fifth voltage. Clause 6. Semiconductor storage device according to Clause 5, where The control circuit performs controls to execute the second operation, wherein the second operation is the application of a seventh voltage (VPGM), greater than the fifth and sixth voltages, after the application of the fourth voltage to the word line, the maintenance of the voltage applied to the third channel at the fourth voltage, the maintenance of the voltage applied to the first channel at the fifth voltage, the maintenance of the voltage applied to the second channel at the first voltage, and the writing of a threshold voltage of any one of the two n or includes more different levels in a second memory cell transistor. Clause 7. Semiconductor storage device according to Clause 6, further comprising a read amplifier section (SAU) connected to each of the first bit line, the second bit line and the third bit line, each of which includes a plurality of latch circuits (SDL, ADL, BDL, CDL, XDL) and a transistor (122) connected to a control signal line (BLC) and are capable of the 2 n or to generate and store more different levels of threshold voltages by performing an arithmetic operation using the multitude of latch circuits, where The control circuit controls the read amplifier section connected to the second bit line to perform the second operation, which includes supplying the threshold voltage of any of the different levels to the second bit line and the second memory cell transistor. Clause 8. Semiconductor storage device according to Clause 7, where The control circuit performs controls to execute the second operation, the second operation including supplying an eighth voltage (VDD+VTH), greater than the second voltage, to the control signal, turning on the transistor, and then supplying a threshold voltage of any one of the different levels to the second bit line and the second memory cell transistor. Clause 9. Semiconductor storage device according to Clause 8, where The control circuit applies the eighth voltage to the control signal after the application of a ninth voltage (VBLDR), which is greater than the eighth voltage. Clause 10. Semiconductor storage device according to Clause 7, where The control circuit performs controls to execute the second operation, wherein the second operation is adjusting the timing of the application of the second voltage to the third channel according to the 2 n or includes more different levels of threshold voltages generated by the reading amplifier section.

[0181] While certain embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of protection of the disclosures. These novel embodiments can be implemented in various other forms and in suitable combinations without deviating from the scope of protection of the disclosure, and various omissions, substitutions, and modifications can be made. These embodiments and modifications thereof are included within the scope of protection of the disclosure. It is intended that the appended claims cover forms or modifications such as would fall within the scope of protection of the disclosure.

Claims

[1] Non-volatile semiconductor storage device comprising: a plurality of first memory cell transistors (Mcb1(BLk)), a plurality of second memory cell transistors (Mcb1(BLk-1)) and a plurality of third memory cell transistors (Mcb1(BLk)+1), each of which is set to a threshold voltage of 2 n (n is an integer, equal to 2 or greater) or more different levels can be set, a first bit line (BLk) that extends in a first direction (X-direction), a second bit line (BLk-1) and a third bit line, parallel to the first bit line (BLk+1), a source line (SL1) that is located on one side, opposite to the first bit line, with respect to the first direction and extends along a second direction (Y-direction) which intersects the first direction, a first semiconductor layer (channel(k)) extending in the first direction and enclosing the plurality of first memory cell transistors electrically connected between the first bit line and the source line, a second semiconductor layer (channel(k-1)) which encloses the multitude of second memory cell transistors, electrically connected between the second bit line and the source line and stacked with the first semiconductor layer along a third direction that intersects both the first direction and the second direction, a third semiconductor layer (channel(k+1), which includes the plurality of third memory cell transistors, electrically connected between the third bit line and the source line and stacked on one side of the first semiconductor layer, opposite to a side on which the second semiconductor layer is stacked, along the third direction, and a control circuit (15) configured to control each of the plurality of first memory cell transistors, each of the plurality of second memory cell transistors, and each of the plurality of third memory cell transistors to perform a write operation that includes a first operation and a second operation, where When performing the write operation to write data to a second memory cell transistor among the multitude of second memory cell transistors, the control circuit performs controls in such a way that it is possible to carry out the first operation of supplying a first voltage (VSS) as a reference voltage to the second bit line and a second channel of the multitude of second memory cell transistors, supplying a second voltage (VDD), greater than the first voltage, to the first bit line and a first channel of the multitude of first memory cell transistors, and then supplying the second voltage to the third bit line and a third channel of the multitude of third memory cell transistors and driving up the voltage supplied to the first channel to a third voltage (VDD+dV), greater than the second voltage. [2] Non-volatile semiconductor storage device according to claim 1, further comprising a word line (WLb1) parallel to the source line along the second direction, where the word line is connected to a second memory cell transistor, a first memory cell transistor among the multitude of first memory cell transistors, and a third memory cell transistor among the multitude of third memory cell transistors, and a first memory cell transistor is connected to a threshold voltage of the lowest level ("Er" level) among the 2 n or is programmed with more different levels. [3] Non-volatile semiconductor storage device according to claim 1 or 2, further comprising: a drain-side selection gate line (SGD) that cuts the first bit line, the second bit line, and the third bit line, a source-side selection gate line (SGS), parallel to the source line, a first drain-side selection transistor (ST1-K-1) that is electrically connected between the first bit line and the plurality of first memory cell transistors, a first source-side selection transistor (ST2-K-1) that is electrically connected between the plurality of first memory cell transistors and the source line, a second drain-side selection transistor (ST1-K) that is electrically connected between the second bit line and the plurality of second memory cell transistors, a second source-side selection transistor (ST2-K) that is electrically connected between the multitude of second memory cell transistors and the source line, a third drain-side selection transistor (ST1-K+1) that is electrically connected between the third bit line and the plurality of third memory cell transistors, and a third source-side selection transistor (ST2-K+1) that is electrically connected between the plurality of third memory cell transistors and the source line, where the drain-side selection gate line is connected to the first drain-side selection transistor, the second drain-side selection transistor, and the third drain-side selection transistor, and the source-side selection gate line is connected to the first source-side selection transistor, the second source-side selection transistor, and the third source-side selection transistor. [4] Semiconductor storage device according to claim 3, provided that it is dependent on claim 2, where The control circuit performs controls to execute the first operation, wherein the first operation includes supplying a voltage (VCHPCH) equal to the second voltage to the word line, supplying a voltage (VSGPCH) equal to or greater than the second voltage and equal to or less than the third voltage to the drain-side select gate line, and supplying the first voltage to the source-side select gate line. [5] Semiconductor storage device according to claim 4, where The control circuit performs controls to execute the second operation, wherein the second operation, after the first operation, includes applying the first voltage to the word line, the drain-side select gate line, and the source-side select gate line; applying a voltage (VSG) greater than the first voltage and less than the second voltage to the drain-side select gate line after applying the first voltage; applying a fourth voltage (VPASS) greater than the third voltage to the word line after applying the first voltage; boosting a voltage applied to the third channel to a fifth voltage (VCHB) greater than the second voltage; and boosting a voltage applied to the first channel to a sixth voltage (VCHC) greater than the third voltage. the sixth voltage is greater than the fifth voltage. [6] Semiconductor storage device according to claim 5, where The control circuit performs controls to execute the second operation, wherein the second operation is the application of a seventh voltage (VPGM), greater than the fifth and sixth voltages, after the application of the fourth voltage to the word line, the maintenance of the voltage applied to the third channel at the fourth voltage, the maintenance of the voltage applied to the first channel at the fifth voltage, the maintenance of the voltage applied to the second channel at the first voltage, and the writing of a threshold voltage of any one of the two n or includes more different levels in a second memory cell transistor. [7] Semiconductor storage device according to claim 6, further comprising a read amplifier part (SAU) connected to each of the first bit line, the second bit line and the third bit line, each of which includes a plurality of latch circuits (SDL, ADL, BDL, CDL, XDL) and a transistor (122) connected to a control signal line (BLC) and are capable of recording the 2 n or to generate and store more different levels of threshold voltages by performing an arithmetic operation using the multitude of latch circuits, where The control circuit controls the read amplifier section connected to the second bit line to perform the second operation, which includes supplying the threshold voltage of any of the different levels to the second bit line and the second memory cell transistor. [8] Semiconductor storage device according to claim 7, where The control circuit performs controls to execute the second operation, the second operation including supplying an eighth voltage (VDD+VTH), greater than the second voltage, to the control signal, turning on the transistor, and then supplying a threshold voltage of any one of the different levels to the second bit line and the second memory cell transistor. [9] Semiconductor storage device according to claim 8, where The control circuit applies the eighth voltage to the control signal after the application of a ninth voltage (VBLDR), which is greater than the eighth voltage. [10] Semiconductor storage device according to any one of claims 7 to 9, where The control circuit performs controls to execute the second operation, wherein the second operation is adjusting the timing of the application of the second voltage to the third channel according to the 2 n or includes more different levels of threshold voltages generated by the reading amplifier section.

Images