METHOD AND EQUIPMENT FOR STACKS OF GLASS LAYERS WITH DEEP TRUCK CAPACITATORS

Abstract

Systems, equipment, manufacturing articles, and methods for stacking glass layers, including deep-trench capacitors, are disclosed. An exemplary substrate for an integrated circuit package disclosed herein comprises a first glass layer, a second glass layer coupled to the first glass layer, and a deep-trench capacitor embedded in the first core.

Description

STATE OF THE ART

[0001] Integrated circuit (IC) chips and / or semiconductor dies are routinely interconnected to larger printed circuit boards (PCBs), such as motherboards and other types of PCBs, via a package substrate. With increasingly smaller IC chips and / or dies and increasing interconnect densities, alternatives to conventional substrate layers are being developed to provide stable transmission of high-frequency data signals between different circuit configurations and / or increased power delivery. One option under consideration is the implementation of package substrates with glass cores. Generally, glass core implementations offer several advantages over implementations with conventional epoxy cores, including higher plated-through-hole (PTH) density, lower signal loss, and less overall thickness variation. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 illustrates an exemplary integrated circuit (IC) package constructed according to the teachings disclosed herein. Fig. Figure 2A illustrates an exemplary first substrate core that can be used to build the exemplary substrate core from Fig. 1 to implement. Fig. Figure 2B illustrates an exemplary second substrate core that can be used to build the exemplary substrate core from Fig. 1 to implement. Fig. Figures 3-13 illustrate different intermediate stages in an exemplary process for producing the exemplary substrate core from Fig. 2A and Fig. 2B. Fig. Figure 14 illustrates an intermediate step in an exemplary process for producing the exemplary first substrate core from Fig. 2A. Fig. Figure 15 illustrates an intermediate step in an exemplary process for producing the exemplary second substrate core from Fig. 2B. Fig. Figure 16 is a flowchart that is representative of exemplary procedures used to produce the substrate core from Fig. 2A-2B can be carried out. Fig. Figure 17 is a top view of a wafer containing dies that may be contained in an IC package constructed according to the teachings disclosed herein. Fig. Figure 18 is a cross-sectional side view of an IC device which may be contained in an IC package constructed according to the teachings disclosed herein. Fig. Figure 19 is a cross-sectional side view of an IC device arrangement which may include an IC package constructed according to the teachings disclosed herein. Fig. Figure 20 is a block diagram of an exemplary electrical device which may include an IC package constructed according to the teachings disclosed herein.

[0002] Generally, the same reference symbols are used throughout the drawing(s) and accompanying written description to refer to the same or similar parts. The figures are not necessarily to scale. Rather, the thickness of the layers or areas in the drawings may be enlarged. Although the figures show layers and areas with clear lines and boundaries, some or all of these lines and / or boundaries may be idealized. In practice, the boundaries and / or lines may be imperceptible, blend into one another, and / or be irregular. DETAILED DESCRIPTION

[0003] Fig. Figure 1 shows an example of a package for an integrated circuit (IC) 100 constructed in accordance with the teachings disclosed herein. In the example shown, the IC package 100 is electrically connected to a printed circuit board 102 via a series of contact pads 104 (e.g., lands, etc.) on a mounting surface 105 (e.g., a base) of the package. In some examples, the IC package 100 may include balls, pins, and / or pads in addition to or instead of the lands 104 to enable the electrical connection of the IC package 100 to the printed circuit board 102. In this example, the package 100 includes two semiconductor dies 106, 108 (e.g., silicon dies, etc.) (sometimes also called chips or chiplets) mounted on a package substrate 110 and enclosed by a package cover or molding compound 112. The housing substrate 110 thus represents an example of a means for receiving a semiconductor die.Although the exemplary IC package is 100 of . Fig. In one example, the IC package 100 contains two dies 106 and 108; in other examples, it can contain only one die or more than two dies. In some examples, one of the dies 106 and 108 (or a separate die) is embedded in the package substrate 110. The dies 106 and 108 can provide any suitable type of functionality (e.g., data processing, memory, etc.).

[0004] As shown in the illustrated example, each of the dies 106, 108 is electrically and mechanically coupled to the housing substrate 110 via corresponding arrays of intermediate connections 114. Fig. In Figure 1, the intermediate connections are shown as contact mounds. In addition to or instead of the contact mounds shown, the intermediate connections 114 can be any other type of electrical connection (e.g., balls, pins, pads, wire bonds, etc.). The electrical connections between the dies 106, 108 and the package substrate 110 (e.g., the intermediate connections 114) are sometimes referred to as first-level intermediate connections. In contrast, the electrical connections between the IC package 100 and the printed circuit board 102 (e.g., the lands 104) are sometimes referred to as second-level intermediate connections. In some examples, one or both of the dies 106, 108 may be stacked on one or more other dies and / or an interposer.In such examples, the dies 106, 108 are coupled to the underlying die and / or interposer by a first set of first-level intermediate connections, and the underlying die and / or interposer may be connected to the housing substrate 110 via a separate set of first-level intermediate connections associated with the underlying die and / or interposer. Thus, first-level intermediate connections, as used herein, refer to intermediate connections (e.g., spheres, contact bumps, pins, pads, wire bonds, etc.) between a die and a housing substrate or between a die and an underlying die and / or interposer.

[0005] As in Fig. As shown in Figure 1, the intermediate connections 114 of the first-level interconnects include two different types of contact mounds, corresponding to core contact mounds 116 and bridge contact mounds 118. The core contact mounds 116, as used here, are contact mounds on the dies 106, 108 through which electrical signals pass between the dies 106, 108 and components outside the IC package 100. In particular, as shown in the illustrated example, the core contact mounds 116 are physically connected and electrically coupled to contact pads 120 on an inner surface 122 of the substrate 110 when the dies 106, 108 are mounted on the package substrate 110. The contact pads 120 on the inner surface 122 of the housing substrate 110 are electrically connected via internal intermediate connections 124 within the housing substrate 110 to the lands 104 on the lower surface 105 (e.g. the lower, external surface, etc.) of the housing substrate 110 (e.g.a surface opposite the inner surface 122). As a result, there is a continuous electrical signal path between the core contact hills 116 of the dies 106, 108 and the lands 104 mounted on the circuit board 102, passing through the contact pads 120 and the intermediate connections 124 provided between them.

[0006] The bridge contact hills 118, as used here, are contact hills on dies 106 and 108 through which electrical signals travel between different dies 106 and 108 within the IC package 100. Accordingly, as shown in the illustrated example, the bridge contact hills 118 of the first die 106 are electrically coupled to the bridge contact hills 118 of the second die 108 via a silicon-based interconnect die 126 (e.g., an interconnect bridge) embedded in the package substrate 110. As shown in Fig. As shown in Figure 1, core contact hills 116 are typically larger than bridge contact hills 118. In some examples, the intermediate connecting bridge 126 and the associated bridge contact hills 118 are omitted.

[0007] In some examples, a backing material 119 is arranged between the dies 106, 108 and the housing substrate 110 around and / or between the first-level intermediate connections 114 (e.g., around and / or between the core contact mounds 116 and / or the bridge contact mounds 118). In the illustrated example, only the first die 106 is associated with the backing material 119. In other examples, however, both dies 106, 108 are associated with the backing material 119. In other examples, the backing material 119 is omitted. In some examples, the molding compound 112 is used as a backing material surrounding the first-level intermediate connections 114.

[0008] In some examples, the IC package includes 100 additional passive components, such as surface-mounted resistors, capacitors and / or inductors, which are arranged on the lower surface 105 of the package substrate 110 and / or the inner surface 122 (e.g. the upper surface etc.) of the package substrate 110.

[0009] In Fig. Figure 1: The package substrate 110 of the exemplary IC package 100 includes a substrate core 128 (e.g., a main core, a total core) between two separate build areas 130 (e.g., build layers, buffer layers). As shown in the illustrated example, the substrate core 128 includes several different glass cores (e.g., multiple glass layers, multiple glass core layers, etc.), namely an exemplary upper glass core 132 (e.g., a first glass core, etc.), an exemplary middle glass core 134 (e.g., a second glass core, etc.), and an exemplary lower glass core 136 (e.g., a third glass core, etc.). In the illustrated example from Fig. 1 the glass cores 132, 134, 136 (e.g. subcores, glass substrates, glass layers, glass plates etc.) are stacked vertically on top of each other.

[0010] In some examples, the glass cores 132, 134, 136 contain at least one of the following: aluminosilicate, borosilicate, aluminoborosilicate, silicon dioxide, and / or molten silicon dioxide. In some examples, the glass cores 132, 134, 136 contain one or more additives, including: aluminum oxide (Al₂O₃), boron trioxide (B₂O₃), magnesium oxide (MgO), calcium oxide (CaO), stoichiometric silicon dioxide (SrO), barium oxide (BaO), tin dioxide (SnO₂), nickel alloy (Na₂O), potassium oxide (K₂O), phosphorus trioxide (P₂O₃), zirconium dioxide (ZrO₂), lithium oxide (Li₂O), titanium (Ti), and / or zinc (Zn). In some examples, the glass cores 132, 134, 136 contain silicon and oxygen. In some embodiments, the glass cores 132, 134, 136 comprise silicon and oxygen, as well as one or more of the following: aluminium, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium and zinc.In some examples, the glass cores 132, 134, 136 comprise at least 23 wt. percent silicon and at least 26 wt. percent oxygen. In some examples, the glass cores 132, 134, 136 are single glass layers containing silicon, oxygen, and aluminum. In some examples, the glass cores 132, 134, 136 comprise at least 23 wt. percent silicon, at least 26 wt. percent oxygen, and at least 5 wt. percent aluminum.

[0011] In some examples, the glass cores 132, 134, 136 are amorphous solid glass sheets. In some examples, the glass cores 132, 134, 136 are glass sheets that do not contain any organic adhesive or organic material. In some examples, the glass cores 132, 134, 136 are solid glass sheets that have the same rectangular shape when viewed from above. In other examples, some or all of the glass cores 132, 134, 136 have different shapes. In some examples, the glass cores 132, 134, 136, as glass substrates, comprise at least one glass sheet and do not include epoxy or glass fibers (e.g., no epoxy-based prepreg layer with glass fabric). In some examples, the glass cores 132, 134, 136 correspond to a single piece of glass that extends over the entire height / thickness of each corresponding core.

[0012] In some examples, the glass cores 132, 134, 136 have a rectangular shape that, in a top view, is essentially congruent with the layers above and below the core. In some examples, the glass cores 132, 134, 136 have a thickness in the range of about 25 micrometers (µm) to about 400 µm (where the total thickness of the substrate core 128 is in the range of about 50 µm to about 1.4 millimeters (mm)). In some examples, the glass cores 132, 134, 136 can have dimensions from about 10 mm on one side to about 250 mm on one side (e.g., 10 mm × 10 mm to 250 mm × 250 mm). In some examples, the glass cores 132, 134, 136 correspond to rectangular prism volumes with sections (e.g. vias) that have been removed and filled with other materials (e.g. metal, etc.).

[0013] The development areas 130 are in Fig. 1 represented as masses / blocks, with the internal intermediate connections 124 extending in straight lines through the build-up areas 130 (and the glass cores 132, 134, 136). This was shown in Fig. 1 However, this is simplified only for the sake of clarity and as an example. In fact, the intermediate connections are not necessarily straight. In particular, in some examples, the build-up regions 130 are defined by alternating layers of dielectric material and layers of conductive material (e.g., a metal such as copper, etc.). The conductive (metal) layers serve as the basis for the internal intermediate connections 124, which are represented in a simplified form by straight lines, as in Fig. Figure 1 shows that in some examples, the metal layers are structured to define electrical pathways or conductors that are electrically coupled between different metal layers by conductive (e.g., metal) vias extending through intervening dielectric layers. Furthermore, the electrical pathways or conductors on both sides of the substrate core 128 can be electrically coupled by glass vias (TGVs) (e.g., copper-clad vias) extending through the glass cores 132, 134, 136.

[0014] Glass cores are advantageous over epoxy-based cores for several reasons, including the fact that glass is stiffer and therefore provides greater mechanical support or strength to the housing substrate. Thus, the substrate core 128 and, in particular, the individual glass cores 132, 134, and 136 are exemplary means of reinforcing the housing substrate. In addition to mechanical advantages, glass cores also offer other benefits, including higher plated-through-hole (PTH) density, lower signal loss, and less overall thickness variation. However, glass cores also present challenges due to the fragile (e.g., brittle) nature of glass and the possibility of defects that can develop into cracks propagating through the glass.

[0015] A common type of failure in known glass cores is called a SeWaRe defect. SeWaRe defects result in the separation of a glass core along a crack that propagates from an edge of the core along its length and width between the principal outer surfaces (e.g., top and bottom surfaces, front and back surfaces) of the core. That is, SeWaRe defects are characterized by a glass core being split into two separate glass plates along a line that generally extends parallel to the principal plane of the core.

[0016] Factors contributing to SeWaRe defects include defects at the edges of glass cores resulting from singulation and internal stress induced by mismatch in the coefficient of thermal expansion (CTE) between the glass core and the material in the build-up areas during thermal cycling of the housing substrate 110. In particular, housing substrates, such as the housing substrate 110 made of Fig. 1, often manufactured on a large sheet, which is then separated or cut into individual units with a saw. Thus, in the example shown, this includes Fig. 1 The housing substrate 110, which includes the substrate core 128 (and the associated glass cores 132, 134, 136) and the build-up areas 130, opposite edges 138 which are produced by cutting with a saw. Such sawing can lead to defects that are located at the edges of glass cores (e.g. the edges 138 of the glass cores 132, 134, 136 in Fig. 1) develop cracks that can propagate laterally across the center of the glass core, splitting it into two parts. Crack development and propagation in this manner are enhanced by stress induced by temperature fluctuations and the difference in the CTE of the buildup regions relative to the CTE of the glass core. Generally, the material in the buildup regions 130 exhibits a higher CTE than the glass. Consequently, in response to thermal fluctuations, the material in the buildup regions 130 expands and contracts more than the glass core, causing internal stress within the glass core that can promote crack propagation.

[0017] Examples revealed herein reduce (e.g., minimize) concerns regarding SeWaRe errors by implementing the substrate core 128 of the substrate with several different (e.g., disaggregated) glass cores (e.g., glass cores 132, 134, 136, etc.) stacked on top of each other, as in Fig. Figure 1 shows. In particular, in the examples disclosed herein, the glass cores 132, 134, 136 are implemented by different materials (or different compositions of the same materials) associated with different CTEs. In some examples, the glass cores located closer to the build-up areas 130 are manufactured with a CTE that is closer to the CTE of the build-up areas 130 than the CTE of the glass cores located farther from the build-up areas 130 (e.g., closer to the center of the stack of glass cores). In this way, the substrate core 128 is defined by a gradation of CTEs or incremental changes in the CTE (between each of the glass cores 132, 134, 136) that provide a transition between the different layers in the housing substrate 110 to reduce stress at any given location.Thus, in some examples, the middle glass core 134 has a lower CTE than the upper glass core 132 and a lower CTE than the lower glass core 136. In other examples, the CTE of the upper glass core 132 and the lower glass core 136 are the same. Therefore, in some examples, the different CTEs of the glass cores 132, 134, and 136 are symmetrical across the total thickness of the substrate core 128. That is, the arrangement or order of the stack of glass cores 132, 134, and 136 and their associated CTEs define a symmetrical sequence of CTEs from a bottommost glass core (e.g., the lower glass core 136) to a topmost glass core (e.g., the upper glass core 132). In other examples, the different CTEs may not be symmetrical.

[0018] In addition to implementing multiple glass cores with different CTEs to reduce stress, in some examples a buffer material 140 (e.g., an adhesive) is placed between adjacent glass cores 132, 134, 136 to hold the glass cores together. In some such examples, the buffer material 140 has a relatively low modulus of elasticity to absorb stress resulting from thermal fluctuations and the different CTEs of the glass cores 132, 134, 136, thereby further reducing stress within the substrate core 128. In some examples, the buffer material is an organic dielectric material (e.g., polyimide, parylene, etc.). In other examples, the buffer material is an inorganic dielectric material (e.g., silicon dioxide (SiO₂)). x ), silicon nitride (SiN xIn some examples, the buffer material comprises a carbon-doped oxide (CDO). In some examples, one or more of the layers of buffer material 140 can be omitted, so that different glass cores 132, 134, 136 are in direct contact with it. In some examples, the layers of buffer material 140 include conductive material that enables the redistribution of electrical paths between the glass cores 132, 134, 136. Therefore, the materials between the glass cores are also referred to here as redistribution material, which defines one or more buffer layers in the housing substrate 110.

[0019] Although three different glass cores (e.g., glass cores 132, 134, 136, etc.) are used in the exemplary substrate core 128 Fig. As shown in Figure 1, any other suitable number of glass cores with corresponding CTEs can be implemented to define a specific CTE gradient across the total thickness of the substrate core 128. Thus, in some examples, only two glass cores, each with a different CTE, are used. In other examples, more than three glass cores are used. In some such examples, each glass core differs from every other glass core in the stack of cores. In other examples, two or more of the glass cores can have the same CTE (e.g., made from the same materials with the same composition), with at least one glass core having a different CTE than the others.

[0020] In the illustrated example from Fig. Figure 1 shows each of the glass cores 132, 134, 136 having the same thickness (e.g., approximately the same thickness, etc.). However, in some examples, the thickness of the glass cores 132, 134, 136 may differ. For example, in some examples, the middle glass core 134 is thicker than the upper glass core 132 and thicker than the lower glass core 136. In other examples, the middle glass core 134 is thinner than the upper glass core 132 and thinner than the lower glass core 136. Any suitable thicknesses for the glass cores can be implemented to achieve a suitable CTE gradient that reduces stress to mitigate SeWaRe defects while also providing sufficient stiffness for the housing substrate.

[0021] Stacking multiple glass cores 132, 134, 136 with different CTEs, as disclosed herein, can serve to reduce stresses that could otherwise lead to SeWaRe failures. The exemplary substrate cores disclosed herein also include embedded deep-trench capacitors. These exemplary substrate cores include deep-trench capacitors to improve power delivery to components coupled to the housing substrates, such as dies 106, 108 of Fig. 1. Some exemplary substrate cores disclosed herein include a deep trench capacitor (e.g., arranged within it, etc.) embedded in one of the uppermost stacked glass cores. Other exemplary substrate cores disclosed herein include one or more deep trench capacitors arranged in other stacked glass cores. Other exemplary substrate cores disclosed herein include deep trench capacitors arranged in two or more stacked glass cores. Examples of substrate cores with embedded deep trench capacitors are given below in conjunction with Fig. 2A-2B described.

[0022] Fig. Figure 2A illustrates an exemplary first substrate core 200 that can be used to create the exemplary substrate core 128 from Fig. 1 to implement. Similar to Fig. 1 contains the first substrate core 200 from Fig. 2. An exemplary first glass core 202, an exemplary second glass core 204, and an exemplary third glass core 206, stacked on top of each other. In this example, the glass cores 202, 204, and 206 correspond to the glass cores 132, 134, and 136 respectively from [reference missing]. Fig. 1. Thus, the glass cores 202, 204, and 206 contain different CTEs, as described above. For example, in some examples, the second glass core 204 (e.g., the middle glass core) has a lower CTE than either the first glass core 202 or the third glass core 206. In this example, each of the glass cores 202, 204, and 206 has approximately the same thickness. In some examples, the thickness is about 350 micrometers (µm). In other examples, the thickness may be greater or less than 350 µm. Furthermore, in some examples, different glass cores 202, 204, and 206 may have different thicknesses. Additionally, although three glass cores are shown, any other suitable number of glass cores (e.g., 2, 4, 5, 6, 7, etc.) can be implemented. In such examples, the stack of glass cores can define any suitable CTE gradient based on differences in the CTE for each glass core in the stack.In some examples, the CTE gradient is symmetrical over the total thickness of the first substrate core 200. In other examples, the CTE gradient may not be symmetrical.

[0023] In the illustrated example from Fig. In 2A, the glass cores 202, 204, and 206 are separated by intervening layers of adhesive dielectric 208 (e.g., a buffer material, an adhesive material, a bonding layer, etc.). In some examples, the adhesive dielectric 208 comprises an organic epoxy-based dielectric. However, any other suitable dielectric can also be used, either additionally or alternatively. In some examples, the adhesive dielectric 208 couples corresponding glass cores 202, 204, and 206 together. For example, the layer of adhesive dielectric 208 between the first glass core 202 and the second glass core 204 adhesively couples the first glass core 202 to the second glass core 204, and so on.

[0024] In the example shown from Fig. In 2A, the first substrate core 200 comprises an exemplary first buffer layer 210A, an exemplary second buffer layer 210B, an exemplary third buffer layer 210C, an exemplary fourth buffer layer 210D, an exemplary fifth buffer layer 210E, and an exemplary sixth buffer layer 210F. The buffer layers 210A, 210B, 210C, 210D, 210E, and 210F contain (e.g., consist of, etc.) a dielectric filler material (e.g., Ajinomoto build-up film (ABF), etc.) and may include one or more conductive intermediate connections (e.g., vias, contact pads, contact bumps, etc.) arranged within a The conductive intermediate connections of the buffer layers 210A, 210B, 210C, 210D, 210E, 210F transmit power and / or electrical signals between adjacent glass cores 202, 204, 206. In some examples, some or all of the buffer layers 210A, 210B, 210C, 210D, 210E, 210F are redistribution layers.In some such examples, the intermediate connections of some or all buffer layers 210A, 210B, 210C, 210D, 210E, 210F cannot connect vertically aligned TGVs 222 and TSV 223.

[0025] In the illustrated example from Fig. In 2A, the first buffer layer 210A and the sixth buffer layer 210F are located on the outermost surfaces of the outermost glass cores (e.g., the first glass core 202 and the third glass core 206). Thus, in the illustrated example, they define Fig. 2A the first buffer layer 210A and the sixth buffer layer 210F, an exemplary first outer surface 211 and an exemplary second outer surface 212 of the first substrate core 200. In some examples, all of the buffer layers 210A, 210B, 210C, 210D, 210E, 210F are missing. In such examples, corresponding glass cores 202, 204, 206 are directly adjacent to a corresponding layer of the adhesive dielectric 208. An exemplary substrate core in which the second buffer layer 210B, the third buffer layer 210C, the fourth buffer layer 210D, the fifth buffer layer 210E, and the sixth buffer layer 210F are missing is shown below in conjunction with Fig. 2B described In some such examples, the first buffer layer 210A and the sixth buffer layer 210F, which are in Fig. 2A are shown, may be omitted and / or a first layer of development areas (e.g. the development areas 130 of Fig. 1) on both sides of the first substrate core 200. In such examples, the outer surfaces of the first glass core 202 and the third glass core 206 define the first outer surface 211 and the second outer surface 212 of the first substrate core 200.

[0026] In the example shown from Fig. The first substrate core 200 contains an exemplary deep-trench capacitor 214 embedded in an exemplary opening 216A (e.g., a cavity, etc.). The deep-trench capacitor 214 includes structures for a capacitor fabricated on a semiconductor substrate (e.g., silicon). Thus, the deep-trench capacitor 214 is an example of a semiconductor die embedded in the opening 216A. The deep-trench capacitor 214 is used to provide efficient power delivery to a fully integrated voltage regulator within a substrate core 200 (e.g., the first die 106 of the IC package 100). Fig. 1 etc.) assembled to enable this. In the illustrated example from Fig. In 2A, the deep trench capacitor 214 has a smaller thickness than the first glass core 202 and is electrically coupled to a surface of the first glass core 202 via exemplary intermediate connections 218. In other examples, the deep trench capacitor 214 has the same thickness as the first glass core 202 and is approximately flush with the outer surfaces of the first glass core 202. In other examples, the deep trench capacitor 214 is mounted on a spacer (e.g., a base, etc.). Although the examples described herein refer to one or more deep trench capacitors (e.g., the deep trench capacitor 214, etc.), the examples disclosed herein are also applicable to other embedded semiconductor devices (e.g., EMIBs, a die, etc.).

[0027] In the illustrated example of Fig. In example 2A, the first substrate core 200 contains a single trench capacitor (e.g., trench capacitor 214, etc.). In other examples, the first substrate core 200 may contain additional trench capacitors within the first glass core 202 (e.g., two trench capacitors, three trench capacitors, etc.). In some such examples, separate trench capacitors are placed within the same opening 216A of the first glass core 202. In other examples, different trench capacitors are placed within different openings in the first glass core 202. Additionally or alternatively, the first substrate core 200 may contain additional trench capacitors embedded in one or more openings of the second glass core 204 and / or the third glass core 206.An exemplary substrate core incorporating deep trench capacitors embedded in the second glass core 204 and the third glass core 206 is shown below in conjunction with . Fig. 2B described.

[0028] In the illustrated example from Fig. In 2A, the glass cores 202, 204, 206 also include exemplary first through-hole vias (TGVs) 222, which are electrically coupled by additional conductive material 224 extending through the intervening layers of the adhesive dielectric 208. In the illustrated example from Fig. 2A the TGVs 222 border the lateral edges of the first substrate core 200. That is, in the illustrated example from Fig. In 2A, the center of the first substrate core 200 does not contain any TGVs. In other examples, the substrate core 200 may contain other arrangements of TGVs 222 and deep trench capacitors (e.g., the deep trench capacitor 214, etc.). For example, the deep trench capacitor 214 may be located near one of the side edges, and the TGVs 222 may be located near the center of the first substrate core 200. In such examples as the illustrated example of Fig. 2A, the TGVs 222 are not vertically aligned with areas of the first substrate core 200 that contain a deep trench capacitor (e.g., the deep trench capacitor 214, etc.). In the illustrated example from Fig. In 2A, the intermediate connections of the buffer layers 210B, 210C, 210D, 210E couple the vertically oriented TGVs 222. In other examples, the intermediate connections of the buffer layers 210B, 210C, 210D, 210E can redistribute (e.g., divide, merge, redirect, etc.) the electrical connections between the TGVs 222. That is, the buffer layers 210B, 210C, 210D, 210E allow non-vertically oriented TGVs 222 to be electrically coupled. In some examples, the TGVs 222 are plated with the same material used in the additional conductive material 224 (e.g., copper paste, plated copper pads, liquid metal (LM) paste, etc.). In some examples, at least some of the additional conductive material 224 may contain a different material than the TGVs 222. In the illustrated example from Fig. 2A includes the first substrate core 200, exemplary first conductive pads 226, which are positioned on the outer surfaces 211, 212 of the first substrate core 200 and electrically coupled to the TGVs 222 and the additional conductive material 224. In this example, the first conductive pads 226 define opposite ends of intermediate connections (e.g., parts of the intermediate connections 124 made of Fig. 1), which extend through the full thickness of the substrate core 200. In the illustrated example from Fig. 2A includes the first substrate core 200 exemplary second conductive pads 228, which are electrically coupled to the intermediate connections 218 of the trench capacitor 214. In some examples, the second conductive pads 228 can be connected to corresponding intermediate connections within the assembly area 130 of Fig. 1. They may be coupled to improve the power distribution to dies 106 and 108. In some examples, one or more of the second conductive pads 228 and one or more first conductive pads 226 can be implemented by one or more identical electrical pads. That is, a single electrical pad can be coupled to at least one of the intermediate connections 218 of the deep trench capacitor 214 and at least one of the TGVs 222.

[0029] Fig. Figure 2B illustrates an exemplary second substrate core 230 that can be used to create the exemplary substrate core 128 from Fig. 1 to implement. In the illustrated example from Fig. 2B contains the second substrate core 230 and the glass cores 202, 204, 206 made of Fig. 2A, the adhesive dielectric 208 made of Fig. 2A, the buffer layers 210A, 210B, 210C, 210D, 210E, 210F Fig. 2A, the outer surfaces 211, 212 from Fig. 2A, the opening 216A from Fig. 2A (in conjunction with Fig. 2B, designated as the first opening 216A), the TGVs 222 from Fig. 2A, the additional conductive material 224 made of Fig. 2A and the additional conductive pads 226, 228 from Fig. 2A. The second substrate core 230 made of Fig. 2B is the first substrate core 200 from Fig. 2A similar, except that the second substrate core 230 includes an exemplary first deep trench capacitor 232A embedded in the first opening 216A of the first glass core 202, an exemplary second deep trench capacitor 232B embedded in an exemplary second opening 216B in the second glass core 204, and an exemplary third deep trench capacitor 232C embedded in an exemplary third opening 216C of the third glass core 206.

[0030] In the illustrated example from Fig. 2B contains the second substrate core 230 exemplary silicon vias (TSVs) 223. The TSVs 223 are similar to the first TGV 222 except for the differing specifications. In the Fig. In example 2B, the second TGVs are electrically connected with intermediate links 218. Fig. 2A coupled. The TSVs 223 extend through the openings 216A, 216B, 216C in the center of the glass cores 202, 204, 206 and electrically couple the deep-trench capacitors 232A, 232B, 232C in series. In other examples, the TSVs 223 can be arranged at a different location in the second substrate core 230 (e.g., depending on the position of the deep-trench capacitors 232A, 232B, 232C, etc.). In the example in Fig. In the example shown in Figure 2B, corresponding TSVs 223 are coupled via the additional conductive material 224. In some examples, some of the TSVs 223 are electrically coupled to the first TGVs 222 via intermediate connections of the buffer layers 210A, 210B, 210C, 210D, 210E, 210F.

[0031] In the example shown from Fig. 2B resembles the deep trench capacitors, 232A, 232B, 232C the deep trench capacitor 214 from Fig. 2A, except that the TSVs 223 extend through the trench capacitors 232A, 232B, 232C. That is, the trench capacitors 232A, 232B, 232C include intermediate connections that allow the transmission of electrical power through the trench capacitors 232A, 232B, 232C. In other examples, the trench capacitors 232A, 232B, 232C do not include any internal intermediate connections associated with the TSVs 223. In some examples, the TSVs 223 are arranged inside the openings 216A, 216B, 216C and outside the trench capacitors 232A, 232B, 232C. In some examples, the TSVs 223 are referred to here as through-dielectric vias (TDVs). In the example shown by Fig. The trench capacitors 232A, 232B, 232C have the same size and shape as the trench capacitor 214. Fig. 2A. In other examples, the trench capacitors 232A, 232B, 232C may have a different size, shape, and / or configuration than the first trench capacitor 214. In the example shown by Fig. In example 2C, the trench capacitors 232A, 232B, 232C are arranged in the openings 216A, 216B, 216C (e.g., embedded, etc.). In other examples, some or all of the trench capacitors 232A, 232B, 232C are missing. In the example shown, Fig. In example 2B, the trench capacitors 232A, 232B, and 232C are electrically coupled in series. In other examples, the trench capacitors 232A, 232B, and 232C can be arranged in parallel and / or in any other suitable configuration. In the illustrated example from Fig. In 2B, the second substrate core 230 contains an equal number of glass core layers (e.g., a first set of layers, three layers, etc.) and deep trench capacitors (e.g., a second set of deep trench capacitors, three deep trench capacitors, etc.). In other examples, the second substrate core 230 may contain a greater number of deep trench capacitors than the glass core layers. In some such examples, each of the glass cores 202, 204, 206 may contain multiple deep trench capacitors.

[0032] Fig. Figures 3-13 illustrate various stages in an exemplary manufacturing process for producing a glass core assembly, which includes the exemplary first substrate core 200 made of Fig. 2A and / or the exemplary second substrate core 230 from Fig. 2B can be used. As used herein, the term “glass core assembly” refers to a glass core of a substrate core, which includes a stack of glass cores and any associated components embedded therein or arranged thereon (e.g., TGVs, deep trench capacitors, buffer layers, etc.). Fig. Figure 14 illustrates an intermediate stage in another exemplary manufacturing process for producing the first substrate core 200 from Fig. 2A, which represents the different intermediate stages Fig. 3-13 can follow. Fig. Figure 15 illustrates an intermediate stage in another exemplary manufacturing process for producing the second substrate core 230 from Fig. 2B, which represents the different intermediate stages Fig. 3-13 may follow. It is understood that other methods and / or intermediate steps for the production of the exemplary first memory core 200 of Fig. 2A and / or the exemplary second substrate core 230 of Fig. 2B can be used. Exemplary operations for the preparation of substrate cores 200, 230 of Fig. 2A and Fig. 2B via some or all of the intermediate stages of Fig. 3-13 are subsequently referred to in conjunction with Fig. 16 described.

[0033] Fig. Figure 3 is a schematic cross-sectional view of an exemplary first intermediate stage 300 of the assembly / manufacturing of a glass core assembly, which is connected with the first substrate core 200 of Fig. 2A and the second substrate core 230 from Fig. 2B is associated. In the first intermediate stage 300, an exemplary glass plate 302 is provided. The glass plate 302 can correspond to the initial state of any of the glass cores 202, 204, 206. For explanatory purposes, the glass plate 302 is to be considered the second glass core 204 (e.g., the middle glass core in the substrate cores 200, 230). Fig. 2A and Fig. 2B) shown and described accordingly. In some examples, the glass plate 302 is manufactured to a thickness corresponding to the final thickness of the glass core 204. However, in some examples, the glass plate 302 is initially slightly larger than the final thickness of the second glass core 204 to allow for the removal of a certain amount of glass during subsequent polishing or planarizing processes, as discussed below.

[0034] Fig. Figures 4-8 describe the formation of through-glass vias (TGVs) in the second glass core 204. The in Fig. The intermediate stages shown in Figures 4-8 illustrate the formation of TGVs on the lateral sides of the second glass core 204 (e.g., the first TGVs 222 from Fig. 2A and Fig. 2B etc.) and an opening in the middle of the second glass core 204 (e.g. the openings 216A, 216B, 216C from Fig. 2B etc.). If a glass core associated with a glass core assembly that does not include a deep trench capacitor is to be manufactured (e.g., the glass cores 204, 206 in the first substrate core 200 from Fig. 2A etc.), the processing of the center of the glass core during the in Fig. The intermediate stages shown in 4-8 can be omitted. Additionally or alternatively, depending on the planned position of the trench capacitors to be embedded in the second glass core 204, the first TGVs 222 can be generated at a different location within the second glass core 204 (e.g., in the center of the second glass core 204, etc.).

[0035] Fig. Figure 4 is a schematic cross-sectional view of an exemplary second intermediate stage 400 of the assembly / manufacturing of a glass core assembly, which is connected to the first substrate core 200 of Fig. 2A and the second substrate core 230 from Fig. 2B are associated. In some examples, the second intermediate stage 400 can follow the first intermediate stage 300. Fig. 3. During the second intermediate stage 400, the second glass core 204 is exposed to a laser as part of a laser-induced deep etching (LIDE) process. The laser is concentrated on defined areas 402 of the glass core 204 in order to modify the optical and chemical properties of the glass core 204 in these areas 402.

[0036] Fig. Figure 5 is a schematic cross-sectional view of an exemplary third intermediate stage 500 of the assembly / manufacturing of a glass core assembly, which is connected with the first substrate core 200 of Fig. 2A and the second substrate core 230 from Fig. 2B is associated. In some examples, the third intermediate stage 500 can follow the second intermediate stage 400. Fig. 4. During the third intermediate stage 500, the second glass core 204 is subjected to a chemical etching process to modify the material in the modified areas 402 of the Fig. 3 to remove the glass core 204 shown in order to create the opening 216A and exemplary additional openings 502 for the in Fig. 2A and Fig. To define the TGVs 222 shown in 2B. In the example shown from Fig. In 5, the openings 216A, 502 have a cross-sectional profile that generally corresponds to an hourglass shape, wherein the width (e.g., diameter) of the openings 216A, 502 is narrower near a midpoint of the openings between opposing first and second surfaces 504, 506 of the glass core 204. In other examples, one or more of the openings 216A, 502 may have a different cross-sectional shape. For example, in some examples, one or more of the openings 216A, 502 may have a generally conical or tapered shape, wherein the width (e.g., diameter) is smallest at one of the two surfaces 504, 506 of the second glass core 204 and the width (e.g., diameter) is largest at surfaces 504, 506. In other examples, the width (e.g.,the diameter) of one or more of the openings 216A, 502 along a full length of the openings 502 between the opposing surfaces 504, 506 of the second glass core 204 approximately consistent.

[0037] Fig. 6 is a schematic cross-sectional view of an exemplary fourth intermediate stage 600 of the assembly / manufacturing of a glass core assembly, which is connected with the first substrate core 200 of Fig. 2A and the second substrate core 230 from Fig. 2B is associated. In some examples, the fourth intermediate stage 600 can follow the third intermediate stage 500. Fig. 5. During the fourth intermediate stage 600, an exemplary conductive carrier 602 is deposited onto the second surface 506. In the example shown from Fig. 6 the conductive carrier includes a conductive layer 604 (e.g. a copper layer) and a separating layer 606 (e.g. a dielectric adhesive layer).

[0038] Fig. Figure 7 is a schematic cross-sectional view of an exemplary fifth intermediate stage 700 of the assembly / manufacturing of a glass core assembly, which is connected with the first substrate core 200 of Fig. 2A and the second substrate core 230 from Fig. 2B is associated. In some examples, the fifth intermediate stage 700 can follow the fourth intermediate stage 600 from Fig. 6. During the fifth intermediate stage 700, the trench capacitor 232A is deposited onto the conductive support 602 within the first opening 216A. In the illustrated example of Fig. 7 includes the first deep trench capacitor 232A, exemplary first DTC pads 702 and exemplary second DTC pads 704, which enable the first deep trench capacitor 232A to be electrically connected to external components (e.g. the dies 106, 108 of Fig. 1 etc.) is coupled. In the illustrated example from Fig. 7 The second trench capacitor 232B is positioned within the first opening 216A, such that the first DTC pads 702 are essentially flush with the first surface 504 and the second DTC pads 704 are in contact with the conductive support 602 (e.g., abutting it, etc.) and are essentially flush with the second surface 506. Although Fig. 7 with reference to the arrangement of the second trench capacitor 232B in the first opening 216A, other trench capacitors (e.g. the trench capacitor 214 from Fig. 2A, the first deep trench capacitor 232A, the third deep trench capacitor 232C, etc.) can be arranged similarly in a glass core. For example, the deep trench capacitor 214 can be made of Fig. 2A are arranged within the first opening 216A so that the pads of the trench capacitor 214 are in contact with the conductive support 602 and are substantially flush with the second surface 506.

[0039] Fig. Figure 8 is a schematic cross-sectional view of an exemplary sixth intermediate stage 800 of the assembly / manufacturing of a glass core assembly, which is connected to the first substrate core 200 of Fig. 2A and the second substrate core 230 from Fig. 2B is associated. In some examples, the sixth intermediate stage 800 can be followed by the fifth intermediate stage 700. Fig. 7. During the sixth intermediate stage 800, the first opening 216A in the second glass core 204 is filled with the dielectric material 802. In the example shown, Fig. The dielectric material 802 surrounds and / or encloses the first trench capacitor 232A. In some examples, the dielectric material 802 is introduced into the opening as a liquid or paste and subsequently crosslinked. In some examples, any excess of the dielectric material 802 extending beyond the first surface 504 of the second glass core 204 is removed by a polishing process (e.g., a chemical-mechanical planarization (CMP) process, etc.). In some examples, this polishing process slightly thins the second glass core 204.

[0040] Fig. Figure 9 is a schematic cross-sectional view of an exemplary seventh intermediate stage 900 of the assembly / manufacturing of a glass core assembly, which is connected with the first substrate core 200 of Fig. 2A and the second substrate core 230 from Fig. 2B is associated. In some examples, the seventh intermediate stage 900 can follow the sixth intermediate stage 800 from Fig. 8. During the seventh intermediate stage 900, an exemplary mask 902 (e.g., via photolithography) is deposited to cover the first surface 504, except for the openings 502 of the glass core. Furthermore, the following takes place: Fig. Figure 9 shows the manufacturing stage after an etching process (e.g., plasma etching, dry etching) for removing portions of the separating layer 606 that are exposed within the openings 502 of the glass core 204, thereby exposing the underlying conductive layer 604. The mask 902 protects the dielectric material 802 during the etching process.

[0041] Fig. Figure 10 is a schematic cross-sectional view of an exemplary eighth intermediate stage 1000 of the assembly / manufacturing of a glass core assembly, which is connected with the first substrate core 200 of Fig. 2A and the second substrate core 230 from Fig. 2B is associated. In some examples, the eighth intermediate stage 1000 can follow the seventh intermediate stage 900. Fig. 9. During the eighth intermediate stage 1000, a conductive material (e.g., copper, etc.) is deposited (e.g., plated, etc.) within the openings 502 to define the TGVs 222 that extend through the second glass core 204. In this example, the TGVs 222 are plated upwards from the exposed portions of the conductive layer 604. Therefore, in this example, no nucleation layer is deposited along the walls of the openings 502 prior to the plating process. However, in other examples, a nucleation layer may be used to facilitate the plating of the TGVs 222.

[0042] Fig. Figure 11 is a schematic cross-sectional view of an exemplary ninth intermediate stage 1100 of the assembly / manufacturing of a glass core assembly, which is connected to the first substrate core 200 of Fig. 2A and the second substrate core 230 from Fig. 2B is associated. In some examples, the ninth intermediate stage 1100 can follow the eighth intermediate stage 1000 from Fig. 10. During the ninth intermediate stage 1100, the conductive carrier 602, including the conductive layer 604 and the separating layer 606, is removed. In some examples, the second surface 506 of the glass core undergoes a polishing process (e.g., a CMP process, etc.) to make the TGVs 222 and TSVs 223 flush with the second surface 506. In some examples, the second glass core 204 also undergoes a cleaning process to remove any residual materials.

[0043] Fig. Figure 12 is a schematic cross-sectional view of an exemplary tenth intermediate stage 1200 of the assembly / manufacturing of a glass core assembly, which is connected with the first substrate core 200 of Fig. 2A and the second substrate core 230 from Fig. 2B is associated. In some examples, the tenth intermediate stage 1200 can follow the ninth intermediate stage 1100 from Fig. 11. During the tenth intermediate stage 1200, an exemplary third buffer layer 210C and an exemplary fourth buffer layer 210D were deposited on the first surface 504 and the second surface 506, respectively, of the second glass core 204. The buffer layers 210C and 210D contain (e.g., consist of) a dielectric material, e.g., ABF, and a conductive material, e.g., copper. In the illustrated example, the buffer layers 210C and 210D were structured such that the TGVs 222 and TSVs 223 extend through the buffer layers 210C and 210D. For example, the buffer layers 210C and 210D can be drilled to create openings aligned with the TGVs 222 and TSVs 223, and conductive material can be introduced into the created openings.

[0044] Additionally, during the tenth intermediate stage, 1200 exemplary first pads 1206 and exemplary second pads 1208 are structured on the third buffer layer 210C and the fourth buffer layer 210D. In the example shown from Fig. In Figure 12, the first pads 1206 on buffer layers 210A, 210B are structured to align with the first TGVs 222, and the second pads 1208 on buffer layers 210A, 210B are structured to align with the TSVs 223. In some examples, pads 1206, 1208 are deposited by lithography. Additionally or alternatively, pads 1206, 1208 can be deposited by another suitable process (e.g., atomic layer deposition (ALD), chemical vapor deposition (CVD), electroplating, etc.) or a combination thereof.

[0045] Fig. Figure 13 is a schematic cross-sectional view of an exemplary eleventh intermediate stage 1300 of the assembly / manufacturing of an exemplary first glass core assembly 1302, which is connected with the first substrate core 200 of Fig. 2A and the second substrate core 230 from Fig. 2B is associated. In some examples, the eleventh intermediate stage 1300 can follow the tenth intermediate stage 1200 from Fig. 12. During the eleventh intermediate step 1300, the adhesive dielectric 208 is deposited onto the first buffer layer 210A. Additionally, during the eleventh intermediate step 1300, the additional conductive material 224 (e.g., a liquid metal, copper paste, etc.) is deposited between portions of the interfaces defined by a conductive material to electrically couple the conductive material in the stack. In other examples, intermediate step 1300 is omitted. In some such examples, adjacent glass core assemblies in a stack can be coupled via another method (e.g., fusion bonding, etc.). After the execution of the processes associated with intermediate step 1300, the fabrication of an exemplary first glass core assembly 1302 is complete.

[0046] Fig. Figure 14 is a schematic cross-sectional view of an exemplary twelfth intermediate stage 1400, which is associated with the assembly / production of the first substrate core 200 of Fig. 2A is associated. In some examples, the twelfth intermediate stage 1400 can occur after the fabrication of an exemplary second glass core assembly 1402, an exemplary third glass core assembly 1404, and an exemplary fourth glass core assembly 1406. The glass core assemblies 1402, 1404, and 1406 are similar to the first glass core assemblies 1302 of Fig. 13, except where otherwise stated. In the example shown of Fig. 14 include the second glass core assembly 1402, the third glass core assembly 1404 and the fourth glass core assembly 1406 corresponding to the first glass core 202 of Fig. 2A, the second glass core 204 of Fig. 2A and the third glass core 206 from Fig. 2A .

[0047] In some examples, each of the glass core assemblies 1402, 1404, 1406 can be derived via some or all of the intermediate stages 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300 of Fig. 3-13 can be manufactured. For example, the first glass core assembly 1302 can be produced via any of the intermediate stages 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200. Fig. 3-12 are produced (e.g., the deposition of the adhesive dielectric 208 and the additional conductive material 224 during the intermediate stage 1300 from Fig. 13 omitted, etc.). In some such examples, the deep trench capacitor 214 is made from Fig. 2A during the execution of the intermediate stage 700 from Fig. 7 arranged in the first opening 216A. The third glass core assembly 1404 and the fourth glass core assembly 1406 can be arranged via the intermediate stages 300, 400, 500, 600, 900, 1100, 1200 from Fig. 3-6, 9, 11 and 12 are produced (e.g. the arrangement of a deep trench capacitor, such as the deep trench capacitor 214, during the intermediate stage 700 from Fig. 7 and subsequent processing during the intermediate stage 800 from Fig. 8 are omitted). In other examples, the glass core assemblies 1402, 1404, 1406 can be made from Fig. 14 can be produced via any other suitable process. During the twelfth intermediate stage 1400, the three glass cores 202, 204, 206 are assembled or stacked by combining or joining the respective glass core assemblies 1402, 1404, 1406. The result of combining or joining the glass core assemblies 1402, 1404, 1406 produces the first substrate core 200. Fig. 2A.

[0048] Fig. Figure 15 is a schematic cross-sectional view of an exemplary thirteenth intermediate stage 1500, which is associated with the assembly / production of the second substrate core 230 of Fig. 2B is associated. In some examples, the thirteenth intermediate stage 1500 can be made after the production of the first glass core assembly 1302. Fig. 13, an exemplary fourth glass core assembly 1502 and an exemplary fifth glass core assembly 1504. In the example shown of Fig. 15 include the fourth glass core assembly 1502 and the fifth glass core assembly 1504, the second glass core 204 of Fig. 2B and the third glass core 206 from Fig. 2A or 2B. The fourth glass core assembly 1502 can be produced via any of the intermediate stages 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200. Fig. 3-12 are produced (e.g., the deposition of the adhesive dielectric 208 and the additional conductive material 224 during the intermediate stage 1300 from Fig. 13 omitted, etc.). The fifth glass core assembly 1504 can be selected from any of the intermediate stages 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300. Fig. 3-13 can be manufactured. In other examples, the glass core assemblies 1302, 1502, 1504 can be made from Fig. 15. They can be produced via any other suitable process. During the thirteenth intermediate stage 1500, the three glass cores 202, 204, 206 are assembled or stacked by combining or joining the respective glass core assemblies 1302, 1502, 1504. The glass core assemblies 1302, 1502, 1504 are made of Fig. 15 can be stacked in a similar way to the glass core assemblies 1402, 1404, 1406. Fig. 14 stacked / assembled, as in connection with Fig. 14 described. The result of combining or joining the glass core assemblies 1302, 1502, 1504 produces the second substrate core 230 from Fig. 2B.

[0049] Fig. Figure 16 is a flowchart illustrating an exemplary procedure that can be carried out to prepare any of the exemplary first substrate core 200 of Fig. 2A and the second substrate core 230 of Fig. 2B via the intermediate stages 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1500 from Fig. 3-15 to manufacture. In some examples, some or all of the components in the exemplary procedure are made from Fig. The 16 operations described are performed automatically by equipment programmed to carry out the operations. Although the exemplary procedure refers to the one described in Fig. As described in the illustrated flowchart 16, alternative methods can be used. For example, the execution order of the blocks can be changed, and / or some of the described blocks can be combined, subdivided, rearranged, omitted, eliminated, and / or implemented in any other way. Furthermore, in some examples, additional processing operations can be performed before, between, and / or after any of the blocks shown in the illustrated example.

[0050] The exemplary procedure from Fig. Step 16 begins at block 1602 by preparing a glass core (e.g., any one of the glass cores 202, 204, 206) with a given coefficient of thermal expansion (CTE). For example, the coefficients of thermal expansion of each of the glass cores 202, 204, 206 can be adjusted by modifying (e.g., varying, changing, etc.) the composition of the glass in each of the layers. That is, the coefficients of thermal expansion of each of the glass cores 202, 204, 206 can be adjusted by changing the relative proportions of Al₂O₃, B₂O₃, Li₂O, Na₂O, K₂O, Sb₂O₃, and / or other additives in each of the layers and / or through processing variations (e.g., lamination, thermal treatment, etc.). In some examples, the composition of materials used in the glass core is selected to achieve the CTE intended for a specific glass layer within an entire substrate core that includes multiple stacked glass cores.In some examples, the composition of materials used in the glass core is selected to achieve the CTE specified for a particular glass layer within an entire substrate core comprising multiple stacked glass cores. The point of fabrication after completion of block 1602 corresponds to the structure of the first intermediate stage 300. Fig. 3. For block 1604, the exemplary procedure may involve adding openings through the glass core. For example, openings corresponding to the first TGVs 222 and / or one of the openings 216A, 216B, 216C may be formed in the glass core 204. In some examples, if the glass core assembly is not to include a DTC, no opening is added in the center of the second glass core 204 (e.g., one of the openings 216A, 216B, 216C, etc.). The openings may be formed, for example, by laser cutting and / or etching. The point of fabrication after completion of block 1602 corresponds to the structure of the third intermediate stage 500 of Fig. 5. In block 1606, the exemplary method involves applying a support to the glass core 202. For example, the second glass core 204 can be applied to the conductive support 602 via the separating layer 606. Fig. 6 are separated. The point of manufacture after completion of block 1606 corresponds to the structure of the fourth intermediate stage 600 of Fig. 6.

[0051] In block 1608, the procedure involves determining whether one or more trench capacitors (e.g., one of the trench capacitors 214, 232A, 232B, 232C, etc.) are to be arranged in the second opening 216B of the second glass core 204. If a trench capacitor is to be arranged on the second glass core 204, the procedure proceeds to block 1610. If no trench capacitor is to be arranged in the second opening 216B of the second glass core 204, the procedure proceeds to block 1614. In block 1610, the trench capacitor 232B is deposited onto the support 602 in the opening 216B. For example, the second trench capacitor 232B (and / or another of the trench capacitors 214, 232A, 232B) can be made from Fig. 2A and Fig. 2B, etc.) in the second opening 216B using a mechanical assembly technique (e.g., pick-and-place, etc.). In other examples, the second trench capacitor 232B can be arranged in opening 216A, 216B, 216C using a different technique and / or manufactured therein using several manufacturing techniques. The point of manufacture after completion of block 1610 corresponds to the structure of the fifth intermediate stage 700 of Fig. 7. In block 1612, the second opening 216B in the second glass core 204 is filled with the dielectric material 802. For example, the dielectric material 802 can be placed in the second opening 216B such that the dielectric material surrounds and / or seals the second deep trench capacitor 232B. The point of manufacture after completion of block 1612 corresponds to the structure of the seventh intermediate stage 900 of Fig. 9.

[0052] In block 1614, a conductive material is deposited into the openings to the first TGVs 222 through the second glass core 204. For example, the TGVs 222 in the openings can be formed by electroplating a conductive layer of the attached support (e.g., completely electroplated from bottom to top, partially electroplated from bottom to top, etc.). In some examples, a mask (e.g., mask 902 made of Fig. 9 etc.) are deposited on the second glass core 204 to shield other components of the glass core 204 during the deposition of the conductive material. The point of manufacture after completion of block 1614 corresponds to the structure of the eighth intermediate stage 1000 of Fig. 10. In block 1616, the exemplary procedure involves detaching the conductive support 602 from the second glass core 204. In some examples, the second glass core 204 is polished and cleaned after detachment of the conductive support 602. The point of manufacture after completion of block 1616 corresponds to the structure of the ninth intermediate stage 1100 of Fig. 11.

[0053] In Block 1618, the process involves determining whether one or more buildup layers (e.g., buffer layers 210A, 210B, etc.) are to be deposited on the second glass core 204. If a buildup layer is to be deposited on the second glass core 204, the process continues to Block 1620. If no buildup layer is to be deposited on the second glass core 204, the process continues to Block 1622. In Block 1620, the process involves depositing buffer layers on the upper surface and / or the lower surface of the second glass core 204. For example, materials for additional redistribution layer(s) (e.g., dielectric layers, interlinking, etc.) can be deposited on the second glass core 204. In some examples, the buffer layers 210A, 210B can be processed (e.g. drilled, structured by lithography, etc.) to form openings aligned with the TGVs 222 and TSVs 223.In some such examples, conductive material can be deposited in order to extend the TGVs to the outer surfaces of the buffer layers 210A, 210B.

[0054] For block 1622, the procedure involves structuring the pads on the TGVs 222 and TSVs 223. For example, the first pads 1206 of Fig. 12 on the buffer layers 210A, 210B are structured to be aligned with the TGVs 222, and the second pads 1208 of Fig. Pads 12 can be structured on buffer layers 210A and 210B to align with TSV 223. In some examples, pads 1206 and 1208 are deposited by lithography. Additionally or alternatively, pads 1206 and 1208 are deposited by another suitable process (e.g., ALD, CVD, electroplating, etc.). The fabrication point after completion of block 1622 corresponds to the structure of the tenth intermediate 1200. Fig. 12.

[0055] In block 1624, the process involves the deposition of the adhesive dielectric 208. For example, the adhesive dielectric 208 can be deposited (e.g., via spin coating, lamination, etc.) on the first buffer layer 210A. In some examples, the additional conductive material 224 (e.g., a liquid metal, copper paste, etc.) is deposited between portions of the interfaces defined by a conductive material to electrically couple the conductive material in the stack. The point of fabrication after completion of block 1626 corresponds to the structure of the eleventh intermediate stage 1300 of Fig. 13.

[0056] In block 1626, the exemplary procedure involves determining whether to fabricate a different glass core assembly (e.g., glass core assemblies 1302, 1402, 1404, 1406, 1502, 1504, etc.). If so, the process returns to block 1602 to repeat the process for the different glass core assembly. In some examples, the different glass core assembly may be constructed with a different CTE, include a different configuration of deep-trench capacitors (e.g., their absence or presence, etc.), and / or include a different configuration of buffer layers. In some examples, separate iterations through the exemplary process may be performed in parallel rather than sequentially. Once no further glass core assemblies are to be fabricated, the exemplary process proceeds to block 1628, which involves stacking (e.g., combining, etc.) the glass core assemblies.In some examples, the glass core assemblies, such as those completed up to block 1626, are directly connected to each other to form a corresponding substrate core 200, 230. Fig. Forming 2A-2B. The conclusion of the exemplary process from Fig. Step 16 results in a complete substrate core (e.g., any of the substrate cores 200, 230, etc.). The completed substrate core can then be subjected to any suitable subsequent processing (e.g., adding build layers, attaching one or more dies, and implementing other packaging processes).

[0057] Although exemplary operations with reference to the in Fig. As described in the flowchart shown in section 16, many other methods for assembling / producing the substrate cores 200, 230 can alternatively be used. Fig. 2A and Fig. 2B can be used. For example, the execution order of the blocks can be changed and / or some of the described blocks can be modified, eliminated or combined.

[0058] The exemplary IC packages 100 made of Fig. 1 (e.g. with any of the exemplary substrate cores 200, 230 etc. disclosed herein) can be included in any suitable electronic component. Fig. Figures 17-20 illustrate various examples of devices that include or may be contained in the IC package 100 disclosed herein.

[0059] Fig. Figure 17 is a top view of a 1700 wafer and a 1702 die, which are housed in the IC package 100 of Fig. The wafer 1700 may contain (e.g., any suitable dies 106, 108). The wafer 1700 contains a semiconductor material and one or more dies 1702 with a circuit arrangement. Each die 1702 can be a repeating unit of a semiconductor product. After the fabrication of the semiconductor product is complete, the wafer 1700 can undergo a singulation process in which the dies 1702 are separated from each other to provide discrete "chips". The die 1702 contains one or more transistors (e.g., some of the transistors 1840 from Fig. 18, which are discussed below), a support circuit arrangement for routing electrical signals to the transistors, passive components (e.g., conductive traces, resistors, capacitors, inductors, and / or other circuit arrangement), and / or any other components. In some examples, the Die 1702 may include and / or implement a storage device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a conductive bridge RAM (CBRAM), etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or other suitable circuit arrangement. Several of these devices can be combined on a single chip (e.g., the Die 1702, etc.).A memory array can, for example, consist of multiple memory circuits on the same die (e.g., the 1702 die, etc.) like a programmable circuit arrangement (e.g., the 2002 processor circuit arrangement from ). Fig. 20) and / or another logic circuit arrangement. Such a memory can store information for use by the programmable circuit arrangement. The exemplary IC package 100 disclosed herein can be fabricated using a die-on-wafer assembly technique in which some dies are attached to a wafer 1700, which contains the other dies, and the wafer 1700 is subsequently singulated.

[0060] Fig. Figure 18 is a cross-sectional side view of an IC device 1900, which may be contained in the exemplary IC package 100 (e.g., in any of the dies 106, 108). One or more of the IC devices 1800 may be contained in one or more dies 1702 ( Fig. 17). The IC device 1800 can be mounted on a die substrate 1802 (e.g., the wafer 1700 of Fig. 17) be formed and can be in a Die (e.g. the Die 1702 of Fig. 17) may be included. The die substrate 1802 may be a semiconductor substrate comprising semiconductor materials, including, for example, n-type or p-type material systems (or a combination of both). The die substrate 1802 may, for example, include a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some examples, the die substrate 1802 may be formed using alternative materials, which may or may not be combined with silicon, including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, III-V, or IV may also be used to form the die substrate 1802.Although some examples of materials from which the die substrate 1802 can be formed are described here, any material that can serve as a basis for an IC device 1800 can be used. The die substrate 1802 can be part of a single die (e.g., the die 1702 made of...). Fig. 17) or a wafer (e.g., wafer 1700 from Fig. 17).

[0061] The IC device 1800 can include one or more device layers 1804 arranged on and / or above the die substrate 1802. The device layer 1804 can have features of one or more transistors 1840 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1802. For example, the device layer 1804 can include one or more source and / or drain (S / D) regions 1820, a gate 1822 for controlling current flow between the S / D regions 1820, and one or more S / D contacts 1824 for conducting electrical signals to / from the S / D regions 1820. The transistors 1840 can have additional features, not shown for clarity, such as isolation regions, gate contacts, and the like. The 1840 transistors are not suitable for the ones in Fig. The type and configuration shown in Figure 18 are limited and can include a wide variety of other types and configurations, such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors can include FinFET transistors, such as dual-gate or tri-gate transistors, and wrap-around or all-around-gate transistors, such as nanoband and nanowire transistors.

[0062] Each 1840 transistor can include a 1822 gate, including a gate dielectric and a gate electrode. The gate dielectric can consist of a single layer or a stack of layers. The single layer(s) can consist of silicon dioxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material. The high-k dielectric material can include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and / or zinc. Examples of high-k materials usable in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide and / or lead zinc cniobate.In some examples, the gate dielectric can be subjected to a tempering process to improve its quality when a high-k material is used.

[0063] The gate electrode can be formed on the gate dielectric and, depending on whether the 1840 transistor is to be a p-type metal-oxide semiconductor (PMOS) transistor or an n-type metal-oxide semiconductor (NMOS) transistor, may have at least one p-type or one n-type source metal. In some implementations, the gate electrode may include a stack of two or more metal layers, one or more of which are source metal layers and at least one of which is a filler metal layer. Additional metal layers may be included, for example, as a depletion layer. For a PMOS transistor, metals suitable for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and / or any of the metals discussed below with reference to an NMOS transistor (e.g.,(for work function tuning). In an NMOS transistor, metals suitable for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide and / or aluminum carbide) and / or any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).

[0064] In some examples, when viewed as a cross-section of transistor 1840 along the source-channel-drain direction, the gate electrode may comprise a U-shaped structure comprising a lower section that is substantially parallel to the top surface of the die substrate 1802 and two sidewall portions that are substantially perpendicular to the top surface of the die substrate 1802. In other examples, at least one of the metal layers forming the gate electrode may be a planar layer that is substantially parallel to the top surface of the die substrate 1802 and does not include any sidewall portions that are substantially perpendicular to the top surface of the die substrate 1802. In still other examples, the gate electrode may comprise a combination of U-shaped structures and / or planar, non-U-shaped structures.For example, the gate electrode can include one or more U-shaped metal layers formed on top of one or more planar, non-U-shaped layers.

[0065] In some examples, a pair of sidewall spacers can be formed on opposite sides of the gate stack to secure the gate stack. The sidewall spacers can be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and / or silicon oxynitride. Processes for forming sidewall spacers are known from the prior art and generally involve deposition and etching processes. In some examples, multiple pairs of spacers can be used; for example, two pairs, three pairs, or four pairs of sidewall spacers can be formed on opposite sides of the gate stack.

[0066] The S / D regions 1820 can be formed within the die substrate 1802 adjacent to the gate 1822 of one or more corresponding transistors 1840. The S / D regions 1820 can be formed, for example, using an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic can be ion-implanted into the die substrate 1802 to form the S / D regions 1820. The ion implantation process can be followed by an annealing process, which activates the dopants and causes them to diffuse further into the die substrate 1802. In the latter process, the die substrate 1802 can first be etched to form depressions at the locations of the S / D regions 1820. Afterwards, an epitaxial deposition process can be carried out to fill the depressions with material that is used to fabricate the S / D areas 1820.In some implementations, the S / D regions 1820 can be fabricated using a silicon alloy, such as silicon germanium or silicon carbide. In some examples, the epitaxially deposited silicon alloy can be doped in situ with dopants such as boron, arsenic, or phosphorus. In some examples, the S / D regions 1820 can be formed using one or more alternative semiconductor materials, such as germanium or a material or alloy from Group III-V. In other examples, one or more layers of metal and / or metal alloys can be used to form the S / D regions 1820.

[0067] Electrical signals, such as power and / or input / output (I / O) signals, can be routed to and / or from the devices (e.g., transistors 1840) of the device layer 1804 through one or more interconnection layers arranged on the device layer 1804 (in Fig. 18 illustrated as interconnection layers 1806-1810). For example, electrically conductive features of the device layer 1804 (e.g., the gate 1822 and the S / D contacts 1824) can be electrically coupled to the interconnection structures 1828 of the interconnection layers 1806 to 1810. The one or more interconnection layers 1806-1810 can form a metallization stack (also referred to as an "ILD stack") 1819 of the IC device 1800.

[0068] The interconnection structures 1828 can be arranged within the interconnection layers 1806-1810 to conduct electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to those shown in Fig. 18 special configurations of interconnect structures shown (limited in 1828). Although a special number of interconnect layers were used in 1806-1810 in Fig. The examples shown in Figure 18 include IC devices with more or fewer interconnect layers than shown.

[0069] In some examples, the interconnection structures 1828 may include conductors 1828A and / or vias 1828B filled with an electrically conductive material, such as a metal. The conductors 1828A may be arranged to conduct electrical signals in a direction along a plane that is substantially parallel to a surface of the die substrate 1802 on which the device layer 1804 is formed. For example, the conductors 1828A may be arranged from the perspective of Fig. 18 electrical signals are conducted in a direction leading into and out of the side. The vias 1828B can be arranged to conduct electrical signals in a direction along a plane that is substantially perpendicular to the surface of the die substrate 1802 on which the device layer 1804 is formed. In some examples, the vias 1828B can electrically couple conductors 1828A of different interconnection layers 1806-1810.

[0070] The intermediate interconnection layers 1806 to 1810 can have a dielectric material 1826 arranged between the intermediate interconnection structures 1828, as shown in Fig. Figure 18 shows. In some examples, the dielectric material 1826 arranged between the intermediate interconnection structures 1828 in different intermediate interconnection layers 1806-1810 may have different compositions; in other examples, the composition of the dielectric material 1826 may be the same between different intermediate interconnection layers 1806-1810.

[0071] A first interconnect layer 1806 (designated as metal 1 or "M1") can be formed directly on the fixture layer 1804. In some examples, the first interconnect layer 1806 can include conductors 1828A and / or vias 1828B, as shown. The conductors 1828A of the first interconnect layer 1806 can be coupled to contacts (e.g., the S / D contacts 1824) of the fixture layer 1804.

[0072] A second interconnect layer 1808 (designated as Metal 2 or "M2") can be formed directly on top of the first interconnect layer 1806. In some examples, the second interconnect layer 1808 may include vias 1828B to couple the leads 1828A of the second interconnect layer 1808 to the leads 1828A of the first interconnect layer 1806. Although the leads 1828A and the vias 1828B are structurally delineated by a line within each interconnect layer (e.g., within the second interconnect layer 1808) for clarity, in some examples the leads 1828A and the vias 1828B may be structurally and / or materially related (e.g., filled simultaneously during a dual-damascene process).

[0073] A third interlinking layer 1810 (designated as Metal 3 or “M3”) (and additional interlinking layers if required) can be formed sequentially on the second interlinking layer 1808 according to similar techniques and configurations described in connection with the second interlinking layer 1808 or the first interlinking layer 1806. In some examples, the interlinking layers located “further up” in the metallization stack 1819 in the IC device 1800 (i.e., farther from the device layer 1804) can be thicker.

[0074] The IC device 1800 can include a solder mask material 1834 (e.g., polyimide or a similar material) and one or more conductive contacts 1836 formed on the interlinking layers 1806-1810. Fig. Figure 18 illustrates the conductive contacts 1836 as taking the form of bond contact patches. The conductive contacts 1836 can be electrically coupled to the interconnection structures 1828 and configured to conduct the electrical signals from the one or more transistors 1840 to other external devices. For example, solder bonds can be formed on the one or more conductive contacts 1836 to mechanically and / or electrically couple a chip containing the IC device 1800 to another component (e.g., a printed circuit board). The IC device 1800 can include additional or alternative structures for conducting the electrical signals from the interconnection layers 1806-1810; for example, the conductive contacts 1836 can include other analog features (e.g., posts) that conduct the electrical signals to external components.

[0075] Fig. Figure 19 is a cross-sectional side view of an IC device arrangement 1900, which may include the IC package 100 disclosed herein. In some examples, the IC device arrangement corresponds to the IC package 100. The IC device arrangement 1900 includes a number of components arranged on a printed circuit board 1902 (which may, for example, be a main board). The IC device arrangement 1900 includes components arranged on a first face 1940 of the printed circuit board 1902 and an opposing second face 1942 of the printed circuit board 1902; generally, components may be arranged on one or both faces 1940 and 1942. Any of the IC packages discussed below with reference to the IC device arrangement 1900 may have the shape of the exemplary IC package 100. Fig. exhibit 1.

[0076] In some examples, the 1902 printed circuit board (PCB) can be a printed circuit board (PCB) comprising several metal layers separated by layers of dielectric material and interconnected by electrically conductive vias. Any number of the metal layers can be formed in a desired circuit structure to conduct electrical signals (optionally in conjunction with other metal layers) between the components connected to the 1902 printed circuit board. In some examples, the 1902 printed circuit board can be a non-PCB substrate.

[0077] The in Fig. Figure 19 illustrates the IC device arrangement 1900, which features a case-on-interposer structure 1936 coupled to the first surface 1940 of the printed circuit board 1902 by coupling components 1916. The coupling components 1916 can electrically and mechanically couple the case-on-interposer structure 1936 to the printed circuit board 1902 and can accommodate solder balls (as in Fig. 19), including male and female sections of a base, an adhesive, a backer rod and / or any other suitable electrical and / or mechanical coupling structure.

[0078] The package-on-interposer structure 1936 can include an IC package 1920 coupled to an interposer 1904 by coupling components 1918. The coupling components 1918 can take any form suitable for the application, such as the forms discussed above with reference to the coupling components 1916. Although a single IC package 1920 in Fig. As shown in Figure 19, multiple IC packages can be coupled to the interposer 1904; in fact, additional interposers can be coupled to the interposer 1904. The interposer 1904 can provide an intermediate substrate used to bridge the printed circuit board 1902 and the IC package 1920. The IC package 1920 can, for example, be a die (the die 1702 of Fig. 17), an IC device (e.g. the IC device 1800 from Fig. 18) or any other suitable component or include such a component. In general, the interposer 1904 can spread a connection to a wider grid dimension or redirect a connection to another connection. For example, the interposer 1904 can couple the IC package 1920 (e.g., a die) to a set of conductive BGA contacts of the coupling components 1916 for coupling to the printed circuit board 1902. In the case of the Fig. In the 19 illustrated examples, the IC package 1920 and the printed circuit board 1902 are attached to opposite sides of the interposer 1904; in other examples, the IC package 1920 and the printed circuit board 1902 may be attached to the same side of the interposer 1904. In some examples, three or more components may be connected to each other by means of the interposer 1904.

[0079] In some examples, the Interposer 1904 may be formed as a PCB comprising several metal layers separated by layers of dielectric material and interconnected by electrically conductive vias. In some examples, the Interposer 1904 may be formed from an epoxy resin, a glass-fiber-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some examples, the Interposer 1904 may be formed from alternative rigid or flexible materials, which may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other materials of Groups III-V and IV.The Interposer 1904 may incorporate metal interconnects 1908 and vias 1910, including, but not limited to, silicon vias (TSVs) 1906. The Interposer 1904 may further incorporate embedded devices 1914, including both passive and active devices. These devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and storage devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, may also be formed on the Interposer 1904.The case-on-interposer structure 1936 can take the form of any case-on-interposer structure known according to the state of the art.

[0080] The IC device arrangement 1900 can include an IC package 1924, which is coupled to the first surface 1940 of the printed circuit board 1902 by coupling components 1922. The coupling components 1922 can take the form of any of the examples discussed above with reference to the coupling components 1916, and the IC package 1924 can take the form of any of the examples discussed above with reference to the IC package 1920.

[0081] The in Fig. Figure 19 illustrates the IC device arrangement 1900, which includes a case-on-case structure 1934 coupled to the second surface 1942 of the printed circuit board 1902 by coupling components 1928. The case-on-case structure 1934 can include a first IC package 1926 and a second IC package 1932, which are coupled to each other by coupling components 1930 such that the first IC package 1926 is located between the printed circuit board 1902 and the second IC package 1932. The coupling components 1928 and 1930 can take the form of any of the coupling component examples 1916 discussed above, and the IC packages 1926 and 1932 can take the form of any of the IC package examples 1920 discussed above. The package-on-package structure 1934 can be configured according to any of the package-on-package structures known in the prior art.

[0082] Fig. Figure 20 is a block diagram of an exemplary electrical device 2000, which may include one or more of the exemplary IC packages 100. For example, any suitable components of the electrical device 2000 may include one or more of the device arrangements 1900, IC devices 1800, or dies 1702 disclosed herein and may be arranged in the exemplary IC package 100. A number of components are shown in Fig. Figure 20 illustrates components included in Electrical Device 2000; however, any one or more of these components may be omitted or duplicated as appropriate for the application. In some examples, some or all of the components included in Electrical Device 2000 may be attached to one or more mainboards. In some examples, some or all of these components may be fabricated on a single system-on-a-chip (SoC) die.

[0083] Additionally, the electrical device 2000 can, in various examples, perform one or more of the functions described in Fig.The electrical device 2000 may not include the components shown in Figure 20, but it may include an interface circuit arrangement for coupling with one or more of the components. For example, the electrical device 2000 may not include a display 2006, but it may include a display interface circuit arrangement (e.g., a connector and a driver circuit arrangement) to which a display 2006 can be coupled. In another set of examples, the electrical device 2000 may not include an audio input device 2018 (e.g., a microphone) or an audio output device 2008 (e.g., a loudspeaker, headphones, earphones, etc.), but it may include an audio input or output device interface circuit arrangement (e.g., a connector and a support circuit arrangement) to which an audio input device 2018 or audio output device 2008 can be coupled.

[0084] The electrical device 2000 may include a programmable circuit arrangement 2002 (e.g., one or more processing devices). The programmable circuit arrangement 2002 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device 2000 may include a memory 2004, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random-access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard disk.In some examples, memory 2004 may include a memory that shares a die with programmable circuit arrangement 2002. This memory may be used as cache memory and may include embedded dynamic random-access memory (eDRAM) or magnetic spin transfer torque random-access memory (STT-MRAM).

[0085] In some examples, the electrical device 2000 may include a communication chip 2012 (e.g., one or more communication chips). For example, the communication chip 2012 may be configured to manage wireless communications for the transmission of data to and from the electrical device 2000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, procedures, techniques, communication channels, etc., that can communicate data through a non-solid medium by using modulated electromagnetic radiation. The term does not imply that the associated devices contain no wires whatsoever, although in some examples they may not.

[0086] The 2012 communications chip can implement any number of wireless standards or protocols, including, but not limited to, Institute for Electrical and Electronic Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), the Long-Term Evolution (LTE) project along with all amendments, updates, and / or revisions (e.g., the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16-compliant Broadband Wireless Access networks (BWA networks) are commonly referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, a mark of approval for products that pass compliance and interoperability tests for the IEEE 802.16 standards.The 2012 Communications Chip can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The 2012 Communications Chip can operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The 2012 Communications Chip can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and variations thereof, as well as any other wireless protocols referred to as 3G, 4G, 5G, and beyond. The 2012 communication chip can also operate according to other wireless protocols in other examples.The electrical device 2000 may have an antenna 2022 to support wireless communications and / or to receive other wireless communications (such as AM or FM radio transmissions).

[0087] In some examples, the 2012 Communications Chip can manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., Ethernet). As mentioned above, the 2012 Communications Chip can contain multiple communication chips. For example, a first 2012 Communications Chip can be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and a second 2012 Communications Chip can be dedicated to longer-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some examples, a first 2012 Communications Chip can be dedicated to wireless communications and a second 2012 Communications Chip can be dedicated to wired communications.

[0088] The electrical device 2000 may include a battery / power circuit arrangement 2014. The battery / power circuit arrangement 2014 may include one or more energy storage devices (e.g., batteries or capacitors) and / or a circuit arrangement for coupling components of the electrical device 2000 to a power source separate from the electrical device 2000 (e.g., AC mains power).

[0089] The electrical device 2000 may include a display 2006 (or a corresponding interface circuit arrangement, as discussed above). The display 2006 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0090] The electrical device 2000 may include an audio output device 2008 (or a corresponding interface circuit arrangement, as discussed above). The audio output device 2008 may include any device that produces an acoustic indicator, such as a loudspeaker, headphones, or earphones.

[0091] The electrical device 2000 may include an audio input device 2018 (or a corresponding interface circuit arrangement, as discussed above). The audio input device 2018 may include any device that generates a signal representing sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments with a Musical Instrument Digital Interface (MIDI) output).

[0092] The electrical device 2000 can include a GPS circuit arrangement 2016. The GPS circuit arrangement 2016 can communicate with a satellite-based system and receive a location data for the electrical device 2000, as is known from the prior art.

[0093] The electrical device 2000 may include any other output device 2010 (or a corresponding interface circuit arrangement, as discussed above). Examples of the other output device 2010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0094] The electrical device 2000 may include any other input device 2020 (or a corresponding interface circuit arrangement, as discussed above). Examples of the other input device 2020 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0095] The Electrical Device 2000 can be of any desired form factor, such as a handheld or mobile electrical device (e.g., a mobile phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultramobile personal computer, etc.), a desktop electrical device, a server or other networked computing component, a printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or portable electrical device. In some examples, the Electrical Device 2000 can be any other electronic device that processes data.

[0096] "Including" and "comprising" (and all forms and tenses thereof) are used here as open terms. It is understood that whenever a claim uses any form of "including" or "comprising" (e.g., encompasses, exhibits, encompassing, including, exhibiting, etc.) as a preamble or within any kind of claim statement, additional elements, terms, etc., may be present without falling outside the scope of protection of the claim or statement in question. When used in this document, the expression "at least" is used as the transitional term in, for example, a preamble of a claim, it is open in the same way as the terms "comprising" and "including" are open.The term "and / or," when used in a form such as A, B and / or C, refers to any combination or subset of A, B, C, such as (1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) B with C, or (7) A with B and with C. When used in this document in the context of describing structures, components, elements, objects, and / or things, the phrase "at least one of A and B" refers to implementations that include any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, when used in this document in the context of describing structures, components, elements, objects and / or things, the phrase “at least one of A or B” shall refer to implementations that include any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.When used in this document in the context of describing the execution or performance of processes, instructions, actions, activities, etc., the phrase "at least one of A and B" shall refer to implementations that include any one of (1) at least one A, (2) at least one B, and (3) at least one A and at least one B. Similarly, when used in this document in the context of describing the execution or performance of processes, instructions, actions, activities, and / or steps, the phrase "at least one of A or B" shall refer to implementations that include any one of (1) at least one A, (2) at least one B, and (3) at least one A and at least one B.

[0097] When used in this document, singular references (e.g., "a," "an," "first," "second," etc.) do not preclude plurality. The term "a" object, when used in this document, refers to one or more of that object. The terms "a" (or "an"), "one or more," and "at least one" are used interchangeably here. Furthermore, although listed individually, multiple means, elements, or actions can be implemented by, for example, the same entity or object. Additionally, although individual features may be included in different examples or claims, they may potentially be combined, and inclusion in different examples or claims does not imply that a combination of features is not feasible and / or advantageous.

[0098] As used here, the term "above," unless otherwise specified, describes the relationship of two parts relative to the Earth. A first part is above a second part if the second part has at least one part between the Earth and the first part. Likewise, a first part is "below" a second part, as used here, if the first part is closer to the Earth than the second part. As noted above, a first part may be above or below a second part, with one or more of: other parts in between, without other parts in between, with the first and second parts in contact, or without the first and second parts being in direct contact with each other.

[0099] Notwithstanding the foregoing, when referring to a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, and / or an integrated circuit (IC) package containing a semiconductor die, during fabrication or manufacturing, the term “above” refers not to the ground, but instead to an underlying substrate on which relevant components are fabricated, assembled, mounted, supported, or otherwise provided. Thus, as used herein and unless otherwise specified or implied from the context, a first component within a semiconductor die (e.g., a transistor or other semiconductor device) is “above” a second component within the semiconductor die if, during fabrication / manufacturing, the first component is further supported by a substrate (e.g., a substrate).a semiconductor wafer) is located further away than the second component on which the two components are fabricated or otherwise provided. Unless otherwise specified or implied from the context, a first component within an IC package (e.g., a semiconductor die) is likewise located “over” a second component within the IC package during fabrication if the first component is located farther away from a printed circuit board (PCB) on which the IC package is to be mounted or attached. It is understood that semiconductor devices are frequently used in a different orientation than their orientation during fabrication. Thus, when referring to a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, and / or an integrated circuit (IC) package containing a semiconductor die during use, the definition of “over” in the preceding paragraph (i.e.,The term “over” describes the relationship of two parts relative to the Earth) presumably determined based on the context of use.

[0100] As used in this patent, the indication that any part (e.g., a layer, a film, a region, an area, or a plate) is located on another part in any way (e.g., positioned, situated, arranged, or formed on it, etc.) indicates that the part referred to is either in contact with the other part or that the part referred to is located above the other part with one or more intermediate part(s) in between.

[0101] As used here, connection references (e.g., attached, coupled, connected, and affixed) can include intermediate elements between the elements referenced by the connection reference and / or relative movement between those elements, unless otherwise specified. Therefore, connection references do not necessarily imply that two elements are directly and / or in a fixed relationship to each other. As used here, the statement that any part is in "contact" with another part is defined as meaning that there is no intermediate element between the two parts.

[0102] Unless specifically stated otherwise, descriptors such as "first," "second," "third," etc., are used herein without implying any significance of priority, physical order, arrangement in a list, and / or sequence, or otherwise indicating any such significance. They are used merely as labels and / or arbitrary names to distinguish elements for the purpose of facilitating understanding of the disclosed examples. In some examples, the descriptor "first" may be used to refer to an element in the detailed description, while the same element in a claim may be referred to by a different descriptor, such as "second" or "third." In these cases, it is understood that such descriptors are used solely to uniquely identify those elements within the context of the discussion (e.g.,within a claim) where the elements might otherwise share the same name, for example.

[0103] As used here, "approximately" and "about" modify their subjects / values ​​to account for the potential presence of variations that occur in real-world applications. For example, the terms "approximately" and "about" can modify dimensions that, due to manufacturing tolerances and / or other imperfections in the real world, are not exact as understood by the average person. For example, "approximately" and "about" can indicate that such dimensions may fall within a tolerance range of + / - 10%, unless otherwise specified here.

[0104] As used herein, “essentially real-time” refers to a near-instantaneous occurrence, acknowledging that real-world delays for data processing, transmission, etc., may occur. Thus, unless otherwise specified, “essentially real-time” refers to real-time + 1 second.

[0105] As used herein, the term “in communication”, including variations thereof, encompasses direct communication and / or indirect communication through one or more intermediaries, and does not require direct physical (for example, wired) communication and / or continuous communication, but additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals and / or one-off events.

[0106] As used herein, a “programmable circuit” is defined as comprising (i) one or more specialized electrical circuits (for example, an application-specific integrated circuit (ASIC)) structured to perform one or more specific operations and including one or more semiconductor-based logic devices (for example, electrical hardware implemented by one or more transistors), and / or (ii) one or more semiconductor-based general-purpose electrical circuits programmable with instructions to perform one or more specific functions and / or operations, and including one or more semiconductor-based logic devices (for example, electrical hardware implemented by one or more transistors). Examples of a programmable circuit arrangement include programmable microprocessors, such as central processing units (CPUs).that can execute first instructions to perform one or more operations and / or functions, field-programmable gate arrays (FPGAs) that can be programmed with second instructions to configure and / or structure the FPGAs in order to instantiate one or more operations and / or functions according to the first instructions, graphics processing units (GPUs) that can execute first instructions to perform one or more operations and / or functions, digital signal processors (DSPs) that can execute first instructions to perform one or more operations and / or functions, XPUs, network processing units (NPUs), one or more microcontrollers that can execute first instructions to perform one or more operations and / or functions,and / or integrated circuits such as application-specific integrated circuits (ASICs). For example, an XPU can be implemented by a heterogeneous computing system that incorporates several types of programmable circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and / or any combination thereof) and an orchestration technology (e.g., an application programming interface (API) that can assign a computational task to any of the several types of programmable circuitry that is suitable and available to perform the computational task).

[0107] As used here, an integrated circuit / circuit assembly is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit can be implemented as one or more ASICs, FPGAs, chips, microchips, programmable logic devices, semiconductor substrates coupling multiple circuit elements, systems-on-chips (SoCs), etc.

[0108] From the foregoing, it is understood that exemplary systems, devices, articles, and processes have been disclosed that enable the fabrication of deep-trench capacitors within substrate cores containing a stack of multiple disaggregated glass cores with different CTEs. The deep-trench capacitors of the exemplary substrate cores disclosed herein provide improved power delivery, energy storage, signal coupling, and filtering for such substrate cores. The different CTEs define a CTE gradient that reduces stress within housing substrates and, in particular, mitigates SeWaRe faults known to occur in substrates with a single solid glass core containing a single CTE.Consequently, the examples disclosed herein improve the yield loss in the manufacture of package substrates and also improve the reliability and / or service life of IC packages compared to known techniques.

[0109] Systems, equipment, manufacturing articles, and methods for stacking glass layers, including deep trench condensers, are disclosed. Further examples and combinations thereof include the following:

[0110] Example 1 includes a substrate comprising a first glass layer, a second glass layer coupled to the first glass layer, and a capacitor embedded in the first glass layer.

[0111] Example 2 includes the substrate of Example 1, wherein the first glass core has a first coefficient of thermal expansion and the second glass core has a second coefficient of thermal expansion that differs from the first coefficient of thermal expansion.

[0112] Example 3 includes the substrate of Example 1, which further includes an adhesive layer between the first glass layer and the second glass layer.

[0113] Example 4 includes the substrate of Example 1, which further includes a buffer layer between the first glass layer and the second glass layer.

[0114] Example 5 includes the substrate of Example 1, where the capacitor is a deep trench capacitor.

[0115] Example 6 includes the substrate of Example 5, wherein the deep trench capacitor is a first deep trench capacitor and further includes a second deep trench capacitor embedded in the second glass layer, wherein the first deep trench capacitor is electrically coupled to the second deep trench capacitor.

[0116] Example 7 includes the substrate of Example 1, which further includes a third glass layer, the second glass layer between the first glass layer and the third glass layer, a first layer between the second glass layer and the first glass layer, and a second layer between the third glass layer and the second glass layer.

[0117] Example 8 includes the substrate of Example 7, where the first layer is a buffer layer and the second layer is an adhesive layer.

[0118] Example 9 includes the substrate of Example 8, which further includes a second deep trench capacitor in the third glass layer.

[0119] Example 10 includes the substrate of Example 7, wherein the first glass layer, the second glass layer and the third glass layer have the same shape and thickness.

[0120] Example 11 includes an integrated circuit package comprising a first build area, a second build area and a core between the first and second build areas, the core comprising a stack of glass layers and a capacitor.

[0121] Example 12 includes the integrated circuit package of Example 11, wherein the glass layers comprise a first glass layer with a first coefficient of thermal expansion and a second glass layer with a second coefficient of thermal expansion that differs from the first coefficient of thermal expansion.

[0122] Example 13 includes the integrated circuit package of Example 12, wherein the glass layers further include a third glass layer, wherein the second glass layer is located between the first glass layer and the third glass layer, and wherein the third glass layer has the first coefficient of thermal expansion.

[0123] Example 14 includes the integrated circuit package from Example 11, where the capacitor is a deep trench capacitor.

[0124] Example 15 includes the integrated circuit package of Example 14, wherein the trench capacitor is a first trench capacitor and the core further includes a second trench capacitor, wherein the first trench capacitor is electrically coupled to the second trench capacitor.

[0125] Example 16 includes the integrated circuit package of Example 11, wherein the stack includes a first set of glass layers and the core further includes a second set of deep trench capacitors including the deep trench capacitor, wherein the second set is equal to or greater than the first set.

[0126] Example 17 includes the integrated circuit package of Example 11, wherein the core further includes an adhesive layer between a first of the glass layers and a second of the glass layers, and a buffer layer between the second of the glass layers and a third of the glass layers.

[0127] Example 18 includes a device comprising a semiconductor die, a housing substrate on the semiconductor die, wherein the housing substrate comprises a plurality of vertically arranged glass layers, and a capacitor enclosed in a glass layer of the stack of glass layers.

[0128] Example 19 includes the setup of Example 18, wherein the capacitor is a first deep trench capacitor and the setup further includes a second deep trench capacitor coupled to the first deep trench capacitor.

[0129] Example 20 includes the setup of Example 19, wherein the first deep trench capacitor is aligned with the second deep trench capacitor in a direction perpendicular to the glass layers in the stack.

[0130] The following claims are hereby incorporated into this detailed description by reference. Although certain exemplary systems, devices, articles, and processes have been disclosed herein, the scope of protection of this patent is not limited thereto. Rather, this patent covers all systems, devices, articles, and processes that ordinarily fall within the scope of protection of the claims of this patent.

Claims

[1] Substrate, comprising: a first layer of glass; a second glass layer that is coupled to the first glass layer; and a capacitor embedded in the first glass layer. [2] Substrate according to claim 1, wherein the first glass layer has a first coefficient of thermal expansion and the second glass layer has a second coefficient of thermal expansion which differs from the first coefficient of thermal expansion. [3] Substrate according to one of the preceding claims, further comprising an adhesive layer between the first glass layer and the second glass layer. [4] Substrate according to one of the preceding claims, further comprising a buffer layer between the first glass layer and the second glass layer. [5] Substrate according to any of the preceding claims, wherein the capacitor is a deep trench capacitor. [6] Substrate according to claim 5, wherein the deep trench capacitor is a first deep trench capacitor and further comprises a second deep trench capacitor embedded in the second glass layer, wherein the first deep trench capacitor is electrically coupled to the second deep trench capacitor. [7] Substrate according to any of the preceding claims, further comprising: a third glass layer, wherein the second glass layer is located between the first glass layer and the third glass layer, a first layer between the second glass layer and the first glass layer; and a second layer between the third glass layer and the second glass layer. [8] Substrate according to claim 7, wherein the first layer is a buffer layer and the second layer is an adhesive layer. [9] Substrate according to claim 8, further comprising a second deep trench capacitor in the third glass layer. [10] Substrate according to claim 7, 8 or 9, wherein the first glass layer, the second glass layer and the third glass layer have the same shape and thickness. [11] Integrated circuit housing comprising the substrate according to any one of claims 1-10. [12] Electronic device comprising the integrated circuit housing according to claim 11. [13] Integrated circuit package comprising: a first development area; a second development area; and a core between the first and second development areas, the core comprising the following: a stack of glass layers; and a capacitor. [14] Integrated circuit housing according to claim 13, wherein the glass layers comprise: a first glass layer with a first coefficient of thermal expansion; and a second glass layer with a second coefficient of thermal expansion that differs from the first coefficient of thermal expansion. [15] Integrated circuit housing according to claim 14, wherein the glass layers include a third glass layer, wherein the second glass layer is located between the first glass layer and the third glass layer; wherein the third glass layer has a first coefficient of thermal expansion. [16] Integrated circuit housing according to one of claims 13-15, wherein the capacitor is a deep trench capacitor. [17] Integrated circuit housing according to claim 16, wherein the trench capacitor is a first trench capacitor and the core further includes a second trench capacitor, wherein the first trench capacitor is electrically coupled to the second trench capacitor. [18] Integrated circuit housing according to one of claims 13-17, wherein the stack includes a first number of glass layers and the core further includes a second number of deep trench capacitors including the deep trench capacitor, wherein the second number is equal to or greater than the first number. [19] Integrated circuit package according to any one of claims 13-18, wherein the core further comprises: an adhesive layer between a first glass layer and a second glass layer; and a buffer layer between the second glass layer and a third glass layer. [20] Institution, comprehensive: a semiconductor die; a housing substrate on the semiconductor die, wherein the housing substrate comprises a plurality of vertically arranged glass layers; and a capacitor enclosed in a glass layer of vertically arranged glass layers. [21] Device according to claim 20, wherein the first capacitor is a first deep trench capacitor and the device further includes a second deep trench capacitor coupled to the first deep trench capacitor. [22] Device according to claim 21, wherein the first deep trench capacitor is aligned with the second deep trench capacitor in a direction perpendicular to the vertically arranged glass layers. [23] Device according to one of claims 20-22, wherein the plurality of vertically arranged glass layers comprises the following: a first glass layer with a first coefficient of thermal expansion; and a second glass layer with a second coefficient of thermal expansion that differs from the first coefficient of thermal expansion. [24] Device according to claim 23, further comprising an adhesive layer between the first glass layer and the second glass layer. [25] Integrated circuit housing comprising the device according to any one of claims 20-24.

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