CELL PROGRAMMING FOR DIGITAL-TO-ANALOGUE CONVERTERS

Abstract

An electronic device can include a digital-to-analog converter (DAC) containing programmable features in corresponding DAC unit cells. Programming data can be written to a corresponding unit cell using an address and a sample signal. If desired, a read marker and read data path can be provided to read data from the corresponding unit cell. The DAC can include an address decoding circuit arrangement, which is located at each unit cell and / or shared by multiple unit cells.

Description

[0001] This application claims priority over US patent application No. 18 / 897,739, filed on September 26, 2024, which is hereby incorporated herein by reference in its entirety. AREA

[0002] This disclosure relates generally to electronic devices, for example, electronic devices with digital-to-analog converters. BACKGROUND

[0003] Electronic devices are often provided with wireless communication capabilities. An electronic device with wireless communication capabilities includes a wireless communication circuit arrangement. The wireless communication circuit arrangement may include a digital-to-analog converter (DAC). It may be desirable to program the DAC to function appropriately when converting digital data to analog voltage(s). Programming the DAC can be challenging, especially when a large number of fine-grained features need to be programmed into the DAC. SUMMARY

[0004] An electronic device can include a digital-to-analog converter (DAC) that incorporates programmable features, such as configurable circuitry, in corresponding DAC unit cells. Programming data transmitted via a write data path can be written to a corresponding unit cell using an address and a sample signal. Optionally, a read marker and data read path can be provided to read data from the corresponding unit cell. The DAC can include an (address) decoding circuit arrangement that is present at each unit cell and / or shared by multiple unit cells.

[0005] One aspect of the disclosure provides a wireless communication circuit arrangement. The wireless communication circuit arrangement may include a digital-to-analog converter (DAC) having a plurality of unit cells, a programming circuit arrangement configured to program the plurality of unit cells, and a plurality of data paths coupled to the programming circuit arrangement and the DAC, including address data paths. The programming circuit arrangement may be configured to transmit address bits, via the address data paths and to the DAC, which together form an address that identifies a particular unit cell within the plurality of unit cells.

[0006] One aspect of the revelation provides a digital-to-analog converter. The digital-to-analog converter can include a plurality of unit cells. A particular unit cell within the plurality of unit cells can have a programmable feature and a storage circuit configured to store programming data for the programmable feature. The digital-to-analog converter can include a plurality of address data paths coupled to and configured with the plurality of unit cells to transmit an address for the respective unit cell, a sampling signal path coupled to and configured with the plurality of unit cells to transmit a sampling signal, and a write data path coupled to and configured with the plurality of unit cells to provide the programming data to the storage circuit based on the address and the sampling signal.

[0007] One aspect of the revelation provides a digital-to-analog converter. The digital-to-analog converter can include a plurality of unit cells, each comprising a configurable circuit, an input coupled to the plurality of unit cells and configured to receive digital data, an output coupled to the plurality of unit cells and configured to provide an analog voltage corresponding to the digital data using the plurality of unit cells, and a plurality of programming inputs coupled to the plurality of unit cells and configured to receive an address and programming data for controlling the configurable circuit of a unit cell identified by the address within the plurality of unit cells. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a representation of an illustrative electronic device comprising a wireless communication circuit arrangement according to some embodiments. Fig. Figure 2 is a representation of an illustrative wireless communication circuit arrangement according to some embodiments. Fig. Figure 3 is a representation of an illustrative digital-to-analog converter circuit arrangement according to some embodiments. Fig. Figure 4 is a representation of an illustrative programming circuit arrangement for a digital-to-analog converter according to some embodiments. Fig. Figure 5 is a diagram of a local address decoding circuit arrangement at a unit cell coupled to a digital-to-analog converter programming circuit arrangement for communication purposes, according to some embodiments. Fig. Figure 6 is a representation illustrating digital-to-analog converter cells that include a local address decoding circuit arrangement, according to some embodiments. Fig. Figure 7 is a representation illustrating digital-to-analog converter cells coupled to a shared address decoding circuit arrangement for communication purposes, according to some embodiments. Fig. Figure 8 is a representation of an illustrative shared address decoding circuit arrangement at a division between cells according to some embodiments. Fig. Figure 9 is a flowchart illustrating processes for performing shared and local address decoding for a digital-to-analog converter according to some embodiments. DETAILED DESCRIPTION

[0008] An electronic device may include one or more digital-to-analog converters (DACs). In illustrative configurations, sometimes described herein as examples, one or more DACs may be provided as part of a wireless communication circuit arrangement (e.g., configured as part of a transmitter circuit arrangement that interfaces between a digital baseband circuit arrangement and an analog high-frequency circuit arrangement). To enable the desired conversion operations, a DAC may include one or more features that must be programmed into each unit cell. Given the large number of cells and the corresponding features to be programmed, it can be challenging to run the same large number of lines to each unit cell to provide programming data for the feature(s) in each unit cell.

[0009] To facilitate the programming of these unit cells (e.g., the features they contain), the DAC programming circuitry can transmit programming data, along with a corresponding address and a sampling signal, to the DAC. If desired, the DAC can also provide a read marker and a corresponding read path (for reading data from a unit cell). The transmitted information (including the programming data, the address, the sampling signal, and the read marker) can be processed by the DAC so that, during a write operation, the programming data is written to the appropriate cell(s) (e.g., specified by the address) for the corresponding feature(s), and / or, during a read operation, the corresponding data is read from the appropriate cell (e.g., specified by the address).The DAC can include an address decoding circuit arrangement locally at each unit cell and / or a shared address decoding circuit arrangement at divisions between multiple cells (which, for example, branch to them). An illustrative electronic device in which a DAC circuit arrangement (e.g., the DAC and the programming circuit arrangement configured in the illustrative manner described above) can be used is shown in [reference]. Fig. 1 shown.

[0010] Fig. Figure 1 is a representation of an illustrative electronic device, such as electronic device 10. Electronic device 10 may be a data processing device, such as a laptop computer, a desktop computer, a computer monitor containing an embedded computer, a tablet computer, a mobile phone, a media playback device, or any other handheld or portable electronic device; a smaller device, such as a wristwatch device, a pendant device, a headphone or earphone device, a device embedded in eyeglasses or other equipment worn on a user's head, or any other wearable or miniature device; a television set; a computer display not containing an embedded computer; a gaming device; a navigation device; an embedded system, such as a systemin which electronic equipment with a display is mounted in a kiosk system or automobile, a wirelessly connected internet voice-controlled speaker, a home entertainment device, a remote control device, a game control unit, a peripheral user input device, a wireless base station or access point, equipment implementing the functionality of two or more of these devices, or other electronic equipment.

[0011] As shown in the schematic representation of Fig. As shown in Figure 1, the device 10 can include components located on or within the housing of an electronic device, such as the housing 12. The housing 12, which may sometimes be referred to as an enclosure, can be made of plastic, glass, ceramic, fiber composites, metal (e.g., stainless steel, aluminum, metal alloys, etc.), other suitable materials, or a combination of these materials. In some situations, parts or all of the housing 12 may be made of dielectric or other low-conductivity materials (e.g., glass, ceramic, plastic, sapphire, etc.). In some situations, the housing 12, or at least some of the structures comprising the housing 12, may be made of metal elements.

[0012] The device 10 may include a control circuit arrangement 14. The control circuit arrangement 14 may include storage, such as a storage circuit arrangement 16. The storage circuit arrangement 16 may include hard disk drive storage, non-volatile memory (e.g., flash memory or other electrically programmable read-only memory configured to form a solid-state drive), volatile memory (e.g., static or dynamic random-access memory), etc. The storage circuit arrangement 16 may include data storage integrated into the device 10 and / or removable storage media.

[0013] The control circuit arrangement 14 can include a processing circuit arrangement such as the processing circuit arrangement 18 (e.g., one or more processors 18). The processing circuit arrangement 18 can be used to control the operation of the device 10. The processing circuit arrangement 18 can include one or more microprocessors, microcontrollers, digital signal processors, host processors, integrated baseband processor circuits, application processors, application-specific integrated circuits, central processing units (CPUs), general-purpose processors, or other types of processors. The control circuit arrangement 14 can be configured to perform operations in the device 10 using hardware (e.g., dedicated hardware or circuit arrangement), firmware, and / or software. Software code for performing operations in the device 10 can be stored on the storage circuit arrangement 16 (e.g.,The storage circuit arrangement 16 can include non-transient (tangible) computer-readable storage media that store the software code. The software code can sometimes be referred to as program instructions, software, data, instructions, or code. Software code stored on the storage circuit arrangement 16 can be executed by the processing circuit arrangement 18.

[0014] The control circuit arrangement 14 can be used to run software on the device 10, such as satellite navigation applications, internet browsing applications, voice-over-internet protocol (VoIP) telephone calling applications, email applications, media playback applications, operating system functions, etc. To support interactions with external devices, the control circuit arrangement 14 can be used to implement communication protocols. Communication protocols that can be implemented using the control circuit arrangement 14 include internet protocols, wireless local area network (WLAN) protocols (e.g., IEEE 802.11 protocols—sometimes referred to as Wi-Fi®), protocols for other short-range wireless communication links such as the Bluetooth® protocol or other wireless personal area network (WPAN) protocols, IEEE 802.11ad protocols (e.g., Bluetooth).Ultra-wideband protocols), mobile phone protocols (e.g., 3G protocols, 4G protocols (LTE protocols), 5G New Radio (NR) protocols, etc.), MIMO protocols, antenna diversity protocols, satellite navigation system protocols (e.g., Global Positioning System protocols (GPS protocols), Global Navigation Satellite System protocols (GLONASS protocols), etc.), antenna-based spatial rangefinding protocols (e.g., Radio Detection and Ranging protocols (RADAR protocols) or other desired rangefinding protocols for signals transmitted at millimeter and centimeter wave frequencies), or any other desired communication protocols. Each communication protocol can be associated with a corresponding Radio Access Technology (RAT), which specifies a physical linking methodology used in implementing the protocol.

[0015] The device 10 can include an input / output circuit arrangement 20. The input / output circuit arrangement 20 can include input / output devices 22. Input / output devices 22 can be used to allow data to be supplied to the device 10 and to allow data from the device 10 to be provided to external devices. The input / output devices 22 can include user interface devices, data port devices, and other input / output components. For example, the input / output devices 22 can include touch sensors, displays, light-emitting components such as displays without touch sensor capabilities, buttons (mechanical, capacitive, optical, etc.).), scroll wheels, touchpads, keypads, keyboards, microphones, cameras, buttons, speakers, status indicators, audio jacks and other audio port components, digital data port devices, motion sensors (accelerometers, gyroscopes, and / or compasses that detect movement), capacitance sensors, proximity sensors, magnetometers, force sensors (e.g., force sensors coupled with a display to detect pressure applied to the display), etc. In some configurations, keyboards, headphones, displays, pointing devices such as trackpads, mice, electronic pens (e.g., styluses) and joysticks, and other input / output devices may be paired with Device 10 using wired or wireless connections (e.g.,Some of the input / output devices may be peripheral devices that are coupled to a main processing unit or other section of the device 10 via a wired or wireless connection).

[0016] The input / output circuit arrangement 20 can include a wireless communication circuit arrangement such as the wireless communication circuit arrangement 24 (hereafter sometimes referred to as wireless circuit arrangement 24) for wirelessly transmitting radio frequency signals. Fig. Figure 2 is a representation showing illustrative components within the wireless circuit arrangement 24. As in Fig. As shown in Figure 2, the wireless circuit arrangement 24 can include one or more processors, such as a processor 26, a high-frequency transceiver circuit arrangement (HF transceiver circuit arrangement), such as the high-frequency transceiver circuit arrangement 28, a high-frequency front-end circuit arrangement, such as the high-frequency front-end circuit arrangement 40 (which, when integrated, may sometimes be referred to as the front-end module 40), and one or more antennas, such as the antenna(s) 42. The processor 26 can be a baseband processor, an application processor, a general-purpose processor, a microprocessor, a microcontroller, a digital signal processor, a host processor, or another type of processor. If desired, the processor 26 can be implemented as part of the control circuit arrangement 14. The processor 26 can be coupled to the transceiver circuit arrangement 28 via path 34 for communication purposes.The transceiver 28 can be coupled to one or more antennas 42 via one or more high-frequency transmission line paths 36 for communication purposes. The high-frequency front-end circuit arrangement 40 can be arranged along the high-frequency transmission line path(s) 36 (e.g., on them) between the transceiver circuit arrangement 28 and the antenna(s) 42.

[0017] In the example of Fig. For clarity, the wireless circuit arrangement 24 is illustrated as including a single processor 26, a single instance of the transceiver circuit arrangement 28, a single instance of the front-end circuit arrangement 40, and a single set of one or more antennas 42. In general, the wireless circuit arrangement 24 can include any number of processors 26, any number of instances of the transceiver circuit arrangement 28, any number of instances of the front-end circuit arrangement 40, and any number of sets of one or more antennas 42. Each processor 26 can be coupled to one or more transceivers (e.g., instances of the transceiver circuit arrangement 28) via respective paths 34 for communication purposes.Each transceiver 28 can include a transmitter circuit 30 configured to output uplink signals to the antenna(s) 42, can include a receiver circuit 32 configured to receive downlink signals from the antenna(s) 42, and can be coupled to one or more antennas 42 via respective high-frequency transmission line paths 36 for communication purposes. Each high-frequency transmission line path 36 can have a respective front-end circuit arrangement 40 mounted on it. If desired, two or more instances of (different types of) front-end circuit arrangements 40 can be arranged on the same high-frequency transmission line path 36. If desired, one or more of the high-frequency transmission line paths 36 can be implemented in the wireless circuit arrangement 24 without a front-end circuit arrangement 40 mounted on it.

[0018] The antenna(s) 42 can be formed using any desired antenna structures. For example, each antenna 42 can be an antenna with an antenna resonant element formed from loop antenna structures, patch antenna structures, inverted F-antenna structures, slotted antenna structures, planar inverted F-antenna structures, helical antenna structures, monopole antennas, dipole antennas, hybrids of these designs, etc. Two or more antennas 42 can be arranged in one or more phased antenna arrays (e.g., for transmitting high-frequency signals at millimeter-wave frequencies). Parasitic elements can be included in the antenna 42 to adjust the antenna power. The antenna 42 can be provided with a conductive cavity that supports the antenna resonance element of the antenna 42 (e.g.Antenna 42 can be a cavity-supported antenna, such as a cavity-supported slotted antenna.

[0019] Each high-frequency transmission line path 36 can be coupled to an antenna feed at the antenna 42 for communication purposes. The antenna feed can, for example, include a positive antenna feed terminal and a ground antenna feed terminal. The high-frequency transmission line path 36 can have a positive transmission line signal path that is coupled to the positive antenna feed terminal at the antenna 42 for communication purposes. The high-frequency transmission line path 36 can have a ground transmission line signal path that is coupled to the ground antenna feed terminal at the antenna 42 for communication purposes. This example is for illustrative purposes only, and in general, antennas 42 can be fed using any desired antenna feed scheme.If desired, the antenna 42 can have multiple antenna feeds which are coupled to one or more high-frequency transmission line paths 36 for communication purposes.

[0020] The high-frequency transmission line path 36 can include transmission lines used to carry high-frequency signals within the device 10 ( Fig. 1) These transmission lines can include coaxial cables, microstrip transmission lines, stripline transmission lines, flank-locked microstrip transmission lines, flank-locked stripline transmission lines, transmission lines formed from combinations of these types of transmission lines, etc. If desired, transmission lines in high-frequency transmission line paths 36 can be integrated into rigid printed circuit boards and / or flexible printed circuit board substrates.

[0021] When performing a wireless signal transmission, the processor(s) 26 (e.g., digital signals or baseband signals) can provide transmit signals to the transceiver circuit arrangement 28 via path 34. The transceiver circuit arrangement 28 can further include a circuit arrangement for converting the (baseband) transmit signals received by the processor 26 into corresponding high-frequency signals. For example, the transceiver circuit arrangement 28 can include a mixer circuit arrangement for stepping up (or modulating) the (baseband) transmit signals to high frequencies before transmission via the antenna 42. The example of Fig. Figure 2, in which the processor 26 communicates with the transceiver circuit arrangement 28, is for illustrative purposes only. In general, the transceiver circuit arrangement 28 can communicate with a baseband processor, an application processor, a general-purpose processor, a microcontroller, a microprocessor, or one or more processors within the circuit arrangement 18 (which, for example, implements the functions of the processor 26). The transceiver circuit arrangement 28 can also include digital-to-analog converter (DAC) circuit arrangements and / or analog-to-digital converter (ADC) circuit arrangements for converting signals between digital and analog domains. The transceiver circuit arrangement 28 can use a transmitter (TX) 30 to transmit the high-frequency signals via the antenna(s) 42 through the high-frequency transmission line path 36 and the front-end circuit arrangement 40.The antenna(s) 42 can / can send the high-frequency signals to external wireless equipment by transmitting / emitting the high-frequency signals into free space.

[0022] When performing wireless reception, the antennas 42 can receive radio frequency signals from the external wireless equipment. The received radio frequency signals can be transmitted to the transceiver circuit arrangement 28 via the radio frequency transmission line path 36 and the front-end circuit arrangement 40. The transceiver circuit arrangement 28 can include a circuit arrangement such as a receiver (RX) 32 for receiving signals from the front-end circuit arrangement 40 and for converting the received radio frequency signals into appropriate baseband signals. For example, the transceiver circuit arrangement 28 can use a mixer circuit arrangement to down-convert (or demodulate) the received radio frequency signals to baseband frequencies before the received signals are transmitted via path 34 to the processor 26 (or the control circuit arrangement 18, which implements the function of the processor 26).

[0023] The high-frequency front-end circuit arrangement 40 can process the high-frequency signals transmitted (sent and / or received) via the high-frequency transmission line path 36. The front-end circuit arrangement 40 can, for example, include components of the front-end module (FEM), such as a high-frequency filter circuit arrangement 44 (e.g., low-pass filter, high-pass filter, notch filter, band-pass filter, multiplexer circuit arrangements, duplexer circuit arrangements, diplexer circuit arrangements, triplexer circuit arrangements, etc.), switching circuit arrangements 46 (e.g., one or more high-frequency switches), high-frequency amplifier circuit arrangements 48 (e.g., one or more power amplifier circuits and / or one or more low-noise amplifier circuits), impedance matching circuit arrangements (e.g.,a circuit arrangement that helps to match the impedance of the antenna 42 to the impedance of the high-frequency transmission line 36), antenna tuning circuit arrangements (e.g., networks of capacitors, resistors, inductors, and / or switches that adjust the frequency response of the antenna 42), high-frequency coupler circuit arrangements, charge pump circuit arrangements, power supply management circuit arrangements, digital control and interface circuit arrangements, and / or any other desired circuit arrangement that processes the high-frequency signals transmitted and / or received by the antenna 42. Each of the front-end module components can be mounted on a common (shared) substrate, such as a rigid printed circuit board substrate or a flexible printed circuit board substrate. If desired, the various front-end module components can also be integrated into a single integrated circuit chip.

[0024] The filter circuit arrangement 44, the switching circuit arrangement 46, the amplifier circuit arrangement 48, and other circuit arrangements can be arranged along the high-frequency transmission line path 36 (e.g., on it), can be integrated into a front-end module, and / or can be incorporated into the antenna 42 (e.g., to support antenna tuning, to support operation in desired frequency bands, etc.). At least some of these components can form antenna tuning components that are adjusted (e.g., using the control circuit arrangement 14) to adapt the frequency response and wireless operating characteristics of the antenna 42 over time.

[0025] While the control circuit arrangement 14 in the example consists of Fig. For clarity, the wireless circuit arrangement 24 is shown separately from the wireless circuit arrangement 24. The wireless circuit arrangement 24 can include a processing circuit arrangement that forms part of the processing circuit arrangement 18, and / or a storage circuit arrangement that forms part of the storage circuit arrangement 16 of the control circuit arrangement 14 (e.g., sections of the control circuit arrangement 14 can be implemented on the wireless circuit arrangement 24). As an example, the processor 26 and / or sections of the transceiver circuit arrangement 28 (e.g., a host processor on the transceiver circuit arrangement 28) can form part of the control circuit arrangement 14. The control circuit arrangement 14 (e.g.,Sections of the control circuit arrangement 14 formed on the processor 26, sections of the control circuit arrangement 14 formed on the transceiver 28, and / or sections of the control circuit arrangement 14 that are separate from the wireless circuit arrangement 24) can provide control signals (e.g. via one or more control paths in the device 10) that control the operation of the front-end control circuit arrangement 40.

[0026] The transceiver circuit arrangement 28 can be separate from the front-end circuit arrangement 40. For example, the transceiver circuit arrangement 28 can be formed on a different substrate, such as the main logic board of the device 10, a rigid printed circuit board, or a flexible printed circuit, than the one on which the front-end control circuit arrangement 40 is provided.

[0027] The high-frequency transceiver circuit arrangement 28 (and other sections of the wireless circuit arrangement 24, such as the front-end circuit arrangement 40) can handle the transmission and / or reception of high-frequency signals in various high-frequency communication bands. For example, the high-frequency transceiver circuit arrangement 28 (and other sections of the wireless circuit arrangement 24, such as the front-end circuit arrangement 40) can transmit high-frequency signals in communication bands of local area wireless networks (WLAN communication bands) such as the 2.4 GHz and 5 GHz Wi-Fi® bands (IEEE 802.11), WPAN communication bands such as the 2.4 GHz Bluetooth® communication band, cellular communication bands such as a cellular low band (LB) (e.g., 600 to 960 MHz), a cellular low mid band (LMB) (e.g., 1400 to 1550 MHz), a cellular mid band (MB) (e.g., 1700 to 2200 MHz), a cellular high band (HB) (e.g.,from 2300 to 2700 MHz), a mobile communications ultra-high band (UHB) (e.g., from 3300 to 5000 MHz) or other mobile communications bands between approximately 600 MHz and approximately 5000 MHz (e.g., 3G bands, 4G LTE bands, 5G New Radio Frequency Range 1 bands (FR1 bands) below 10 GHz, 5G New Radio Frequency Range 2 bands (FR2 bands) on millimeter and centimeter wavelengths between 20 and 60 GHz, etc.), a near-field communication band (NFC band) (e.g., at 13.56 MHz), satellite navigation bands (e.g., an L1 GPS band (GPS = Global Positioning System) at 1575 MHz, an L5 GPS band at 1176 MHz, a GLONASS band (GLONASS = Global Navigation Satellite System), a BeiDou Navigation Satellite System band (BDS band, etc.), an ultra-wideband communication band (UWB communication band, UWB = ultra-wideband) supported by the IEEE 802.15.4 protocol and / or other UWB communication protocols (e.g.a first UWB communication band at 6.5 GHz and / or a second UWB communication band at 8.0 GHz), and / or any other desired communication bands. The communication bands processed (e.g., covered) by the high-frequency transceiver circuit arrangement 28 (and other sections of the wireless circuit arrangement 24, such as the front-end circuit arrangement 40) may sometimes be referred to herein as frequency bands or simply as "bands" and may span corresponding ranges of frequencies.

[0028] The electronic device 10 ( Fig. 1) can include a first circuit arrangement operating in a digital domain and a second circuit arrangement operating in an analog domain. To form an interface between the first and second circuits, or more precisely, to perform operations in the analog domain based on operations in the digital domain, the electronic device 10 can include one or more digital-to-analog converters (DACs). An illustrative DAC circuit arrangement including a DAC 50 is shown in Fig. Figure 3 shows that the DAC 50 can include a DIN input configured to receive digital data (e.g., from digital circuitry) containing any number of bits whose values ​​together specify a corresponding digital data value. The DAC 50 can convert the received digital data value into a corresponding analog voltage value, which is provided at the DOUT output of the DAC 50 (e.g., to the analog circuitry). The analog voltage values ​​can be reference voltage levels corresponding to different digital input data values ​​specified by different combinations of digital data bit values.

[0029] The conversion process performed by the DAC 50 can utilize a cell array 52 containing any suitable number of unit cells 54 (sometimes referred to as cells 54). Each unit cell 54 can include a combination of circuit elements such as one or more resistors, capacitors, inductors, transistors (e.g., switches), and / or combinational logic circuits (e.g., logic gates). In some illustrative configurations sometimes described herein as examples, the DAC 50 can be a capacitive DAC, and each unit cell 54 can include one or more capacitors (e.g., combinations thereof forming one or more capacitor banks). Based on the configuration of its circuit elements, each unit cell 54 can, based on the digital data value (e.g.,one or more bits of the digital data value) generate a voltage (or current) which, together with one or more other unit cells 54, provides or otherwise causes the final analog voltage value that is provided at the DOUT output.

[0030] In some of the illustrative configurations described herein as examples, the DAC circuit arrangement may differ from Fig. 3 including the DAC 50 as part of the wireless communication circuit arrangement 24 in Fig. 2. For example, the high-frequency transceiver circuit arrangement 28, or more precisely the transmitter 30, can include the DAC 50. In particular, the DAC 50 can be located between the (digital baseband) processor(s) 26 and the corresponding analog high-frequency processing stages (e.g., filtering, switching, amplification stages) in the transmitter 30 and in the front-end circuit arrangement 40. In other words, the DIN input of the DAC 50 can be coupled to the digital baseband sections of the processor(s) 26 for communication purposes, and the VOUT output of the DAC 50 can be coupled to the analog signal processing sections of the transmitter 30 and / or the front-end circuit arrangement 40 for communication purposes. If desired, the DAC 50 can be located elsewhere in the wireless circuit arrangement 24 to provide digital-to-analog conversion functions.If desired, the DAC 50 can be provided at another location in the device 10 (e.g. outside the wireless circuit arrangement 24).

[0031] To provide and / or improve the conversion functionality of the DAC 50, each unit cell 54 can include one or more circuit features 56 (sometimes referred to as circuit(s) 56), each of which is programmable (e.g., configurable between different states depending on the stored programming data). The differently programmed circuits 56 can provide different properties for the conversion functionality of the DAC 50 (e.g., cause the DAC 50 to convert the same digital data value at the DIN input into (slightly) different analog voltage values). In this way, a set of programmed states can be used to improve the conversion functionality of the DAC 50 (e.g., by providing a more accurate analog voltage value for a digital input data value).

[0032] For example, the circuit features 56 for a given cell 54 may include one or more configurable circuits that enable or disable the entire cell, that enable or disable one or more sections or a specific circuit element or elements of the cell, that adjust the properties of circuit elements in the cell (e.g., adjust the resistance value of a resistor, adjust the capacitance of a capacitor, adjust the inductance value of an inductor, adjust a bias voltage or bias current of a transistor, etc.), and / or that generally connect or disconnect paths within the cell. As an example, illustrative configurations are sometimes described herein in which these configurable circuits each connect to a corresponding control input (e.g.,a control bit) are instructed to switch the configurable circuit between two or more states (e.g., between enabled and disabled states, between connected and disconnected states, between multiple states corresponding to values ​​for corresponding properties, etc.). These control bits for controlling the states of configurable circuits 56 (features 56) are sometimes referred to herein as programming bits. Each cell 54 can store programming bits (e.g., a bit value for a corresponding programming bit) that program (e.g., control, cause, etc.) the corresponding configurable circuits 56, so that each exhibits a specific (programmed) state.

[0033] In some cases, a DAC can be configured for all features in all cells to receive a programming bit via a dedicated guide path (e.g., from an external programming circuit arrangement to the corresponding cell). However, as the number of cells and / or programmable features within each cell in the DAC increases, so does the number of guide paths required to route the programming bits to each cell. For example, in a scenario where the DAC includes 256 cells, each with one programmable feature, 256 guide paths are provided to route the programming data to each of the 256 cells. Allocating such a large area to provide all these guide paths can be impractical and undesirable. This therefore limits the number of cells and / or features that can be implemented in the DAC, undesirably restricting its functionality.

[0034] To overcome these limitations and / or achieve other advantages (e.g., providing a scalable programmable DAC architecture), the DAC circuit design of Fig. 3. A programming circuit arrangement 58 (sometimes referred to as a programming interface circuit arrangement 58 or DAC programming circuit arrangement 58) is provided with a programming circuit arrangement 58, which is coupled to the DAC 50 for communication purposes (e.g., at corresponding programming inputs and / or programming outputs of the DAC 50). Instead of being coupled to each cell 54 of the DAC 50 via at least one programming data path, thereby requiring a large number of programming data paths (each for a specific cell), the programming circuit arrangement 58 can be coupled to the cell array 52 for communication purposes via paths for programming (writing) data, for an address, for a sample signal, for a read marker, and for reading data. Corresponding programming inputs and / or outputs of the DAC 50 can be coupled externally to the programming circuit arrangement 58 and / or internally to the cell array 53 via these paths.The number of programming / write data paths can correspond to a number of features (e.g., greater than or equal to) implemented on a particular cell 54 (e.g., the cell(s) 54 that have the largest number of features in the cell array 52). The number of address data paths for transmitting address bits can correspond to a number of bits (e.g., greater than or equal to) required to uniquely address each cell 54 in the array 52. ​​The sample signal path and the read marker path can each be a one-bit path. Any suitable number of read data paths (e.g., one or more) can be provided to access desired data (e.g., programmed data and / or other data) in the given cell 54.

[0035] Fig. Figure 4 is a representation of an illustrative DAC programming circuit arrangement (e.g., for implementing the programming circuit arrangement 58 in Fig. 3 usable). In the example of Fig. 4. The programming circuit arrangement 58 can include a data storage circuit arrangement that implements a lookup table 60 (e.g., stores entries for it). The lookup table 60 can include entries such as 62-1, 62-2, 62-3, etc., each containing programming data and an address associated with the programming data (e.g., for programming the features of the cell 54 identified by the address). The multiplexing circuit arrangement 64 (sometimes called the multiplexer 64), which is coupled to the data storage circuit arrangement (which provides the table 60) for communication purposes, can select the corresponding entry 62 (e.g., entry 62-1) for transmission based on its control input, which is coupled to path 65 for communication purposes. The multiplexing circuit arrangement 64 can transmit the programming data (e.g.,DATA1) in entry 62 is transferred via one or more (programming data) paths 70 so that write data (WDATA) can be written to the corresponding cell, and the address (bits) (e.g., ADDR1) can be transferred via address data paths 72. When the data on path 70 and the data on path 72 are stable, the programming circuit arrangement 58 can transfer an (activated) sampling signal along the sampling signal path 74 so that the corresponding cell (e.g., the one specified based on the address data on path 72) can temporarily store the transferred data on path 70.

[0036] Path 74 can be coupled to one or more signal memories 66 for communication purposes and provide the activated sampling signal to the signal memory(s) 66 to increment the output value using an incrementing circuit 68, which is coupled for communication purposes between output Q and input D of the signal memory(s) 66. Accordingly, the output Q of the signal memory(s) 66 coupled to path 65 for communication purposes can subsequently provide an incremented value to the control element of the multiplex circuit arrangement 64, allowing the contents of the next entry 62 (e.g., programming data DATA2 and address ADDR2 of entry 62-2) to be transmitted via paths 70 and 72 (together with the next activated sampling signal on path 74). In this way, programming data in each entry 62 can be iteratively programmed into the cell corresponding to the address in the respective entry 62.

[0037] To facilitate cell reading operations, the programming circuit arrangement 58 can additionally provide a read marker (e.g., a read bit) along data path 76 and read data path 78, from which read data can be obtained. Specifically, if the address for the cell to be read is provided on path 72 and the read marker is set on path 76, the data from the corresponding cell can be accessed on read data path 78. Accordingly, the programming circuit arrangement 58 can store the data read from path 78 and / or otherwise utilize the data read from path 78. The read data can include any suitable (digital) data configured for access from the cell (e.g., stored programming data).

[0038] The programming circuit arrangement 58 can provide multiple write data paths 70 (e.g., for simultaneously providing multiple programming bits for the same feature or for different features in the addressed cell). Similarly, the programming circuit arrangement 58 can provide multiple read data paths 80 (e.g., for simultaneously reading multiple bits from the addressed cell).

[0039] The use of lookup table 60 and the process of iteratively writing programming data to cells based on the entries 62 in lookup table 60, as described above, are for illustrative purposes only. If desired, the DAC programming circuit arrangement 58 can obtain programming data and an address for the cell to be programmed in any suitable way (e.g., from the control circuit arrangement 14 in Fig. 1 as instructions from the processing circuit arrangement 18 and / or by accessing programming data stored in the storage circuit arrangement 16, from processors 26 as instructions based on the operations of the wireless circuit arrangement 24, etc.).

[0040] In some illustrative configurations, each of the paths 70, 72, 74, and 76 can be coupled to each cell 54 of the array 52 for communication purposes (e.g., via outputs and / or inputs of the programming circuit arrangement 58 and via programming inputs and / or programming outputs of the DAC 50). Based on the address decoding on the paths 72 during a write operation, only the corresponding (addressed) cells 54 can store (e.g., buffer) the write data on the paths 70 when the sampling signal is enabled. The stored write data (e.g., programming data) can be used to control the configurable circuits 56 by setting them to the appropriate states. Based on the address decoding on the paths 72 during a read operation, only the corresponding (addressed) cell 54 can provide the read data on the paths 78.

[0041] Fig. Figure 5 is a representation of an illustrative address decoding circuit arrangement, such as address decoding circuit arrangement 80, which is implemented in cell 54 of array 52 (e.g., a corresponding instance of it is implemented in each cell 54 of array 52). Because address decoding circuit arrangement 80 is implemented in cell 54, decoding circuit arrangement 80 may sometimes be referred to as a local decoding circuit or local address decoding circuit.

[0042] The decoding circuit arrangement 80 can determine whether the cell 54 in which it is located is the cell addressed (e.g., specified) by the address on the address data paths 72. In particular, the decoding circuit arrangement 80 can include a comparator circuit 82. The circuit 82 can receive the address on the paths 72 at a first input and compare the address with the local mask (e.g., the locally stored address of the cell in which the circuit arrangement 80 is located) received at a second input. Based on the comparison, the circuit 82 can provide a first binary value (e.g., "1") at its output if the received address matches the local address (mask), and a second binary value (e.g., "0") if there is no match.

[0043] An AND logic gate 84 of the circuit arrangement 80 can have a first input, which is coupled to the output of the circuit 82 for communication purposes, and a second input, which is coupled to the sampling signal path 74 for communication purposes. Based on the activation of the sampling signal on path 74 and based on the circuit 82 matching the received address on path 72 with the local address (and providing the first binary value as output), the output of the AND logic gate 84 can provide a first binary value (e.g., "1") and therefore a rising edge to the clock input of the signal memory 86. Accordingly, based on the output of the logic gate 84, write data WDATA can be buffered (e.g., stored) on path 70, which is coupled to the input D of the signal memory 86 for communication purposes, and made available at output Q.

[0044] Stored data WDATA (e.g., programming data) can be used to control the state of cell 54 (e.g., the state of a configurable circuit 56 in cell 54). In other words, a data storage circuit arrangement (e.g., the signal memory 86) that stores the programming data can be used for communication purposes with a configurable circuit 56 ( Fig. 3) be coupled to program the configurable circuit 56 using the stored programming data (which is provided, for example, as control input for the configurable circuit 56). If desired, write data (e.g., programming data) can be stored on multiple data paths 70 by appropriate data storage circuit arrangements (e.g., a plurality of signal memories, a register, other data storage circuit arrangements, etc.) based on the (clock) output signal of the AND logic gate 84. The appropriate data storage circuit arrangements can be coupled to different configurable circuits 56 to program the configurable circuits 56 using the different parts of stored programming data (which is provided, for example, as control input for the configurable circuits 56).

[0045] For a read operation, an AND logic gate 88 of the circuit arrangement 80 can have a first input, which is coupled to the output of the circuit 82 for communication purposes, and a second input, which is coupled to the read marker data path 76 for communication purposes. Based on the set (activated) read marker on path 76 and based on the circuit 82 matching the received address on path 72 with the local address (and providing the first binary value as output), the output of the AND logic gate 88 can provide a first binary value (logic high) (e.g., "1") to a tri-state buffer 90. When the cell is set to the logic high state, read data from cell 54 can be forwarded to the read data path 78 for output (e.g., to the programming circuit arrangement 58). The use of the tri-state buffer 90 (e.g.,(If buffer 90 is set to a high-impedance state when the cell is not addressed) allows reading other cells using the same path 78 (e.g., by setting the other tri-state buffers to the high-impedance state).

[0046] An illustrative section 52-1 of unit cells in the array 52 is shown in Fig. 6 shown. Configurations where cells in the array 52 are provided in a fractal arrangement are sometimes described herein as illustrative examples (e.g., in connection with Fig. 6 and Fig. 7) However, if desired, the cells in the array 52 can also be provided in a matrix cell arrangement or other suitable arrangements, and the embodiments described herein (e.g. in connection with Fig. 3 to 9) can be applied similarly to these arrangements.

[0047] In the example of Fig. 6. Each unit cell in section 52-1 may have a local address decoding circuit arrangement, such as the circuit arrangement 80 in Fig. 5. The programming circuit arrangement 58 ( Fig. 4) can provide a set of data paths 92 (e.g. including write data paths 70, address data paths 72, sample signal path 74, read marker data path 76 and read data paths 78) to one or more unit cells 54-1, one or more unit cells 54-2, one or more unit cells 54-3 and one or more unit cells 54-4 in section 52-1.

[0048] In particular, when paths 92 are routed to section 52-1 of the unit cells (e.g., enter this section), paths 92 can have a width of M bits (e.g., be an M-bit wide set of paths or an M-bit data bus). Even when distributed to each of the unit cells 54-1, 54-2, 54-3, and 54-4 (e.g., when routed to or entering them), the widths of the paths 92 can remain the same. Furthermore, each set of unit cells 54-1 can represent multiple unit cells within it, and paths 92 having a bit width M can be further distributed to each unit cell in the set of unit cells 54-1. Accordingly, if required, using this guidance scheme, the same set of data paths 92, which have the same width, can run between the programming circuit arrangement 58 and each unit cell 54-1 in section 52-1 and couple them for communication purposes.In an illustrative configuration, where the in . Fig. Section 52-1 shown in Figure 6 represents the entirety of the array 52. ​​The same set of data paths 92, which have the same bit width M, can run between the programming circuit arrangement 58 and each unit cell 54 in the array 52 and couple them for communication purposes.

[0049] Using this guidance scheme, the local address decoding circuit arrangement of each unit cell 54 in Section 52-1 can be configured to receive and process the set of data paths 92, or more precisely, to receive and decodecode the entirety (e.g., all bits) of the address in the address data paths of the data paths 92. As described in the context of Fig. As described in section 5, the comparator circuit 82 can receive all bits of the address (e.g. provided by the programming circuit arrangement 58) on corresponding address data paths 72, and the local mask (e.g. the stored local address) can have the same number of bits as the address.

[0050] While providing guide paths for write data (e.g., programming data) of a sample signal and address (and, if desired, for a read marker and read data) can reduce the number of guide paths required (compared to providing individual programming paths to each cell of the array), it may be desirable to further reduce the number of guide paths, e.g., at least for guiding to a section of the cells. Fig. Figure 7 is a representation of an illustrative section 52-2 of unit cells in the array 52, which has a shared address decoding circuit arrangement that can reduce the number of lower-level guide paths (e.g., branches of guide paths that are farther from the original set of incoming guide paths 94). For example, Fig. 7. A section of the address decoding can be performed in a shared address decoding circuit arrangement (e.g., address decoding circuit arrangement 96, 100, and 100, which is coupled to paths 94 for communication purposes) before all paths 94 each unit cell in the Fig. 7, section 52-2 shown.

[0051] In particular, the programming circuit arrangement 58 ( Fig. 4) provide a set of data paths 94 (e.g., including write data paths 70, address data paths 72, sample signal path 74, read marker data path 76, and read data paths 78) to one or more unit cells 54-5, one or more unit cells 54-6, one or more unit cells 54-7, and one or more unit cells 54-8 in section 52-2. When paths 94 are routed to section 52-2 of the unit cells (e.g., enter this section), paths 94 may have a width of N bits (e.g., be an N-bit wide set of paths or an N-bit data bus).

[0052] After paths 94 have been routed to section 52-2 of the unit cells, they can first be received by the address decoding circuit arrangement 96. In other words, paths 94 can be coupled to the decoding circuit arrangement 96 for communication purposes. The address decoding circuit arrangement 96 can process (e.g., resolve, decode, etc.) a first bit (e.g., the most significant bit) of the address data bits on the address data paths 72 in the paths 94. In particular, the decoding circuit arrangement 96 can determine, based on the most significant bit of the address, whether the addressed cell is on the left side of array section 52-2 (e.g., a cell in the set of cells 54-5 or in the set of cells 54-7) or on the right side of array section 52-2 (e.g., a cell in the set of cells 54-6 or in the set of cells 54-8).

[0053] In response to the fact that the addressed cell is on the left, the remaining signals on paths 94 (e.g., excluding the resolved address bit) can be passed to paths 98-1. In response to the fact that the addressed cell is on the right, the remaining signals on paths 94 (e.g., excluding the resolved address bit) can be passed to paths 98-2. By using the information in the (most significant) address bit to narrow down the position of the address cell on a corresponding address data path of paths 94, the corresponding address data path no longer needs to be routed past the decoding circuit 96 to identify the addressed cell.Accordingly, the set of paths 98-1 and the set of paths 98-2 can each have a width of (N-1) bits, with the bit resolved by the decoding circuit arrangement 96 in the address data path being missing in both sets of paths.

[0054] Paths 98-1 can be coupled between decoding circuit arrangement 96 and decoding circuit arrangement 100. Address decoding circuit arrangement 100 can process (e.g., resolve, decode, etc.) a second bit (e.g., the second most significant bit) of the original address data bits on address data paths 72 of paths 94 (or the most significant bit of the address data bits on address data paths 72 of paths 98-1). In particular, based on the (second most significant) bit of the original address, decoding circuit arrangement 100 can determine whether the addressed cell is a cell in the set of cells 54-5 (e.g., in the right branch of cells from the perspective of circuit arrangement 100) or a cell in the set of cells 54-7 (e.g., in the right branch of cells from the perspective of circuit arrangement 100).

[0055] In response to the fact that the addressed cell is located in the set of cells 54-5, the remaining signals on paths 98-1 (e.g., excluding the address bit resolved by circuit arrangement 100) can be passed to paths 102-1. Similarly, in response to the fact that the addressed cell is located in the set of cells 54-7, the remaining signals on paths 98-1 (e.g., excluding the address bit resolved by circuit arrangement 100) can be passed to paths 102-2. By using the information in the second-most significant bit of the address on a corresponding address data path of paths 98-1, the decoding circuit arrangement 100 narrows down the position of the address cell, thus eliminating the need for the corresponding address data path to bypass decoding circuit arrangement 100 to identify the addressed cell.Accordingly, the set of paths 102-1 and the set of paths 10-2 can each have a width of (N-2) bits, with the address data path having the additional (second most significant) bit of the original address that was resolved by the decoding circuit arrangement 100 and is missing in both sets of paths.

[0056] Analogously to the above description for the left side of Section 52-2 and the decoding circuit arrangement 100, corresponding data received on paths 98-2 can be processed similarly by the decoding circuit arrangement 104 (e.g., by decoding the second most significant bit of the original address). Accordingly, paths 106-1 and 106-2 can each have a width of (N-2) bits, omitting the two address data paths 72 of paths 94, which contain address bits (e.g., the most significant and second most significant address bits) that were decoded by the decoding circuit arrangements 96 and 104.

[0057] If desired, this type of shared decoding scheme can be continued down to the last two sets of paths branching off from the last shared address decoding circuit arrangement (which is shared by only two cells). These last two sets of paths may be missing arbitrary address data paths, since all address bits have been decoded by the entire upstream shared address decoding circuit arrangement. This scenario can be illustrated by paths 94, which have only two address bits on two corresponding address data paths 72 of paths 94. Accordingly, paths 102-1 (and likewise paths 102-2, paths 106-1, and paths 106-2) may be missing arbitrary address data paths 72 (but they may include the other data paths such as write data paths 70, sample signal path 74, read marker data path 76, and read data paths 78).If desired, when using this fully shared address decoding scheme in the local address decoding circuit arrangement (e.g., using circuit arrangement 80 in . Fig. 5 is implemented) the comparator circuit 82, the AND logic gate 84 and the AND logic gate 88 can be omitted, the sampling signal path 74 can be connected to the clock input of the signal memory 86, and the read marker data path 78 can be connected to the control input of the buffer 90.

[0058] Fig. Figure 8 is a representation of an illustrative shared address decoding circuit arrangement 108 (of which, for example, a corresponding instance can be implemented at each branch from the routing paths). Examples related to Fig. 7. An instance of the circuit arrangement 108 can be implemented at the branch of paths 94 into paths 98-1 and 98-2 (as decoding circuit arrangement 96), an instance of the circuit arrangement 108 can be implemented at the branch of paths 98-1 into paths 102-1 and 102-2 (as decoding circuit arrangement 100), an instance of the circuit arrangement 108 can be implemented at the branch of paths 98-2 into paths 106-1 and 106-2 (as decoding circuit arrangement 104), etc.

[0059] In the example of Fig. Figure 8 shows two illustrative types of decoding circuits, 108-1 and 108-2. The decoding circuit 108-1 can be used to decode a specific bit of the address (e.g., the most significant bit of the received address bits) in order to bypass the write data, the other (e.g., remaining) address bits, the sampling signal, and the read marker at the decoding circuit arrangement 108. Specifically, the path 110, which provides the address bit to be decoded, can be coupled to a first input of the AND logic gate 114-1 and, via an intermediate inverter 116, to a first input of the AND logic gate 114-2. The inverter 116 can provide the first input of the AND logic gate 114-2 with the bit ADDRB, which is an inverted version of the address bit on the path 110. The other data bit (e.g.(a write data bit, another address bit, the sample signal bit, the read marker bit) can be provided on path 112, which is coupled to the second input of AND logic gate 114-1 and is coupled to the second input of AND logic gate 114-2.

[0060] Accordingly, depending on the value of the address bit to be resolved, the other data bit on path 112 is output by one of the AND logic gates 114-1 or 114-2, and the other output of either AND logic gate 114-1 or 114-2 is a fixed binary value (e.g., "0"). In the example of Fig. 8. The AND logic gate 114-1 outputs the value on path 112 (for example, forwards it), and the AND logic gate 114-2 outputs the fixed binary value (for example, forwards it).

[0061] In the example of Fig. 8. Paths 110 and 112 can be coupled to or part of the paths before the branch, while the outputs of logic gates 114-1 and 114-2 can be coupled to the branched paths.

[0062] If desired, multiple instances of the decoding circuit 108-1 can be provided to process all other bits that are to pass through the circuit arrangement 108 (e.g., all write data bits, all unresolved address bits, the sampling signal bit, the read flag bit). If desired, the inverter 116 can be shared by multiple instances of the circuit 108-1.

[0063] If desired, a single instance of the decoding circuit 108-1 can be used to determine the output or pass-through path, and the remaining other bits can be passed along paths parallel to the determined output or pass-through path (e.g., in the same direction as it) without themselves being directly controlled by the logic gates 114-1, 114-2, and 116.

[0064] The decoding circuit 108-2 can be used to decode a specific address bit (e.g., the most significant bit of the received address bits) in order to transfer the read data from the unit cell to the programming circuit arrangement 58. Specifically, path 110, which provides the address bit to be decoded, can be coupled to a first input of the AND logic gate 118-1. Path 110', which provides an inverted version of the address bit to be decoded (e.g., the ADDRB bit provided by inverter 116), can be coupled to a first input of the AND logic gate 118-2. Path 120-1 from a first branched path (e.g., for providing read data from a first set of cells) can be coupled to the second input of the AND logic gate 118-1. Path 120-2 branches off from a second path (e.g.(To provide read data from a second set of cells) can be coupled to the second input of the AND logic gate 118-2. The outputs of logic gates 118-1 and 118-2 can be coupled to corresponding inputs of the OR logic gate 122. In such a configuration, the corresponding AND gate 118-1 or 118-2 (e.g., on the side containing the addressed cell) outputs or passes on the read data bit (RDATA1 or RDATA2), which is passed through the OR logic gate 122 and made available at the output of the OR logic gate 122 (e.g., as RDATA).

[0065] In the example of Fig. 8. Path 110 and the output of the OR logic gate 122 can be coupled to the paths before the branching, while paths 120-1 and 120-2 can be coupled to the branched paths.

[0066] In connection with a Fig. In the example described in section 6, address decoding can be performed completely (e.g., for all address bits) in the local address decoding circuit arrangement (e.g., circuit arrangement 80 in [reference]). Fig. 5) take place. In connection with a Fig. In the example described in section 7, address decoding can be performed completely (e.g., for all address bits) in the shared address decoding circuit arrangement (e.g., circuit arrangement 108 in [reference]). Fig. 8) . If desired, a combination (e.g. a hybrid) of these two address decoding schemes can be used.

[0067] As shown in the illustrative flowchart of Fig. As shown in Figure 9, the illustrative DAC 50 can include one or more instances of a shared address decoding circuit arrangement (e.g., instances of the decoding circuit arrangement 108) that perform a shared decoding in block 124 at a corresponding number (e.g., "X") of divisions to decode a set of most significant bits of the address for the other data (e.g., bits of write data, unresolved address bits, the sample signal bit, the read marker bit, and bits of read data). The illustrative DAC 50 can also include a local address decoding circuit arrangement at each cell 54 (e.g., instances of the decoding circuit arrangement 80) that performs local decoding (e.g., at the cell level) in block 126 to decode the remaining bits (e.g., the least significant bits) of the address for the other data (e.g.,to decode bits of write data, unresolved address bits, the sampling signal bit, the read marker bit and bits of read data) accordingly.

[0068] The above in connection with Fig. The procedures and operations described in sections 1 to 9 can be performed by the components of the device 10 using software, firmware, and / or hardware (e.g., a dedicated circuit arrangement or hardware). Software code for performing these operations can be stored on non-volatile, computer-readable storage media (e.g., physical computer-readable storage media) located on one or more of the components of the device 10 (e.g., the storage circuit arrangement 16 and / or the wireless communication circuit arrangement 24). Fig. 1) are stored. The software code may sometimes be referred to as software, data, instructions, program instructions, or code. The non-volatile, computer-readable storage media may include drives, non-volatile memory such as non-volatile random access memory (NVRAM), removable flash drives or other removable media, other types of random access memory, etc. The software stored on the non-volatile, computer-readable storage media may be executed by the processing circuitry of one or more components of the device 10 (e.g., by the processing circuitry in the wireless circuitry 24, the processing circuitry 18 of Fig.1 etc.). The processing circuit arrangement may include microprocessors, application processors, digital signal processors, central processing units (CPUs), application-specific integrated circuits with processing circuit arrangement, or other processing circuit arrangements.

[0069] According to one embodiment, the wireless communication circuit arrangement includes: a digital-to-analog converter having a plurality of unit cells; a programming circuit configured to program the plurality of unit cells; and a plurality of data paths coupled to the programming circuit arrangement and the digital-to-analog converter, including address data paths, wherein the programming circuit arrangement is configured to transmit address bits via the address data paths to the digital-to-analog converter, which together form an address that identifies a particular unit cell in the plurality of unit cells.

[0070] According to another embodiment, the plurality of data paths optionally includes a programming data path, and the programming circuit arrangement is configured to transmit programming data to be stored in the specific unit cell to the plurality of unit cells via the programming data path.

[0071] According to another embodiment, the plurality of data paths optionally includes a sampling signal path, and the programming circuit arrangement is configured to transmit a sampling signal via the sampling signal path to the plurality of unit cells, which, when activated, causes the programming data to be stored in the specified unit cell.

[0072] According to another embodiment, the specific unit cell optionally has a configurable circuit, and the programming data, when stored in the specific unit cell, cause the configurable circuit to exhibit a state.

[0073] According to another embodiment, the plurality of data paths optionally includes a read marker data path, and the programming circuit arrangement is configured to transmit a read marker via the read marker data path to the plurality of unit cells, which, when set, causes data to be read from the specified unit cell.

[0074] According to another embodiment, the plurality of data paths optionally includes a read data path, and the programming circuit arrangement is configured to receive the read data via the read data path and from the specified unit cell when the read marker is set.

[0075] According to another embodiment, the specific unit cell optionally includes a local address decoding circuitry configured to receive and decode at least one address bit of the address bits.

[0076] According to another embodiment, the local address decoding circuit arrangement is optionally configured to receive and decode each address bit of the address bits.

[0077] According to another embodiment, the digital-to-analog converter optionally includes a shared address decoding circuit arrangement coupled to a first set of unit cells in the plurality of unit cells and coupled to a second set of unit cells in the plurality of unit cells, and the shared address decoding circuit arrangement is configured to receive and decode at least one address bit of the address bits.

[0078] According to another embodiment, the specific unit cell optionally includes a local address decoding circuitry configured to receive and decode at least one address bit of the address bits.

[0079] According to another embodiment, the shared address decoding circuit arrangement is optionally configured to receive and decode at least one most significant bit of the address, and the local address decoding circuit arrangement is configured to receive and decode at least one least significant bit of the address.

[0080] According to another embodiment, the wireless communication circuit arrangement optionally also includes a transmitter that incorporates the digital-to-analog converter.

[0081] According to one embodiment, a digital-to-analog converter includes: a plurality of unit cells, wherein a particular unit cell in the plurality of unit cells has a programmable feature and a storage circuit configured to store programming data for the programmable feature; a plurality of address data paths coupled to the plurality of unit cells and configured to transmit an address for the particular unit cell; a sampling signal path coupled to the plurality of unit cells and configured to transmit a sampling signal; and a write data path coupled to the plurality of unit cells and configured to provide the storage circuit with the programming data based on the address and the sampling signal.

[0082] According to another embodiment, the digital-to-analog converter optionally includes a read marker data path coupled to the plurality of unit cells and configured to transmit a read marker, as well as a read data path coupled to the plurality of unit cells and configured to provide data from the given unit cell based on the address and the read marker.

[0083] According to another embodiment, the specific unit cell optionally has a local address and includes a comparison circuit configured to perform a comparison of the address transmitted through the multitude of address data paths with the local address, and the write data path is configured to provide the programming data to the storage circuit based on the comparison.

[0084] According to another embodiment, the digital-to-analog converter optionally further includes a shared address decoding circuit arrangement coupled between the plurality of address data paths and the plurality of unit cells, wherein the shared address decoding circuit arrangement is configured to decode one address bit of the address transmitted on one address data path of the plurality of address data paths.

[0085] According to another embodiment, the digital-to-analog converter optionally includes an additional shared address decoding circuit arrangement coupled between the plurality of address data paths and the plurality of unit cells, wherein the additional shared address decoding circuit arrangement is configured to decode an additional address bit of the address transmitted on an additional address data path of the plurality of address data paths.

[0086] According to another embodiment, the digital-to-analog converter optionally includes an input configured to receive digital data and an output configured using the plurality of unit cells to provide an analog voltage corresponding to the digital data.

[0087] According to one embodiment, a digital-to-analog converter includes: a plurality of unit cells, each comprising a configurable circuit; an input coupled to and configured with the plurality of unit cells to receive digital data; an output coupled to and configured with the plurality of unit cells to provide an analog voltage corresponding to the digital data using the plurality of unit cells; and a plurality of programming inputs coupled to and configured with the plurality of unit cells to receive an address and programming data for controlling the configurable circuit of a unit cell identified by the address within the plurality of unit cells.

[0088] According to a further embodiment, the digital-to-analog converter optionally includes a first address decoding circuit arrangement coupled between the first and second sets of unit cells in the plurality of unit cells and configured to provide address decoding for a first part of the address and for the first and second sets of unit cells, wherein the unit cell identified by the address includes a second address decoding circuit arrangement configured to provide address decoding for a second part of the address and for the unit cell.

[0089] The foregoing is for illustrative purposes only, and various modifications can be made to the described embodiments. The foregoing embodiments can be implemented individually or in any combination.

[0090] It goes without saying that when using personal data, privacy policies and practices should be followed that are generally accepted and meet or exceed industry-specific or regulatory requirements for protecting user privacy. In particular, personal data should be managed and handled in a way that minimizes the risk of accidental or unauthorized access or use, and the nature of permitted use should be clearly communicated to users. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 18 / 897,739

[0001]

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