VERTICAL DIE-TO-DIE (D2D)-CONNECTED CHIPLETS ON A GLASS CORE

Abstract

Vertical die-to-die (D2D) interconnected chiplets on a glass core. The chiplets are two distinct integrated circuit dies, often referred to as "hot" dies and here called the top dies. The glass core contains a cavity. An active I / O die resides within the cavity to provide D2D communication, with its top face flush with the top surface of the glass core. Two differently sized microcontact bumps are used: the first microcontact bumps have a smaller pitch (e.g., "fine pitch") and serve to attach the top dies to the top face; the second microcontact bumps are larger than the first (e.g., "coarse pitch") and serve to attach the top dies to the top surface of the glass core. An organic build-up and solder ball backing may be fabricated on the bottom surface of the glass core.

Description

STATE OF THE ART Semiconductor systems and packaged assemblies that connect multiple chiplets require chiplet-to-chiplet communication channels. Chiplet-to-chiplet communication channels implemented as die-to-die (D2D) interconnects often suffer from bandwidth, latency, and power consumption losses. Therefore, improved architectures and methods for D2D interconnects are desirable. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a simplified cross-sectional illustration of vertical D2D-connected chiplets on a glass core according to various embodiments. Fig. 2 is a simplified cross-sectional illustration of an input / output (I / O) die according to various embodiments. Figs. 3-6 show various fabrication stages of vertical D2D-connected chiplets on a glass core according to various embodiments. Fig. 7 illustrates an exemplary process for vertical D2D-connected chiplets on a glass core according to various embodiments. Fig. 8 illustrates additional embodiments supported by the provided methods and architectures. Fig. 9 is a top view of a wafer and dies that may be contained in a microelectronic arrangement according to any of the embodiments disclosed herein.Figure 10 is a simplified cross-sectional side view showing an implementation of an integrated circuit on a die, which may be contained in various embodiments according to any of the embodiments disclosed herein. Figure 11 is a cross-sectional side view of a microelectronic assembly, which may contain any of the embodiments disclosed herein. Figure 12 is a block diagram of an exemplary electrical device, which may contain any of the embodiments disclosed herein. DETAILED DESCRIPTION Semiconductor systems and package assemblies that connect multiple chiplets rely on chiplet-to-chiplet communication channels implemented as die-to-die (D2D) interconnects. Technical challenges for chiplet-to-chiplet communication persist in various applications; in particular, D2D communication channels can suffer from bandwidth, latency, and power consumption losses. Some solutions, referred to as lateral D2D solutions, place the dies in the same plane, so their communication channels are lateral in a cross-sectional view. However, since latency and power consumption are proportionally affected by the length of the communication channels between the dies / chiplets, it is desirable to improve lateral D2D solutions. Some solutions implement vertical interconnects for chiplet-to-chiplet communication, either using current micro-solder ridge connections or hybrid bonding; these solutions can be implemented in a front-to-front (F2F) and / or front-to-back (F2B) orientation of two dies / chiplets. However, these solutions are often implemented in silicon intermediate carriers or silicon bridges using silicon through-hole vias (TSVs). The higher switching performance requirements of applications such as artificial intelligence (AI), coupled with scaling needs, are expected to necessitate that package assemblies implement glass core substrates. Therefore, D2D interconnect solutions that reduce communication channel length and are adapted to glass core substrates are considered essential. The embodiments described herein provide a technical solution to these technical challenges in the form of vertically D2D-connected chiplets on a glass core. These embodiments arrange dies on a glass core semiconductor substrate in a staggered, stacked manner, thereby enabling vertically D2D-connected chiplets (dies). The vertical D2D communication channels are shorter than the lateral D2D communication channels, which improves latency and power consumption. These concepts are elaborated in more detail below. Exemplary embodiments are described below in conjunction with the following drawing figures, where identical reference numerals denote identical elements. Unless otherwise indicated, the figures are not necessarily to scale but may be used for the spatial orientation and relative positioning of features. As can be seen, certain terms such as "ceiling" and "floor," as well as "upper," "top," "lower," "above," "below," "below," "underside," and "top," refer to directions based on the referenced figures. Furthermore, terms such as "front," "back," "rear," "side," "vertical," and "horizontal" may describe the orientation and / or position of sections of the component within a consistent, yet arbitrary, frame of reference, which is clarified by reference to the text and accompanying figures describing the component under discussion.Such terminology may include the words explicitly mentioned above, derivatives thereof, and words with similar meanings. As used herein, the term "adjacent" refers to layers or components that are in direct physical contact with each other without any intervening layers or components. For example, layer X adjacent to layer Y refers to a layer that is in direct physical contact with layer Y.In contrast, as used herein, the phrase(s) “located on” (alternatively “located under”, “located above / over”, or “located next to” in the context of a first layer or component located on top of a second layer or component) include (i) configurations in which the first layer or component is directly physically attached to (i.e., adjacent to) the second layer, and (ii) components and configurations in which the first layer or component is attached to (i.e., coupled to) the second layer or component via one or more intervening layers or components. The following detailed description is not intended to restrict the application and use of the disclosed technologies. It may be obvious that the novel embodiments can be implemented without any of the details described herein. For the sake of brevity, well-known structures and devices may be shown in block diagram form to facilitate their description. Fig. 1 is a simplified cross-sectional illustration of vertically D2D-connected chiplets on a glass core. Embodiment 100 shows three dies (or chiplets) arranged on a glass core that has a cavity formed therein. The first die 102 and the third die 104 are vertically D2D-connected through a second die 106. In various embodiments, the first die 102 and the third die 104 are integrated circuit dies, and the second die 106 is an input / output channel die. A staggered and / or partially stacked arrangement of the first die 102 and the second die 106 is shown in section 108-1, and a corresponding staggered / partially stacked arrangement of the third die 104 and the second die 106 is shown in section 108-2. This staggered arrangement is an architectural feature that can be observed visually to indicate the practice of the embodiments described herein. The first die 102 and the third die 104 may be referred to as the “upper die” because they are attached to the upper surface of the glass core 124. The second die 106 may also be referred to as the “lower die” (or chiplet) for the same reasons. Areas 108-1 and 108-2 represent overlapping surfaces (or "staggered" or "stacked" surfaces) between an upper die (the first die 102 and the third die 104, respectively) and the lower die 106, and the vertical D2D intermediate connections can be identified in these areas. Although only two upper dies and one lower die are shown in this embodiment, those skilled in the art will recognize that in other embodiments, as a top view may reveal, there may be more than two upper dies communicating via the lower die; furthermore, other embodiments may include a second lower die in a second cavity and support additional upper dies in the same manner as described for this example. The vertical D2D interconnects are structures implemented in area 108-1 and area 108-2, each containing a set of conductive contacts called microcontact hills 114. In various embodiments, the microcontact hills 114 have a solder contact hill pitch (BP) in a range of 25 micrometers to 55 micrometers ± 10% (often referred to as the "fine pitch"). In some scenarios, the fine pitch BP may be 10 micrometers ± 10%. For clarity, one microcontact hill 114 is shown in area 108-1 and one microcontact hill 114 is shown in area 108-2. As is clear, in a top view, this would appear as a series of microcontact hills 114 in area 108-1 and a series of microcontact hills 114 in area 108-2.The length 134 of the overlap or overhang can be varied, representing up to approximately 5-10% of the planar surface of the upper die (where approximately means plus or minus 10%), and in other embodiments more than one series of microcontact hillocks 114 can be supported in the area 108-1 and in the area 108-2. In the overlapping regions 108-1 and 108-2, the vertical D2D interconnect structures include respective microcontact hill connection fields, which are conductive connection fields on the upper die and on the lower die for attaching them to the microcontact hills 114. In various embodiments, the lower surface of the upper die includes at least one microcontact hill connection field 112, and the upper surface of the lower die includes at least one microcontact hill connection field 116 to accommodate a microcontact hill 114.When the microcontact hill 114 is attached to the microcontact hill terminal field 112, it provides an electrical path via internal vias and conductor tracks (generally represented by the via 110) to an electronic circuit arrangement within the upper die (of the third die 104); likewise, when a microcontact hill is present in the region 108-1, it provides an electrical path via internal vias and conductor tracks to an electronic circuit arrangement within the upper die (of the third die 102). When the microcontact hill 114 is attached to a microcontact hill terminal field on the upper surface of the lower die (microcontact hill terminal field 116), it provides an electrical path via internal vias and traces (generally represented by the via 118) to an electronic circuit arrangement within the lower die 106 (and similarly, when a microcontact hill is attached in the region 108-1, it provides an electrical path via internal vias and traces to an electronic circuit arrangement within the lower die 106). Finally, the microcontact hills 114 attach the upper dies to the lower die, thereby completing one or more electrical paths between the two or more upper dies through the lower die. In addition to being attached to the lower die via the vertical D2D interconnect structures, the two upper dies (the first die 102 and the third die 104) are also attached to the glass core 124 by a second set of microcontact hills 122. The first die 102 extends over the upper surface of the glass layer and includes one array of microcontact hills 122; the third die 104 extends over the upper surface of the glass layer and includes another array of microcontact hills 122. As illustrated, the first die 102 and the third die 104 are arranged side by side but are not adjacent to each other, and their lower surfaces are coplanar and face the upper surface of the glass layer or glass core 124. The second set of microcontact hills 122 can be arranged with a “coarse grid,” which denotes a grid size > 90 micrometers plus or minus 10%.The second set of microcontact hills 122 attaches the respective upper dies to the upper surface of the glass core 124 and couples electrically with conductive material in respective glass vias (TGV 132). It should be noted that the second die 106 / the lower die is located within a cavity in the glass core 124, which is enclosed on the sides and bottom by the cavity formed in the glass core 124. This advantageously provides thermal insulation to the lower die, in addition to keeping the profile or Z-height smaller than solutions that place the die on a cavityless glass core. The lower die is positioned such that its upper surface is essentially planar with the upper surface of the glass core 124, as illustrated. Although the image is drawn in two dimensions, it is understood that the cavity can be defined in three dimensions, so that when the lower die is placed within the cavity, only its upper surface is exposed to the upper surface of the glass core 124. Embodiment 100 shows an organic build-up layer 126 on the lower surface of the glass core 124 and solder balls 128 on the lower surface of the organic build-up layer 126. In various embodiments, the lower die, the die 106, provides one or more electrical paths through the glass core 124, through various vias and conductive traces in the organic build-up layer 126, to one or more of the solder balls 128 on the bottom surface of the organic build-up layer 126. For this purpose, the lower die 106 can have conductive connection pads on its lower surface to couple electrically with conductive material in the glass vias (e.g., TGV 132) in the glass core 124. In a housing assembly, a potting / backfilling material (MUF 130) can surround the upper dies 102 and 104 on the upper surface of the glass core 124. A dielectric layer 123 can be superimposed on the upper surface of the glass core 124 and inserted between the upper dies and the upper surface of the glass core. Optionally, as shown, some embodiments can attach a dummy silicon block 120 to the exposed portion of the upper surface of the lower die 106, i.e., where it is not covered by the overhangs of regions 108-1 and 108-2. The upper dies 102 and 104 can be an unencapsulated integrated circuit die and can alternatively be referred to as chips, chiplets, chip complexes, or chiplet complexes. While the terms die, chip, and chiplet can be used interchangeably, the term chiplet is sometimes used for an integrated circuit that implements a subset of the functionality of a larger integrated circuit. Chiplets can vary in type / functionality (e.g., computing, memory, I / O, power management, i.e., controlling power input and / or providing power to components). In various applications, the first die 102 and / or the third die 104 are "hot" dies, such as a central processing unit (CPU), a graphics processing unit (GPU), or the like. The described and illustrated architecture advantageously keeps the upper surfaces of the hot dies exposed at the top surface of the embodiments. The glass core surrounding / enclosing the lower die 106 provides thermal insulation from the heat generated by the hot dies. The dummy block 120 can also serve the purpose of heat dissipation. Embodiments make the CPU or the hot upper dies easily coolable, as they are exposed; this advantageously allows the implementation of further heat-reducing techniques and methods (e.g., heat spreaders). Embodiments of the vertical D2D-connected chiplets are described in more detail in the following discussion. With reference to Fig. 2, the lower die or I / O die is described in more detail. A simplified cross-sectional view of an embodiment 200 of an input / output (I / O) die according to various embodiments is shown. The I / O die is more complex than a simple passive bridge. An active circuit layer 202 is superimposed on a silicon substrate 204. The silicon substrate 204 has a plurality of silicon vias (TSV 206). The embodiment 200 of the I / O die has at least one electrical path from the microcontact hill termination field 116-1 on its upper surface through the active circuit layer 202 to the microcontact hill termination field 116-2 on its upper surface (with reference to Fig. 1, the microcontact hill termination field 116-1 corresponds to region 108-1 and the microcontact termination field 116-2 corresponds to region 108-2).Additionally, at least one electrical path extends from the active circuit layer 202 through a TSV 206 to the lower surface, where the TSVs are attached to copper terminals 208 in an insulating material 210. The total Z-height 205 of the I / O die (minus the microcontact ridge terminals) is specified. The cavity in the glass core 124 has a Z-depth sufficient to accommodate the Z-height 205. The micro-terminal fields 116 can comprise a metal and can comprise copper. In various embodiments, the TSVs 206 have a conductive material, such as copper, inside them. The insulating material 210 can be any dielectric material, such as a suitable nitride or oxide, for example SiOx, silicon dioxide (SiO2), carbon-doped silicon dioxide (C-doped SiO2, also known as CDO or organosilicate glass, which is a material comprising silicon, oxygen, and carbon), fluorine-doped silicon dioxide (F-doped SiO2, also known as fluorosilicate glass, which is a material comprising fluorine, silicon, and oxygen), or hydrogen-doped silicon dioxide (H-doped SiO2, which is a material comprising silicon, oxygen, and hydrogen). In some embodiments, a dielectric layer comprises a photoimaginable dielectric (PID). In some embodiments, the dielectric layer comprises an Ajinomoto build-up film (often referred to as ABF), which is a material comprising an organic resin matrix with various types of fillers (e.g.,The design includes silica fillers of various sizes, or hollow fillers of various sizes, for controlling the coefficient of thermal expansion (CTE) and / or the electrical properties (e.g., the dielectric constant (DC) and / or the loss factor (insertion loss) (DF)). In other embodiments, the dielectric material can be any type of epoxy resin casting compound. Fig. 3, Fig. 4, Fig. 5 and Fig. 6 represent different manufacturing phases of vertical D2D-connected chiplets on a glass core, and Fig. 7 illustrates an exemplary process for the vertical D2D-connected chiplets on a glass core according to different embodiments. In 702, a glass layer, which becomes the glass core 124, is structured with TGVs 304 and the cavity 306 is formed in it. The glass core 124 / 302 / 402 / 502-1 / 502-2 can comprise a glass layer (as used herein, glass can be an alkali-free alkaline earth boro-aluminosilicate glass, such as glass containing aluminum, oxygen, boron, silicon, and an alkaline earth metal (for example, beryllium, magnesium, calcium, strontium, barium, radium, such as glass containing SiO2, Al2O3, B2O3, and MgO) or a photosensitive glass (light-machinable or light-structured glass). In some embodiments, a photosensitive glass can be a glass belonging to the lithium silicate family of glass (for example, a glass containing lithium, silicon, and oxygen) that includes metallic particles, such as gold, silver, or other suitable metallic particles. The glass core 124 / 302 / 402 / 502-1 / 502-2 can have a CTE in the range of 2–20 exhibit ppm / K.In some embodiments, it is advantageous that the glass layer 402 has a CTE that matches that of the intended core dies 102 / 104 in the assembled product. In various embodiments, the core dies 102 / 104 are integrated circuit dies (e.g., matching the CTE of silicon) or have a CTE that matches that of a substrate or a printed circuit board. In some embodiments, the glass core 124 / 302 / 402 / 502-1 / 502-2 can comprise several glass sheets bonded together with an adhesive layer; and can furthermore have a CTE gradient along the Z-axis. In various embodiments, e.g., in a glass substrate or embodiment 300 with a Z-height (in the drawing) in a range of approximately ≤1 millimeter (mm) to 5 mm, the glass sheet 302 or the glass core can have a thickness (Z-height) in a range of approximately 50 ± 5 micrometers to approximately 1.5 millimeters, ±10%. The TGVs 304 are volumes in which glass is removed and conductive materials are placed within the volumes sufficient to enable electrical communication from an upper surface to a lower surface. As illustrated in embodiment 300 of the glass layer 302, the TGVs 304 are essentially perpendicular to an upper surface of the glass layer 302.In embodiments that each produce a panel, the X length of a glass layer and a corresponding Y length (which defines an area in a top or top view) can be in a range of a first length (for example, X) in a range of 10 millimeters to 500 millimeters and a second length (for example, Y) in a range of 10 millimeters to 500 millimeters, wherein the first length is perpendicular to the second length. The embodiment 300 represents the glass core 124 / 204 / 402 with glass vias (TGVs 304) produced therein and a cavity 306 formed in the upper surface of the glass core or glass layer 302. The figures show cross-sectional views in which the section for the cavity is represented as a width from left to right on the side; however, in a top view, the section for the cavity would appear as a surface. The TGVs 304 and the cavity 306 are produced in the glass core or glass layer 302 by removing a quantity of glass material. The TGVs 304 and the cavity 306 can be produced by wet etching followed by laser drilling or ablation. TGV sidewalls and cavity walls are essentially straight (i.e.,90 degrees from perpendicular to an upper surface of the glass core or glass layer 302 plus or minus 20 degrees; however, in other embodiments the cavity walls may be 90 degrees plus or minus 10 degrees) and may have an internal taper reflecting the drilling or ablation process used to open the cavity. In embodiment 704, as specified in embodiment 330, a die attach film (DAF) 332 is applied to the lower surface of the I / O chiplet (e.g., the lower die embodiment 200), and then the I / O chiplet is inserted into the cavity 306, so that the DAF 332 attaches the I / O chiplet to the bottom of the cavity, as shown. In 706, laser cleaning techniques 352 are used in the TGVs, which are applied from the lower surface of the glass core or glass layer 302 to remove the DAF in the TGVs in order to expose the Cu terminal fields 208 on the lower surface of the lower die embodiment 200 on the respective TGVs, as illustrated in embodiment 350 and embodiment 370. In 708, embodiment 370 illustrates the application of a copper metallization to fill the TGV holes and form copper terminal fields on an upper surface and on the lower surface of the glass layer 302. In 710, embodiment 400 illustrates the application of a solder mask or a polyimide film lamination over the top surface of embodiment 370 to create embodiment 400. As used here, “filling” the TGVs with copper means that sufficient copper material is present in the through-hole of the TGV to provide an electrical path in the TGV from one surface of the glass layer to the opposite surface of the glass layer. As illustrated in embodiment 430, the upper surface of embodiment 400 is removably attached to a temporary support 432. In some manufacturing processes, the temporary support 432 supports two front-to-front configurations (402-1 and 402-2), as shown. In 712, an organic buildup layer 504 is produced on the lower surface of the glass core 402-1 or 402-2. The organic buildup layers 504 comprise one or more dielectric layers with structured redistribution layer (RDL) traces therein, as is known in the art. The dielectric layers can be a suitable dielectric, as described above. The conductive material used for conductive contacts, RDL traces, and vias can comprise a metal (e.g., copper, aluminum, nickel, cobalt, iron, tin, gold, silver, or combinations thereof) or another suitable conductive material. After completion of the fabrication of the organic build-up layers, the glass core substrates of embodiments 532-1 and 532-2 can be removed from the temporary support (as illustrated in embodiment 530), turned over again, and a glass support 622 can be attached to a lower surface of the organic build-up layer 504 of the embodiments (e.g., of embodiment 532-1, as shown in embodiment 600). In embodiment 716, the microcontact hills 122 and 114 described above can be added, and the upper dies (die 102 and die 104) are attached to the embodiment 532-1 via the microcontact hills 122 and 114. The optional silicon block 120 can be attached to the I / O die. In various embodiments, the microcontact hills 122 and 114 can be subjected to heat (melting) to complete the attachment of the upper dies to the embodiment 532-1. In 718, the application of a potting mold / underfill (MUF 130) around the upper dies can be carried out on the upper surface of embodiment 532-1 of the glass core substrate, and the deposition of conductive contacts, such as solder balls 128 arranged in a ball grid array (BGA), can be carried out, thereby generating embodiment 630, which is analogous to embodiment 100. At or after 718, embodiment 630 can be further assembled into a system housing, such as being attached to a printed circuit board (PCB) or mainboard, with an overlay encapsulation material, with an electrically coupled power supply, and the like. In addition, overmolding and thermal solutions (not shown) can be added. Fig. 8 illustrates some additional variations that embodiments can realize. Since the glass core 124 can be manufactured as a single sheet, a sheet with a gradient from an upper surface to a lower surface, or as several fused sheets, which in the non-limiting example are specified as three layers (e.g., glass layer 302 / 402 / 502-1), where a sheet is a glass layer, as described above, those skilled in the art will recognize that other variations are supported by the methodology and setup described herein. Embodiment 800 illustrates the glass core 802-1 comprising only one glass sheet / layer, and the cavity 306 extends completely through the glass core 802-1 (i.e., the cavity is a through-hole).The copper connection fields 208 on the lower surface of the lower die embodiment 200 can be directly attached to respective conductive connection fields within the organic build-up layer 504. In embodiment 830, there is one less glass sheet or glass layer in the glass core 802-2, and the cavity 306 extends through the first glass layer. The I / O chiplet or I / O die is attached to the cavity on the upper surface of the lower glass layer by the DAF, as described above. Thus, vertical D2D-connected chiplets on a glass core have been described. The above embodiments can provide the functionality conventionally associated with a monolithic single-chip system (SoC) in a multi-die package or multi-die assembly. The above is not an exhaustive list of multi-die assemblies or systems implementing an underhung buffer architecture. Those skilled in the art will recognize that additional, unillustrated multi-die assembly embodiments are supported based on the figures and descriptions contained herein. The following figures and description provide additional context for the cores, wafers, and assemblies described above. Fig. 9 is a top view of wafer 900 and dies 902, which may be included in any of the embodiments disclosed herein. The wafer 900 may be made of semiconductor material and may include one or more dies 902 formed on a surface of the wafer 900. After the fabrication of the integrated circuit components on the wafer 900 is complete, the wafer 900 may be subjected to a singulation process in which the dies 902 are separated from one another to provide discrete “chips” or are intended for an encapsulated integrated circuit component. The individual dies 902 comprising an integrated circuit component may include one or more transistors (e.g., some of the transistors 1040 of Fig. 10 discussed below), a support circuit arrangement for conducting electrical signals to the transistors, passive components (e.g.,signal traces, resistors, capacitors, or inductors) and / or any other integrated circuit components. In some embodiments, the wafer 900 or the die 902 may include a memory device (e.g., a random-access memory device (RAM device), such as a static RAM device (SRAM device), a magnetic RAM device (MRAM device), a resistive RAM device (RRAM device), a conductive bridge RAM device (CBRAM device), etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Additionally, several devices may be combined on a single die 902. For example, a memory arrangement formed by several memory devices may be integrated on the same chip 902 as a processor unit (e.g., the processor unit 1202 from Fig. 1).12) or other logic designed to store information in the storage devices or to execute instructions stored in the storage arrangement. In some embodiments, a die 902 can be attached to a wafer 900 which has other dies, and the wafer 900 is subsequently singulated; this manufacturing process is called the die-to-wafer assembly technique. Fig. 10 is a cross-sectional side view of an integrated circuit 1000, which may be included in any of the embodiments disclosed herein. One or more of the integrated circuits 1000 may be contained in one or more dies 902 (Fig. 9). The integrated circuit 1000 may be formed on a die substrate 1002 (e.g., the wafer 900 of Fig. 9) and may be contained in a die (e.g., the die 902 of Fig. 9). The die substrate 1002 can be a semiconductor substrate consisting of semiconductor material systems, for example, n-type or p-type material systems (or a combination of both). The die substrate 1002 can, for example, include a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 1002 can be formed using alternative materials, which may or may not be combined with silicon, including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, III-V, or IV can also be used to form the die substrate 1002.Although some examples of materials from which the die substrate 1002 can be formed are described herein, any material that can serve as the basis for an integrated circuit 1000 can be used. The die substrate 1002 can be part of a single die (e.g., the die 902 from Fig. 9) or of a wafer (e.g., the wafer 900 from Fig. 9). The integrated circuit 1000 can include one or more device layers 1004 arranged on the die substrate 1002. The device layer 1004 can have features of one or more transistors 1040 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1002. The transistors 1040 can, for example, have one or more source and / or drain regions (S / D regions) 1020, a gate 1022 for controlling current flow between the S / D regions 1020, and one or more S / D contacts 1024 for conducting electrical signals to / from the S / D regions 1020. The Gate 1022 can be composed of at least two layers: a gate dielectric and a gate electrode. The gate dielectric can consist of a single layer or a stack of layers. The single or multiple layers can contain silicon dioxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material. The high-k dielectric material can contain elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used in the gate dielectric include hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc cniobate.In some embodiments, a tempering process can be performed on the gate dielectric to improve its quality when a high-k material is used. The gate electrode can be formed on the gate dielectric and, depending on whether the transistor 1040 is to be a p-type metal-oxide-semiconductor (PMOS) transistor or an n-type metal-oxide-semiconductor (NMOS) transistor, can have at least one p-type or one n-type exit metal. In some implementations, the gate electrode can comprise a stack of two or more metal layers, where one or more metal layers are exit metal layers and at least one metal layer is a filler metal layer. Additional metal layers may be included for other purposes, such as a depletion layer. For a PMOS transistor, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning). In some embodiments, when viewed as a cross-section of transistor 1040 along the source-channel-drain direction, the gate electrode may comprise a U-shaped structure including a lower section that is substantially parallel to the top surface of the die substrate 1002 and two side wall sections that are substantially perpendicular to the top surface of the die substrate 1002. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the die substrate 1002 and has no side wall sections that are substantially perpendicular to the top surface of the die substrate 1002. In still other embodiments, the gate electrode may comprise a combination of U-shaped structures and planar, non-U-shaped structures.For example, the gate electrode can comprise one or more U-shaped metal layers formed on top of one or more planar, non-U-shaped layers. In some embodiments, a pair of sidewall spacers can be formed on opposite sides of the gate stack to clamp the gate stack. The sidewall spacers can be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the field and include deposition and etching processes. In some embodiments, a plurality of spacer pairs can be used; for example, two pairs, three pairs, or four pairs of sidewall spacers can be formed on opposite sides of the gate stack. The S / D regions 1020 can be formed within the die substrate 1002 adjacent to the gate 1022 of individual transistors 1040. The S / D regions 1020 can be formed, for example, using an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic can be ion-implanted into the die substrate 1002 to form the S / D regions 1020. A tempering process, which activates the dopants and causes them to diffuse further into the die substrate 1002, can follow the ion implantation process. In the latter process, the die substrate 1002 can first be etched to form depressions at the locations of the S / D regions 1020. An epitaxial deposition process can then be carried out to fill the depressions with a material used to fabricate the S / D areas 1020.In some implementations, the S / D regions 1020 can be fabricated using a silicon alloy, such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy can be doped in situ with dopants such as boron, arsenic, or phosphorus. In some embodiments, the S / D regions 1020 can be formed using one or more alternative semiconductor materials, such as germanium or a Group III-V material or alloy. In other embodiments, one or more layers of metal and / or metal alloys can be used to form the S / D regions 1020. Electrical signals, such as power and / or input / output (I / O) signals, can be routed to and / or from the devices (e.g., transistors 1040) of the device layer 1004 through one or more interconnection layers arranged on the device layer 1004 (illustrated in Fig. 10 as interconnection layers 1006-1010). For example, electrically conductive features of the device layer 1004 (e.g., the gate 1022 and the S / D contacts 1024) can be electrically coupled to the interconnection structures 1028 of the interconnection layers 1006-1010. The one or more interconnection layers 1006 to 1010 can form metallization stacks (also referred to as "ILD stacks") 1019 of the integrated circuit 1000. The interconnection structures 1028 can be arranged within the interconnection layers 1006 to 1010 to conduct electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the specific configuration of interconnection structures 1028 shown in Fig. 10. Although a specific number of interconnection layers 1006 to 1010 is shown in Fig. 10, embodiments of the present disclosure have integrated circuits with more or fewer interconnection layers than shown. In some embodiments, the interconnection structures 1028 can include conductors 1028a and / or vias 1028b filled with an electrically conductive material, such as a metal. The conductors 1028a can be arranged to conduct electrical signals in a direction along a plane that is substantially parallel to a surface of the die substrate 1002 on which the device layer 1004 is formed. For example, the conductors 1028a can conduct electrical signals in a direction into and out of the side and / or in a direction across the side. The vias 1028b can be arranged to conduct electrical signals in a direction along a plane that is substantially perpendicular to the surface of the die substrate 1002 on which the device layer 1004 is formed.In some embodiments, the vias 1028b can electrically couple the conductors 1028a of different intermediate interconnection layers 1006 to 1010. The interconnection layers 1006 to 1010 can comprise a dielectric material 1026 arranged between the interconnection structures 1028, as shown in Fig. 10. In some embodiments, the dielectric material 1026 arranged between the interconnection structures 1028 in different interconnection layers 1006 to 1010 can have different compositions; in other embodiments, the composition of the dielectric material 1026 can be the same between different interconnection layers 1006 to 1010. The device layer 1004 can comprise a dielectric material 1026 that is also arranged between the transistors 1040 and a lower layer of the metallization stack.The dielectric material 1026 contained in the device layer 1004 may have a different composition than the dielectric material 1026 contained in the intermediate compound layers 1006-1010; in other embodiments, the composition of the dielectric material 1026 in the device layer 1004 may be the same as that of a dielectric material 1026 contained in any of the intermediate compound layers 1006-1010. A first interconnect layer 1006 (designated as metal 1 or "M1") can be formed directly on the device layer 1004. In some embodiments, the first interconnect layer 1006 can include the conductors 1028a and / or the vias 1028b, as shown. The conductors 1028a of the first interconnect layer 1006 can be coupled to contacts (e.g., the S / D contacts 1024) of the device layer 1004. The vias 1028b of the first interconnect layer 1006 can be coupled to the conductors 1028a of a second interconnect layer 1008. The second interconnect layer 1008 (referred to as metal 2 or “M2”) can be formed directly on the first interconnect layer 1006. In some embodiments, the second interconnect layer 1008 can include a via 1028b to couple the interconnect structures 1028 of the second interconnect layer 1008 to the conductors 1028a of a third interconnect layer 1010. Although the conductors 1028a and the vias 1028b are structurally separated by a line within individual interconnect layers for clarity, in some embodiments the conductors 1028a and the vias 1028b can be structurally and / or materially related (e.g., filled simultaneously during a dual-damascene process). The third interconnect layer 1010 (designated as metal 3 or “M3”) (and, if required, additional interconnect layers) can be formed sequentially on the second interconnect layer 1008 according to similar techniques and configurations described in connection with the second interconnect layer 1008 or the first interconnect layer 1006. In some embodiments, the interconnect layers located “higher up” in the metallization stack 1019 in the integrated circuit 1000 (i.e., farther from the device layer 1004) can be thicker than the interconnect layers located lower down in the metallization stack 1019, with the conductors 1028a and the vias 1028b in the higher interconnect layers being thicker than those in the lower interconnect layers. The integrated circuit 1000 can include solder mask material 1034 (for example, polyimide or a similar material) and one or more conductive contacts 1036 formed on the interconnection layers 1006-1010. In Fig. 10, the conductive contacts 1036 are illustrated to take the form of bond contact patches. The conductive contacts 1036 can be electrically coupled to the interconnection structures 1028 and configured to conduct the electrical signals from the transistor(s) 1040 to external devices. For example, solder joints can be formed on the one or more conductive contacts 1036 to mechanically and / or electrically couple an integrated circuit die containing the integrated circuit 1000 to another component (e.g., a printed circuit board).The integrated circuit 1000 may include additional or alternative structures to conduct the electrical signals from the interconnection layers 1006-1010; for example, the conductive contacts 1036 may include other analog features (e.g., pins) that conduct the electrical signals to external components. In some embodiments where the integrated circuit 1000 is a double-sided die, the integrated circuit 1000 may include an additional (not shown) metallization stack on the opposite side of the one or more device layers 1004. This metallization stack may include several interconnection layers, as discussed above with reference to the interconnection layers 1006-1010, to provide electrically conductive paths (e.g., including conductive traces and vias) between the one or more device layers 1004 and (not shown) additional conductive contacts on the side of the integrated circuit 1000 opposite the conductive contacts 1036. In other embodiments, where the integrated circuit 1000 is a double-sided die, the integrated circuit 1000 may include one or more silicon vias (TSVs) through the die substrate 1002; these TSVs may make contact with the one or more device layers 1004 and may provide electrically conductive paths between the one or more device layers 1004 and (not shown) additional conductive contacts on the side of the integrated circuit 1000 opposite the conductive contacts 1036.In some embodiments, TSVs extending through the substrate can be used to conduct power and ground signals from conductive contacts on the opposite side of the integrated circuit 1000 from the conductive contacts 1036 to the transistors 1040 and any other components integrated into the integrated circuit 1000, and the metallization stack 1019 can be used to forward I / O signals from the conductive contacts 1036 to the transistors 1040 and any other components integrated into the integrated circuit 1000. Multiple integrated circuits (ICCs) can be stacked with one or more interconnects (TSVs) in each stacked device, providing a connection between any one of the devices and any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die, and TSVs in the HBM dies can provide a connection between the individual HBM die and the base integrated circuit die. Conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine-pitch solder bumps (micro-bumpers). Fig. 11 is a cross-sectional side view of a microelectronic assembly 1100, which may include any of the embodiments disclosed herein. The microelectronic assembly 1100 comprises several integrated circuit components arranged on a printed circuit board 1102 (which may be a motherboard, a system board, a main board, etc.). The microelectronic assembly 1100 may include components arranged on a first surface 1140 of the printed circuit board 1102 and on an opposing second surface 1142 of the printed circuit board 1102; generally, components may be arranged on one or both surfaces 1140 and 1142. In some embodiments, the circuit board 1102 can be a printed circuit board (PCB) comprising several metal layers (or interconnect layers) separated from one another by layers of a dielectric material and interconnected by electrically conductive vias. The individual metal layers include conductive traces. One or more of the metal layers can be formed in a desired circuit pattern to conduct electrical signals (optionally in conjunction with other metal layers) between components coupled to the circuit board 1102. In some embodiments, the circuit board 1102 can be a non-PCB substrate. The microelectronic assembly 1100 illustrated in Fig. 11 includes a package-on-intermediate-support structure 1136 coupled to the first surface 1140 of the circuit board 1102 by coupling components 1116.The coupling components 1116 can electrically and mechanically couple the housing-on-intermediate-carrier structure 1136 to the printed circuit board 1102 and can comprise solder balls (as shown in Fig. 11), pins (e.g. as part of a pin grid arrangement (PGA)), contacts (e.g. as part of a contact patch arrangement (LGA)), plug and socket sections of a socket, an adhesive, a backing material and / or any other suitable electrical and / or mechanical coupling structure. The package-on-intermediate-carrier structure 1136 can include an integrated circuit component 1120, which is coupled to an intermediate carrier 1104 by coupling components 1118. The coupling components 1118 can take any shape suitable for the application, such as the shapes discussed above with reference to the coupling components 1116. Although a single integrated circuit component 1120 is shown in Fig. 11, several integrated circuit components can be coupled to the intermediate carrier 1104; in fact, additional intermediate carriers can be coupled to the intermediate carrier 1104. The intermediate carrier 1104 can provide an intermediate substrate that forms a bridge between the printed circuit board 1102 and the integrated circuit component 1120. The integrated circuit component 1120 can be an encapsulated or unencapsulated integrated circuit component comprising one or more integrated circuit dies (for example, the die 902 of Fig. 9, the integrated circuit 1000 of Fig. 10) and / or one or more other suitable components. The unencapsulated integrated circuit component 1120 comprises solder pads that are attached to the contacts on the die. The solder pads allow the die to be mounted directly onto the intermediate carrier 1104. In embodiments where the integrated circuit component 1120 comprises multiple integrated circuit dies, the dies can be of the same type (a homogeneous integrated circuit component on multiple dies) or of two or more different types (a heterogeneous integrated circuit component on multiple dies). In addition to comprising one or more processor units, the integrated circuit component 1120 can include additional components, such as an embedded DRAM, a stacked high-bandwidth memory (HBM), shared buffers, input / output (I / O) controllers, or memory controllers.Any of these additional components may reside on the same integrated circuit die as a processor unit, or on one or more integrated circuit dies separate from the integrated circuit dies containing the processor units. These separate integrated circuit dies may be referred to as "chiplets." In embodiments where an integrated circuit component comprises multiple integrated circuit dies, connections between the dies may be provided by the package substrate, one or more silicon intermediate supports, one or more silicon bridges embedded in the package substrate, or combinations thereof. An encapsulated multi-die integrated circuit component may be referred to as a multi-chip package (MCP) or multi-chip module (MCM). The intermediate carrier 1104 can spread connections to a larger grid spacing or redirect one connection to another. For example, the intermediate carrier 1104 can couple the component of an integrated circuit 1120 to a set of conductive ball-grid array (BGA) contacts of the coupling components 1116 for coupling to the printed circuit board 1102. In the embodiment illustrated in Fig. 11, the integrated circuit component 1120 and the printed circuit board 1102 are mounted on opposite sides of the intermediate carrier 1104; in other embodiments, the integrated circuit component 1120 and the printed circuit board 1102 can be mounted on the same side of the intermediate carrier 1104. In some embodiments, three or more components can be interconnected by means of the intermediate carrier 1104. In some embodiments, the intermediate support 1104 can be formed as a PCB comprising several metal layers separated from one another by layers of a dielectric material and interconnected by electrically conductive vias. In some embodiments, the intermediate support 1104 can be formed from an epoxy resin, a glass-fiber-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material, such as polyimide. In some embodiments, the intermediate support 1104 can be formed from alternative rigid or flexible materials, which may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other Group III-V and Group IV materials.The intermediate carrier 1104 can have metal interconnects 1108 and vias 1110, including, but not limited to, through-hole vias 1110-1 (extending from a first face 1150 of the intermediate carrier 1104 to a second face 1154 of the intermediate carrier 1104), blind vias 1110-2 (extending from the first or second face 1150 or 1154 of the intermediate carrier 1104 to an internal metal layer) and buried vias 1110-3 (connecting internal metal layers). In some embodiments, the intermediate carrier 1104 may comprise a silicon intermediate carrier. Silicon vias (TSVs) extending through the silicon intermediate carrier may connect a first face of the silicon intermediate carrier to an opposite second face of the silicon intermediate carrier. In some embodiments, an intermediate carrier 1104 comprising a silicon intermediate carrier may further comprise one or more conduction layers to conduct connections on a first face of the intermediate carrier 1104 to an opposite second face of the intermediate carrier 1104. The intermediate support 1104 can further include embedded devices 1114, which comprise both passive and active devices. Such devices can include, among others, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and storage devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, can also be formed on the intermediate support 1104. The package-on-intermediate-support structure 1136 can assume the form of any package-on-intermediate-support structure known in the art. The integrated circuit assembly 1100 can include an integrated circuit component 1124, which is coupled to the first surface 1140 of the printed circuit board 1102 by coupling components 1122. The coupling components 1122 can take the form of any of the embodiments discussed above with reference to the coupling components 1116, and the component of an integrated circuit 1124 can take the form of any of the embodiments discussed above with reference to the component of an integrated circuit 1120. The integrated circuit assembly 1100 illustrated in Fig. 11 comprises a case-on-case structure 1134, which is coupled to the second surface 1142 of the printed circuit board 1102 by coupling components 1128. The case-on-case structure 1134 can include an integrated circuit component 1126 and an integrated circuit component 1132, which are coupled to each other by coupling components 1130 such that the integrated circuit component 1126 is located between the printed circuit board 1102 and the integrated circuit component 1132. The coupling components 1128 and 1130 can take the form of any embodiment of the coupling components 1116 discussed above, and the integrated circuit components 1126 and 1132 can take the form of any embodiment of the integrated circuit component 1120 discussed above.The case-on-case structure 1134 can be configured according to any case-on-case structure known in the art. Fig. 12 is a block diagram of an exemplary electrical device 1200, which may include one or more of the embodiments disclosed herein. For example, any suitable components of the electrical device 1200 may comprise one or more of the microelectronic assemblies 1100, integrated circuit components 1120, integrated circuits 1000, or integrated circuit dies 902 or structures disclosed herein. A number of components are illustrated in Fig. 12 as being included in the electrical device 1200; however, any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in the electrical device 1200 may be mounted on one or more motherboards, mainboards, printed circuit boards, or system boards.In some embodiments, one or more of these components can be manufactured on a single system-on-a-chip die (SoC die). In various embodiments, the electrical device 3000 is enclosed by or integrated into a housing. Furthermore, in various embodiments, the electrical device 1200 may not include any of the components illustrated in Fig. 12, but the electrical device 1200 may have an interface circuit for coupling to one or more of the components. For example, the electrical device 1200 may not include a display device 1206, but may include a display device interface circuit (e.g., a connector and a driver circuit) to which a display device 1206 can be coupled. In another set of examples, the electrical device 1200 may not include an audio input device 1224 or an audio output device 1208, but may include an audio input or output device interface circuit (e.g., a connector and a driver circuit)connectors and a support circuit) to which an audio input device 1224 or an audio output device 1208 can be coupled. The electrical device 1200 can comprise one or more processor units 1202 (for example, one or more processor units). As used herein, the term "processor unit", "processing unit", or "processor" can refer to any device or any part of a device that processes electronic data from registers and / or from a memory in order to transform such electronic data into other electronic data that can be stored in registers and / or a memory.The 1202 processor unit can include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processing units (DPUs), accelerators (for example, graphics accelerators, compression accelerators, artificial intelligence accelerators), control cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, controllers, or any other suitable type of processor unit. Therefore, the processor unit can be referred to as an XPU (or xPU). The electrical device 1200 can include a memory 1204, which itself can comprise one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memory), solid-state memory, and / or a hard disk. In some embodiments, the memory 1204 can include memory located on the same integrated circuit die as the processor unit 1202. This memory can be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last-Level Cache (LLC)) and can include embedded dynamic random access memory (eDRAM) or magnetic spin transfer torque random access memory (STT-MRAM). In some embodiments, the electrical device 1200 may comprise one or more processor unit(s) 1202 that are heterogeneous or asymmetric with respect to another processor unit 1202 in the electrical device 1200. There may be a multitude of differences between the processor units 1202 in a system with respect to a range of performance metrics, including architectural, microarchitecture, thermal, energy consumption characteristics, and the like. These differences may effectively manifest as an asymmetry and heterogeneity among the processor units 1202 in the electrical device 1200. In some embodiments, the electrical device 1200 may include a communication component 1212 (e.g., one or more communication components). For example, the communication component 1212 may manage wireless communications for the transmission of data to and from the electrical device 1200. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that communicate data through a non-solid medium using modulated electromagnetic radiation. The term "wireless" does not imply that the associated devices do not contain wires, although in some embodiments they may not. The 1212 communication component can implement any number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (for example, IEEE 802.16-2005 Supplement), Long-Term Evolution (LTE) project along with any supplements, updates and / or revisions (for example, Advanced LTE Project, Ultra-Mobile Broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16-compliant Broadband Wireless Access (BWA) networks are commonly referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, a mark of approval for products that pass compliance and interoperability tests for the IEEE 802.16 standards.The 1212 communication component can operate according to a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The 1212 communication component can operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The 1212 communication component can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols referred to as 3G, 4G, 5G, and beyond. The communication component 1212 can operate according to other wireless protocols in other embodiments.The electrical device 1200 can include an antenna 1222 to facilitate wireless communications and / or to receive other wireless communications (such as AM or FM radio transmissions). In some embodiments, the communication component 1212 can manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., IEEE 802.3 Ethernet standards). As mentioned above, the communication component 1212 can include multiple communication components. For example, a first communication component 1212 can be dedicated to wireless communications at closer range, such as Wi-Fi or Bluetooth, and a second communication component 1212 can be dedicated to wireless communications at more distant ranges, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication component 1212 can be dedicated to wireless communications, and a second communication component 1212 can be dedicated to wired communications. The electrical device 1200 can include a battery / power circuit 1214. The battery / power circuit 1214 can include one or more energy storage devices (e.g., batteries or capacitors) and / or a circuit for coupling components of the electrical device 1200 to a power source that is separate from the electrical device 1200 (e.g., AC mains power). The electrical device 1200 can include a display device 1206 (or a corresponding interface circuit, as discussed above). The display device 1206 can include one or more embedded or wired or wirelessly connected external optical indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display. The electrical device 1200 can include an audio output device 1208 (or a corresponding interface circuit, as discussed above). The audio output device 1208 can include any embedded, wired, or wireless device that produces an audible indicator, such as a loudspeaker, headphones, or earphones. The electrical device 1200 may include an audio input device 1224 (or a corresponding interface circuit, as discussed above). The audio input device 1224 may include any embedded, wired, or wireless device that generates a signal representing sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments with a Musical Instrument Digital Interface (MIDI) output). The electrical device 1200 may include a global navigation satellite system (GNSS) device 1218 (or a corresponding interface circuit arrangement, as discussed above), such as a global positioning system (GPS) device.The GNSS device 1218 can communicate with a satellite-based system and can determine a geographic location of the electrical device 1200 based on information received from one or more GNSS satellites, as is known in the prior art. The electrical device 1200 may include another output device 1210 (or a corresponding interface circuit arrangement, as discussed above). Examples of the other output device 1210 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for supplying information to other devices, or an additional storage device. The electrical device 1200 may include another input device 1220 (or a corresponding interface circuit arrangement, as discussed above). Examples of the other input device 1220 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., a monoscopic or stereoscopic camera), a trackball, a trackpad, a touch panel, a keyboard, a cursor control device such as a mouse, a stylus, a touchscreen, a proximity sensor, a microphone, a barcode reader, a quick-response (QR) code reader, an electrocardiogram sensor (ECG sensor), a photoplethysmogram (PPG) sensor, a galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader. The electrical device 1200 can have any desired form factor, such as a handheld or mobile electrical device (for example, a mobile phone, a smartphone, a mobile internet device, a music player, a tablet computer, a laptop computer, a convertible 2-in-1 computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable game console, etc.).), an electrical desktop device, a server, a rack-level computing solution (for example, blade, tray, or sled computing systems), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a home gaming console, a smart television, a vehicle control unit, a digital camera, a digital video recorder, an electrical wearable device, or an embedded computing system (for example, computing systems that are part of a vehicle, a smart home appliance, a consumer electronics product or equipment, or manufacturing equipment). In some embodiments, the electrical device 1200 can be any other electronic device that processes data. In some embodiments, the electrical device 1200 can comprise several discrete physical components.In view of the variety of devices that the electrical device 1200 can manifest itself in in different embodiments, the electrical device 1200 can be referred to as a calculating device or calculating system in some embodiments. Although at least one embodiment has been presented in the foregoing detailed description, it should be noted that a multitude of variations exist. It should also be noted that the disclosed embodiments are only examples and are not intended to limit the scope, applicability, or configuration of the disclosure in any way. Rather, the foregoing detailed description will provide those skilled in the art with a practical roadmap for implementing the disclosed exemplary embodiments. Various modifications can be made to the function and arrangement of elements without departing from the scope of the disclosure as set forth in the appended claims and their legal equivalents. As used herein, the term “electronic component” can refer to an active electronic circuit (for example, a processing unit, a memory, a storage device, FET) or a passive electronic circuit (for example, a resistor, an inductor, a capacitor). As used herein, the term "integrated circuit component" can refer to an electronic component configured on a semiconducting material to perform a function. An integrated circuit (IC) component may include one or more of any computing system components described or referenced herein, or any other computing system component, such as a processing unit (for example, system-on-a-chip (SoC), processor core, graphics processing unit (GPU), accelerator, chipset processor), I / O control, memory, or network interface control, and may include one or more additional active or passive devices such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and storage devices. A non-restrictive example of an unencapsulated integrated circuit component includes a single monolithic integrated circuit die; the die may include solder pad mounds attached to contacts on the die. The solder pad mounds, or other conductive contacts, if present on the die, may allow direct attachment of the die to a printed circuit board (PCB) or other substrates. A non-restrictive example of an encapsulated integrated circuit component comprises one or more integrated circuit dies mounted on a package substrate, with the integrated circuit dies and the package substrate being encapsulated in an enclosure material, such as metal, plastic, glass, or ceramic. The enclosure often includes an integrated heat spreader (IHS). The encapsulated integrated circuit component frequently has contact bumps, leads, or pins that are attached to the package substrate (either directly or via wires that secure the contact bumps, leads, or pins to the package substrate) to mount the encapsulated integrated circuit component to a printed circuit board (or mainboard or baseboard) or other component. As used herein, terms such as “one embodiment,” “different embodiments,” “some embodiments,” and the like indicate that some embodiments may have some, all, or none of the features described for other embodiments. “First,” “second,” “third,” and the like describe a common object and indicate different instances of similar objects being referred to; unless expressly stated otherwise, they do not imply any particular sequence, either temporal or spatial, in terms of precedence or in any other way. In accordance with the terminology used in the patent application, “connected” refers to elements that are in direct physical or electrical contact with one another, and “coupled” refers to elements that cooperate or interact with one another; coupled elements may or may not be in direct physical or electrical contact.Furthermore, the terms “comprehensive”, “exhibiting”, “with” and the like are used synonymously to denote non-exclusive inclusions. As used in this description and in the claims, a list of objects joined by the phrase "at least one of" or "one or more of" can mean any combination of the listed terms. For example, the phrase "at least one of A, B, or C" can mean A; B; C; A and B; A and C; B and C; or A, B, and C. Likewise, the phrase "one or more of A, B, or C" can mean A; B; C; A and B; A and C; B and C; or A, B, and C. As used in this application and the claims, the phrase “a single one of” or “a respective one of”, followed by a list of elements that have been named or specified as having a property, feature, etc., means that all elements in the list have the specified or named property, feature, etc. For example, the phrase “single ones of A, B or C comprising a side wall” or “respective ones of A, B or C comprising a side wall” means that A comprises a side wall, B comprises a side wall and C comprises a side wall. Operating theories, scientific principles, or other theoretical descriptions presented herein with reference to the devices or methods of this disclosure are provided for convenience only and are not intended to limit the scope. The devices and methods in the accompanying claims are not limited to those devices and methods that function in the manner described by such operating theories. The following examples relate to additional embodiments of the technologies disclosed herein. EXAMPLES Example 1 is a device comprising: a first die comprising a top surface with a first set of first conductive terminals in a first region and a second set of first conductive terminals in a second region; a second die on the first region; a third die on the second region; a plurality of first conductive contacts for attaching the second die in the first region to the first conductive terminals and for attaching the third die in the second region to the second set of conductive terminals; a glass layer with multiple glass vias and a cavity formed in a cover surface; wherein the first die is located in the cavity; wherein the second die extends over the cover surface and is attached to the cover surface by a first set of second conductive contacts;and wherein the third die extends over the cover surface and is attached to the cover surface by a second set of the second conductive contacts; wherein the plurality of first conductive contacts has a smaller pitch than the second conductive contacts. Example 2 includes the subject of Example 1, where the first die is an input / output die comprising an active circuit layer on a silicon substrate. Example 3 includes the subject of Example 1 or Example 2, wherein the second die is an integrated circuit die and the third die is another integrated circuit die. Example 4 includes the subject of Example 1 or Example 2, wherein the second die or the third die is a central processing unit or a graphics processing unit. Example 5 includes the subject of Example 1 or one of Examples 2-4, wherein the plurality of first conductive contacts comprises solder contact mounds defined by a first grid dimension in a range of 25 micrometers to 55 micrometers + / - 10%. Example 6 includes the subject of Example 5, wherein the second conductive contacts also include solder and are defined by a second grid dimension > 90 micrometers + / - 10%. Example 7 includes the subject matter of Example 1 or one of Examples 2-6, further comprising an organic build-up layer on a base surface of the glass layer, wherein the organic build-up layer comprises a dielectric material with one or more conductor tracks therein. Example 8 contains the subject matter of Example 7, further comprising: a plurality of solder balls on a lower surface of the organic build-up layer; and at least one electrical path from the first die to a solder ball. Example 9 includes the subject matter of Example 8, which further comprises a printed circuit board attached to the plurality of solder balls. Example 10 includes the object of Example 8, which further comprises a form and underfill material surrounding the second die and the third die on the upper surface of the glass layer. Example 11 includes the subject of Example 1 or one of Examples 2-10, wherein the glass layer has a thickness in the range of 20 micrometers + / - 5 micrometers to 1.5 millimeters + / - 5 micrometers. Example 12 includes the subject of Example 2, wherein: the silicon in the input / output die comprises silicon vias (TSVs); and at least some of the TSVs serve to electrically couple the active circuit layer to a bottom surface of the glass layer. Example 13 is a multi-die assembly comprising: a glass layer with multiple glass vias extending from a top face to a bottom face, and a cavity formed in the top face; a first die in the cavity, the first die comprising a top surface with a plurality of first conductive termination fields arranged in a first set in a first region and a second set in a second region; a second die on the top face of the glass layer and on the first region; a third die on the top face of the glass layer and on the second region;a plurality of first conductive contacts, wherein some of the plurality of first conductive contact fields are electrically coupled to the second die via a first conductive contact in the first region, and a remainder of the plurality of first conductive contact fields are electrically coupled to the third die in the second region via another first conductive contact; wherein the second die is attached to the top surface by a first set of second conductive contacts; wherein the third die is attached to the top surface by a second set of second conductive contacts; wherein the plurality of first conductive contacts has a smaller pitch than the second conductive contacts; and an organic build-up layer on the bottom surface. Example 14 contains the subject matter of Example 13, further comprising: a plurality of solder balls on a lower surface of the organic build-up layer; and at least one electrical path from the second die or from the third die to a solder ball. Example 15 includes the subject of Example 13, where the first die is an input / output die comprising an active circuit layer on a silicon substrate. Example 16 includes the subject of Example 13, wherein the second die or the third die is a central processing unit or a graphics processing unit. Example 17 includes the subject of Example 13, wherein the plurality of first conductive contacts comprises solder contact mounds defined by a first grid dimension in a range of 25 micrometers to 55 micrometers + / - 10%, and the second conductive contacts also comprise solder and are defined by a second grid dimension > 90 micrometers + / - 10%. Example 18 is a method comprising: fabricating a glass substrate to accommodate a plurality of glass through-hole vias (TGVs) and a cavity in a top surface; attaching an active input / output (I / O) die to a bottom of the cavity, with a top surface of the I / O die exposed on the top surface; filling the TGVs with copper; attaching a first integrated circuit die to the top surface and to a first region of the top surface of the I / O die; and attaching a second integrated circuit die to the top surface and to a second region of the top surface of the I / O die. Example 19 includes the subject matter of Example 18, further comprising: using a Die Attach Film (DAF) to attach the active input / output die to the bottom of the cavity; and laser cleaning the DAF from the TGVs prior to filling the TGVs with copper. Example 20 includes the subject matter of Example 19, further comprising: mounting the first integrated circuit die and the second integrated circuit die on the top surface with a first grid size of solder contact bumps; and mounting the first integrated circuit die and the second integrated circuit die on the top surface of the I / O die with a second grid size of solder contact bumps that is smaller than the first grid size.

Claims

Device comprising: a first die comprising a top surface with a first set of first conductive terminals in a first region and a second set of first conductive terminals in a second region; a second die on the first region; a third die on the second region; a plurality of first conductive contacts for attaching the second die in the first region to the first conductive terminals and for attaching the third die in the second region to the second set of conductive terminals; a glass layer with multiple glass vias and a cavity formed in a cover surface; wherein the first die is located in the cavity; wherein the second die extends over the cover surface and is attached to the cover surface by a first set of second conductive contacts;and wherein the third die extends over the top surface and is attached to the top surface by a second set of second conductive contacts; wherein the plurality of first conductive contacts has a smaller pitch than the second conductive contacts.; Device according to claim 1, wherein the first die is an input / output die comprising an active circuit layer on a silicon substrate. Device according to claim 2, wherein: the silicon substrate in the input / output die comprises silicon vias (TSVs); and at least some of the TSVs serve to electrically couple the active circuit layer to a bottom surface of the glass layer. Device according to one of claims 1-3, wherein the second die is an integrated circuit die and the third die is another integrated circuit die. Device according to one of claims 1-3, wherein the second die or the third die is a central processing unit or a graphics processing unit. Device according to one of claims 1-5, wherein the plurality of first conductive contacts comprises solder contact mounds defined by a first grid dimension in a range of 25 micrometers to 55 micrometers + / - 10%. Device according to claim 6, wherein the second conductive contacts also comprise solder and are defined by a second grid dimension > 90 micrometers + / - 10%. Device according to one of claims 1-7, further comprising an organic build-up layer on a base surface of the glass layer, wherein the organic build-up layer comprises a dielectric material with one or more conductor tracks therein. The apparatus of claim 8, further comprising: a plurality of solder balls on a lower surface of the organic build-up layer; and at least one electrical path from the first die to a solder ball. Device according to claim 9, further comprising a circuit board attached to the plurality of solder balls. Device according to one of claims 9-10, further comprising a form and underfill material surrounding the second die and the third die on the upper surface of the glass layer. Device according to one of claims 1-11, wherein the glass layer has a thickness in the range of 20 micrometers + / - 5 micrometers to 1.5 millimeters + / - 5 micrometers. A multi-die assembly comprising: a glass layer with multiple glass vias extending from a top face to a bottom face, and a cavity formed in the top face; a first die in the cavity, the first die comprising a top surface with a plurality of first conductive termination fields arranged in a first set in a first region and a second set in a second region; a second die on the top face of the glass layer and on the first region; a third die on the top face of the glass layer and on the second region;a plurality of first conductive contacts, wherein some of the plurality of first conductive contact fields are electrically coupled to the second die via a first conductive contact in the first region, and a remainder of the plurality of first conductive contact fields are electrically coupled to the third die in the second region via another first conductive contact; wherein the second die is attached to the top surface by a first set of second conductive contacts; wherein the third die is attached to the top surface by a second set of second conductive contacts; wherein the plurality of first conductive contacts has a smaller pitch than the second conductive contacts; and an organic build-up layer on the bottom surface. Multi-die assembly according to claim 13, further comprising: a plurality of solder balls on a lower surface of the organic build-up layer; and at least one electrical path from the second die or from the third die to a solder ball. Multi-die assembly according to one of claims 13-14, wherein the first die is an input / output die comprising an active circuit layer on a silicon substrate. Multi-die assembly according to one of claims 13-15, wherein the second die or the third die is a central processing unit or a graphics processing unit. Multi-die assembly according to one of claims 13-16, wherein the plurality of first conductive contacts comprises solder contact mounds defined by a first grid dimension in a range of 25 micrometers to 55 micrometers + / - 10%, and the second conductive contacts also comprise solder and are defined by a second grid dimension > 90 micrometers + / - 10%. Method comprising: Fabricating a glass substrate to accommodate a plurality of glass through-hole vias (TGVs) and a cavity in a top surface; Attaching an active input / output (I / O) die to a bottom of the cavity, with a top surface of the I / O die exposed at the top surface; Filling the TGVs with copper; Attaching a first integrated circuit die to the top surface and to a first region of the top surface of the I / O die; and Attaching a second integrated circuit die to the top surface and to a second region of the top surface of the I / O die. The method of claim 18, further comprising: using a die attach film (DAF) to attach the active input / output die to the bottom of the cavity; and laser cleaning the DAF from the TGVs before filling the TGVs with copper. The method of claim 19, further comprising: mounting the first integrated circuit die and the second integrated circuit die on the upper surface with a first grid spacing of solder contact bumps; and mounting the first integrated circuit die and the second integrated circuit die on the top surface of the I / O die with a second grid spacing of solder contact bumps that is smaller than the first grid spacing.

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