High-voltage delta-sigma modulator analog-to-digital converter

Abstract

A delta-sigma modulator (DSM) analog-to-digital converter (ADC) and a method for operating it are provided. In general, the ADC comprises an input stage to receive an analog input voltage, a second-order DSM coupled to the input stage (the DSM comprising a first integrator stage and a second integrator stage coupled in a cascade architecture), and a quantizer coupled to an output of the DSM, which can be operated to receive an output from it and generate a multi-bit digital signal.The ADC has a fully differential architecture, wherein the input stage couples a positive input voltage and a negative input voltage to an integrator in the first integrator stage, wherein the first integrator stage couples a first positive output signal and a first negative output signal to a second integrator in the second integrator stage, and the second integrator stage couples a second positive output signal and a second negative output signal to the quantizer.

Description

TECHNICAL AREA

[0001] This disclosure relates generally to analog-to-digital converters (ADCs) for battery management system applications and in particular to high-voltage delta-sigma modulator ADCs (ΔΣADCs) and methods for operating them. BACKGROUND

[0002] An analog-to-digital converter (ADC) is an electronic circuit or device circuit that converts an analog voltage or waveform into a discrete digital representation or sequence. ADCs are essential components or blocks of many devices and systems, including, for example, battery monitoring or management systems (BMS) used in battery-powered electric vehicles. Several different types of conventional ADCs can be used in these applications, including integrating ADCs, successive approximation register (SAR) ADCs, and delta-sigma ADCs. Other types of high-speed ADCs exist, such as flash and pipeline ADCs; however, cost constraints, power requirements, and the size limitations imposed by integrated circuits (ICs) restrict their usefulness in many mobile applications, including automotive and portable wireless devices.

[0003] Furthermore, there are a number of problems with existing or conventional ADCs, including an insufficient effective number of bits (ENOB) and electromagnetic compatibility (EMC) problems, such as susceptibility to electromagnetic interference (EMI) due to the unintentional generation, propagation and reception of electromagnetic energy in the environment in which they are used.

[0004] The ENOB (Enhanced Optical Constraint) indicates the number of bits an ADC requires to effectively represent an analog value and is commonly used as a measure of the ADC's resolution and dynamic range. Ideally, a 16-bit ADC would have an ENOB of nearly 16. However, due to noise and distortion introduced by imperfect components in the ADC and the system in which it is used, the effective number of precision bits in a real ADC is significantly lower. Thus, a 16-bit ADC may have an ENOB of 12 or less.

[0005] Accordingly, there is a need for an improved ADC and a method for operating it to increase the ENOB while simultaneously reducing susceptibility to EMI problems and power consumption. Furthermore, it is desirable that the new ADC meets size and cost requirements for use in mobile applications. SUMMARY

[0006] A delta-sigma modulator analog-to-digital converter (ΔΣADC) and a method for operating it are disclosed to increase the effective number of bits (ENOB) while simultaneously reducing susceptibility to EMI problems and power consumption. The ΔΣADC includes an input stage that can be operated to provide an analog input voltage (VA). INThe ΔΣADC has a fully differential architecture, with the input stage coupling a positive input signal (inp) and a negative input signal (inn) to an integrator in the first integrator stage, the first integrator stage coupling a first positive output signal (op1) and a first negative output signal (on1) to a second integrator in the second integrator stage, and the second integrator stage coupling a second positive output signal (op2) and a second negative output signal (on2) to the quantizer.The fully differential architecture allows the ΔΣADC to minimize potential electromagnetic compatibility (EMC) problems.

[0007] In general, the input stage and the first integrator stage can be operated to perform correlated double sampling on the positive input signal (inp) and the negative input signal (inn) to eliminate any unwanted offset in the analog input voltage (V). IN ) to remove. Additionally, the first integrator stage further comprises a number of chopper circuits that can be operated to remove any residual offset in V. IN to remove.

[0008] In some embodiments, the input stage includes a high-voltage interface (HVIF) to enable the ΔΣADC to support voltages of 120 VDC or more.

[0009] The ΔΣADC is particularly useful in an integrated battery management system (BMS) configured to monitor the voltages of a large number of battery cells connected in series.

[0010] Further features and advantages of embodiments of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. It should be noted that the invention is not limited to the specific embodiments described herein. Such embodiments are presented here for illustrative purposes only. Additional embodiments will be apparent to a person skilled in the relevant field(s) based on the teachings contained herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments of the invention are now described only by way of example with reference to the accompanying schematic drawings, in which corresponding reference numerals indicate corresponding parts. Furthermore, the accompanying drawings included herein and forming part of the description illustrate embodiments of the present invention and, together with the description, also serve to explain the principles of the invention and to enable a person skilled in the relevant field(s) to manufacture and use the invention. Fig. Figure 1 is a schematic diagram illustrating an embodiment of a second-order delta-sigma modulator analog-to-digital converter (ΔΣADC); Fig. 2 is a timing diagram showing different signals for the operation of the ΔΣADC of Fig. 1 illustrates; Fig. 3 is a flowchart that shows a procedure for operating the ΔΣADC of Fig. 1 illustrates; Fig. 4A and Fig. 4B are graphs that compare the rest tone of a ΔΣADC with a first-order DSM and of a ΔΣADC with a second-order DSM; Fig. 5A- Fig. Figure 5C are graphs illustrating the rest tone of a second-order DSM with an input step size of 20 µV for various oversampling ratios (OSR); Fig. 6A is a block diagram showing an embodiment of a high-voltage interface (HVIF) for use in the ΔΣADC of Fig. 1 illustrates; Fig. 6B is a schematic diagram showing an embodiment of one side or half of the HVIF of Fig. 6A illustrates; Fig. 7A is a timing diagram showing the operation of the HVIF of Fig. 6A and Fig. 6B in the ΔΣADC of Fig. 1 for a battery voltage VBAT illustrated in 5 V; Fig. 7B is a time diagram showing the operation of the HVIF by Fig. 6A and Fig. 6B in the ΔΣADC of Fig. 1 for a battery voltage V BAT illustrated in -2 V; Fig. Figure 8 is a schematic block diagram showing charge pump outputs for the HVIF of Fig. 6A and Fig. 6B illustrates the situation at V BAT can be operated from 5 V and -2 V; and Fig. 9 is a block diagram illustrating a battery management system (BMS) that controls a number of ΔΣADCs from Fig. 1 includes. DETAILED DESCRIPTION

[0012] A switched capacitor delta-sigma modulator analog-to-digital converter (ΔΣADC) and a method for operating the same to convert a multi-bit binary number corresponding to an analog input voltage (V) INThe methods for approximating, converting, or providing an output are disclosed. The ΔΣADC and the method of the present disclosure provide a high effective number of bits (ENOB) and high throughput while minimizing potential electromagnetic compatibility (EMC) problems and reducing the area required for implantation in an integrated circuit (IC), making the ΔΣADC particularly useful in an integrated battery management system (BMS) configured to monitor the voltages of a plurality of battery cells connected in series.

[0013] In general, the ΔΣADC includes an input stage that can be operated to provide an analog input voltage (V). INThe ΔΣADC has a fully differential architecture, with the input stage coupling a positive input signal (inp) and a negative input signal (inn) to an integrator in the first integrator stage, the first integrator stage coupling a first positive output signal (op1) and a first negative output signal (on1) to a second integrator in the second integrator stage, and the second integrator stage coupling a second positive output signal (op2) and a second negative output signal (on2) to the quantizer.The fully differential architecture allows the ΔΣADC to minimize potential problems of the EMC.

[0014] In some embodiments, the input stage and the first integrator stage can be operated to perform correlated double sampling on the positive input signal (inp) and the negative input signal (inn) to achieve an offset in V IN to remove. Additionally, the first integrator stage also includes a chopper circuit that can be operated to remove any residual offset in V. IN to remove the input stage, which is coupled to the first integrator stage.

[0015] Embodiments of the ΔΣADC and methods for operating them will now be described in more detail with reference to the Fig. 1 to Fig. 5 described.

[0016] Fig. Figure 1 is a schematic diagram illustrating an embodiment of a second-order delta-sigma modulator analog-to-digital converter (ΔΣADC). With reference to Fig. 1 The ΔΣADC 100 includes an input stage 102 which can be operated to provide an analog input voltage (V IN The ΔΣADC 100 includes a second-order delta-sigma modulator (DSM 104) comprising a first integrator stage 106 and a second integrator stage 108 coupled in a cascade architecture, and a quantizer 110 coupled to the output of the DSM 104, which can be operated to generate and output a multi-bit digital signal. The ΔΣADC 100 further includes a sampling clock and control circuit (Clk / Cntrl 112) to control the operation of switches in the ΔΣADC and a chopper circuit.

[0017] The input stage 102 includes an input interface 114, which comprises a pair of sampling or first input capacitors (Cin1) with input nodes coupled to input terminals by sampling switches (S1, S2, S3, S4) to provide V IN to receive. Switches S1, S2, S3, and S4 are controlled by P1 and P2 signals from the Clk / Cntrl 112. The input stage 102 also includes a pair of digital-to-analog converter (DAC) capacitors (C DAC ) with input nodes that are alternately coupled to a high reference voltage (Vrefh) and a low reference voltage (Vrefl) by reference switches (S5, S6, S7, S8), and output nodes that are coupled to output nodes of the first input capacitors (Cin1) and to input nodes of the first integrator stage 106 in the second order DSM 104.

[0018] Switches S6 and S7 are turned on or closed by the product of a first signal P1 of the sampling clock (Clk / Cntrl 112) and the results of a previous quantization (D), and turned off or opened by the product of a second signal P2 of the sampling clock and the results of a subsequent quantization (Db). Similarly, switches S5 and S7 are turned on by the product of the second signal P2 and the results of a previous quantization (D), and turned off by the product of the first signal P1 and the results of a subsequent quantization (Db). The difference between the reference voltages Vrefl and Vrefh defines a range of valid V IN -Inputs into the ΔΣADC 100.

[0019] The first integrator stage 106 comprises a first integrator 116 with fully differential outputs and a common-mode voltage input (vcm) to integrate the first integrator of variations in a common-mode voltage in V INto isolate. The first integrator stage 106 further comprises a chopper circuit pair CH1 / CH2 coupled between the inputs and outputs of the first integrator 116, and first integrating or feedback capacitors (Cf1) coupled in series with feedback switches (S9, S10) between each input and an associated output, and reset switches (S11, S12) coupled in parallel with the feedback capacitors (Cf1) and feedback switches (S9, S10). The feedback switches (S9, S10) are operated by a second signal P2e, where 'e' stands for an early meaning that this signal comes slightly before the clock P2 from the sampling clock (Clk / Cntrl 112) in order to turn on or off to begin the integration, and the reset switches (S11, S12) are operated by a first P1 early signal (P1e) to reset the first integrator 116 after a sampling or integration operation.

[0020] The first integrator 116 can be operated to calculate the integral of input voltage signals (Vp, Vn) and output signals (op1, on1), reflecting the cumulative effect of the input voltage signals (Vp, Vn) over time. As mentioned above, the fully differential architecture of the first integrator stage 106 minimizes potential electromagnetic compatibility (EMC) problems. Additionally, the fully differential architecture and common-mode voltage input (vcm) of the first integrator 116 essentially eliminate any offset of the first integrator, while the chopper circuit pair CH1 / CH2 removes any residual offset from the output signals (op1, on1).

[0021] The second integrator stage 108 is cascaded with the first integrator stage 106 via output switches of the first stage (S13, S14), which are switched on by the second signal from the sampling clock (Clk / Cntrl 112). The second integrator stage 108 comprises a pair of second input capacitors (Cin2), a second integrator 118 with fully differential outputs, a pair of first feedforward capacitors (Cff1) coupled between the input and output nodes of the second integrator stage 108, and a pair of second feedforward capacitors (Cff2) coupled between the outputs of the second integrator and the outputs of the second integrator stage 108 via output switches (S15, S16), which are switched on by the second signal from the sampling clock (Clk / Cntrl 112).The second integrator stage 108 further comprises second integration or feedback capacitors (Cf2) which are coupled in parallel with reset switches (S17, S18) between each input via switches (S25, S26) and a corresponding output of the second integrator 118. The reset switches (S17, S18) are turned on by a reset signal (RST) from the sampling clock (Clk / Cntrl 112) after a complete conversion of the analog input voltage into a binary multi-bit output signal (D, Db).

[0022] The second integrator stage 108 further comprises a number of common-mode voltage switches (S19-S24) that couple the input and output nodes of the second input capacitors (Cin2) and the second feedforward capacitors (Cff2) to the common-mode voltage in order to reset these capacitors between integration operations. Specifically, the input switches of the second stage (S13, S14) are turned on by a second signal (P2) from the sampling clock (Clk / Cntrl 112) to enable the integration of the first output signals (op1, on1) in the second integration stage 108, and the common-mode voltage switches S19, S20, S21, S22, S23, and S24 are turned on by the first signal (P1) of the sampling clock to reset the second integration stage 108 for the integration of subsequent signals from the first integration stage 106.

[0023] The quantizer 110 is coupled to the output of the second-order DSM 104 and can be operated to receive second positive and negative output signals (op2, on2) that reflect the cumulative effect of the first output signals (op1, on1) over time from the second integrator 118, and to generate a digital multi-bit signal (D, Db).

[0024] The operation of the ΔΣADC 100 by Fig. 1 will now be referred to with reference to the Fig. 2 and Fig. 3 described Fig. 2 is a time diagram of different signals, which are divided by the ΔΣADC of Fig. 1 are generated, and Fig. 3 is a flowchart illustrating a procedure for operating the ΔΣADC.

[0025] With reference to Fig. 2. Before time t0, a reset signal (dsm_rst_1v) is applied for approximately 20 clock cycles to reset switches (S17, S18) in the second integrator stage 108 to reset the second integrator 118 and feedback capacitors (Cf2). At time t0, a vcm input (vcm_good_1v) is applied to the first and second integrators 116 and 118.

[0026] With reference to Fig. 3. The procedure begins with the receipt of an analog input voltage (V). IN ) in an input stage in the ADC (step 302) and at time t1 applying the signal P1 to the switches S2 and S3 to V IN to couple with a first integrator stage in a second-order DSM (step 304). From time t1 to t3, the positive component of V IN (Vp) and the negative component of V IN(Vn) from the input stage is coupled to the second-order DSM and is integrated at time t2 using the first integrator stage with a signal from the sampling clock (Clk / Cntrl 112) (step 306). The signal from the sampling clock can either be a 4 MHz signal (clk4M) from the sampling clock and control circuit (Clk / Cntrl 112), as shown in Fig. 1 shown, or include a different main clock frequency, for example 5 MHz. As above with reference to Fig. As shown and described in Figure 1, the ΔΣADC has a fully differential architecture such that, at a time immediately before t1, the signal P1e applied to switches S11 and S12 enables the integration of the negative input signal (inn), and at a time immediately before t2, switches S11 and S12 are opened and the signal P2e is applied to switches S9 and S10 to enable the integration of the positive input signal (inp). Additionally, in some embodiments, such as the one in Figure 1, the ΔΣADC includes a fully differential architecture such that, at a time immediately before t1, the switches S11 and S12 are opened and the signal P2e is applied to switches S9 and S10 to enable the integration of the positive input signal (inp). Fig. 1 shown, the first integrator stage 106 further a chopper circuit CH1 / CH2, so that the coupling of V IN The first integrator stage 116 includes operating the chopper circuit to eliminate any residual offset in V IN to remove the input stage, which is coupled to the first integrator stage.

[0027] Next, results of the first integration of V will be presented. INThe first integrator stage 106 is coupled to a second integrator stage in the second-order DSM, which is connected to the first integrator stage via a cascade architecture (step 308). The coupling of the first integration of V IN The second integrator stage involves coupling a first positive output signal (op1) and a first negative output signal (on1) to a second integrator in the second integrator stage by applying signal P2 to switches S13 and S14. The first integration of V IN , which is coupled by the first integration stage, is then integrated using the second integrator stage with the sampling clock to perform a second integration of V INto generate (step 310). That is, the signal P2 applied to switches S17 and S18 enables a second or further integration of op1 immediately after which switches S17 and S18 are opened, and the signal P1 is applied to switches S25 and S26 to enable a second or further integration of op1. At this point, the signal P1 is also applied to switches S19 and S20 to couple vcm signals in order to isolate variations in the common-mode voltage from the input sides of capacitors Cin2.

[0028] Next, the second integration of V will be performed. IN from an output of the second-order DSM coupled with a quantizer in the ΔΣADC (step 312), and the quantization of the second integration of V IN is performed to generate a digital multi-bit signal that is used for V IN is representative (step 314). Coupling the second integration of V INThe quantizer operation involves coupling a second positive output signal (op2) and a second negative output signal (on2) to the quantizer via capacitors cff2 by applying signal p2 to switches S15 and S16. At the same time, signal P1 is applied to switches S21 to S24 to couple vcm signals, isolating common-mode voltage variations from capacitors cff2 and the quantizer. Generally, as mentioned above, the first integrator 116 and the second integrator 118 also each include a common-mode voltage input (vcm) to measure common-mode voltage variations in V. INto isolate the output (op2 and on2) to the quantizer 110. The output of the quantizer 110 is buffered by applying a p_Latch signal to store a first most significant bit (MSB) or first digit (D) of a digital multi-bit signal. The p_Latch signal is generated using an 8 MHz signal (clk8M) from the Clk / Cntrl 112 and has a pulse with a duty cycle equal to one-quarter of the main sampling clock signal (clk4M). The digit (D) is applied in conjunction with signals P1 and P2 to operate switches S5-S7 to alternately charge capacitors C. DAC The process involves applying high (Vrefh) and low (Vrefl) reference voltages, which prepare the 100 for the conversion of the next MSB of the digital multi-bit signal, starting at time t3. The process continues until the last bit or position of the digital multi-bit signal, i.e., position Db, has been resolved.

[0029] The advantages of a second-order DSM in a ΔΣADC are now discussed with reference to the Fig. 4A- Fig. 4B and Fig. 5A to Fig. 5C described.

[0030] Fig. 4A and Fig. 4B are graphs comparing the rest-tone or quantization noise for a ΔΣADC with a single first-order DSM and a ΔΣADC with a second-order DSM, as above with reference to Fig. Figure 1 shows and describes the data for both graphs. Data for both graphs were obtained using MATLAB software simulating ΔΣADC with a 1-bit quantizer and operating at an oversampling rate or oversampling ratio (OSR) of 1024. With reference to Fig. As shown in Figure 4A, for a ΔΣADC that includes a single first-order DSM, the ΔΣADC exhibits an in-band noise of up to approximately -65 dB. In contrast, with reference to Fig. 4B shows that for a ΔΣADC which includes a second-order DSM, the ΔΣADC has a maximum in-band noise of less than about -120 dB.

[0031] Fig. 5A- Fig. 5C are graphs illustrating the rest tone for a ΔΣADC with a second-order DSM and a simulated input step size of 20 µV for various OSRs. Fig. Figure 5A illustrates the in-band noise for a ΔΣADC with a second-order DSM operating at an OSR of 128. Fig. Figure 5B illustrates the in-band noise for a ΔΣADC with a second-order DSM operating at an OSR of 256, and Fig. Figure 5C illustrates the in-band noise for a ΔΣADC with a second-order DSM operating at an OSR of 512. Thus, it is evident that for a ΔΣADC with a second-order DSM, as above with reference to Fig. As shown and described in Figure 1, the idle tone becomes smaller and narrower when operated with larger OSRs.

[0032] In some embodiments, which are in Fig. 6A and Fig. As shown in 6B, the input interface 114 is used by Fig. 1 replaced by a high-voltage interface (HVIF 600) to provide an input voltage or battery voltage (V BAT ) to attenuate and level-shift, which enables the ΔΣADC 100 to support negative differential input voltages and voltages up to 120 V absolute voltage. Fig. Figure 6A is a block diagram illustrating one embodiment of the HVIF 600. With reference to Fig. 6A generally includes HVIF 600, a positive or Vp-half-HVIF 602a, which is between V BAT or V IN and is coupled to a Vp node of the first integrator 116, and a negative half-HVIF 602b, which is between V BAT or V INand is coupled to a Vn node of the first integrator. Each half of HVIF 602a and 602b is essentially identical and will now be referred to as follows: Fig. 6B described. Fig. Figure 6B is a schematic diagram illustrating an embodiment of one side or half of HVIF 602a, 602b, or HVIF 600.

[0033] With reference to Fig. 6B comprises the half-HVIF 602a, 602b a first charge pump 604 with a first or charge pump input node coupled to a positive voltage input (vcp) of the HVIF, and a second or charge pump output node coupled to a positive source voltage node (Source_P), and a second charge pump 606 with a first charge pump input node coupled to a negative voltage input (vcn) of the HVIF, and a second or charge pump output node coupled to a negative source voltage node (Source_N). Source_P is equal to the sum of vcp and an output of the first charge pump 604, and Source_N is equal to the sum of vcn and an output of the second charge pump 606.The half-HVIF 602a, 602b further comprises an output stage 608, a limiter circuit, in parallel to the first and second charge pumps 604, 606, and an output node (outp) which is coupled between the output stage and via an output capacitor (Cout) to a virtual node or a ground 610 of the integrator.

[0034] The limiter circuit comprises a first section 612a with a first diode-connected transistor (Q1a) coupled in series with a second transistor (Q1b) between Source_P and vcp, and a second section 612b with a first diode-connected transistor (Q2a) coupled in series with a second transistor (Q2b) coupled between Source_N and vcn. A gate of the second transistor Q1b in the first section 612a of the limiter circuit is coupled to vcn, and a gate of the second transistor Q2b in the second section 612b of the limiter circuit is coupled to vcp.

[0035] The output stage 608 comprises a first pair of series-connected transistors (Q3a, Q3b) coupled in series with a second pair of series-connected transistors (Q4a, Q3b) between vcp and vcn in a source-follower configuration, with the output node (outp) coupled between the common drains of the first and second pairs of transistors. Gates of t transistors (Q3a, Q3b, Q4a, Q4b) are coupled between Source_P of the first charge pump 604 by a pair of series-connected transistors (Q5a, Q5b) and Source_N of the second charge pump 606 by another pair of series-connected transistors (Q6a, Q6b).

[0036] To minimize the increased layout area for the ΔΣADC 100, the HVIF 600 can be implemented using only 5 V devices and configured or operated to provide an input or battery voltage (V BAT ) to receive in a range of -2 V to +5 V.

[0037] The operation of HVIF by Fig. 6A and Fig. 6B will now be referred to in relation to the Fig. 7A, Fig. 7B and Fig. 8 described. Fig. 7A is a timing diagram showing the operation of the HVIF in the ΔΣADC of Fig. 1 for an input battery voltage V BAT illustrated by 5 V, and Fig. 7B is a timing diagram showing the operation of the HVIF 600 in the ΔΣADC of Fig. 1 for a battery voltage V BAT illustrated in -2 V. Fig. Figure 8 is a timing diagram illustrating charge pump outputs for the HVIF 600, which operate at V BAT They can be operated from 5V and -2V.

[0038] With reference to Fig. At approximately 1.1 ms, a VBAT of 5 V is applied to the vcp and vcn inputs of the HVIF 600, with a vcp of 15 V and a vcn of 10 V. A charge pump clock signal (CP clock) of 5 V at 100 kHz is applied to the first and second charge pumps 604 and 606, respectively, starting at approximately 1.11 ms. The first charge pump operates to generate a voltage of approximately 1.1 V, increasing Source_P to approximately 16.1 V at approximately 1.14 ms. Simultaneously, the second charge pump operates to generate a voltage of approximately -1.1 V, decreasing Source_N to approximately 8.9 V. The output node (outp) of the HVIF 600 begins to output a signal with a peak-to-peak voltage of approximately 5 V at the same frequency, but in opposite phase to the CP clock signal.

[0039] With reference to Fig. At 1.1 ms, a vcp of approximately 8 V and a vcn of approximately 10 V are applied to the vcp and vcn inputs of the HVIF 600 for a VBAT of -2 V. A charge pump clock signal (CP clock) of 5 V at 100 kHz is applied to the first and second charge pumps 604 and 606, respectively, starting at a second time point of approximately 1.11 ms. The first charge pump operates to generate a voltage of approximately 3.4 V, which increases Source_P to a voltage of approximately 11.4 V at a third time point of approximately 1.14 ms. Simultaneously, the second charge pump operates to generate a voltage of approximately -3.3 V, which decreases Source_N to a voltage of approximately 6.7 V. The output node (outp) of the HVIF 600 begins to output a signal with a peak-to-peak voltage of approximately 5 V at the same frequency, but in opposite phase to the CP clock signal.

[0040] Referring to a left-hand side of Fig. 8 for the HVIF 600, which is at V BAT Operating from a 5 V supply with a vcp of 5 V and a vcn of 0 V, the first charge pump 604 operates with an output of 1.1 V to generate a Source_P voltage that alternates between 5 V and 6.1 V, and the second charge pump 606 operates with an output of -1.1 V to generate a Source_N voltage that alternates between 0 V and -1.1 V. A gate signal (Gate) to the transistors (Q3a, Q3b, Q4a, Q4b) of the output stage 608 switches between Source_P and Source_N. Since the transistors Q1B and Q2B of the limiting circuit 612a, 612b are fully switched on, the limiting voltage is the simplest of a threshold voltage (vth) of Q1B and Q2B, and a device stand voltage of transistors in the HVIF 600 and the ΔΣADC 100 is not exceeded.

[0041] Referring to a right-hand side of Fig. 8 for the HVIF 600, which is at V BATOperating from -2 V with a vcp of 0 V and a vcn of -2 V, the first charge pump 604 operates with an output of 3.4 V to generate a Source_P voltage that alternates between -2 V and 1.4 V, and the second charge pump 606 operates with an output of -3.3 V to generate a Source_N voltage that alternates between 0 V and -3.3 V. A gate signal (Gate) to the transistors (Q3a, Q3b, Q4a, Q4b) of the output stage 608 switches between Source_P and Source_N. Since transistors Q1B and Q2B of the limiting circuit 612a, 612b are in a source-follower state, the limiting voltage is equal to the sum of -2 V and twice the threshold voltage (vth) of the transistors, or approximately 3.3 V.

[0042] The ΔΣADC and the method of the present disclosure provide a high effective number of bits (ENOB) and high throughput while minimizing potential electromagnetic compatibility (EMC) problems and reducing the area required for implantation in an integrated circuit (IC), making the ΔΣADC particularly useful in an integrated battery management system (BMS) configured to monitor the voltages of a plurality of battery cells connected in series.

[0043] Fig. Figure 9 is a block diagram illustrating a block diagram of a section of a battery management system (BMS 900) for monitoring and managing a battery pack 902, wherein the BMS includes a number of second-order ΔΣADCs 904 according to an embodiment of the present invention. With reference to Fig.In the embodiment shown, the battery pack 902 includes, for example, 24 lithium-ion battery cells (cell 1 to cell 24) of approximately five (5) volts each, for a total battery voltage of approximately 120 VDC. The battery pack is coupled to the BMS by a filter network 906, which includes an analog resistor-capacitor filter for each of the battery cells.

[0044] The BMS 900 is integrally designed on a single integrated circuit (IC) chip and includes a balancing network 908 through which each of the analog filters in the filter network 906 and an associated battery cell (cell 1 to cell 24) of the battery pack 902 are coupled to one of the ΔΣADCs 904. The BMS 900 further includes a high-voltage interface multiplexer (HVIF MUX 910) with inputs coupled to each of the battery cells through the filter network 906 and an output coupled through a scaling amplifier 912 to a first low-voltage multiplexer (LVMUX1 914), and through the LVMUX1 to a successive approximation register analog-to-digital converter (SARADC 916). In some embodiments, such as the one shown, the BMS 900 further includes a number of sensors 918 to measure, for example, the die temperature (Die Temp), the die voltage (Stress Sen) and the outside temperature (Ext.The BMS 900 also includes reference regulators and control circuits 924 to provide reference voltages (Ref A, Ref B) to the ADCs 904, 916 and 922 and to provide control signals (S1, S2, ...S21) to the ADCs and multiplexers, and a digital sequencer 926 to provide digital multi-bit outputs (D. out N, N = 1 to 25) to be received from the ADCs.

[0045] The filter network 906, the balancing network 908, and each of the ΔΣADCs 904 form one of a number of first or main cell voltage measurement paths 928 for each of the battery cells. Additionally, each of the battery cells is coupled to the HVIF MUX 912 via the filter network 906 and the balancing network 908, and to the SAR_ADC 918 via the scaling amplifier 914 and the LVMUX 916, to form a number of second or diagnostic voltage measurement paths 930 for each of the battery cells.

[0046] During normal operation, the control circuits 924 operate the filter network 906, the compensation network 908 and each of the ΔΣADCs 904 to form a number of main measurement paths 928, and then operate each ΔΣADC to generate a digital value that is associated with the sampled analog voltage at the input, using a combination of oversampling and noise shaping techniques as described above.

[0047] During diagnostic operation, the control circuits 924 configure the HVIF MUX 912 to select a diagnostic voltage measurement path 930 assigned to a specific battery cell (e.g., cell 1) and configure the scaling amplifier 914 and the LVMUX 916 to measure the voltage across that specific battery cell using the SAR_ADC 918. Typically, the SAR_ADC 918 incorporates a multi-bit digital-to-analog converter (DAC) and integrator. It samples and holds the analog input voltage, then generates a voltage using the DAC and compares the generated voltage to the voltage sampled at the input using the integrator. This sequence is repeated for all battery cells in the battery pack 902. Since SAR_ADCs and their use in measuring analog voltage are well established in engineering, their operation will not be discussed further.

[0048] Since voltage measurements of the battery pack 902 involve sequentially repeating the above steps for each of the battery cells, voltage measurements taken using the SAR_ADC 918 are much slower and are only used diagnostically to verify measurements taken along the main measurement path 928.

[0049] Thus, a ΔΣADC was disclosed comprising a second-order delta-sigma modulator with a first and a second integrator stage operable to isolate variations in the input common-mode voltage, and an input stage operable to perform correlated double sampling (CDS) for chopping to reduce offset and flicker noise. Embodiments of the present invention have been described above with the aid of functional and schematic block diagrams illustrating the implementation of specified functions and their relationships. The boundaries of these functional blocks have been arbitrarily defined herein for ease of description. Alternative boundaries may be defined as long as the specified functions and their relationships are appropriately implemented.

[0050] The foregoing description of the specific embodiments will disclose the general character of the invention so completely that others, by applying their technical knowledge, will be able to easily modify and / or adapt such specific embodiments for different applications without undue effort and without deviating from the general concept of the present invention.

[0051] It is understood that the detailed description section, and not the summary and abstract sections, should be used to interpret the claims. The summary and abstract sections may present one or more, but not all, exemplary embodiments of the present invention as considered by the inventor(s) and are therefore not intended to limit the present invention and the accompanying claims in any way.

[0052] The breadth and scope of the present invention should not be limited by any of the exemplary embodiments described above, but should only be defined in accordance with the following claims and their equivalents.

Claims

[1] Analog-to-digital converter (ADC), comprising: an input stage (102) that can be operated to provide an analog input voltage (V IN ) to receive; a second-order delta-sigma modulator (second-order DSM) (104) coupled to the input stage (102), wherein the second-order DSM (104) comprises a first integrator stage (106) and a second integrator stage (108) coupled in a cascade architecture; and a quantizer (110) coupled to an output of the second order DSM (104) which is operable to receive an output from the second order DSM (104) and generate a digital multi-bit signal (D, Db). [2] ADC according to claim 1, wherein the ADC has a fully differential architecture, wherein the input stage (102) couples a positive input voltage (Vp) and a negative input voltage (Vn) to an integrator in the first integrator stage (116), wherein the first integrator stage (106) couples a first positive output signal (op1) and a first negative output signal (on1) to a second integrator in the second integrator stage (118), and the second integrator stage (108) couples a second positive output signal (op2) and a second negative output signal (on2) to the quantizer (110). [3] ADC according to claim 2, wherein the fully differential architecture of the ADC is operable to minimize possible electromagnetic compatibility (EMC) problems. [4] ADC according to claim 1 or 2, wherein the first integrator stage (106) is operable to perform correlated double sampling on the positive input voltage (Vp) and the negative input voltage (Vn). [5] ADC according to one of the preceding claims, wherein the first integrator stage (106) is operable to measure the analog input voltage (V IN ) to double. [6] ADC according to one of the preceding claims, wherein the first integrator stage (106) and the second integrator stage (108) each comprise a common-mode voltage input (vcm) and are operable to isolate variations in an input common-mode voltage (vcm). [7] ADC according to one of the preceding claims, wherein the first integrator stage (106) comprises a chopper circuit (CH1, CH2) and is operable to eliminate any residual offset in the analog input voltage (V INto remove ), which is coupled from the input stage (102) to the first integrator stage (106). [8] ADC according to one of the preceding claims, wherein the input stage (102) comprises a high-voltage interface (600). [9] Battery management system (BMS) (900) configured to monitor the voltages of a plurality of battery cells (cell 1 to cell 24) connected in series, the BMS (900) comprising: for each of the battery cells (cell 1 to cell 24) a main cell measurement path which includes an analog-to-digital converter (ADC), comprising: an input stage (102) that can be operated to provide an analog input voltage (V IN ) to receive; a second-order delta-sigma modulator (second-order DSM) (104) coupled to the input stage (102), wherein the second-order DSM (104) comprises a first integrator stage (106) and a second integrator stage (108) coupled in a cascade architecture; and a quantizer (110) coupled to an output of the second order DSM (104) which is operable to receive an output from the second order DSM (104) and generate a digital multi-bit signal (D, Db). [10] BMS (900) according to claim 9, wherein the ADC has a fully differential architecture, wherein the input stage (102) couples a positive input voltage (Vp) and a negative input voltage (Vn) to an integrator in the first integrator stage (116), wherein the first integrator stage (106) couples a first positive output signal (op1) and a first negative output signal (on1) to a second integrator in the second integrator stage (118), and the second integrator stage (108) couples a second positive output signal (op2) and a second negative output signal (on2) to the quantizer (110). [11] BMS (900) according to claim 10, wherein the fully differential architecture of the ADC is operable to minimize possible electromagnetic compatibility (EMC) problems. [12] BMS (900) according to any one of claims 9 to 11, wherein the first integrator stage (106) is operable to perform correlated double sampling on the positive input voltage (Vp) and the negative input voltage (Vn). [13] BMS (900) according to one of claims 9 to 12, wherein the first integrator stage (106) is operable to measure the analog input voltage (V IN ) to double. [14] BMS (900) according to any one of claims 9 to 13, wherein the first integrator stage (106) and the second integrator stage (108) each comprise a common-mode voltage input (vcm) and are operable to block a common-mode voltage (vcm) coupled from the input stage (102). [15] BMS (900) according to any one of claims 9 to 14, wherein the first integrator stage (106) comprises a chopper circuit (CH1, CH2) and is operable to eliminate any residual offset in the analog input voltage (V INto remove ), which is coupled from the input stage (102) to the first integrator stage (106). [16] BMS (900) according to any one of claims 9 to 15, wherein the input stage (102) comprises a high-voltage interface (600). [17] Method for operating an analog-to-digital converter (ADC), comprising: Receiving an analog input voltage (V IN ) in an input stage (102) in the ADC; Coupling of V IN with a second-order delta-sigma modulator (second-order DSM) (104) in the ADC; Integrating V IN using a first integrator stage (106) in the second order DSM (104) to perform a first integration of V IN to produce; Coupling the first integration of V IN with a second integrator stage (108) in the second order DSM (104), which is coupled in a cascade architecture with the first integrator stage (106); Integrating the first integration of V IN using the second integrator stage (108) to perform a second integration of V IN to produce; Coupling the second integration of V IN from a second-order DSM output (104) with a quantizer (110) in the ADC; and Performing a quantization of the second integration of V IN , to generate a digital multi-bit signal (D, Db) that is suitable for V IN is representative. [18] Method according to claim 17, wherein the ADC has a fully differential architecture and wherein: receiving V IN in the input stage (102) includes receiving a positive input voltage (Vp) and a negative input voltage (Vn) and performing a correlated double sampling on Vp and Vn; the coupling of V INwith the second-order DSM (104) includes coupling Vp and Vn with an integrator in the first integrator stage (116); the coupling of the first integration of V IN the second integrator stage (108) includes coupling a first positive output signal (op1) and a first negative output signal (on1) with a second integrator in the second integrator stage (118); and the coupling of the second integration of V IN with the quantizer (110) includes coupling a second positive output signal (op2) and a second negative output signal (on2) with the quantizer (110). [19] Method according to claim 17 or 18, wherein the first integrator stage (106) and the second integrator stage (108) each comprise a common-mode voltage input (vcm) and wherein the integrating of V IN in the first integrator stage (106) and the integration of the first integration of V INin the second integration stage (108) includes the removal of the common-mode voltage (vcm) coupled to the input. [20] Method according to any one of claims 17 to 19, wherein the first integrator stage (106) comprises a chopper circuit (CH1, CH2) and the coupling of V IN with the second-order DSM (104) includes operating the chopper circuit to eliminate any residual offset in V IN , which is coupled from the input stage (102) to the first integrator stage (106).

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