Semiconductor circuit and semiconductor module

Abstract

Task: The thickness of a semiconductor module is to be reduced. Solution: A semiconductor circuit is provided comprising a plurality of first devices and a plurality of second devices arranged on the front of the main board, each of the first device and the second device having a plurality of electrodes comprising a first main electrode and a second main electrode arranged on a top side, the first main electrode and the second main electrode being connected to the front of the main board; each of the first devices having a first end side facing the second device; each of the second devices having a second end side facing the first device; on the top side of the first device, an entire region between the first main electrode and the first end side in the first direction is a first region in which no other electrode is arranged;and on the top side of the second device, an entire area between the second main electrode and the second end side in the first direction is a second area in which no other electrode is arranged.

Description

BACKGROUND 1. TECHNICAL AREA

[0001] The present invention relates to a semiconductor circuit and a semiconductor module. 2. STATE OF THE ART

[0002] Patent document 1 discloses a semiconductor module comprising “an insulating circuit board 1 and semiconductor chips 3a to 3d mounted on the insulating circuit board 1 via bonding materials 2a to 2d, such as solder or sintered materials” (paragraph 0015).Patent document 2 discloses a power semiconductor circuit characterized in that it is a power semiconductor circuit which connects the two surface-mounted power semiconductor devices as at least one upper arm and one lower arm in series, wherein the orientation of a drain and a source of the power semiconductor device on one side of the upper arm is reversed with the orientation of a drain and a source of the power semiconductor device on one side of the lower arm element, and a power semiconductor device on the upper arm side and a power semiconductor device on the lower arm side are connected adjacently on different circuit substrates (paragraph 0015). Fig. Paragraph 4 of patent document 2 discloses an arrangement of a drain electrode 6, a source electrode 7 and a gate electrode 8, and paragraph 0003 describes that "in the example described below, the gate electrode 8 is not an essential element, which is why it is omitted from the illustration". Patent document 1: Japanese publication no. 2022-191879 Patent document 2: Japanese publication no. 2017-005212 Summary of the invention: Technical tasks

[0003] The thickness of a semiconductor module is to be reduced. SUMMARY

[0004] To solve this problem, a semiconductor circuit is provided in a first aspect of the present invention, comprising a mainboard, a plurality of first devices arranged on a front face of the mainboard, and a plurality of second devices arranged on the front face of the mainboard. In the semiconductor circuit, a plurality of electrodes, comprising a first main electrode and a second main electrode, can be arranged on a top face in each of the first devices and the second devices, and the first main electrode and the second main electrode can be connected to the front face of the mainboard. In each semiconductor circuit described above, the first devices and the second devices can be arranged side by side in a first direction parallel to the front face of the mainboard.In each semiconductor circuit described above, the plurality of first devices can be arranged parallel to the front face of the main board and side by side in a second direction intersecting the first direction, and the plurality of second devices can be arranged side by side in the second direction. In each semiconductor circuit described above, each of the first devices can have a first end face facing the second device, and each of the second devices can have a second end face facing the first device. In each semiconductor circuit described above, on the top surface of the first device, the entire region between the first main electrode and the first end face in the first direction can be a first region in which no other electrode is located.In each semiconductor circuit described above, on the top side of the second device, an entire area between the second main electrode and the second end side in the first direction can be a second area in which no other electrode is arranged.

[0005] In each semiconductor circuit described above, on the top side of the first device, an entire region between the second main electrode and the first end face in the first direction can be a region in which no other electrode is located. In each semiconductor circuit described above, on the top side of the second device, an entire region between the first main electrode and the second end face in the first direction can be a region in which no other electrode is located.

[0006] In each semiconductor circuit described above, the first main electrode and the second main electrode can be arranged side by side in the second direction on the top side of the first device.

[0007] In each semiconductor circuit described above, the first device may comprise a semiconductor chip, which is a switching element, and a gate electrode located on its top surface. In each semiconductor circuit described above, the semiconductor chip may have a first main field located on its top surface, which may include a gate field, and a second main field located on its bottom surface. In each semiconductor circuit described above, the first main electrode may be connected to the first main field, the second main electrode may be connected to the second main field, and the gate electrode may be connected to the gate field. In each semiconductor circuit described above, an insulating material may be placed between the first main electrode, the second main electrode, and the gate electrode.

[0008] In each semiconductor circuit described above, a direction from the first main electrode to the second main electrode in the first device can be a direction that is opposite to a direction from the first main electrode to the second main electrode in the second device.

[0009] In each semiconductor circuit described above, the first main electrode of the first device and the second main electrode of the second device can be arranged side by side in the first direction.

[0010] In each semiconductor circuit described above, the second main electrode of the first device and the first main electrode of the second device can be arranged side by side in the first direction.

[0011] Each semiconductor circuit described above may further include intermediate component wiring connecting the first main electrode of the first device and the second main electrode of the second device.

[0012] Each semiconductor circuit described above can have positive wiring through which the second main electrodes of the plurality of first devices are interconnected; and negative wiring through which the first main electrodes of the plurality of second devices are interconnected. In each semiconductor circuit described above, the intermediate component wiring can connect the first main electrodes of the plurality of first devices and the second main electrodes of the plurality of second devices across each of the first region and the second region.

[0013] In each semiconductor circuit described above, the intermediate component wiring between the positive wiring and the negative wiring can be arranged in top view.

[0014] In each semiconductor circuit described above, the intermediate component wiring cannot overlap with either the positive wiring or the negative wiring in top view.

[0015] In each semiconductor circuit described above, the intermediate component wiring can be located in a position that is identical to the positive and negative wiring in a third direction perpendicular to the front of the main board.

[0016] In each semiconductor circuit described above, the main board can be a printed circuit board on which the positive wiring, negative wiring, and intermediate component wiring are arranged.

[0017] In each semiconductor circuit described above, the first device can have a gate electrode with a control signal from the first device input. In each semiconductor circuit described above, the gate electrode can be located on one side opposite the second device with respect to either the first main electrode or the second main electrode of the first device.

[0018] In each semiconductor circuit described above, the second device can have a gate electrode with a control signal from the second device input. In each semiconductor circuit described above, the gate electrode of the second device can be located on one side opposite the first device with respect to either the first main electrode or the second main electrode of the second device.

[0019] In each semiconductor circuit described above, an arrangement of the first main electrode and the second main electrode of the first device can correspond to an arrangement obtained by rotating by 180 degrees an arrangement of the first main electrode and the second main electrode of a second device.

[0020] In each semiconductor circuit described above, the first device can include a first semiconductor chip, which is a switching element; and a gate electrode into which a control signal from the first semiconductor chip is input. In each semiconductor circuit described above, the gate electrode can be located in a position that does not overlap with the first semiconductor chip.

[0021] In each semiconductor circuit described above, the first device can include a first semiconductor chip, which is a switching element; and a lower electrode through which a current flows corresponding to a current flowing between the second main electrode and the first main electrode. In each semiconductor circuit described above, the lower electrode can be located in a position that does not overlap with the first semiconductor chip.

[0022] In each semiconductor circuit described above, the first device can include a first semiconductor chip that is a switching element. In each semiconductor circuit described above, the first main electrode can be located in a position that does not overlap with the first semiconductor chip.

[0023] In each semiconductor circuit described above, the first device can have a gate electrode into which a control signal of the first device is input; and two sub-electrodes through which a current flows corresponding to a current flowing between the second main electrode and the first main electrode. In each semiconductor circuit described above, the gate electrode can be located between the two sub-electrodes.

[0024] In each semiconductor circuit described above, two of the first devices can be arranged side by side in the second direction. In each semiconductor circuit described above, the lower electrodes of the two first devices can be connected to each other.

[0025] To solve the problem described above, a second aspect of the present invention provides a semiconductor module comprising each semiconductor circuit described above and a heat sink in which the semiconductor circuit is arranged. The semiconductor module may include a circuit sealing unit that seals at least a portion of the semiconductor circuit.

[0026] In each semiconductor module described above, at least part of a surface on which the cooler's semiconductor circuit is located may not be sealed.

[0027] The summary section does not necessarily describe all necessary features of the embodiments of the present invention. Furthermore, the present invention may also be a subcombination of the features described above. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 illustrates a perspective view of a semiconductor chip 10 according to the present embodiment. Fig. Figure 2 illustrates a perspective view of a device 200 according to the present embodiment. Fig. Figure 3 illustrates a perspective view of a growing substrate 210 according to the present embodiment. Fig. Figure 4 illustrates a perspective view according to the present embodiment, wherein a semiconductor chip 10, a source electrode 220, a gate electrode 240 and a subsource electrode 250 are in a bonded state on the growing substrate 210. Fig. Figure 5 illustrates an arrangement of the wiring of a semiconductor circuit 800 according to the present embodiment. Fig. Figure 6 illustrates an enlarged drawing of a first device 200-1 and a second device 200-2, arranged facing each other in a first direction. Fig. Figure 7 illustrates an example of an A-A' cross-section in Fig. 5. Fig. Figure 8 illustrates a wiring arrangement of a semiconductor circuit 900 in a comparative example. Fig. Figure 9 illustrates an example of a B-B' cross-section in Fig. 8. Fig. Figure 10A illustrates an example of an enlarged drawing in a top view of an interference region 30. Fig. Figure 10B illustrates another example of an enlarged drawing in a top view of the interference region 30. Fig. Figure 11 illustrates a modification of the semiconductor circuit 800. DESCRIPTION OF EXAMPLES OF EXECUTION

[0028] The present invention is described below by means of embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Furthermore, not all combinations of features described in the embodiments are essential for a solution of the invention.

[0029] In the present description, a case where a term such as "same" or "identical" is mentioned may contain a defect due to a variation in manufacturing or the like. The defect is, for example, within 10%.

[0030] Fig. Figure 1 illustrates a perspective view of a semiconductor chip 10 according to the present embodiment. The semiconductor chip 10 is a switching device such as a MOSFET (metal-oxide-semiconductor field-effect transistor). The semiconductor chip 10 can be a vertical switching device. The semiconductor chip 10 in the present example is a vertical MOSFET. The semiconductor chip 10 can be a silicon semiconductor device such as a silicon MOSFET, or it can be a silicon carbide semiconductor device such as a silicon carbide MOSFET capable of faster switching, or it can be a device using a large-gap semiconductor such as GaN, diamond, gallium nitride materials, gallium oxide materials, AlN, AlGaN, or ZnO. Alternatively, the semiconductor chip 10 can be a semiconductor switching device such as an IGBT (insulated-gate bipolar transistor), or it can be a silicon carbide IGBT. Furthermore, the semiconductor chip 10 can be a HEMT (high electron mobility transistor).

[0031] The semiconductor chip 10 has a top surface 21 and a bottom surface 23. The top surface 21 and the bottom surface 23 are two main surfaces of the semiconductor chip 10. The semiconductor chip 10 has a source array 100 and a gate array 110 arranged on the top surface 21, and a drain array 120 arranged on the bottom surface 23. The source array 100 is an example of the first main array, and the drain array 120 is an example of the second main array. If the semiconductor chip 10 is, for example, an IGBT, an emitter array is arranged as the first main array instead of a source array 100, and a collector array is arranged as the second main array instead of a drain array 120. Each array can be formed from a metal such as aluminum. By applying a predetermined gate voltage to the gate array 110, a main current flows between the source array 100 and the drain array 120. The semiconductor chip 10 can also have a measuring array 130 on its upper surface 21.

[0032] Fig. Figure 2 illustrates a perspective view of the device 200 according to the present embodiment. In general, the semiconductor module, which incorporates the switching element as described in Fig. The semiconductor chip 10 shown in Figure 1 uses a structure that bonds a field (drain field 120) located on one surface (for example, the bottom 23) of the switching element to a wiring pattern on the substrate and electrically connects each field (for example, the source field 100, the gate field 110, and the sensing field 130) on the other surface (for example, the top 21) to a different wiring pattern by wire bonding. Such a semiconductor module is implemented as an integral module by encapsulating, using a resin, a substrate on which the switching element is mounted, each bond wire, and each metal plate connected to a positive terminal, a negative terminal, and an output terminal.

[0033] On the other hand, the device 200 has a structure that exposes each electrode electrically connected to each field of the semiconductor chip 10 on a surface of the plate-shaped device 200. In the present embodiment, the device 200 comprises a growing substrate 210, a source electrode 220, a drain electrode 230, a gate electrode 240, a subsource electrode 250, and a sealing section 260.

[0034] The growing substrate 210 builds the semiconductor chip 10 on a growing area 25 (the top side in the drawing). The source electrode 220 is electrically connected to the source field 100 of the semiconductor chip 10. The drain electrode 230 is electrically connected to the drain field 120 of the semiconductor chip 10. The gate electrode 240 is electrically connected to the gate field 110 of the semiconductor chip 10. The subsource electrode 250 is electrically connected to the source field 100 of the semiconductor chip 10.

[0035] The source electrode 220 is an example of a first main electrode, and the drain electrode 230 is an example of a second main electrode. The first and second main electrodes are electrodes through which a main current of the semiconductor chip 10 flows. The main current refers to a current with the largest amplitude among the currents flowing through the semiconductor chip 10. For example, the main current is a current flowing between an emitter and a collector in an IGBT, or a current flowing between a source and a drain in a MOSFET. If the semiconductor chip 10 is an IGBT, for example, an emitter electrode is arranged as the first main electrode instead of the source electrode 220, and a collector electrode is arranged as the second main electrode instead of the drain electrode 230. Furthermore, the subsource electrode 250 is an example of a subelectrode.If the semiconductor chip 10 is an IGBT, a sub-emitter electrode is arranged as the sub-electrode instead of the sub-source electrode 250.

[0036] One of the two main surfaces of the device 200 is defined as the top surface 261. The top surface 261 is a surface facing one side of the growing substrate 210 in the device 200. The top surface 261 is also a surface of the sealing section 260. The source electrode 220, the drain electrode 230, the gate electrode 240, and the subsource electrode 250 are arranged on the top surface 261. The sealing section 260 exposes at least a portion of the source electrode 220, the drain electrode 230, the gate electrode 240, or the subsource electrode 250 while covering the semiconductor chip 10 and the growing area 25. The same applies to the subsource electrode 250 and the other electrodes. The sealing section 260 can be made of a molded material. However, the sealing section 260 can also be made of a molded material.

[0037] Instead of modularizing the switching element such that the semiconductor chip 10, as previously described, is bonded to the wiring pattern on the substrate by bonding each electrode on the top surface 261 of the device 200, in the present embodiment, all necessary electrodes on the semiconductor chip 10 can be electrically connected to the wiring on the substrate without wire bonding using the device 200. Therefore, it can be bonded directly to a printed circuit board or the like, as described below, making it possible to reduce the thickness of the module and significantly decrease the inductance and thermal resistance.

[0038] It should be noted that the device 200 may further have an electrode on its top surface 261, which is electrically connected to the measuring field 130. Furthermore, either the source electrode 220 or the sub-source electrode 250 is electrically connected to the source field 100 of the semiconductor chip 10, but the source electrode 220 is used for a large surface area and a large current (main current) flowing through it, and the sub-source electrode 250 is used to control the semiconductor chip 10 in a pair with the gate electrode 240. In another form, the device 200 may not have a sub-source electrode 250, and in this case, the source electrode 220 can be used to control the semiconductor chip 10.

[0039] Fig. Figure 3 illustrates a perspective view of the growing substrate 210 according to the present embodiment. The growing substrate 210 comprises an insulating substrate 500, a source electrode wiring 510, a gate electrode wiring 520, and a sub-source electrode wiring 530.

[0040] The insulating substrate 500 can be a substrate made of Si, silicon nitride, or aluminum nitride, or the like, or it can be made of other ceramic materials or the like. A wiring pattern of the source electrode wiring 510, the gate electrode wiring 520, and the subsource electrode wiring 530 is arranged on the growing area 25, which is the area of ​​the insulating substrate 500.

[0041] The source electrode wiring 510 is formed from a conductive metal film or a metal sheet such as copper. The source electrode wiring 510 has a source field contact 513, a wiring 515, and a source electrode contact 517. The source field contact 513 is an area connected to the source field 100 of the semiconductor chip 10. The wiring 515 electrically connects the source field contact 513 and the source electrode contact 517. The source electrode contact 517 is an area connected to the source electrode 220. Fig. Figure 3 shows the source field contact 513 and the source electrode contact 517 hatched. The source electrode wiring 510 is an example of the first main electrode wiring. If the semiconductor chip 10 is, for example, an IGBT, the first main electrode wiring becomes an emitter electrode wiring instead of the source electrode wiring 510.

[0042] The gate electrode wiring 520 is formed from a conductive metal film or a metal sheet such as copper, similar to the source electrode wiring 510. The gate electrode wiring 520 has a gate field contact 523, a wire 525, and a gate electrode contact 527. The gate field contact 523 is a region connected to the gate field 110 of the semiconductor chip 10. The wire 525 electrically connects the gate field contact 523 and the gate electrode contact 527. The gate electrode contact 527 is a region connected to the gate electrode 240. Fig. 3 The gate field contact 523 and the gate electrode contact 527 are hatched.

[0043] The sub-source electrode wiring 530 is formed from a conductive metal film or a metal sheet such as copper, similar to the source electrode wiring 510. The sub-source electrode wiring 530 has a source field contact 513, a wiring 535, and a sub-source electrode contact 537. The source field contact 513 is shared with the source electrode wiring 510. The sub-source electrode wiring 530 may use a portion of the source field contact 513 that is used by the source electrode wiring 510. The wiring 535 electrically connects the source field contact 513 and the sub-source electrode contact 537 between them. The wiring width of the wiring 535 may be smaller than that of the wiring 515. The sub-source electrode contact 537 is an area connected to the sub-source electrode 250. Fig. Figure 3 shows the subsource electrode contact 537, which is hatched. The subsource electrode wiring 530 is an example of subsource electrode wiring. If the semiconductor chip 10 is, for example, an IGBT, the subsource electrode wiring becomes subemitter electrode wiring instead of subsource electrode wiring 530.

[0044] Fig. Figure 4 illustrates a perspective view of the growing substrate 210 according to the present embodiment, wherein a semiconductor chip 10, a source electrode 220, a gate electrode 240, and a subsource electrode 250 are bonded to the growing substrate 210. In this example, the drain electrode 230 is bonded to the drain field 120 of the semiconductor chip 10. The drain electrode 230 is also a conductive plate-like element, such as a copper plate. Fig. 4 is the position of the semiconductor chip 10, which is located under the drain electrode 230, indicated by a dotted line.

[0045] The drain electrode 230 can be bonded to the drain field 120 using a nanosilver sintering agent or by direct gold-gold bonding. In addition to the above, the drain electrode 230 can be bonded using solder materials or by direct copper-copper bonding. Furthermore, a plurality of bumps, arranged regularly or irregularly on the drain electrode 230, can be bonded to the drain field 120 of the semiconductor chip 10. This electrically connects the drain electrode 230 to the drain field 120. It should be noted that the drain electrode 230 may not be arranged. In this case, the drain field 120 may be directly exposed on the top surface 261 of the device 200. In this case, the drain electrode 230 in this description comprises the drain field 120.

[0046] The semiconductor chip 10 is bonded to the growing surface 25 of the growing substrate 210, with the top surface 21 of the semiconductor chip 10 in Fig. 1 is facing downwards. This bonds the source field 100 of the semiconductor chip 10 to the source electrode wiring 510 and the source field contact 513 of the sub-source electrode wiring 530, and the gate field 110 of the semiconductor chip 10 bonds to the gate field contact 523 of the gate electrode wiring 520. These bonding methods can be similar to the bonding methods of the drain electrode 230 to the drain field 120.

[0047] In Fig. 4. The source electrode 220, the gate electrode 240, and the sub-source electrode 250 are bonded to the growing substrate 210 according to the present embodiment. The source electrode 220 is bonded to the source electrode contact 517 of the source electrode wiring 510. The gate electrode 240 is bonded to the gate electrode contact 527 of the gate electrode wiring 520. The sub-source electrode 250 is bonded to the sub-source electrode contact 537 of the sub-source electrode wiring 530. These bonding methods can be similar to the bonding methods of the drain electrode 230 to the drain field 120.

[0048] This means that the source electrode 220 is electrically connected to the source field 100 and the gate electrode 240 is electrically connected to the gate field 110. A main current flows between the drain electrode 230 and the source electrode 220, and a control signal from the semiconductor chip 10 is input into the gate electrode 240.

[0049] As in Fig. As shown in Figure 4, the source electrode 220 is positioned so that it does not overlap with the semiconductor chip 10. The same applies to the gate electrode 240 and the subsource electrode 250. This ensures a specific distance between the semiconductor chip 10 and each electrode and can suppress the heat generation effect from the semiconductor chip 10.

[0050] When a gate voltage is applied to gate electrode 240, with the potential of source electrode 220 serving as a reference potential, the gate voltage can be affected by noise due to the main current flowing through source electrode 220. The heat generated by source electrode 220 can also distort the waveform of the gate signal. Therefore, as described above, the control signal (gate voltage) of semiconductor chip 10 can be applied to gate electrode 240, with the potential of sub-source electrode 250 serving as the reference potential.

[0051] The subsource electrode 250 has the same potential as the source electrode 220, and a current equal to the main current flowing between the drain electrode 230 and the source electrode 220 flows through the subsource electrode 250. For example, a measuring current, smaller than the main current and with a predetermined ratio to the main current, flows through the subsource electrode 250. The semiconductor chip 10 can have a main area through which the main current flows and a measuring area through which the measuring current flows. The ratio of the measuring current to the main current is determined according to the ratio of the measuring area to the main area. The magnitude of the main current can be determined by measuring the measuring current.Since the subsource electrode 250 in this example is located in a position that does not overlap with the semiconductor chip 10, it is less likely that heat generation from the semiconductor chip 10 will be transferred, and distortion of the gate signal can be suppressed. Since the gate electrode 240 in this example is also located in a position that does not overlap with the semiconductor chip 10, it is likewise less likely that heat generation from the semiconductor chip 10 will be transferred, and distortion of the gate signal can be suppressed.

[0052] It should be noted that if the lower source electrode 250 is not present, the gate voltage can be applied between the gate electrode 240 and the source electrode 220. Since the source electrode 220 is located in a position that does not overlap with the semiconductor chip 10, heat generation from the semiconductor chip 10 is less likely in this case as well, and distortion of the gate signal can be suppressed.

[0053] Fig. Figure 5 illustrates an arrangement of the wiring of the semiconductor circuit 800 according to the present embodiment. The semiconductor circuit 800 in the present example comprises a plurality of devices 200 and a main board 810. Although the semiconductor circuit 800 may include a cooler on a surface on one side opposite the main board 810 of the device 200, in Fig. 5 of the coolers were omitted.

[0054] The semiconductor circuit 800 according to the present embodiment is an inverter device and comprises a plurality of devices 200. The plurality of devices 200 is each assigned to an upper arm and a lower arm of each of one or more phases. In the example of Fig. Figure 5 shows the semiconductor circuit 800 arranged in a half-bridge configuration, with four semiconductor devices 200 assigned to each upper arm and four semiconductor devices 200 assigned to each lower arm. It should be noted that the semiconductor circuit 800 can comprise any number of semiconductor devices 200, depending on the application, or it can include another circuit such as a three-phase inverter.

[0055] The main board 810 can be a printed circuit board. The main board 810 can have positive wiring 812, negative wiring 813, and intermediate component wiring 814 on its inner layer. In the present example, a DC voltage is applied between the positive wiring 812 and the negative wiring 813 by an external power supply, and an AC voltage is output by the intermediate component wiring 814. As described below, the positive wiring 812, the negative wiring 813, and the intermediate component wiring 814 can be conductive patterns formed in the same inner layer of the main board 810. The positive wiring 812, the negative wiring 813, and the intermediate component wiring 814 are connected to the device 200 by vias or the like, as described below.

[0056] In the semiconductor circuit 800, the plurality of devices 200 are arranged side by side in a predetermined direction. In the present example, the plurality of devices 200 are arranged side by side in a first direction. The first direction is a direction parallel to the front face of the mainboard 810. The front face is one of two main surfaces of the mainboard 810 to which the device 200 is bonded. Among the devices 200 arranged side by side in the first direction, one is defined as the first device 200-1 and the other as the second device 200-2. In the present example, the first device 200-1 forms the upper arm and the second device 200-2 forms the forearm. Fig. In Figure 5 and subsequent drawings, the first device 200-1 and its configuration may be marked with a sign of -1 and the second device 200-2 and its configuration may be marked with a sign of -2.

[0057] The plurality of first devices 200-1 can be arranged side by side in a second direction. The second direction is parallel to the front of the main board 810 and is a direction intersected by the first direction. Likewise, the plurality of second devices 200-2 can be arranged side by side in the second direction. In the present example, the second direction is orthogonal to the first direction, and the first device 200-1 and the second device 200-2 are arranged side by side in a row of four in the second direction. It should be noted that the second direction in which the plurality of first devices 200-1 are arranged and the second direction in which the plurality of second devices 200-2 are arranged may have an error of ±5° or less. Each first device 200-1 can face the second device 200-2 in the first direction.Furthermore, a direction perpendicular to the front of the 810 mainboard is defined as the third direction. The third direction is perpendicular to both the first and second directions.

[0058] As described above, the source electrode 220 is an example of the first main electrode, and the drain electrode 230 is an example of the second main electrode. That is, each first device 200-1 has a first main electrode (source electrode 220-1) and a second main electrode (drain electrode 230-1), and each second device 200-2 has a first main electrode (source electrode 220-2) and a second main electrode (drain electrode 230-2). That is, the first main electrode of the first device 200-1 and the first main electrode of the second device 200-2 refer to electrodes of the same type, but the individual electrodes are different. The electrode type can refer to the terminal type of the device 200 (for example, emitter, collector, source, drain, gate, base, anode, cathode, or the like). The same applies to the second main electrode.In the following description, the first device 200-1 and the second device 200-2 are examples of MOSFETs.

[0059] On the top surface 261 of the first device 200-1 in the present example, the source electrode 220-1 and the drain electrode 230-1 are arranged side by side in the second direction. In other words, the first main electrode of the first device 200-1 and the second main electrode of the first device 200-1 are arranged side by side in the second direction. Likewise, on the top surface 261 of the second device 200-2 in the present example, the source electrode 220-2 and the drain electrode 230-2 are arranged side by side in the second direction. In other words, the first main electrode of the second device 200-2 and the second main electrode of the second device 200-2 are arranged side by side in the second direction. That is, in the same device 200, at least a portion of the source electrode 220 and at least a portion of the drain electrode 230 are arranged such that they face each other in the second direction.The entire source electrode 220 can be arranged such that it faces the drain electrode 230 in the second direction, and as shown in . Fig. As shown in Figure 5, the entire drain electrode 230 can be arranged such that it faces the source electrode 220 in the second direction. Furthermore, in two devices 200 that are adjacent to each other in the second direction, the source electrode 220 of one device 200 and the drain electrode 230 of the other device 200 are arranged side by side in the second direction. This reduces thermal interference between adjacent devices 200 in the second direction.

[0060] The positive wiring 812 is connected to the drain electrode 230-1 of the first device 200-1. In the present example, the positive wiring 812 extends in the second direction, and the drain electrodes 230-1 of the plurality of first devices 200-1 are connected to each other.

[0061] The negative wiring 813 is connected to the source electrode 220-2 of the second device 200-2. In the present example, the negative wiring 813 extends in the second direction, and the source electrodes 220-2 of the plurality of second devices 200-2 are connected to each other.

[0062] Intermediate component wiring 814 connects the source electrode 220-1 of the first device 200-1 to the drain electrode 230-2 of the second device 200-2. In the present example, the intermediate component wiring 814 extends in the second direction and connects the source electrodes 220-1 of the plurality of first devices 200-1 to the drain electrodes 230-2 of the second devices 200-2. It should be noted that in Fig. 5 the gate rotor, which is connected to the gate electrode 240, and the subsource wiring, which is connected to the subsource electrode 250, have been omitted.

[0063] The intermediate component wiring 814 can be arranged between the negative wiring 813 and the positive wiring 812 in plan view. In the present example, the intermediate component wiring 814 is arranged between the negative wiring 813 and the positive wiring 812 in the first direction. The intermediate component wiring 814 cannot overlap with either the negative wiring 813 or the positive wiring 812 in plan view. This allows the negative wiring 813, the positive wiring 812, and the intermediate component wiring 814 to be arranged on the same layer, as described below, thereby reducing the thickness of the main board 810. Because the wiring length is shortened, the inductance can also be reduced.

[0064] Fig. Figure 6 illustrates an enlarged drawing of the first device 200-1 and the second device 200-2, arranged side by side in the first direction. Fig. Figure 6 shows the main board 810, the positive wiring 812, and the negative wiring 813 omitted, and the intermediate component wiring 814 is indicated by dashed lines. The first device 200-1 has a first end face 201 that faces the second device. The second device 200-2 has a second end face 202 that faces the first device.

[0065] On the top surface 261 of the first device 200-1, the entire area between the source electrode 220-1 and the first end face 201 in the first direction is an area in which no other electrode is arranged. The entire area between the source electrode 220-1 and the first end face 201 is the entire area from the source electrode 220-1 to the first end face 201. In Fig. In section 6, the area is defined as the first area 101. The first area 101 can be an area in which sections other than the electrode of the first device 200-1 are exposed. A sealing section 260 is arranged in the first area 101 in this example. The intermediate component wiring 814 can connect a first source electrode 220-1 and a second drain electrode 230-2 across the first area 101 in a top view. This prevents interference between the positive wiring 812 or the negative wiring 813 and the intermediate component wiring 814, as described below.

[0066] On the upper surface 261 of the second device 200-2, the entire area between the drain electrode 230-2 and the second end face 202 in the first direction is an area in which no other electrode is arranged. The entire area between the drain electrode 230-2 and the second end face 202 is the entire area from the drain electrode 230-2 to the second end face 202. In Fig. In section 6, the area is defined as the second area 102. The second area 102 can be an area in which sections other than the electrode of the second device 200-2 are exposed. The sealing section 260 is located in the second area 102 in this example. The intermediate component wiring 814 can connect the source electrode 220-1 and the drain electrode 230-2 via the first area 101 and the second area 102 in a top view. This prevents interference between the positive wiring 812 or the negative wiring 813 and the intermediate component wiring 814, as described below.

[0067] On the upper surface 261 of the first device 200-1, the entire area between the drain electrode 230-1 and the first end face 201 in the first direction can be an area in which no other electrode is arranged. The entire area between the drain electrode 230-1 and the first end face 201 is the entire area from the drain electrode 230-1 to the first end face 201. In Fig. In section 6, the area is defined as the third area 103. The third area 103 can be an area in which sections other than the electrode of the first device 200-1 are exposed. In the present example, the sealing section 260 is located in the third area 103. This prevents interference between wires, even if the devices 200 of both the upper arm and the forearm are manufactured with the same electrode arrangement. That is, if the devices 200 of the upper arm are used as the devices 200 of the forearm, the third area 103 functions as the second area 102.

[0068] The entire area between the source electrode 220-2 and the second end face 202 in the first direction on the top surface 261 of the second device 200-2 can be an area in which no other electrode is arranged. The entire area between the source electrode 220-2 and the second end face 202 is the entire area from the source electrode 220-2 to the second end face 202. In Fig. In section 6, the area is defined as the fourth area 104. The fourth area 104 can be an area in which sections other than the electrode of the second device 200-2 are exposed. In the present example, the sealing section 260 is located in the fourth area 104. This prevents interference between wires, even if the devices 200 of both the upper arm and the forearm are manufactured with the same electrode arrangement. That is, if the devices 200 of the forearm are used as the devices 200 of the upper arm, the fourth area 104 functions as the first area 101.

[0069] In each device 200, the length of the source electrode 220 in the first direction can be greater than the length of the drain electrode 230 in the first direction. In the present example, the source electrode 220 in the first direction is not adjacent to another electrode of the same device 200. The length of the source electrode 220 in the second direction can be less than the length of the drain electrode 230 in the second direction. Furthermore, in the present example, the source electrode 220 is arranged along an end face that extends in the first direction of the device 200.

[0070] In the present example, the drain electrode 230 is arranged along the other end side that extends in the first direction of the device 200. In the present example, part of the drain electrode 230 is arranged side by side with the gate electrode 240 and the subsource electrode 250 in the first direction.

[0071] In the present example, the gate electrode 240 is arranged on the side opposite the intermediate component wiring 814 with respect to the drain electrode 230. The length in the first direction of the gate electrode 240 can be shorter than that of the source electrode 220 and the drain electrode 230. The length in the second direction of the gate electrode 240 can be shorter than that of the drain electrode 230.

[0072] In the present example, the subsource electrode 250 is arranged on the side opposite the intermediate component wiring 814 with respect to the drain electrode 230. The length of the subsource electrode 250 in the first direction can be shorter than that of the source electrode 220 and the drain electrode 230. The length of the subsource electrode 250 in the second direction can also be shorter than that of the drain electrode 230. In the present example, the subsource electrode 250 is arranged adjacent to a portion of the gate electrode 240 and the source electrode 220 in the second direction.

[0073] In the first device 200-1, a direction from the source electrode 220-1 to the drain electrode 230-1 can be a direction opposite to a direction from the source electrode 220-2 to the drain electrode 230-2 in the second device 200-2. In the present example, a direction from the first source electrode 220-1 to the drain electrode 230-1 is a positive side of the second direction, and a direction from the second source electrode 220-2 to the second drain electrode 230-2 is a negative side of the second direction.

[0074] In the present example, the arrangement of the source electrode 220-1 and the drain electrode 230-1 of the first device 200-1 corresponds to the arrangement of the source electrode 220-2 and the drain electrode 230-2 of the second device 200-2 when rotated by 180 degrees. Therefore, the device 200 can be used with the same electrode arrangement as the first device 200-1 and the second device 200-2. The arrangement can also correspond to the arrangement of the gate electrode 240 or the subsource electrode 250. It should be noted that the arrangements can be different. For example, the electrode arrangement of the first device 200-1 can be the electrode arrangement in the comparison example described below.

[0075] The source electrode 220-1 of the first device 200-1 and the drain electrode 230-2 of the second device 200-2 can be arranged side by side in the first direction. This makes it possible to shorten the wiring length of the intermediate component wiring 814 and to reduce the inductance. Furthermore, the drain electrode 230-1 of the first device 200-1 and the source electrode 220-2 of the second device 200-2 can be arranged side by side in the first direction.

[0076] The gate electrode 240-1 of the first device 200-1 can be located on the opposite side of the second device 200-2 with respect to either the source electrode 220-1 or the drain electrode 230-1. In the present example, the gate electrode 240-1 is located on the opposite side of the second device 200-2 with respect to the drain electrode 230-1. This allows for the separation of the areas where high-voltage wiring, such as the positive wiring 812, and low-voltage gate rotors are located. Since the gate driver circuit can be located far from high-voltage wiring or the like, the effect of noise from the high-voltage wiring can also be reduced. The arrangement of the lower source electrode 250-1 can be similar.

[0077] Similarly, the gate electrode 240-2 of the second device 200-2 can be arranged on the opposite side of the first device 200-1 with respect to the source electrode 220-2 or the drain electrode 230-2. In the present example, the gate electrode 240-2 is arranged on the opposite side of the first device 200-1 with respect to the drain electrode 230-2. Accordingly, an effect similar to that described above can be obtained. The arrangement of the subsource electrode 250-2 can be similar. It should be noted that in Fig. 6, although a pair of first device 200-1 and second device 200-2 is described, another first device 200-1 and another second device 200-2 may also be similar.

[0078] Fig. Figure 7 illustrates an example of the A-A' cross-section in Fig. 5. The A-A' cross-section is a cross-section that traverses the semiconductor circuit 800 in the first direction. In the A-A' cross-section, the semiconductor circuit 800 comprises a first device 200-1, a second device 200-2, a main board 810, and a circuit sealing unit 50. Also in Fig. Figure 7 shows the cooler 60. In the present description, the module comprising the semiconductor circuit 800 and the cooler 60 can be referred to as a semiconductor module.

[0079] A conductive interconnection pattern 818 may be arranged on the front face 825, which is a surface on one side that contacts the device 200 of the main board 810. The interconnection pattern 818 and the intermediate component wiring 814 are electrically connected via vias extending in the third direction. The interconnection pattern 818, the positive wiring 812, and the negative wiring 813 may also have a different cross-sectional area. The positive wiring 812, the negative wiring 813, and the intermediate component wiring 814 may refer to a section extending within a plane that encompasses the first and second directions within the main board 810. That is, the vias extending in the third direction or the interconnection pattern 818 arranged on the front face 825 may not be included.

[0080] The connection pattern 818 connects each electrode of the device 200 via the solder 40. In Fig. Figure 7 shows the solder 40 with fine hatching. In the present example, in the connection pattern 818, which is connected to the intermediate component wiring 814, the connection pattern 818 on the positive side of the first direction is connected to the source electrode 220 of the first device 200-1, and the connection pattern 818 on the negative side of the first direction is connected to the drain electrode 230 of the second device 200-2.

[0081] As in Fig. As shown in Figure 6, in the present example, the first device 200-1 has a first region 101, and the second device 200-2 has a second region 102. In this way, the intermediate component wiring 814 does not interfere with the negative wiring 813 and the positive wiring 812. Therefore, the intermediate component wiring 814 is located in the same position (layer) as the negative wiring 813 and the positive wiring 812 in the third direction. Accordingly, the thickness of the main board 810 can be reduced. Furthermore, there is no interference between the wiring, the wiring length can be shortened, and the inductance can be reduced.

[0082] In the A-A' cross-section, the main board 810 has a sub-source wiring 816. The sub-source wiring 816 is arranged on a layer that is distinct from the intermediate component wiring 814 or the like. One end of the sub-source wiring 816 is connected to the sub-source electrode 250 of the second device 200-2 via the vias and the connection pattern 818. The other end of the sub-source wiring 816 can be connected to the gate driver circuit.

[0083] The circuit sealing unit 50 seals at least a portion of the semiconductor circuit comprising the first device 200-1 and the second device 200-2. In this example, the circuit sealing unit 50 fills the space between the first device 200-1 and the second device 200-2 and the electrodes of each device 200. That is, the circuit sealing unit 50 and the sealing section 260, which are insulating materials, fill the space between the source electrode 220, the drain electrode 230, and the gate electrode 240. The insulating strength of the circuit sealing unit 50 and the sealing section 260 can be greater than that of air. By filling the space between the electrodes, the insulating performance between the electrodes can be improved.

[0084] The semiconductor circuit, comprising the first device 200-1 and the second device 200-2, is arranged in the cooler 60. The cooler 60 can, for example, be a heat distributor, a heat sink, or a heat exchanger for liquid cooling. Each device 200 and each cooler 60 can be bonded with the sintered material 70.

[0085] At least a portion of the surface on which the semiconductor circuit of the cooler 60 is located may not be sealed. In other words, a gap may exist between the cooler 60 and the circuit sealing unit 50, and the circuit sealing unit 50 may not seal the surface bonded to the cooler 60 of the mounting substrate 210. This prevents the circuit sealing unit 50 from becoming a thermal resistor when heat from the device 200 is transferred to the cooler 60. Such a circuit sealing unit 50 can be formed by bonding the device 200 and the main board 810, for example, by using an epoxy flux-type solder paste.

[0086] Fig. Figure 8 illustrates the wiring arrangement of the semiconductor circuit 900 in the comparative example. In the present example, the semiconductor circuit 900 differs from Fig. 5 in the arrangement of the source electrode 220 of the device 200. Therefore, the arrangements of the negative wiring 813 and the intermediate component wiring 814 differ.

[0087] In the present example, in the second device 200-2, the source electrode 220 is arranged between the drain electrode 230 and the first device 200-1 in the first direction. Therefore, the Fig. The second area 102 shown in Figure 6 is not present. As a result, the intermediate component wiring 814 and the negative wiring 813 interfere with each other in interference area 30.

[0088] Fig. Figure 9 illustrates an example of the B-B' cross-section in Fig. 8. The B-B' cross-section is a cross-section that traverses the interference region 30 of the semiconductor circuit 900 in the comparison example in the first direction. In the comparison example, the main board 810 of the semiconductor circuit 900 has a positive wiring 812, a negative wiring 813, an intermediate component wiring 814, a gate rotor 815, and a subsource wiring 816 in the B-B' cross-section.

[0089] As described above, in the comparison example, the negative wiring 813 and the intermediate component wiring 814 interfere with each other in the interference region 30. Therefore, the negative wiring 813 and the intermediate component wiring 814 are arranged in different layers. As a result, the thickness of the main board 810 increases.

[0090] It should be noted that in the present example, the gate rotor 815 is arranged in the same layer as the subsource wiring 816. One end of the gate rotor 815 is connected to the gate electrode 240 of the first device 200-1 via the vias and the interconnection pattern 818. The other end of the gate rotor 815 can be connected to the gate driver IC. The arrangement of the gate rotor 815 can be similar in the example in the semiconductor circuit 800.

[0091] Fig. Figure 10A illustrates an example of an enlarged drawing of the interference region 30 in a top view. Fig. Figure 10A shows part of a first device 200-1, a second device 200-2, and the intermediate component wiring 814. Fig. In the intermediate component wiring 814, the section connected to the source electrode 220 of the first device 200-1 and the section connected to the drain electrode 230 of the second device 200-2 are connected at a position that does not overlap with the source electrode 220 of the second device 200-2 in plan view. The vias connected to the negative wiring 813 are arranged from the source electrode 220 to the top (positive side of the third direction) of the second device 200-2.

[0092] Fig. Figure 10B illustrates another example of the enlarged drawing of the interference region 30 in a top view. In this example, the intermediate component wiring 814 has an opening arranged to expose the source electrode 220 of the second device 200-2 in a top view. A via is arranged to connect to the negative wiring 813 through the opening from the source electrode 220 of the second device 200-2 upwards.

[0093] In any case, the intermediate component wiring 814 is rerouted in the second direction, which increases the wiring length. Therefore, the inductance increases more due to the wiring than in the example.

[0094] Fig. Figure 11 illustrates a modification of the semiconductor circuit 800. In the present example, the first device 200-1 in the semiconductor circuit 800 has two subsource electrodes 250. In each subsource electrode 250, a portion of the current flowing between the drain electrode 230 and the source electrode 220 can flow.

[0095] A gate electrode 240 can be arranged between two subsource electrodes 250. In the present example, the gate electrode 240 is arranged between two subsource electrodes 250 in the second direction. Furthermore, in the present example, two first devices 200-1 are arranged side by side in the second direction. Therefore, the subsource electrodes 250 of the two first devices 200-1 can be connected to each other.

[0096] In Fig.Figure 11 illustrates the gate driver circuit. If the gate driver circuit has a gate voltage applied between the gate electrode 240 and the sub-source electrode 250, the wiring of the sub-source electrodes 250 can be split by connecting them together. This simplifies the wiring of the gate driver circuit.

[0097] This arrangement also improves the degree of freedom in circuit design, as it allows the selection of which subsource electrode 250 to use. For example, the subsource electrodes 250 of the second and third of the first device 200-1 can be separated from the end in the second direction shown in the drawing. The arrangement of the second device 200-2 can be similar.

[0098] Although the present invention has been described above with reference to the embodiments described, the technical scope of the present invention is not limited to that described in the embodiments described above. It is apparent to a person skilled in the art that various modifications or improvements can be made to the embodiments described above. It is also apparent from the description of the claims that the embodiments to which such modifications or improvements are made may fall within the technical scope of the present invention.

[0099] Any process of operations, procedures, steps, stages, and the like performed by a device, system, program, and method shown in the claims, description, and drawings may be carried out in any order, as long as the order is not specified by "before," "before," and the like, and as long as the output of a preceding process is not used in a subsequent process. Even if the sequence of operations is described in the claims, description, and drawings using terms such as "first" or "next" for the sake of simplicity, this does not necessarily mean that the process must be carried out in that order. REFERENCE MARK LIST 10 Semiconductor chips 21 Top 23 Underside 25 cultivation area 30 Interference area 40 Lot 50 Circuit sealing unit 60 coolers 70 Sintered material 100 Source field 101 first section 102 second area 103 third area 104 fourth area 110 Gatterfeld 120 Drain field 130 measuring field 200 Device 201 first end page 202 second end page 210 growing substrate 220 Source electrode 230 Drain electrode 240 gate electrode 250 subsource electrode 260 Sealing section 261 Top 500 insulating substrate 510 Source electrode wiring 513 Source field contact 515 Wiring 517 Source electrode contact 520 Gate electrode wiring 523 Gate field contact 525 Wiring 527 Gate electrode contact 530 Subsource electrode wiring 535 Wiring 537 Subsource electrode contact 800 semiconductor circuit 810 Mainboard 812 positive wiring 813 negative wiring 814 Intermediate component wiring 815 Gate Runner 816 Sub-source wiring 818 connection patterns 825 Front 900 semiconductor circuit QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2022-191879

[0002] JP 2017-005212

[0002]

Claims

[1] Semiconductor circuit comprising: a motherboard; a multitude of initial devices arranged on a front side of the mainboard; and a multitude of secondary devices arranged on the front of the mainboard, wherein each of the first device and the second device has a plurality of electrodes comprising a first main electrode and a second main electrode arranged on a top side, and the first main electrode and the second main electrode are connected to the front side of the main board; the first device and the second device are arranged side by side in a first direction parallel to the front of the mainboard; the multitude of first devices are arranged side by side in a second direction that is parallel to the front of the mainboard and intersects the first direction; the multitude of two devices arranged side by side in the second direction; each of the first devices has a first end side facing the second device; Each of the second devices has a second end side facing the first device; on the top side of the first device, an entire area between the first main electrode and the first end face in the first direction is a first area in which no other electrode is arranged; and On the top side of the second device, an entire area between the second main electrode and the second end side in the first direction is a second area in which no other electrode is arranged. [2] Semiconductor circuit according to claim 1, wherein: on the top side of the first device, an entire area between the second main electrode and the first end face in the first direction is an area in which no other electrode is arranged; and On the top side of the second device, an entire area between the first main electrode and the second end side in the first direction is an area in which no other electrode is arranged. [3] Semiconductor circuit according to claim 1, wherein the first main electrode and the second main electrode are arranged side by side in the second direction on the top side of the first device. [4] Semiconductor circuit according to claim 1, wherein: the first device includes: a semiconductor chip that is a switching element; and a gate electrode located on the top side, the semiconductor chip features: a first main array and a gate array arranged on one top side of the semiconductor chip; and a second main field, which is located on one underside of the semiconductor chip, wherein the first main electrode is connected to the first main field, the second main electrode is connected to the second main field, and the gate electrode is connected to the gate field; and An insulating material is placed between the first main electrode, the second main electrode and the gate electrode. [5] Semiconductor circuit according to claim 1, wherein a direction from the first main electrode to the second main electrode in the first device is a direction that is opposite to a direction from the first main electrode to the second main electrode in the second device. [6] Semiconductor circuit according to claim 1, wherein the first main electrode of the first device and the second main electrode of the second device are arranged side by side in the first direction. [7] Semiconductor circuit according to claim 1, wherein the second main electrode of the first device and the first main electrode of the second device are arranged side by side in the first direction. [8] Semiconductor circuit according to any one of claims 1 to 7, further comprising an intermediate component wiring connecting the first main electrode of the first device and the second main electrode of the second device. [9] Semiconductor circuit according to claim 8, comprising: a positive wiring by which the second main electrodes of the plurality of first devices are connected to one another; and a negative wiring by which the first main electrodes of the multitude of second devices are connected to each other, wherein the intermediate component wiring connects the first main electrodes of the plurality of first devices and the second main electrodes of the plurality of second devices via each of the first region and the second region. [10] Semiconductor circuit according to claim 9, wherein the intermediate component wiring is arranged between the positive wiring and the negative wiring in top view. [11] Semiconductor circuit according to claim 10, wherein the intermediate component wiring does not overlap with any of the positive wiring and the negative wiring in plan view. [12] Semiconductor circuit according to claim 11, wherein the intermediate component wiring is arranged at a position that is identical to the positive wiring and the negative wiring in a third direction perpendicular to the front of the main board. [13] Semiconductor circuit according to claim 9, wherein the main board is a printed circuit board on which the positive wiring, the negative wiring and the intermediate component wiring are arranged. [14] Semiconductor circuit according to one of claims 1 to 3 or of claims 5 to 7, wherein: the first device has a gate electrode with a control signal from the first device input; and the gate electrode is arranged on one side opposite the second device in relation to the first main electrode or the second main electrode of the first device. [15] Semiconductor circuit according to claim 14, wherein: the second device has a gate electrode with a control signal from the second device input; and the gate electrode of the second device is arranged on one side opposite the first device with respect to the first main electrode or the second main electrode of the second device. [16] Semiconductor circuit according to any one of claims 1 to 7, wherein an arrangement of the first main electrode and the second main electrode of the first device corresponds to an arrangement obtained by rotating by 180 degrees an arrangement of the first main electrode and the second main electrode of a second device. [17] Semiconductor circuit according to one of claims 1 to 3 or of claims 5 to 7, wherein: the first device includes: a first semiconductor chip that is a switching element; and a gate electrode into which a control signal from the first semiconductor chip is input, and the gate electrode is positioned in a location that does not overlap the first semiconductor chip. [18] Semiconductor circuit according to any one of claims 1 to 7, wherein: the first device includes: a first semiconductor chip that is a switching element; and a sub-electrode through which a current flows that corresponds to a current flowing between the second main electrode and the first main electrode, and the lower electrode is positioned in a location that does not overlap with the first semiconductor chip. [19] Semiconductor circuit according to any one of claims 1 to 7, wherein: the first device comprises a first semiconductor chip which is a switching element; and the first main electrode is positioned in a location that does not overlap with the first semiconductor chip. [20] Semiconductor circuit according to one of claims 1 to 3 or of claims 5 to 7, wherein: the first device includes: a gate electrode into which a control signal from the first device is input; and two sub-electrodes through which a current flows that corresponds to a current flowing between the second main electrode and the first main electrode, and The gate electrode is positioned between the two lower electrodes. [21] Semiconductor circuit according to claim 20, wherein: two of the first devices are arranged side by side in the second direction; and the lower electrodes of the first two devices are connected to each other. [22] Semiconductor module, comprising: the semiconductor circuit according to any one of claims 1 to 7; a cooler in which the semiconductor circuit is arranged; and a circuit sealing unit that seals at least part of the semiconductor circuit. [23] Semiconductor module according to claim 22, wherein at least a part of a surface on which the semiconductor circuit of the cooler is arranged is not sealed.

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