Nanowire structures with non-discrete source and drain regions and associated fabrication method

Abstract

A semiconductor device (100) comprising the following: a plurality of vertically stacked nanowires (104A-104C) arranged over a substrate (102, 402, 500), each nanowire consisting of a discrete channel region (106, 504A / B) arranged in the nanowire; a gate electrode stack (108) enclosing a plurality of vertically stacked nanowires (104A-104C); and a pair of non-discrete source and drain regions (110 / 112) arranged on both sides of and adjacent to the discrete channel regions (106, 504A / B) of a plurality of vertically stacked nanowires (104A-104C), each of the non-discrete source and drain regions (110 / 112) having a top surface as well as a pair of sidewall surfaces; a contact pair (114) wherein each contact is arranged on the top surface and pair of side walls of a corresponding from the pair of non-discrete source and drain regions (110 / 112), and wherein each contact (114) completely encloses the respective non-discrete source or drain region (110 / 112).

Description

TECHNICAL FIELD

[0001] The embodiments of the invention lie in the field of nanowire semiconductor devices, and in particular in nanowire structures with non-discrete source and drain regions. A nanowire semiconductor device is known, for example, from WO 2012 / 074872 A2. Similar nanowire semiconductor devices are also known from DE 10 2005 038 943 A1, US 2011 / 0062417 A1, or US 7 892 945 B2, as well as from US 2004 / 0227181 A1, US 2010 / 0276761 A1, US 2007 / 0001219 A1, or US 2004 / 0063286 A1. BACKGROUND

[0002] In recent decades, the scaling of integrated circuit features has been the driving force behind the ever-growing semiconductor industry. Scaling to ever smaller features enables greater density of functional units within the limited footprint of semiconductor chips. For example, the ever-shrinking size of transistors enables the integration of a growing number of memory devices on a chip, leading to the production of products with increased capacity. However, the pursuit of ever-increasing capacity is not without its challenges. The need to optimize the performance of each component is playing an increasingly important role.

[0003] Maintaining mobility enhancement and short-channel control poses a challenge in device fabrication as the dimensions of microelectronic devices have passed the 15 nanometer (nm) node. The nanowires used to fabricate the devices offer improved short-channel control. For example, nanowire channel structures made of silicon-germanium (Si x Ge 1-x ) (where x < 0.5) provides mobility enhancement with solid Eg, which is suitable for use in many conventional products that utilize higher voltage ranges. Furthermore, the nanowire channels made of (Si x Ge 1-x ) (where x > 0.5) for mobility improved at lower Egs (e.g. suitable for low voltage products in the mobile / portable equipment sector).

[0004] Many different techniques have been used to improve external resistance (R ext) of the transistors, including improved contact metals, increased dopant activation, and lower barriers between the semiconductor and the contact metal. However, significant improvements in the R ext -reduction is required. SUMMARY

[0005] Embodiments of the present invention include nanowire structures with non-discrete source and drain regions.

[0006] In one embodiment, a semiconductor device comprises a plurality of vertically stacked nanowires arranged above a substrate. Each nanowire includes a discrete channel region available within the nanowire. A gate electrode stack encloses the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is arranged on either side of and adjacent to the discrete channel regions of a plurality of the vertically stacked nanowires.

[0007] In another embodiment, the method for fabricating a nanowire semiconductor device comprises forming a plurality of vertically stacked nanowires over a substrate. Each nanowire includes a discrete channel region available within the nanowire. A gate electrode stack is formed to enclose the discrete channel regions of a plurality of the vertically stacked nanowires. A pair of non-discrete source and drain regions is formed on either side of and adjacent to the discrete channel regions of a plurality of the vertically stacked nanowires.

[0008] In another embodiment, the method for fabricating a nanowire semiconductor device comprises forming a plurality of vertically stacked nanowires over a substrate. Each nanowire includes a discrete channel region available within the nanowire. A gate electrode stack is formed to enclose the discrete channel regions of a plurality of the vertically stacked nanowires. The source and drain regions of a plurality of the vertically stacked nanowires are removed. A pair of non-discrete source and drain regions is then formed on either side of and adjacent to the discrete channel regions of a plurality of the vertically stacked nanowires. BRIEF DESCRIPTION OF THE DRAWINGS Fig. shows a three-dimensional cross-sectional view of a nanowire-based semiconductor structure according to an embodiment of the present invention. Fig. shows a cross-section of the source / drain view of the nanowire-based semiconductor structure of the Fig. along the a-a' axis according to an embodiment of the present invention. Fig. shows a cross-section of the channel view of the nanowire-based semiconductor structure of the Fig. along the b-b' axis according to an embodiment of the present invention. Fig. shows a cross-sectional source / drain view of another nanowire-based semiconductor structure according to an embodiment of the present invention. Fig. shows a cross-section of the channel view of the nanowire-based semiconductor structure of the Fig. according to an embodiment of the present invention. Fig. shows a cross-sectional spacer view of a nanowire-based semiconductor structure according to an embodiment of the present invention. Fig. show three-dimensional cross-sectional views illustrating various operations in a method for providing a starting structure for fabricating a nanowire semiconductor device having non-discrete source and drain regions according to an embodiment of the present invention. Fig. shows a three-dimensional cross-sectional view of a nanowire semiconductor device with metal regions, such as contact regions, as non-discrete source and drain regions according to an embodiment of the present invention. Fig. show cross-sectional views of various operations in the fabrication of a non-discrete source or drain region of a multiple nanowire structure according to an embodiment of the present invention. Fig. show cross-sectional views of various operations in the fabrication of a non-discrete source or drain region of a multiple nanowire structure according to an embodiment of the present invention. Fig. show cross-sectional views of various operations in the fabrication of a non-discrete source or drain region of a multi-nanowire structure according to an embodiment of the present invention. Fig. shows a computing device according to an embodiment of the invention. DETAILED DESCRIPTION

[0009] Nanowire structures with non-discrete source and drain regions are described. In the following description, numerous specific details are set forth, such as the specific integration of the nanowires and material systems, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order not to unnecessarily complicate embodiments of the present invention. Furthermore, it is to be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0010] Described herein are nanowire structures with improved (reduced) external resistance and methods for fabricating these structures, such as structures with non-discrete or global source and drain regions used for devices with two or more nanowires. One or more embodiments of the present invention are directed to approaches for improving (by reducing) the contact area in non-discrete source and drain regions of a multi-nanowire device, or for improving the non-discrete source or drain and contact barriers through doping or materials techniques, or both.Overall, the performance of the device can be improved by reducing the external resistance either by increasing the contact area or by reducing the barrier between a metal and semiconductor or between a heavily doped semiconductor and a lightly doped semiconductor.

[0011] In one embodiment, a nanowire structure with fixed (e.g., non-discrete) source and drain regions exhibits improved (lower) external resistance or channel resistance for a device as fabricated. One or more embodiments are directed to one or more metal source and drain regions, the introduction of increased doping or stress in non-discrete source and drain regions through laser annealing, a zigzag-shaped (e.g., faceted) non-discrete source and drain interface. One or more embodiments are directed to the process flow that delivers dopants to the nanowires or nanowire sections and combines an epitaxially deposited material to ultimately provide fin-like or wrapped contacts.

[0012] The embodiments described in this document may be directed to process flows and resulting structures that are unique to nanowire structures, e.g., as distinct from Fin-FET or Trigate-like architectures. For example, in one embodiment, a laser melting process is used to intermix two materials that would otherwise be used to define alternating nanowires, to dope the nanowires, and, if possible, to stress the channel regions of the nanowires. In another embodiment, a metal source and drain region is provided, where the source and drain regions are actually replaced with a metal that is in contact with the remaining portions of the nanowires, e.g., by using a contact metal both as a contact and in place of the source and drain regions.These embodiments may enable the use of undoped wires and serve as options for optimizing a device formed therefrom. In another embodiment, a non-discrete source or drain region is formed by epitaxial formation followed by crystal orientation-dependent etching to provide a structure with an enlarged contact area. In another embodiment, the process flow enables doping of a nanowire, resulting in merged epitaxial regions in the source and drain regions and, possibly, omega contacts at the source and drain regions. It is contemplated that the embodiments described in this document, like the previously described embodiments, may be used in combination with one another.

[0013] One or more of the embodiments described in this document serve to improve the performance of nanowire-based devices. In one embodiment, the nanowire structure is provided with a contact region (e.g., in the source and drain regions) that scales favorably with the number of nanowires. For example, in one embodiment, a nanowire-based structure has a contact region that wraps around a global source or drain region of a plurality of nanowires, thus providing a large contact area for the same fields. Methods for fabricating these structures are also provided. In one embodiment, source and drain regions are provided from metal. The external resistance (contact + ground) of these devices can be reduced if a metal with a sufficiently low barrier is chosen, since the resistance of the metal is lower than that of the doped silicon.

[0014] Overall, one or more of the approaches described in this document can be used to improve the drive current in a nanowire-based device by reducing the external resistance of the device. Examples of embodiments are listed below.

[0015] In a first example of an embodiment, Fig. a three-dimensional view of a nanowire-based semiconductor structure in cross-section. Fig. shows a cross-section of the source / drain view of the nanowire-based semiconductor structure of the Fig. along the a-a' axis according to an embodiment of the present invention.

[0016] Fig. shows a cross-section of the channel view of the nanowire-based semiconductor structure of the Fig. along the b-b' axis according to an embodiment of the present invention.

[0017] With reference to Fig. A semiconductor device 100 includes one or more vertically stacked nanowires (e.g., a 104-set) arranged above a substrate 102. As an example, a device based on three nanowires with nanowires 104A, 104B, and 104C is shown for illustrative purposes. For ease of description, nanowire 104A is used as an example where the description is directed to one of the nanowires. It is assumed that where the properties of one nanowire are described, embodiments based on a plurality of nanowires will have the same properties for each nanowire.

[0018] Each nanowire 104 includes a channel region 106 disposed within the nanowire. The channel region 106 has a length (L). With reference to Fig. The channel area also has a perimeter (Pc) that is orthogonal to the length (L). With respect to the Fig. A gate electrode stack 108 encloses the entire perimeter (Pc) of each channel region 106. The gate electrode stack 108 includes a gate electrode along with a gate dielectric layer disposed between the channel region 106 and the gate electrode (not shown). The channel region is discrete, meaning it is completely surrounded by the gate electrode stack 108 without any interposed material, such as underlying substrate material or overlying materials for channel processing. Accordingly, in the embodiments having a plurality of nanowires 104, the channel regions 106 of the nanowires are also discrete relative to each other.

[0019] Regarding the Fig. The semiconductor device 100 comprises a pair of non-discrete source and drain regions 110 / 112. The pair of non-discrete source and drain regions 110 / 112 are arranged on either side of the channel regions 106 of a plurality of the vertically stacked nanowires 104. Furthermore, each pair of non-discrete source and drain regions 110 / 112 borders (either directly or indirectly, the latter being Fig. shown) to the channel regions 106 of a plurality of the vertically stacked nanowires 104. The source / drain regions 110 / 112 are not discrete, that is, there are no individual and discrete source and drain regions for each channel region 106 of a nanowire 104. In such an example, as further explained below, the source / drain regions 110 / 112 include interposed material, such as interposed materials for channel processing. Accordingly, in embodiments having a plurality of nanowires 104, the source / drain regions 110 / 112 of the nanowires are global source / drain regions, as opposed to discrete regions for each nanowire.

[0020] According to an embodiment of the present invention and as described in Fig. As shown, the semiconductor device 100 also includes a pair of contacts 114, wherein each contact 114 is arranged on one of the pair of discrete source and drain regions 110 / 112. In such an embodiment, as shown in Fig. As shown, in vertical view, each contact 114 completely encloses the respective non-discrete source or drain region 110 / 112.

[0021] Regarding the Fig. The non-discrete source and drain regions 110 / 112 are global in the sense that a single connecting feature is used as a source or drain region for a plurality (in this case, 3) of nanowires 104 and, in particular, for more than one discrete channel region 106. In one embodiment, the pair of non-discrete source and drain regions 110 / 112 is a pair of semiconductor regions consisting of the same first semiconductor material as the discrete channel region 106 and a second, different semiconductor material. For example, in one of these embodiments, the second material is an intervening material used as an intervening material in the fabrication of discrete nanowires. Such an example will be described in more detail in connection with the following Fig. In a specific embodiment, the first and second semiconductor materials are connected to each other, and the semiconductor regions of the non-discrete source and drain regions 110 / 112 further comprise a dopant. Such an example will be described in more detail in connection with the following Fig. described. As an overall example, in one particular embodiment, the first semiconductor material is silicon-germanium, the second semiconductor material is silicon, and the dopant is a P-type dopant. In another particular embodiment, the first semiconductor material is silicon, the second semiconductor material is silicon-germanium, and the dopant is an N-type dopant. In one embodiment, each pair of the non-discrete source and drain regions 110 / 112 has, from a perspective in cross-section orthogonal to the length of the discrete channel region 106, Fig. a roughly rectangular shape.

[0022] In other respects, the entire perimeter of the non-discrete source and drain regions 110 / 112 may be accessible for contact with the contacts 114. Using the Fig. As a counterexample, the entire perimeter of the non-discrete source and drain regions 110 / 112, viewed along the a-a' axis, is surrounded by the contacts 114. In another embodiment, however, access to the bottom side of the non-discrete source and drain regions is not provided, e.g., through an intervening dielectric layer, whereby the contact 114 only partially surrounds the non-discrete source and drain regions 110 / 112. A particular example of such an embodiment is described in connection with the following Fig. described.

[0023] In other respects, the portions of the nanowires 104A-104C located at the positions of the source and drain regions are removed and replaced with a metal species, such as contact metal. In one embodiment, the pair of non-discrete source and drain regions then actually provides contact to a plurality of the vertically stacked nanowires 104A-104C. That is, the contact regions 114, in addition to providing a contact, also function as non-discrete source and drain regions. A particular example of such an embodiment is described in connection with the following Fig. described.

[0024] In another respect, the discrete sections of a plurality of nanowires are discretely arranged by adding a connecting material. As used in another context, Fig. in a second example of an embodiment, a three-dimensional view of a nanowire-based semiconductor structure in cross section. Fig. shows a cross-section of the source / drain view of the nanowire-based semiconductor structure of the Fig. along the a-a' axis according to another embodiment of the present invention. Fig. shows a cross-section of the channel view of the nanowire-based semiconductor structure of the Fig. along the b-b' axis according to another embodiment of the present invention. With reference to Fig. A semiconductor device 100 comprises one or more vertically stacked nanowires (e.g., a 104 set) arranged over a substrate 102. Each nanowire 104 includes a channel region 106 arranged within the nanowire. With reference to the Fig. A gate electrode stack 108 encloses the entire circumference of each channel region 106. With respect to the Fig. The semiconductor device 100 includes a pair of non-discrete source and drain regions 110 / 112. The pair of non-discrete source and drain regions 110 / 112 are arranged on either side of the channel regions 106 of a plurality of the vertically stacked nanowires 104. Furthermore, each pair of non-discrete source and drain regions 110 / 112 is adjacent to the channel regions 106 of the plurality of vertically stacked nanowires 104. A contact pair 114 is also included. Each contact 114 is arranged in a pair of the non-discrete source and drain regions 110 / 112.

[0025] In relation to Fig. and according to one embodiment of the present invention, a pair of the non-discrete source and drain regions 110 / 112 is a pair of semiconductor regions comprised of the same first semiconductor material as the discrete channel regions 104A-104C, and the faceted (zigzag) semiconductor material 130 at least partially encloses the first semiconductor material. That is, the second semiconductor material 130 provides the discrete portion of the nanowires 104A-104C and the non-discrete or global source and drain regions. In such an embodiment, the first (e.g., the nanowire material) and the second (130) semiconductor materials are the same. A particular example of such an embodiment is described in connection with the following Fig. described.

[0026] With reference again to Fig. In one embodiment, the semiconductor device 100 further comprises a pair of spacers 116. The spacers 116 are arranged between the gate electrode stack 108 and each of the pairs of non-discrete source and drain regions 110 / 112. These spacers 116 will be described in connection with the following Fig. described in more detail. The substrate 102 may be made of a material suitable for the fabrication of semiconductor devices. In one embodiment, the substrate 102 comprises a lower bulk substrate made of a single crystal material, which may include, but is not limited to, silicon, germanium, silicon germanium, or a III-V compound semiconductor material. An upper insulating layer made of a material including, but not limited to, silicon dioxide, silicon nitrate, or silicon oxynitride is disposed on the lower bulk substrate. Therefore, the structure 100 may be fabricated from an initial semiconductor-on-insulator substrate. Alternatively, the structure 100 may be fabricated directly from the bulk substrate using local oxidation to electrically form the insulating portions over the previously described insulating layer.In another alternative embodiment, the structure 100 is formed directly from the bulk substrate, and doping is used to form electrically isolated active regions, such as nanowires, thereon. In such an embodiment, the first nanowire (i.e., immediately adjacent to the substrate) is formed in the shape of an omega-FET-like structure. In one embodiment, the nanowires 104 may be dimensioned as wires or ribbons and may have squarely truncated or rounded corners. Referring to FIG. 1C, in one embodiment, each channel region 106 has a width (Wc) and a height (Hc). The width (Wc) is approximately equal to the height (Hc). That is, the channel regions 106 and the source / drain region 110 / 112 are square or, with rounded corners, circular in profile in cross-section. However, in another embodiment (not shown), the width and height of the channel region need not be the same.For example, the width (Wc) can be significantly larger than the height (Hc). In one particular embodiment, the width (Wc) is approximately 2-10 times larger than the height (Hc). This means that the channel regions 106 and the source / drain regions 110 / 112 are rectangular or, with rounded corners, oval in cross-sectional profile. Nanowires with such a geometry can be referred to as a nanoribbon. In an alternative embodiment (not shown), the nanoribbons are arranged vertically.

[0027] In one embodiment, the nanowires 104 are made of a material such as, but not limited to, silicon, germanium, or a combination thereof. In this embodiment, the nanowires are single-crystalline. For example, for a silicon nanowire 104, a single-crystalline nanowire may be based on a (100) global alignment, i.e., with a <100> -plane in the Z direction. It is anticipated that other orientations are also contemplated. In one embodiment, the dimensions of the nanowires 104 from a cross-sectional perspective are at the nanoscale. For example, in one embodiment, the smallest dimension of the nanowires 104 is less than about 20 nanometers. In one embodiment, the nanowires 104 are composed of a strained material, particularly in the channel regions 106.

[0028] In one embodiment, the gate electrode of gate electrode stack 108 is comprised of a metal gate, and the gate dielectric layer is comprised of a high-k material. For example, in one embodiment, the gate dielectric layer is comprised of a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. Furthermore, a portion of the gate dielectric layer may include a native oxide layer formed from the upper layers of nanowire 104. In one embodiment, the gate dielectric layer is comprised of an upper high-k portion and a lower portion comprised of an oxide of a semiconductor material.In one embodiment, the gate dielectric layer consists of an upper portion of hafnium oxide and a lower portion of silicon dioxide or silicon oxynitride.

[0029] In one embodiment, the gate electrode is composed of a metal layer such as, but not limited to, metallic nitrides, metallic carbides, metallic silicides, metallic aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or conductive metal oxides. In a specific embodiment, the gate electrode is composed of a non-workfunction-setting fill material formed over a metallic workfunction-setting layer.

[0030] In one embodiment, the spacers 116 are made of an insulating dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, or silicon nitride. The contacts 114 are made of metal species in one embodiment. The metal species may be pure metals, such as nickel or cobalt, or alloys, such as a metal-metal alloy or a metal-semiconductor alloy (e.g., silicide material). As described above, in at least several embodiments, the channel regions are discretely configured, while the source and drain regions are not. However, other regions of the nanowires need not be, or even may not be, discretely configured. For example, Fig. a cross-sectional spacer view of a nanowire-based semiconductor structure according to an embodiment of the present invention.

[0031] In relation to Fig. the nanowires 104A-104C are not discrete at the location below the spacers 116. In one embodiment, the stacks of nanowires 104A-104C have an intervening semiconductor material 118, such as silicon germanium, between the silicon nanowires and vice versa, as described below in connection with the Fig. described. In one implementation, the bottom nanowire 104A still has contact with a portion of the substrate 102. Therefore, in one embodiment, a portion of the plurality of vertically stacked nanowires is non-discrete beneath one or both of the spacers, either between the nanowires, beneath the bottom nanowire 104, or both.

[0032] In another aspect, methods for fabricating a nanowire semiconductor device are provided. For example, the Fig. three-dimensional cross-sectional views illustrating various operations in a method for providing a starting structure for fabricating a nanowire semiconductor device having non-discrete source and drain regions according to an embodiment of the present invention.

[0033] A method of fabricating a nanowire semiconductor device may include forming a nanowire over the substrate. In a specific example illustrating the formation of two silicon nanowires, the Fig. a substrate 402 (e.g., a bulk substrate of silicon substrate 402A with an insulating layer of silicon dioxide 420B thereon) with a stack consisting of silicon layer 404 / silicon germanium layer 406 / silicon layer 408 disposed thereon. It is contemplated that in another embodiment, a stack consisting of silicon germanium layer / silicon layer / silicon germanium layer is used to finally form two silicon germanium nanowires.

[0034] In relation to Fig. a part of the stack of silicon layer 404 / silicon germanium layer 406 / silicon layer 408 as well as an upper part of the silicon dioxide layer 402B is patterned in a fin-like structure 410, ie with a mask and plasma etching process.

[0035] The method may also include forming a channel region in the nanowire, wherein the channel region has a length and a perimeter orthogonal to the length. In a specific example showing the formation of three gate structures over two silicon nanowires, Fig. 4C shows the fin-like structure 410 with three sacrificial gates 412A, 412B, and 412C disposed thereon. In such an embodiment, the three sacrificial gates 412A, 412B, and 412C consist of a sacrificial gate oxide layer 414 and a sacrificial polysilicon gate layer 416, which are patterned and deposited over the entire surface using a plasma etching process.

[0036] Although not shown, after patterning to form the three sacrificial gates 412A, 412B, and 412C, spacers may be formed on the sidewalls of the three sacrificial gates 412A, 412B, and 412C, doping may be performed (e.g., tail and / or source and drain doping), and an interlayer dielectric layer may be formed to cover the three sacrificial gates 412A, 412B, and 412C. The interlayer dielectric layer may be ground down to expose the three sacrificial gates 412A, 412B, and 412C for a gate replacement or gate-load process. Additionally, portions of the silicon germanium layer 406 and portions of the insulating silicon dioxide layer 402B of the fin-like structure 410 may be removed in the areas originally covered by the three sacrificial gates 412A, 412B, and 412C. Discrete portions of the silicon layers 404 and 408 remain.Or, in the opposite case, the discrete part of the two silicon-germanium layers remains if one starts with an inverted stack of silicon and silicon-germanium layers.

[0037] Thus, in one embodiment, the discrete portions of germanium layers 404 and 408 ultimately become channel regions in a nanowire-based structure. Therefore, channel engineering or tuning may be performed at the process stage. For example, in one embodiment, the discrete portions of silicon layers 404 and 408 are thinned using oxidation and etching processes. This etching process may be performed at the same time as the wires are separated by etching the silicon germanium layer 406. Accordingly, the initial wires formed from silicon layers 404 and 408 may start thicker and be thinned to an appropriate size suitable for a channel region in a nanowire device, regardless of the dimensions of the device's source and drain regions.

[0038] The initial processing may also include forming a gate electrode stack encompassing the entire perimeter of the channel region. The specific example shows the formation of three gate structures over the two nanowires. A gate dielectric layer (such as a high-K dielectric layer) and a gate electrode layer (such as a metal gate electrode layer) are formed. Furthermore, the subsequent removal of any intervening dielectric layer may be performed after forming the permanent gate stack to allow access to the source and drain regions.

[0039] The process may also include forming a pair of non-discrete source and drain regions for the nanowires on the other side of the channel regions. Therefore, the fabrication and engineering or tuning of the source and drain regions may be performed. Examples of this follow. It is expected that similar engineering or tuning procedures are instead performed earlier in a process flow, i.e., before deposition of an interlayer dielectric layer and formation of the permanent gate electrodes.

[0040] In a first example, where the structure of Fig. as a starting point, shows Fig. a three-dimensional cross-sectional view of a nanowire semiconductor device with metal regions, such as contact regions, as non-discrete source and drain regions according to an embodiment of the present invention.

[0041] A gate electrode stack 512 comprises with respect to Fig. a dielectric gate layer 520, a gate electrode 522, and sidewall spacers 524. The gate electrode stack encloses the discrete nanowire channel regions 504A / B. A pair of non-discrete source and drain regions 510 and 512 adjoin the discrete channel regions 504A / B. A buried oxide layer 502 insulates a substrate 500. The concepts described in this document are believed to be suitable for wires, both in bulk or under fin oxide structures, such as an underlying Omega-FET device. In one embodiment, the pair of non-discrete source and drain regions 510 and 512 successfully contact regions that do not comprise nanowire material. In such an embodiment, the contacts are formed from a metal species. In one such embodiment, the metal species is formed by uniformly depositing a contact metal and then filling the remaining groove volume.The uniform aspect of the deposition can be achieved using chemical vapor deposition (CVD), atomic layer deposition (ALD), or metal reflow. Therefore, the structure can be . Fig. be seen as having contacts that touch the ends of the nanowires (as opposed to merely surrounding them). In one embodiment, to achieve the structure in Fig. from the structure in Fig. A spacer is formed, and the silicon regions in the source / drain openings are selectively etched, leaving the silicon-germanium layers. Additionally, silicon-germanium is then epitaxially grown on top of the existing silicon-germanium wires. Silicon-germanium can also be doped and annealed to introduce the dopants into the adjacent silicon wire surface beneath the spacer. The process flow continues as before, with the formation of an interlayer of dielectric material and the formation of the gate electrode stack. Once the interlayer of dielectric material in the source / drain regions is removed, the epitaxial silicon-germanium layer is exposed and then etched to leave a void at the ends of the silicon wires inserted into the spacer. The contact metal is then deposited to fill the void and bond to the ends of the silicon nanowires.In such an embodiment, this approach is suitable for metallizing contact pads with very low interface barrier heights, where a small contact area is not a significant disadvantage. In another embodiment, an alternative process flow involves etching out the silicon and silicon-geranium wires followed by filling the source and drain regions with metal or another temporary material, which is later removed by etching in a trench formation process.

[0042] In one or more of the methods described herein, in addition to providing electrical contact, the contact metal and deposition method may be selected such that the metal imparts appropriate stress to the channel nanowires to improve device performance. For example, in one embodiment, such as a special case involving an undoped wire, a midgap workfunction metal is used to create contacts, eliminating the need for a high doping level at the metal source / drain interface. A variation of the foregoing process flow may be used to dope or increase the strained atom concentration in the silicon (or alternatively, silicon-germanium) source and drain regions of the nanowires using melt laser annealing or other effective annealing techniques. Fig. show cross-sectional views of various operations in the fabrication of a non-discrete source or drain region of a multiple nanowire structure according to an embodiment of the present invention.

[0043] The spacers are made using the structure in Fig. as a starting point first formed on the gate stacks 412A-412C. With respect to Fig. Either the silicon regions 610 or the silicon-germanium regions 620 are the ends of the nanowires, with the other material being used as an intervening material in the fabrication of the nanowires. A doped silicon or silicon-germanium layer 650 is selectively deposited around the source and drain regions, enclosing the exposed portions of the stacks of regions 610 and 620. Regarding Fig. : An amorphization depth of 699 is formed, followed by a high-dose implantation of the structure of Fig. In one embodiment, a melt laser hardening process (possibly including depositing temporary layers that provide support during melting) is used to melt all layers above the amorphization depth 699. In another embodiment, a non-laser annealing process is used. In such an embodiment, melting causes a redistribution of atoms in the melted layers. The deposited layers can then be doped because the implanted dopant is redistributed in layers 610 and 620, thus reducing the resistance of a ultimately formed non-discrete source and drain region. In one embodiment, if the deposited layers include a straining atom, such as germanium or carbon, the resulting strain in the non-discrete source or drain region is used to increase the strain in the corresponding discrete channel regions.For example, in one particular embodiment, a Ge:B film (as 650) is deposited and melted. As such, the Ge and B concentrations are increased in the portions of a non-discrete source or drain region corresponding to the nanowires. The increased Ge acts as a strain in the PMOS regions of either silicon or silicon-germanium. Such an option may not be compatible with a wraparound contact structure because the source and drain regions have the same Ge concentration.

[0044] Another possibility to improve the resistance of nanowire-based structures may involve increasing the contact areas of multiple nanowires, where facets such as <111> -facet of a semiconductor material. For example, the Fig. Cross-sectional views of various operations in the fabrication of a non-discrete source or drain region of a multiple nanowire structure according to an embodiment of the present invention.

[0045] The spacers are made using the structure in Fig. as a starting point first formed on the gate stacks 412A-412C. With respect to Fig. Either the silicon regions 710 or the silicon-germanium regions 720 are the ends of the nanowires, with the other material being used as an intermediate material during the manufacture of the nanowires. In the specific case shown, the silicon-germanium regions 720 are the ends of the nanowires.

[0046] In relation to Fig. : The silicon regions 710 are selectively removed, leaving the silicon-germanium ends 720 of the nanowires. A silicon-germanium layer 750 is deposited as in Fig. shown, selectively deposited around the source and drain regions, ie, the exposed portions of the silicon-germanium regions 720 are surrounded. With respect to Fig. An orientation-dependent etching agent, such as KOH, is used to <111> -Levels even further and increase the area for contact with the non-discrete source or drain region 760. In one embodiment, the resulting zigzag contact source or drain structure increases the contact area, which reduces the external resistance of a device so fabricated. In one embodiment, a later-formed contact metal wraps around the non-discrete source or drain region 760 so that it touches the sides and top of the non-discrete source or drain region 760, thus increasing the contact metal source or drain contact area.

[0047] In another embodiment, a process flow suitable for doping and providing contacts for the source or drain regions comprises forming wires in non-discrete source and drain regions after forming the spacers (e.g., starting with the structure in Fig. followed by the deposition of spacer material and etching). Later, an internal spacer is added, source / drain dopants are added, or the region is grown epitaxially. The resulting structure is then filled with a sacrificial dielectric, such as silicon dioxide, which is removed in a later processing step. Such an alternative approach can be used to facilitate the doping of the source and drain regions of the nanowires. As an example of process flows, the Fig. Cross-sectional views of various operations in the fabrication of a non-discrete source or drain region of a multi-nanowire structure according to an embodiment of the present invention.

[0048] In relation to Fig. The fin or wire 802 cuts are provided for a structure such as the structure of the Fig. in the source / drain regions 804 between the gate or gate placeholder regions 806. For example, a spacer of the structure may be Fig. after removing the silicon-germanium layers in the source and drain regions 804. A dielectric layer 808 is then formed to fill any open grooves or cavities, as shown in Fig. An insulating layer 810 is shown with respect to Fig. for the source / drain region. The insulating layer 810 of the source / drain region is then formed Fig. The dielectric layer 808 is recessed with respect to Fig. under the wires 802 to expose a larger surface area of ​​the wires 802. In some cases, the entire dielectric layer 808 is removed. This type of approach may include the formation of an internal spacer to separate the source and drain regions from the silicon-germanium layer underlying the channel portions. An epitaxial layer 820 is then formed on the source and drain portions of the wires 802, as shown in Fig. Surrounding the source and drain regions with a doped epitaxial layer in one embodiment enables doping of the source and drain regions of wires 802 and adjusting the doping level between the wires and the contact metal.

[0049] Following the above-mentioned process, the contact metal can be added after etching the contact gap. The previous example of Fig. can be used in one embodiment for nanowire structures formed either on a bulk semiconductor substrate or on an insulated substrate, such as silicon-on-insulator substrate. The Fig. The operations described may only be required in the case of a bulk substrate.

[0050] Accordingly, one or more embodiments of the present invention include methods for fabricating nanowire structures with non-discrete source and drain regions, methods for differentially tuning the regions for channel and contact positions (i.e., the source and drain regions), or methods for performing both during the same process. The structures formed by these methods may enable an improvement (reduction) in external resistance (Rext) over conventional structures. Embodiments include providing increased doping in the source and drain regions (or fabricating the source and drain regions from metal), increasing the contact area, or increasing the strain in the device channel, or both. These approaches may improve the performance of a device fabricated from the nanowire structures as described herein. Fig.shows a computing device 900 according to one implementation of the invention. The computing device 900 includes a circuit board 902. The circuit board 902 may include a number of components, including, but not limited to, a processor 904 and at least one communication chip 906. The processor 904 is physically and electrically coupled to the circuit board 902. In some implementations, at least one of the communication chips 906 is also physically and electrically coupled to the circuit board 902. In further implementations, the communication chip 906 is part of the processor 904. Depending on its applications, the computing device 900 may include other components that may or may not be physically and electrically coupled to the circuit board 902. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g.,ROM), flash memory, a graphics processor, digital signal processor, secret processor, chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, global positioning system (GPS), a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard disk drive, a compact disc (CD), digital versatile disk (DVD), etc.).

[0051] Communication chip 906 enables wireless communications for transferring data to and from computing device 900. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that communicate data using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated components do not include wires, although some embodiments do not. The communication chip 906 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols referred to as 3G, 4G, 5G, and beyond.Computing device 900 may include a plurality of communication chips 906. For example, a first communication chip 906 may be associated with shorter-range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip 906 may be associated with longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0052] The processor 904 of the computing device 900 includes an integrated circuit (IC) die packaged within the processor 904. In some implementations of the invention, the processor's IC die includes one or more devices, such as nanowire transistors, incorporated according to implementations of the invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that can be stored in registers and / or memory. The communication chip 906 also includes an integrated circuit (IC) die packaged within the communication chip 906. According to another implementation of the invention, the communication chip's IC die includes one or more devices, such as nanowire transistors, incorporated according to implementations of the invention.

[0053] In further implementations, another component housed within the computing device 900 may include an IC die including one or more devices such as nanowire transistors incorporated in accordance with implementations of the invention.

[0054] In various implementations, computing device 900 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, computing device 900 may be any other electronic device that processes data.

[0055] Therefore, nanowire structures with non-discrete source and drain regions have been disclosed. In one embodiment, a semiconductor device comprises a plurality of vertically stacked nanowires arranged above a substrate. Each nanowire includes a discrete channel region available within the nanowire. A gate electrode stack encloses the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is arranged on either side of and adjacent to the discrete channel regions of a plurality of the vertically stacked nanowires. In one embodiment, the semiconductor device further comprises a pair of contacts. Each contact is arranged in a pair of the non-discrete source and drain regions. In one implementation, the pair of non-discrete source and drain regions provides contact to a plurality of the vertically stacked nanowires.

Claims

[1] A semiconductor device (100) comprising: a plurality of vertically stacked nanowires (104A-104C) disposed over a substrate (102, 402, 500), each nanowire consisting of a discrete channel region (106, 504A / B) disposed within the nanowire; a gate electrode stack (108) enclosing a plurality of the vertically stacked nanowires (104A-104C); and a pair of non-discrete source and drain regions (110 / 112) disposed on either side of and adjacent to the discrete channel regions (106, 504A / B) of a plurality of the vertically stacked nanowires (104A-104C), each of the non-discrete source and drain regions (110 / 112) having a top surface and a pair of sidewall surfaces; a pair of contacts (114), each contact being disposed on the top surface and the pair of sidewalls of a corresponding one of the pair of non-discrete source and drain regions (110 / 112), and each contact (114) completely enclosing the respective non-discrete source or drain region (110 / 112). [2] The semiconductor device (100) of claim 1, wherein each pair of non-discrete source and drain regions (110 / 112) has an approximately rectangular shape from a perspective in cross-section orthogonal to the length of the discrete channel region (106, 504A1B). [3] The semiconductor device (100) of claim 1, wherein the pair of non-discrete source and drain regions (110 / 112) is a pair of semiconductor regions consisting of a same first semiconductor material as the discrete channel regions (106, 504A / B), and a second semiconductor material (130) at least partially encloses the first semiconductor material. [4] The semiconductor device (100) of claim 1, further comprising: a pair of spacers (116, 524) disposed between the gate electrode stack (108) and the pair of non-discrete source and drain regions (110 / 112). [5] The semiconductor device (100) of claim 4, wherein a portion of the plurality of vertically stacked nanowires (104A-104C) is non-discrete under one or both of the spacers (116, 124). [6] The semiconductor device (100) of claim 1, wherein the gate electrode stack (108) consists of a metal gate and a high-K dielectric gate, and each of the nanowires consists of silicon, germanium, or a combination thereof. [7] A method of manufacturing a nanowire semiconductor device (100), the method comprising: Forming a plurality of vertically stacked nanowires (104A-104C) over a substrate (102, 402, 500), each nanowire consisting of a discrete channel region (106, 504A / B) disposed within the nanowire; Forming a gate electrode stack (108) enclosing the discrete channel regions (106, 504A / B) of a plurality of the vertically stacked nanowires (104A-104C); and Forming a pair of non-discrete source and drain regions (110 / 112) disposed on either side of and adjacent to the discrete channel regions (106, 504A / B) of a plurality of the vertically stacked nanowires (104A-104C), each of the non-discrete source and drain regions (110 / 112) having a top surface and a pair of sidewall surfaces; Forming a contact pair (114), each contact being disposed on the top surface and the pair of sidewalls of a corresponding one of the pair of non-discrete source and drain regions (110 / 112), and each contact (114) being formed to completely enclose the respective non-discrete source or drain region (110 / 112). [8] The method of claim 7, wherein forming the pair of non-discrete source and drain regions (110 / 112) comprises first forming the discrete source and drain regions (504A / B) for each nanowire. [9] The method of claim 8, wherein forming the pair of non-discrete source and drain regions (110 / 112) comprises forming a faceted semiconductor material at least partially enclosing the discrete source and drain regions (504A / B) for each nanowire. [10] The method of claim 7, wherein forming the pair of non-discrete source and drain regions (110 / 112) consists of melting by laser annealing a portion of the vertically stacked nanowires (104A-104C) of a first semiconductor material together with an intermediate second semiconductor material (130) and a surrounding semiconductor layer. [11] The method of claim 7, wherein forming the non-discrete source and drain regions (110 / 112) occurs before forming the discrete channel regions (504A / B). [12] The method of claim 7, wherein forming the non-discrete source and drain regions (110 / 112) occurs after forming the discrete channel regions (504A / B).

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