Light-emitting diode unit at wafer level

Abstract

Light-emitting diode unit, LED, comprising: a semiconductor stack (30) comprising a semiconductor layer of a first conductivity type (25), a semiconductor layer of a second conductivity type (29), and an active layer (27) disposed between the semiconductor layers of the first (25) and second conductivity type (29), wherein a plurality of contact holes (30a) are present in the semiconductor layer of the second conductivity type (29) and the active layer (27) exposing the semiconductor layer of the first conductivity type (25); a first elevation (45a) arranged on a first side of the semiconductor stack, the first elevation (45a) being electrically connected to the semiconductor layer of the first conductivity type (25) via the plurality of contact holes (30a); a second elevation (45b) arranged on the first side of the semiconductor stack, the second elevation (45b) being electrically connected to the semiconductor layer of the second conductivity type (29); a first insulating layer (43) arranged on the first side of the semiconductor stack (30) and covering a side surface of the first elevation (45a); and a wavelength converter (51) arranged on a second side of the semiconductor stack (30), the wavelength converter (51) projecting laterally beyond the semiconductor stack, and wherein the first insulating layer (43) comprises a side surface that is flush with a side surface of the wavelength converter (51).

Description

[Technical Field]The present invention relates to a light emitting diode unit, and more particularly to a wafer-level light emitting diode unit.[Prior Art]A light emitting diode (LED) is a semiconductor device that includes an n-type semiconductor and a p-type semiconductor and emits light by recombination of holes and electrons. Such an LED has many uses, such as display devices, traffic lights, and tail light units. Further, due to the potential benefits of lower power consumption and longer life, the range of applications of LEDs has increased towards general lighting compared to existing incandescent or fluorescent lamps by replacing existing incandescent and fluorescent lamps.The LED may be used in an LED module. The LED module is manufactured by a wafer-level LED chip manufacturing method, a packaging method, and a modulation method. Specifically, semiconductor layers are grown on a substrate such as a sapphire substrate and patterned in a method of manufacturing LED chips having electrode pads, and then divided into individual chips (chip manufacturing method). After mounting the individual chips on a lead frame or a printed circuit board, the electrode pads are connected to terminals via contact wires, and the LED chips are sheathed with a sealing member to provide an LED unit (packaging method). Then, the LED unit is mounted on a circuit board such as a metal circuit board (MC-PCB) to provide an LED module such as a light source module (modulation method).In the packaging method, the LED chip can be provided with a housing and / or the potting element for protecting the chip from external environmental influences. In addition, a phosphor may be included in the sealing member for converting the light emitted by the LED chip, so that the LED unit may emit white light, thereby providing a white LED unit. Such a white LED unit may be mounted on the printed circuit board, such as the MC PCB, and the LED unit may be provided with a secondary lens to adjust the alignment characteristics of the light emitted from the LED unit to provide the desired white LED module.However, it may be difficult to achieve miniaturization and sufficient heat dissipation for a conventional LED unit including the lead frame or the printed circuit board. Further, the light efficiency of the LED may decrease due to light absorption by the lead frame or the printed circuit board, heating by the electric resistance of the terminals, and the like.Further, the chip manufacturing method, the packaging method, and the modulation method can be performed separately, and the time and cost for manufacturing the LED module increase.Meanwhile, alternating current (AC) LEDs have been manufactured and marketed. The AC LED includes an LED directly connected to an AC power source to allow continuous light emission. An example of AC LEDs that can be used directly in conjunction with a high voltage AC power source is disclosed in U.S. Pat. No. 7,417,259 B2 issued to Sakai et al.According to U.S. Pat. No. 7,417,259 B2, LED elements are arranged in a two-dimensional pattern on an insulating substrate, for example a sapphire substrate, and are connected in series to form LED arrays. The LED arrays are connected in series to form a light emitting device that can be operated at high voltage. Further, such LED arrays may be connected anti-parallel on the sapphire substrate, providing a single-chip light emitting device that can be operated under continuous light emission using an AC power supply.Since the AC LED includes light emitting cells on a growth substrate, for example, on a sapphire substrate, the AC LED restricts the structure of the light emitting cells and can restrict improvement in light extraction efficiency. Thus, a light emitting diode, for example an AC LED, has been developed, which is based on a substrate separation method and comprises light emitting cells connected in series.US 2010 / 0140640 A1 discloses a light-emitting diode having a semiconductor stack, in which an upper semiconductor layer and an active layer are removed at a corner of the stack in order to expose a lower semiconductor layer for the contacting.US 2010 / 0207157 A1 discloses a light-emitting diode in which a first semiconductor layer and an active layer have contact holes through which a second semiconductor layer is contacted.[Disclosure of Invention][Technical Object]The invention provides a light emitting diode unit according to appended claim 1. Advantageous embodiments are set out in the dependent claims.Exemplary embodiments provide a wafer-level LED package and a method for manufacturing the same, wherein the wafer-level LED package may be directly formed as a module on a circuit board without using a conventional lead frame or a printed circuit board.Example embodiments also provide a wafer-level LED package and a method for manufacturing the same, having high efficiency and better heat dissipation.Example embodiments also provide a method of manufacturing an LED package that may reduce manufacturing time and cost for an LED module.Example embodiments also provide an LED module and a method for manufacturing the same, having high efficiency and better heat dissipation.Exemplary embodiments also provide a wafer-level light emitting diode unit and a method for manufacturing the same, including a plurality of light emitting cells, and may be directly formed as a module on a circuit board without using a conventional lead frame or a circuit board.Additional features of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.[Technical Solution]An exemplary embodiment of the present invention discloses an LED package comprising: a semiconductor stack including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer; a plurality of contact holes disposed in the second conductivity type semiconductor layer and the active layer, the contact holes exposing the first conductivity type semiconductor layer; a first bump disposed on a first side of the semiconductor stack, the first bump being electrically connected to the first conductivity type semiconductor layer via a plurality of contact holes; a second bump disposed on the first side of the semiconductor stack, the second bump being electrically connected to the second conductivity type semiconductor layer; and a protective insulating layer covering a sidewall of the semiconductor stack.An exemplary embodiment of the present invention discloses a light emitting diode module including the LED unit according to the aforementioned exemplary embodiments. The LED module may include a circuit board; the LED unit mounted on the circuit board; and a lens for adjusting the angle for alignment of the light emitted from the LED unit.An exemplary embodiment also discloses a method of manufacturing an LED package. The method includes forming a semiconductor stack including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer on a first substrate; patterning the semiconductor stack to form a chip isolation region; patterning the second conductivity type semiconductor layer and the active layer to form a plurality of contact holes exposing the first conductivity type semiconductor layer; forming a protective insulating layer covering a sidewall of the semiconductor stack in the chip isolation region; and forming a first bump and a second bump on the semiconductor stack. The first bump is electrically connected to the first conductivity type semiconductor layer via the plurality of contact holes, and the second bump is electrically connected to the second conductivity type semiconductor layer.An exemplary embodiment of the present invention also discloses a light emitting diode unit. The LED unit includes a plurality of light emitting cells, each including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer; a plurality of contact holes disposed in the second conductivity type semiconductor layer and the active layer of each of the light emitting cells, the contact holes exposing the first conductivity type semiconductor layer; a protective insulating layer covering a sidewall of each of the light emitting cells; a connector disposed on a first side of the light emitting cells and electrically connecting two adjacent light emitting cells to each other; a first bump disposed on a first side of the light emitting cells and electrically connected to the first conductivity type semiconductor layer via a plurality of contact holes of a first light emitting cell of the light emitting cells; a second bump disposed on the first side of the light emitting cells and electrically connected to the second conductivity type semiconductor layer of a second light emitting cell of the light emitting cells.An exemplary embodiment of the present invention also discloses a light emitting diode module including the above-described LED unit. The module includes a circuit board; the LED unit disposed on the circuit board; and a lens for adjusting the angle for alignment of the light emitted from the LED unit.An exemplary embodiment also discloses a method of manufacturing an LED package including a plurality of light emitting cells. The method includes forming a semiconductor stack including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer on a first substrate; patterning the semiconductor stack to form a chip separation region and a light emitting cell separation region; patterning the second conductivity type semiconductor layer and the active layer to form a plurality of light emitting cells, each light emitting cell having a plurality of contact holes exposing the first conductivity type semiconductor layer; forming a protective insulating layer covering a sidewall of the semiconductor stack in the chip separation region and the light emitting cell separation region; forming a connector to connect adjacent light emitting cells in series; and forming a first bump and a second bump on the plurality of light emitting cells. Here, the first bump is electrically connected to the first conductivity type semiconductor layer via the plurality of contact holes of a first light emitting cell of the light emitting cells, and the second bump is electrically connected to the second conductivity type semiconductor layer of a second light emitting cell of the light emitting cells.Both the foregoing general description and the following detailed description are to be understood as illustrative and explanatory of the invention and as further set forth as claimed.[Description of Drawings]The accompanying drawings, which provide a further understanding of the invention, are incorporated in and constitute a part of this specification. They illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. FIG. 1 is a schematic cross-sectional view of a light emitting diode unit according to a first exemplary embodiment of the invention. FIG. 2 is a schematic cross-sectional view of a light emitting diode unit according to a second exemplary embodiment. FIG. 3 is a cross-sectional view of a light emitting diode module including the light emitting diode unit according to the first exemplary embodiment. FIGS. 4 to 12 show a method of manufacturing the light emitting diode unit according to the first exemplary embodiment, wherein (a) is a plan view and (b) is a cross-sectional view taken along line A-A of (a) in FIGS. 5 to 10. FIG. 13 is a cross-sectional view showing a method of manufacturing the light emitting diode unit according to the second exemplary embodiment. FIG. 14 is a schematic cross-sectional view of a light emitting diode unit according to a third exemplary embodiment of the invention. FIG. 15 is a schematic cross-sectional view of a light emitting diode unit according to a fourth exemplary embodiment of the invention. FIG. 16 is a cross-sectional view of a light emitting diode module including the light emitting diode unit according to the third exemplary embodiment. FIGS. 17 to 26 show a method of manufacturing the light emitting diode unit according to the third exemplary embodiment, wherein (a) is a plan view and (b) is a cross-sectional view taken along line A-A of (a) in FIGS. 18 to 23. FIG. 27 is a cross-sectional view showing a method of manufacturing the light emitting diode unit according to the fourth exemplary embodiment.[Best Embodiment]Hereinafter, the invention will be described in more detail with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. However, the present invention may have many different embodiments and is not to be construed as being limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided to complete the disclosure and will fully convey the scope of the invention to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals in the drawings designate like elements.When an element such as a layer, film, region or substrate is referred to as being "on" another element, it will be appreciated that it may be directly on the other element or intervening elements may also be present. On the other hand, when an element is referred to as being "directly on" another element, there are no intervening elements present.FIG. 1 is a schematic cross-sectional view of an LED unit 100 according to a first exemplary embodiment of the present invention.Referring to FIG. 1, the LED unit 100 may include a semiconductor stack 30, a first contact layer 35, a second contact layer 31, a first insulating layer 33, a second insulating layer 37, a first electrode array 39 a, a second electrode array 39 b, a first bump 45 a, and a second bump 45 b. The LED unit 100 may further include an insulating layer 43, a dummy bump 45 c, and a wavelength converter 51.The semiconductor stack 30 comprises a first upper semiconductor layer of the first conductivity type 25, an active layer 27 and a lower semiconductor layer of the second conductivity type 29.The active layer 27 and the upper and lower semiconductor layers 25, 29 may consist of a III-N based semiconductor compound, for example of an (Al, Ga, In)N semiconductor. Each of the upper and lower semiconductor layers 25, 29 may be single-layered or multi-layered. For example, the upper and / or lower semiconductor layers 25, 29 may comprise an overlying lattice layer in addition to a contact layer and an overcoat layer. The active layer 27 may have a single quantum well structure or a multiple quantum well structure. The first conductivity type may be an n-type and the second conductivity type may be a p-type. Alternatively, the first conductivity type may be a p-type and the second conductivity type may be an n-type. Since the upper semiconductor layer 25 can be formed of an n-type semiconductor layer having a relatively low resistivity, the upper semiconductor layer 25 can have a relatively large thickness. Therefore, a roughened surface R may be formed on the top surface of the upper semiconductor layer 25, the roughened surface R increasing extraction efficiency of light generated in the active layer 27.The semiconductor stack 30 includes a plurality of contact holes 30 a(see FIG. 5( b) ) formed through the second conductivity type lower semiconductor layer 29 and the active layer for exposing the first conductivity type upper semiconductor layer, and the first contact layer 35 is in contact with the first conductivity type upper semiconductor layer 25 exposed in the plurality of contact holes.The second contact layer 31 is in contact with the lower semiconductor layer of the second conductivity type 29. the second contact layer 31 includes a reflective metal layer for reflecting the light generated in the active layer 27. Further, the second contact layer 31 may be in ohmic contact with the lower second conductivity type semiconductor layer 29.The first insulating layer 33 covers the second contact layer 31, and the first insulating layer 33 covers a side wall of the semiconductor stack 30 exposed in the plurality of contact holes 30 a. In addition, the first insulating layer 33 may cover a side surface of the semiconductor stack 30. The first insulating layer 33 isolates the first contact layer 35 from the second contact layer 31 and also isolates the second conductivity type lower semiconductor layer 29 exposed in the plurality of contact holes 30 aand the active layer 27 from the first contact layer 35. Alternatively, the first insulating layer 33 may be constructed of a distributed Bragg reflector formed by alternately overlying insulating layers having different refractive indices, for example, SiO 2 / TiO 2 or SiO 2 / Nb 2 O 5.The first contact layer 35 is disposed under the first insulating layer 33, and is in contact with the upper first conductivity type semiconductor layer 25 through the first insulating layer 33 via a plurality of contact holes 30 a. The first contact layer 35 includes contact portions 35 afor contacting the first conductivity type upper semiconductor layer 25 and a connection portion 35 bfor connecting the contact portions 35 ato each other. Therefore, the contact portions 35 aare electrically connected to each other by the connection portions 35 b. The first contact layer 35 is formed under some portions of the first insulating layer 33, and may be formed of a reflective metal layer.The second insulating layer 37 located below the first contact layer 35 covers the first contact layer 35 and the second insulating layer 37 covers the first insulating layer 33 while covering a side surface of the semiconductor stack 30. the second insulating layer 37 may be made of a single layer or multiple layers. Further, the second insulating layer 37 may be a distributed Bragg reflector.The first and second electrode pads 39 a, 39 bare disposed under the second insulating layer 37. The first electrode array 39 amay be connected to the first contact layer 35 through the second insulating layer. Further, the second electrode array 39 bmay be connected to the second contact layer 31 through the second insulating layer 37 and the first insulating layer 33.The first land 45 aand the second land 45 bare disposed under the first and second electrode pads 39 a, 39 band are connected to the corresponding electrode pads. The first and second bumps 45 aand 45 bmay be formed by plating. The first and second bumps 45 a, 45 bare terminals electrically connected to a circuit board such as an MC PCB, and have plane parallel distal ends. In addition, the first electrode array 39 amay be formed at the height of the second electrode array 39 bsuch that the first protrusion 45 aand the second protrusion 45 bmay also be formed on the same plane. Therefore, the first and second protrusions 45 a, 45 bmay have the same height.Meanwhile, the dummy bump 45 cmay be disposed between the first bump 45 aand the second bump 45 b. The dummy bump 45 cmay be formed together with the first and second bumps 45 aand 45 bto provide a heat passage for dissipating heat from the semiconductor stack 30.The insulating layer 43 may cover the side surfaces of the first and second bumps 45 a, 45 b. The insulating layer 43 may also cover a side surface of the dummy bump 45 c. In addition, the insulating layer 43 fills the gaps among the first bump 45 a, the second bump 45 b, and the dummy bump 45 cto prevent moisture from entering the semiconductor stack 30 from the outside. In order to protect the first and second electrode pads 39 a, 39 bfrom external environmental factors such as moisture, the insulating layer 43 also covers the side surfaces of the first and second electrode pads 39 a, 39 b. Although the insulating layer 43 may be formed to cover the entire side surfaces of the first and second bumps 45 a, 45 b, the invention is not limited thereto. Alternatively, the insulating layer 43 may cover the side surfaces of the first and second protrusions 45 a, 45 b, except for some areas of the side surfaces near the distal ends of the first and second protrusions.In the present exemplary embodiment, the insulating layer 43 is illustrated as covering the side surfaces of the first and second electrode pads 39 a, 39 b, but the invention is not limited thereto. Alternatively, another insulating layer may be used to cover the first and second electrode pads 39 a, 39 band the insulating layer 43 may be formed under the other insulating layer. In this case, the first and second bumps 45 a, 45 bmay be connected to the first and second electrode pads 39 a, 39 bthrough the other insulating layer.The wavelength converter 51 may be disposed on the first conductivity type upper semiconductor layer 25 on the side opposite to the remaining semiconductor stack 30. The wavelength converter 51 may be adjacent to a top surface of the first conductivity type semiconductor layer 25. The wavelength converter 51 may be a phosphor sheet of uniform thickness, without being limited thereto. Alternatively, the wavelength converter 51 may be a substrate, for example, a sapphire substrate or a silicon substrate, doped with an impurity for wavelength conversion.In the present exemplary embodiment, the side surface of the semiconductor stack 30 is covered with a protective insulating layer. The protective insulating layer may include, for example, the first insulating layer 33 and / or the second insulating layer 37. In addition, for protection from external environmental influences, the first contact layer 35 may be covered with the second insulating layer 37, and the second contact layer 31 may be covered with the first insulating layer 33 and the second insulating layer 37. The first and second electrode pads 39 a, 39 bare also covered by the insulating layer 43, for example. Accordingly, it is possible to prevent damage to the semiconductor stack 30 by moisture.The wavelength converter 51 may be mounted on the upper semiconductor layer of the first conductivity type 25 at wafer level and is then cut together with the protective insulating layer during a chip separation process. Therefore, a side surface of the wavelength converter 51 may be in line with the protective insulating layer. That is, the side surface of the wavelength converter 51 may be rectilinearly flush with a side surface of the protective insulating layer. Further, the side surface of the wavelength converter 51 may be in line with a side surface of the insulating layer 43. Thus, the side surface of the wavelength converter 51, the protective insulating layer, and the insulating layer 43 may be flush on a line.FIG. 2 is a schematic cross-sectional view of a light emitting diode unit 200 according to a second exemplary embodiment.Referring to FIG. 2, the LED unit 200 is almost the same as the above-described LED unit 100 according to the above exemplary embodiment. However, in the present exemplary embodiment, first and second bumps 65 a, 65 bare formed in a substrate 61.Specifically, the substrate 61 includes through holes having the first and second bumps 65 a, 65 bformed therein, respectively. The substrate 61 is an insulating substrate, for example, a sapphire substrate or a silicon substrate, without being limited thereto. The substrate 61 having the first and second bumps 65 a, 65 bmay be mounted on a first electrode array 39 aand a second electrode array 39 b. In order to prevent the first and second electrode pads 39 a, 39 bfrom being exposed to the outside, an insulating layer 49 may cover the side surfaces and lower surfaces of the first and second electrode pads 39 a, 39 b. Further, the insulating layer 49 may include openings exposing the first and second electrode arrays 39 a, 39 band additional metal layers 67 a, 67 bthus formed in the openings. The additional metal layers 67 a, 67 bmay be made of a bonding metal.FIG. 3 is a cross-sectional view of a light emitting diode module including the LED unit 100 according to the first exemplary embodiment.Referring to FIG. 3, the LED module includes a circuit board 71 such as an MC PCB, the LED unit 100, and a lens 81 The circuit board 71 such as the MC PCB has pads 73 a, 73 bto mount the LED units 100 thereon. The first and second bumps 45 a, 45 b(see FIG. 1 ) of the LED unit 100 are connected to the corresponding pads 73 a, 73 b.A plurality of LED units 100 may be mounted on the circuit board 71, and the lens 81 may be disposed on the LED units 100 to adjust the angle for alignment of the light emitted from the LED units 100.According to the second exemplary embodiment, the light emitting diode units 200 may be mounted on the circuit board instead of the LED units 100.FIGS. 4 to 12 show a method of manufacturing the LED unit 100 according to the first exemplary embodiment. In FIGS. 5 to 10, (a) is a plan view and (b) is a cross-sectional view taken along line A-A of (a).Referring to FIG. 4, a semiconductor stack 30 including a first conductivity type semiconductor layer 25, an active layer 27, and a second conductivity type semiconductor layer 29 is formed on a growth substrate 21. The growth substrate 21 may be, but is not limited to, a sapphire substrate. Alternatively, the growth substrate 21 may be another type of heterogeneous substrate, for example, a silicon substrate. The semiconductor layer of both the first and second conductivity types 25, 29 may be constructed from a single layer or multiple layers. Furthermore, the active layer 27 may have a single quantum well structure or a multiple quantum well structure.The compound semiconductor layers may be formed of a III-N based semiconductor on the growth substrate 21 by metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).A buffer layer (not shown) may be formed prior to forming the compound semiconductor layers. The buffer layer is formed for correcting a lattice mismatch between the growth substrate 21 and the compound semiconductor layers, and may be formed of a GaN-based material layer such as gallium nitride or aluminum nitride.Referring to FIGS. 5 (a) and (b), the semiconductor stack 30 is patterned to form a chip (chip unit) separation region 30 b, and the second conductivity type semiconductor layer 29 and the active layer 27 are patterned to form a plurality of contact holes 30 athat expose the first conductivity type semiconductor layer 25. The semiconductor stack 30 may be patterned by photolithography and etching methods.The chip separation region 30 bis a region for cutting the pattern of LED units into individual LED units, and the side surfaces of the first conductivity type semiconductor layer 25, the active layer 27, and the second conductivity type semiconductor layer 29 are exposed in the chip separation region 30 b. Advantageously, the chip separation region 30 bmay be configured to expose the substrate 21, but is limited thereto.The plurality of contact holes 30 amay be circular, without being limited thereto. The contact holes 30 can be shaped in various ways. The second conductivity type semiconductor layer 29 and the active layer 27 are exposed on the sidewalls of the plurality of contact holes 30 a. As shown, the contact holes 30 amay have inclined sidewalls.Referring to FIGS. 6(a) and (b), a second contact layer 31 is formed on the second conductivity type semiconductor layer 29. The second contact layer 31 is formed on the semiconductor stack 30 except for the regions corresponding to the plurality of contact holes 30 a.The second contact layer 31 may include a transparent conductive oxide film such as indium tin oxide (ITO) or a reflective metal layer such as silver (Ag) or aluminum (Al). The second contact layer 31 may be composed of a single layer or multiple layers. The second contact layer 31 may also be configured to be in ohmic contact with the second conductivity type semiconductor layer 29.The second contact layer 31 may be formed before or after the formation of the plurality of contact holes 30 a.Referring to FIGS. 7( a) and ( b), a first insulating layer 33 is formed to cover the second contact layer 31. The first insulating layer 33 may cover the side surface of the semiconductor stack 30 exposed to the chip separation region 30 b, covering the sidewalls of the plurality of contact holes 30 a. Here, the first insulating layer 33 may include openings 33 athat expose the first conductivity type semiconductor layer 25 in the plurality of contact holes 30 a.The first insulating layer 33 may be made of a single layer or multiple layers, such as a silicon oxide or silicon nitride film. Alternatively, the first insulating layer 33 may be a distributed Bragg reflector formed by alternately overlying insulating layers having different refractive indices. For example, the first insulating layer 33 may be formed by alternately stacking SiO 2 / TiO 2 or SiO 2 / Nb 2 O 5. Further, the first insulating layer 33 may be formed by adjusting the thickness of each of the insulating layers so as to provide a high-reflectivity distributed Bragg reflector over a wide wavelength range of blue, green and red light.Referring to FIGS. 8(a) and (b), a first contact layer 35 is formed on the first insulating layer 33. The first contact layer 35 includes contact portions 35 athat are in contact with the upper first conductivity type semiconductor layer 25 exposed in the contact holes 30 aand a connection portion 35 bthat connects the contact portions 35 ato each other. The first contact layer 35 may be made of a metal reflective layer, but is not limited thereto.The first contact layer 35 is formed in some regions of the semiconductor stack 30 such that the first insulating layer 33 is exposed in other regions of the semiconductor stack 30 in which the first contact layer 35 is not formed.Referring to FIGS. 9 (a) and (b), a second insulating layer 37 is formed on the first contact layer 35. The second insulating layer 37 may be made of a single layer or multiple layers, such as a silicon oxide or silicon nitride film. Further, the second insulating layer 37 may be composed of a distributed Bragg reflector formed by alternately overlying insulating layers having different refractive indices.The second insulating layer 37 may cover the first contact layer 35, and also covers the first insulating layer 33. The second insulating layer 37 may also cover the side surface of the semiconductor stack 30 in the chip separation region 30 b.The second insulating layer 37 has an opening 37 athat exposes the first contact layer 35. Further, the second insulating layer 37 and the first insulating layer 33 are formed with an opening 37 bexposing the second contact layer 31.Referring to FIGS. 10( a) and ( b), the first and second electrode pads 39 a, 39 bare formed on the second insulating layer 37. The first electrode array 39 ais connected to the first contact layer 35 through the opening 37 a, and the second electrode array 39 bis connected to the second contact layer 31 through the opening 37 b.The first electrode array 39a is separated from the second electrode array 39b, and both the first and second electrode arrays 39a, 39b can take a relatively large area, for example, not less than 1 / 3 of the area of the LED unit, in plan view.Referring to FIG. 11, an insulating layer 43 is formed on the first and second electrode pads 39 aand 39 b. The insulating layer 43 covers the first and second electrode pads 39 a, 39 band has recesses exposing the upper surfaces of the electrode pads 39 a, 39 b. Further, the insulating layer 43 may include a trench exposing the second insulating layer 37 between the first and second electrode pads 39 a, 39 b.Subsequently, the first and second bumps 45 a, 45 bare formed in the recesses of the insulating layer 43, and a dummy bump 45 cmay be formed between the first bump and the second bump.The protrusions may be formed by plating, for example, electroplating using a metallic material. If desired, a seed layer for plating may also be formed.After the first and second bumps 45 aand 45 bare formed, the insulating layer 43 may be removed. For example, the insulating layer 43 may be formed of a polymer such as a photoresist and removed after the formation of the bumps. Alternatively, the insulating layer 43 may remain for protecting the side surfaces of the first and second protrusions 45 a, 45 b.In the present embodiment, the insulating layer 43 is illustrated as being formed directly on the first and second electrode pads 39 a, 39 b. In other exemplary embodiments, another insulating layer may be formed to cover the first and second electrode pads 39 a, 39 b. The other insulating layer may be formed to have openings exposing the first and second electrode pads 39 a, 39 b. Subsequently, the methods of forming the insulating layer 43 and the bumps may be performed.Referring to FIG. 12, the growth substrate 21 is removed and a wavelength converter is mounted on the first conductivity type semiconductor layer 25. The growth substrate 21 may be removed by an optical method such as a laser lift-off (LLO) method, mechanical polishing, or chemical etching.Subsequently, the exposed surface of the first conductivity type semiconductor layer 25 is anisotropically etched, such as by photoelectrochemical etching (PEC), to form a roughened surface on the first conductivity type semiconductor exposed layer 25.Meanwhile, the wavelength converter such as a phosphor sheet containing phosphors may be mounted on the first conductivity type semiconductor layer 25.Alternatively, the growth substrate 21 may contain an impurity for converting a wavelength of the light generated in the active layer 27. In this case, the growth substrate 21 may be used as the wavelength converter 51.Then, the LED unit pattern is divided into individual units along the chip separation region 30b to provide completed LED units 100. At this time, the second insulating layer 37 is cut together with the wavelength converter 51 so that the cut planes thereof can be formed in a line.FIG. 13 is a cross-sectional view illustrating a method of manufacturing the LED unit 200 according to the second exemplary embodiment.Referring to FIG. 13, the operations in the manufacturing method of the LED unit 200 according to the present exemplary embodiment up to the formation of the first and second electrode pads 39 a, 39 bare the same as those in the above-described (FIGS. 10( a) and ( b)) manufacturing method of the LED unit 100.After forming the first and second electrode pads 39a, 39b, an insulating layer 49 is formed to cover the first and second electrode pads 39a, 39b. The insulating layer 49 may cover the side surfaces of the first and second electrode pads 39 a, 39 bfor protecting the first and second electrode pads 39 a, 39 b. The insulating layer 49 has openings exposing the first and second electrode pads 39a, 39b. Additional metal layers 67a, 67b are then formed in the openings. The additional metal layers 67 a, 67 bmay be made of a bonding metal.The substrate 61 is bonded to the first and second electrode pads 39 a, 39 b. The substrate 61 may have through holes in which the first and second bumps 65 a, 65 bmay be formed. Further, at the distal ends of the first and second protrusions, pads 69 a, 69 bmay be formed. The substrate 61 including the first and second bumps 65 a, 65 band the pads 69 a, 69 bmay be separately manufactured and bonded to a wafer including the first and second electrode pads 39 a, 39 b.Subsequently, as described with reference to FIG. 12, the growth substrate 21 is removed, and a wavelength converter 51 may be applied to the first conductivity type semiconductor layer 25, followed by dividing the structure of LED units into individual LED units. As a result, the completed LED units 200 as described in FIG. 2 are provided.FIG. 14 is a cross-sectional view of an LED unit 300 according to a third exemplary embodiment of the present invention.Referring to FIG. 14, the LED unit 300 may include a semiconductor stack 130 divided into a plurality of light emitting cells (only two light emitting cells S 1, S 2 are shown here), a first contact layer 135, a second contact layer 131, a first insulating layer 133, a second insulating layer 137, a first electrode array 139 a, a second electrode array 139 b, a connector 139 cthat connects adjacent light emitting cells in series, a first bump 145 a, and a second bump 145 b. Further, the LED unit 300 may include a third insulating layer 141, an insulating layer 143, a dummy bump 145 c, a wavelength converter 151, and additional metal layers 140 a, 140 b.The semiconductor stack 130 includes upper one of a first conductivity type semiconductor layer 125, an active layer 127, and a lower one of the second conductivity type semiconductor layers 129. The semiconductor stack 130 of the present exemplary embodiment is almost the same as the semiconductor stack 30 described in FIG. 1, and its detailed description is omitted herein.Each of the light emitting cells S 1, S 2 has a plurality of contact holes 130 a(see FIG. 18( b) ) that extend through the lower second conductivity type semiconductor layer 129 and the active layer 127 to expose the upper first conductivity type semiconductor layer, and the first contact layer 135 is in contact with the upper first conductivity type semiconductor layer 125 exposed in the plurality of contact holes. The light emitting cells S 1, S 2 are separated from each other by a region for separating the cells 130 b(see FIG. 18( b)).The second contact layer 131 is in contact with the lower second conductivity type semiconductor layer 129 of each of the light emitting cells S 1, S 2. The second contact layer 131 comprises a reflective metal layer for reflecting the light generated in the active layer 127. Further, the second contact layer 131 may be in ohmic contact with the lower second conductivity type semiconductor layer 129.The first insulating layer 133 covers the second contact layer 131. Further, the first insulating layer 133 covers a sidewall of the semiconductor stack 130 exposed in the plurality of contact holes 130 a. In addition, the first insulating layer 133 may cover a side surface of each of the light emitting cells S 1, S 2. The first insulating layer 133 isolates the first contact layer 135 from the second contact layer 131, and also isolates the lower second conductivity type semiconductor layer 129 exposed in the plurality of contact holes 130 aand the active layer 127 from the first contact layer 35. The first insulating layer 133 may be made of a single layer or multiple layers, such as a silicon oxide or silicon nitride film. In addition, the first insulating layer 133 may be composed of a distributed Bragg reflector formed by alternately overlying insulating layers having different refractive indices, for example, SiO 2 / TiO 2 or SiO 2 / Nb 2 O 5.The first contact layer 135 is disposed under the first insulating layer 133 and is in contact with the upper first conductivity type semiconductor layer 125 through the first insulating layer 133 in the plurality of contact holes 130 ain each of the light emitting cells S 1, S 2. The first contact layer 135 includes contact portions 135 acontacting the first conductivity type upper semiconductor layer 125, and a connection portion 135 bconnecting the contact portions 135 ato each other. Therefore, the contact portions 135 aare electrically connected to each other by the connection portion 135 b. The first contact layers 135 disposed under the respective light emitting cells S 1, S 2 are separated from each other and formed under some regions of the first insulating layer 133. The first contact layer 135 may be made of a reflective metal layer.The second insulating layer 137 located below the first contact layer 135 covers the first contact layer 135. In addition, the second insulating layer 137 may cover the first insulating layer 133 and also cover the side surface of each of the light emitting cells S 1, S 2. The second insulating layer 137 may be composed of a single layer or multiple layers. Alternatively, the second insulating layer 37 may be a distributed Bragg reflector.The first electrode array 139 aand the second electrode array 139 bare disposed under the second insulating layer 137. The first electrode array 139 amay be connected to the first contact layer 135 of a first light emitting cell S 1 through the second insulating layer 137. Further, the second electrode array 139 bmay be connected to the second contact layer 31 of a second light emitting cell S 2 through the second insulating layer 137 and the first insulating layer 133.The connector 139 cis disposed under the second insulating layer 137 and electrically connects two adjacent light emitting cells S 1, S 2 to each other through the second insulating layer 137. The connector 139 cmay connect the second contact layer 131 of one light emitting cell S 1 to the first contact layer 135 of another light emitting cell S 2 adjacent thereto such that the two light emitting cells S 1, S 2 are connected in series.In the present exemplary embodiment, two light emitting cells S 1, S 2 are illustrated. However, it is understood that two or more light emitting cells may be connected in series via a plurality of connectors 139c. Here, the first and second electrode arrays 139a, 139b of the light emitting cells S1, S2 may be connected in series, opposing each other in such a row-by-row arrangement.Meanwhile, the third insulating layer 141 located below the first electrode array 139 a, the second electrode array 139 b, and the connector 139 cmay cover the first electrode array 139 a, the second electrode array 139 b, and the connector 139 c. The third insulating layer 141 may have an opening exposing the first electrode array 139 aand the second electrode array 139 b. The third insulating layer 141 may be formed of a silicon oxide or silicon nitride film.The first bump 145 aand the second bump 145 bare disposed under the first and second electrode pads 139 a, 139 b, respectively. The first and second bumps 145 a, 145 bmay be formed by plating. The first and second bumps 145 a, 145 bare terminals electrically connected to a circuit board such as an MC PCB, and have distal ends plane parallel to each other. In addition, the first electrode array 139 amay be formed at the same height as the second electrode array 139 bsuch that the first bump 45 aand the second bump 45 bmay also be formed on the same plane. Therefore, the first and second protrusions 45 a, 45 bmay have the same height.The additional metal layers 140 a, 140 bmay be disposed between the first bump 145 aand the first electrode array 139 aand between the second bump 145 band the second electrode array 139 b. Here, the additional metal layers 140 a, 140 bare provided so that the first and second electrode pads 139 a, 139 bare higher than the connector 139 cand may be disposed within the openings of the third insulating layer 141. The first and second electrode pads 139 a, 139 band the additional metal layers 140 a, 140 bmay form the finished electrode pads.Meanwhile, the dummy bump 145 cmay be disposed between the first bump 145 aand the second bump 145 b. The dummy bump 145 cmay be formed together with the first and second bumps 145 a, 145 bto provide a heat passage for dissipating heat from the light emitting cells S 1, S 2. The dummy bump 145 cis separated from the connector 139 cby the third insulating layer 141.The insulating layer 143 may cover the side surfaces of the first and second bumps 145 a, 145 b. The insulating layer 143 may also cover a side surface of the dummy bump 145 c. In addition, the insulating layer 143 fills the gaps between the first bump 145 a, the second bump 145 b, and the dummy bump 145 cin order to prevent moisture from entering the semiconductor stack 130 from the outside. Although the insulating layer 143 may be formed to cover the entire side surfaces of the first and second bumps 145 a, 145 b, the invention is not limited thereto. Alternatively, the insulating layer 143 may cover the side surfaces of the first and second protrusions 145 a, 145 b, except for some portions of the side surfaces near the distal ends of the first and second protrusions.The wavelength converter 151 may be disposed on the light emitting cells S 1, S 2. The wavelength converter 151 may be adjacent to a top surface of the upper first conductivity type semiconductor layer 125. The wavelength converter 151 may also cover a region for separating the cells 130 band a chip separation region. The wavelength converter 151 may be a phosphor sheet of uniform thickness, without being limited thereto. Alternatively, the wavelength converter 51 may be a substrate, for example, a sapphire substrate or a silicon substrate, doped with an impurity for wavelength conversion.In the present exemplary embodiment, the side surfaces of the light emitting cells S 1, S 2 are covered with a protective insulating layer. The protective insulating layer may include, for example, the first insulating layer 133 and / or the second insulating layer 137. In addition, for protection from external environmental influences, the first contact layer 135 may be covered with the second insulating layer 137, and the second contact layer 131 may be covered with the first insulating layer 133 and the second insulating layer 137. Further, the first and second electrode pads 139 a, 139 bare also covered by the third insulating layer 141, for example. Accordingly, it is possible to prevent damage of the light emitting cells S 1, S 2 by moisture.The wavelength converter 151 may be mounted on the upper wafer-level first conductivity type semiconductor layer 125 and is then cut together with the protective insulating layer during a chip separation process (or unit separation process). Therefore, a side surface of the wavelength converter 151 may be in line with the protective insulating layer. Further, the side surface of the wavelength converter 151 may be in line with a side surface of the insulating layer 143.FIG. 15 is a schematic cross-sectional view of a light emitting diode unit 400 according to a fourth exemplary embodiment of the present invention.Referring to FIG. 15, the LED unit 400 is almost the same as the LED unit 300 according to the above exemplary embodiment. However, in the present exemplary embodiment, first and second bumps 165 a, 165 bare formed in a substrate 161.In particular, the substrate 161 includes through-holes having the first and second bumps 165 a, 165 bformed therein, respectively. The substrate 161 is an insulating substrate, for example, a sapphire substrate or a silicon substrate, without being limited thereto.The substrate 161 having the first and second bumps 165 a, 165 bmay be mounted on a third insulating layer 141, and the first and second bumps 165 a, 165 bmay be connected to the first and second electrode pads 139 a, 139 b, respectively. Here, the first and second bumps 165 a, 165 bmay be bonded to the additional metal layers 140 aand 140 b, respectively.FIG. 16 is a cross-sectional view of a light emitting diode module including the LED units 300 according to the third exemplary embodiment on a printed circuit board.Referring to FIG. 16, the LED module includes a circuit board 171, for example, an MC PCB, the LED unit 300, and a lens 181. The circuit board 171, for example, the MC PCB, has pads 173 a, 173 bto mount thereon the LED units 300. The first and second bumps 145 a, 145 b(see FIG. 14 ) of the LED unit 300 are connected to the corresponding pads 173 a, 173 b.A plurality of LED units 300 may be mounted on the circuit board 171, and the lens 181 may be disposed on the LED units 300 to adjust the angle for alignment of the light emitted from the LED units 300.In other exemplary embodiments, the light emitting diode units 400 may be mounted on the circuit board instead of the LED units 300.FIGS. 17 to 25 show a method of manufacturing the LED unit 300 according to the third exemplary embodiment. In FIGS. 18 to 23, (a) is a plan view and (b) is a cross-sectional view taken along the line A-A of (a).Referring to FIG. 17, a semiconductor stack 130 including a first conductivity type semiconductor layer 125, an active layer 127, and a second conductivity type semiconductor layer 129 is formed on a growth substrate 121. The growth substrate 121 and the semiconductor stack 130 are almost the same as the substrate 21 and the semiconductor stack 30 described with reference to FIG. 4, and therefore, their detailed description will be omitted here.Referring to FIGS. 18 (a) and (b), the semiconductor stack 130 is patterned to form a separation region 130 cof the chip (the chip unit) and a region for separating the cells 130 b, while the second conductivity type semiconductor layer 129 and the active layer 127 are patterned to form the light emitting cells S 1, S 2, each having a plurality of contact holes 130 athat exposes the first conductivity type semiconductor layer 125. The semiconductor stack 130 may be patterned by photolithography and etching methods.The chip separation region 130 cis a region for cutting the pattern of LED units into individual LED units, and the side surfaces of the first conductivity type semiconductor layer 125, the active layer 127, and the second conductivity type semiconductor layer 129 are exposed in the chip separation region 130 c. Advantageously, the chip separation region 130 cand the region for separating the cells 130 bmay be configured to expose the substrate 121, but be limited thereto.The plurality of contact holes 130 amay be circular, without being limited thereto. The contact holes 130 can be shaped in various ways. The second conductivity type semiconductor layer 129 and the active layer 127 are exposed at the sidewalls of the plurality of contact holes 130 a. The contact holes 130 amay have inclined sidewalls.Referring to FIG. 19 (a) and (b), a second contact layer 131 is formed on the second conductivity type semiconductor layer 129. The second contact layer 131 is formed on the semiconductor stack 130 in each of the light emitting cells S 1, S 2 except for the regions corresponding to the plurality of contact holes 130 a.The second contact layer 131 may include a transparent conductive oxide film such as indium tin oxide (ITO) or a reflective metal layer such as silver (Ag) or aluminum (Al). The second contact layer 131 may be composed of a single layer or multiple layers. The second contact layer 131 may also be configured to be in ohmic contact with the second conductivity type semiconductor layer 129.The second contact layer 131 may be formed before or after formation of the plurality of contact holes 130 a.Referring to FIGS. 20 (a) and (b), a first insulating layer 133 is formed to cover the second contact layer 131. The first insulating layer 133 may cover the side surface of each of the light emitting cells S 1, S 2, and also cover the sidewalls of the plurality of contact holes 130 a. Here, the first insulating layer 133 may include openings 133 athat expose the first conductivity type semiconductor layer 125 in the plurality of contact holes 130 a.The first insulating layer 133 may be made of a single layer or multiple layers, such as a silicon oxide or silicon nitride film. In addition, the first insulating layer 133 may be composed of a distributed Bragg reflector formed by alternately overlying insulating layers having different refractive indices. For example, the first insulating layer 133 may be formed by alternately stacking SiO 2 / TiO 2 or SiO 2 / Nb 2 O 5. Further, the first insulating layer 133 may be formed by adjusting the thickness of each of the insulating layers so as to provide a high-reflectivity distributed Bragg reflector over a wide wavelength range of blue, green and red light.Referring to FIG. 21 (a) and (b), a first contact layer 135 is formed on the first insulating layer 133. The first contact layer 135 is formed on each light emitting cell S 1, S 2, and includes contact regions 35 athat are in contact with the upper first conductivity type semiconductor layer 125 exposed in the contact holes 130 aand a connection portion 135 bthat connects the contact portions 135 ato each other. The first contact layer 135 may be made of a metal reflective layer, but is not limited thereto.The first contact layer 135 is formed in some regions of each of the light emitting cells S 1, S 2 such that the first insulating layer 133 is exposed in other regions of the semiconductor stack 130 in which the first contact layer 135 is not formed.Referring to FIGS. 22 (a) and (b), a second insulating layer 137 is formed on the first contact layer 135. The second insulating layer 137 may be made of a single layer or multiple layers, such as a silicon oxide film or silicon nitride film. Alternatively, the second insulating layer 137 may be a distributed Bragg reflector formed by alternately overlying insulating layers having different refractive indices.The second insulating layer 137 may cover the first contact layer 135, and also covers the first insulating layer 133. The second insulating layer 137 may also cover the side surface of each of the light emitting cells S 1, S 2. In addition, the second insulating layer 137 may fill the chip separation region 130 cand the region for separating the cells 130 b.The second insulating layer 137 has an opening 137 athat exposes the first contact layer 135 from each of the light emitting cells S 1, S 2. Further, the second insulating layer 137 and the first insulating layer 133 are formed with an opening 137 bexposing the second contact layer 131.Referring to FIGS. 23( a) and ( b), a connector 139 cand the first and second electrode pads 139 a, 139 bare formed on the second insulating layer 137. The first electrode array 139 ais connected to the first contact layer 135 of a first light emitting cell S 1 through the opening 137 a, and the second electrode array 139 bis connected to the second contact layer 131 of a second light emitting cell S 2 through the opening 137 b. Further, the connector 139 cconnects the first contact layer 135 and the second contact layer 131 of adjacent light emitting cells S 1, S 2 in series through the openings 137 a, 137 b.Referring to FIG. 24, a third insulating layer 141 is formed on the first and second electrode pads 139 a, 139 band the connector 139 c. The third insulating layer 141 covers the first and second electrode pads 139 a, 139 band the connector 139 cand has recesses exposing the upper surfaces of the electrode pads 139 a, 139 b. Meanwhile, the third insulating layer 141 may include additional metal layers 140 a, 140 bformed in their recesses. The additional metal layers 140 a, 140 bincreases the height of the electrode pads 139 a, 139 bsuch that the finished electrode pads may be located higher than the connector 139 c. The additional metal layers 140 a, 140 bmay be formed before forming the third insulating layer 141. The top surfaces of the additional metal layers 140 a, 140 bmay be substantially plane parallel to the top surface of the third insulating layer 141.Referring to FIG. 25, a patterned insulating layer 143 is formed on the third insulating layer 141. The patterned insulating layer 143 has recesses exposing the top surface of the first and second electrode pads 139 a, 139 b, for example, the additional metal layers 140 a, 140 b. Further, the patterned insulating layer 143 may include a trench exposing the third insulating layer 141 between the first electrode array 139 aand the second electrode array 139 b.Subsequently, the first and second bumps 145 a, 145 bare formed in the recesses of the insulating layer 143, and a dummy bump 145 cmay be formed between the first and second bumps.The protrusions may be formed by plating, for example, electroplating. If desired, a seed layer for plating may also be formed.After the formation of the first and second bumps 145 aand 145 b, the insulating layer 143 may be removed. For example, the insulating layer 143 may be formed of a polymer, such as a photoresist, and removed after the formation of the bumps. Alternatively, the insulating layer 143 may remain for protecting the side surfaces of the first and second bumps 145 a, 145 b.Referring to FIG. 26, the growth substrate 121 is removed and a wavelength converter 151 is mounted on the light emitting cells S1, S2. The growth substrate 21 may be removed by an optical method such as a laser lift-off (LLO) method, mechanical polishing, or chemical etching.Subsequently, the exposed surface of the first conductivity type semiconductor layer 125 is anisotropically etched, such as by PEC etching, to form a roughened surface on the exposed first conductivity type semiconductor layer 125.Meanwhile, the wavelength converter 151 such as a phosphor sheet containing phosphors may be mounted on the first conductivity type semiconductor layer 125.Alternatively, the growth substrate 121 may contain an impurity for converting a wavelength of the light generated in the active layer 127. In this case, the growth substrate 121 may be used as the wavelength converter 151.Then, the LED unit pattern is divided into individual units along the chip separation region 130 c, thereby providing completed LED units 300. At this time, the second insulating layer 137 is cut together with the wavelength converter 151 so that the cut planes thereof can be formed in a line.FIG. 27 is a cross-sectional view showing a method of manufacturing the LED unit 400 according to the fourth exemplary embodiment of the invention.Referring to FIG. 27, the operations in the manufacturing method of the LED unit 400 according to the present embodiment up to the formation of the third insulating layer 141 and the additional metal layers 140 a, 140 bare the same as those in the above-described manufacturing method of the LED unit 300 (FIG. 24 ).In the present exemplary embodiment, the substrate 161 is bonded to the third insulating layer 141. The substrate 161 may include through-holes in which the first and second bumps 165 a, 165 bmay be formed. Further, pads (not shown) may be formed at the distal ends of the first and second bumps 165a, 165b. In addition, the substrate 161 may have cut-outs partially formed on its bottom side and filled with a metallic material 165c. The metallic material 165c improves heat dissipation.Alternatively, the substrate 161 including the first and second bumps 165 a, 165 bmay be separately manufactured and bonded to a wafer including the first and second electrode pads 139 a, 139 b. The first and second bumps 165 a, 165 bmay be electrically connected to the first and second electrode pads 139 a, 139 b, respectively.Subsequently, as described with reference to FIG. 26, the growth substrate 121 is removed, and a wavelength converter 151 may be applied to the light emitting cells S 1, S 2 followed by dividing the structure of LED units into individual LED units. As a result, the completed LED units 400 as described in FIG. 15 are provided.Thus, the exemplary embodiments of the invention provide wafer level LED devices that can be formed directly on a module fabrication circuit board without the use of a conventional leadframe or printed circuit board. Accordingly, the LED package can have high efficiency and better heat dissipation, reducing cost and time for manufacturing the LED package. In addition, an LED module having the LED unit mounted thereon can have high efficiency and better heat dissipation.Furthermore, the LED unit may include a plurality of light emitting cells connected in series and arrays connected in antiparallel. Further, the plurality of light emitting cells may be connected to a bridge rectifier and used to form a bridge rectifier. Therefore, the LED module including the LED unit can be driven with direct current without a separate AC / DC converter.

Claims

A light emitting diode, LED, unit comprising: a semiconductor stack (30) comprising a first conductivity type semiconductor layer (25), a second conductivity type semiconductor layer (29), and an active layer (27) disposed between the first (25) and second conductivity type semiconductor layers (29), wherein a plurality of contact holes (30a) are present in the second conductivity type semiconductor layer (29) and the active layer (27) exposing the first conductivity type semiconductor layer (25); a first bump (45a) disposed on a first side of the semiconductor stack, the first bump (45a) being electrically connected to the first conductivity type semiconductor layer (25) via the plurality of contact holes (30a); a second bump (45b) disposed on the first side of the semiconductor stack, the second bump (45b) being electrically connected to the second conductivity type semiconductor layer (29); a first insulating layer (43) disposed on the first side of the semiconductor stack (30) and covering a side surface of the first bump (45a); and a wavelength converter (51) disposed on a second side of the semiconductor stack (30), wherein the wavelength converter (51) protrudes laterally beyond the semiconductor stack, and wherein the first insulating layer (43) includes a side surface flush with a side surface of the wavelength converter (51).The LED according to claim 1, further comprising: a first contact layer (35) disposed on the first conductivity type semiconductor layer (25); a second contact layer (31) disposed on the second conductivity type semiconductor layer (29); a second insulating layer (33) covering the second contact layer (31), a side surface of the active layer (27), and a side surface of the second conductivity type semiconductor layer (29), and contacting the first contact layer (35), wherein the second insulating layer (33) comprises a first opening (33a) exposing the first conductivity type semiconductor layer (25) and a second opening (37b) exposing the second contact layer (31); a third insulating layer (37) disposed on the second insulating layer (33), wherein the first insulating layer (43) is disposed on the third insulating layer (37) and covers a side surface of the second bump (45b).The LED of claim 2, wherein the third insulating layer (37) is at least partially arranged directly on the first contact layer (35).The LED according to claim 1, wherein the wavelength converter (51) comprises a phosphor sheet or a substrate doped with an impurity.The LED of claim 2, wherein the second insulating layer (33) separates the first contact layer (35) from the second contact layer (31).The LED of claim 2, wherein the second insulating layer (33), the third insulating layer (37), or both comprise a distributed Bragg reflector.The LED of claim 1, wherein the first insulating layer (43) comprises a polymer.The LED according to claim 1, wherein: the first conductivity type semiconductor layer (25) is an n-type semiconductor layer, and the second conductivity type semiconductor layer (29) is a p-type semiconductor layer.

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