Silicon carbide semiconductor device and method for manufacturing the same

Abstract

Silicon carbide semiconductor device comprising: a semiconductor substrate (5) comprising a substrate (1) of a first conductivity type, a drift layer (2) of a first conductivity type on the substrate (1) of a first conductivity type, a layer (3) of a second conductivity type on the drift layer (2), and a layer (4) of a first conductivity type on the layer (3) of a second conductivity type; a transistor formed in a transistor cell region (R1) of the semiconductor substrate (5); and an external breakdown-resistant structure formed in an external breakdown-resistant structural region (R2) surrounding an outer periphery of the transistor cell region (R1), wherein the external breakdown-resistant structure formed in the external breakdown-resistant structural region (R2) comprises a first recess (17) surrounding the outer periphery of the transistor cell region (R1).a first trench (13) located on a side face of the first depression (17) on an inner periphery of the first depression (17), and comprising an electric field relief structure having an embedded layer (15) of a second conductivity type, the first depression (17) being deeper than the layer (4) of a first conductivity type and the layer (3) of a second conductivity type and reaching the drift layer (2), the first trench (13) surrounding the outer periphery of the transistor cell region (R1), the embedded layer (15) of a second conductivity type being embedded in the first trench (13) and providing the side face of the first depression (17), the transistor cell region (R1) having a second trench (6), a channel layer (7) of a first conductivity type and a second gate region (8) of a second conductivity type, the first trench (13) and the second trench (6) having the same depth,and the embedded layer (15) of a second conductivity type is formed above an embedded layer (14) of a first conductivity type in the first trench (13), wherein the silicon carbide semiconductor device further comprises: a second well (16) which is deeper than one thickness of the layer (4) of a first conductivity type and surrounds the outer periphery of the transistor cell region (R1), wherein the first well (17) is located further away from the transistor cell region (R1) than the second well (16) and is deeper than the second well (16), and the first trench (13) is located at a boundary between the first well (17) and the second well (16).

Description

The present disclosure relates to a silicon carbide (hereinafter referred to as SiC) semiconductor device having an outer breakdown resistant region around a transistor cell region where JFET cells, MOSFET cells, or the like are formed, and also relates to a method of manufacturing the same.An SiC semiconductor device including a JFET having a trench structure is known (for example, see JP 2005-150 352 A). In the SiC semiconductor device, an N -- drift layer, a first P +- gate region and an N -- source region are sequentially formed on an N +- SiC substrate, a trench penetrating therethrough is formed, and then an N -- channel layer and a second P +- gate region are formed in the trench. A gate voltage applied to a gate electrode electrically connected to the second gate region is controlled so that a drain current can flow between a source electrode electrically connected to the N +- source region and a drain electrode electrically connected to the N +- SiC substrate.It can be assumed that when an external breakdown resistant structure is formed in such a SiC semiconductor device as described above, a mesa structure is formed by forming a recess in an external region around a transistor cell region where a JFET is formed, and then a P-RESURF layer or a P-guard ring layer is formed at a boundary of the recess. Although the P-RESURF layer or the P-guard ring layer is formed by selective ion implantation of P-type impurities after the recess is formed, the following problem occurs. This problem will be explained with reference to FIGS. 18A and 18B.FIGS. 18A and 18B are cross-sectional diagrams illustrating processing for forming a P-RESURF layer as an external breakdown resistant structure. As illustrated in the drawings, a JFET base structure is formed by forming an N -- drift layer J 2, a first P +- gate region J 3 and an N +- source region J 4 sequentially on an N +- SiC substrate J 1, forming a trench J 5 penetrating therethrough, and then forming an N -- channel layer J 6 and a second P +- gate region J 7 formed in the trench J 5. Then, a recess J8 is formed deeper than the N +- source region J3 by selective etching using a mask. Then, a recess J 9 is formed deeper than the first gate region J 3 by selective etching using another mask. Then, a P-RESURF layer J10 is formed by selectively ion-implanting P-type impurities.At the same time, it can be assumed that the P-RESURF layer J 10 can be formed by normal ion implantation in which ion implantation of P-type impurities is performed in a normal direction of the substrate surface as illustrated in FIG. 18A, or by inclined ion implantation in which ion implantation of P-type impurities is performed in a predetermined angle with respect to the normal direction of the substrate surface as illustrated in FIG. 18B.However, when ion implantation is performed in the normal direction of the substrate surface, the P-RESURF layer J 10 is not formed on a side surface of the recess J 9 and a corner portion defining a boundary between the side surface and a bottom surface of the recess J 9. Since the first gate region J 3 and the P-RESURF layer J 10 are spaced apart from each other on the side surface of the recess J 9, a drain breakdown voltage at the OFF time is greatly reduced to, for example, 400V or less. That is, since the P-RESURF layer J 10 does not exist at the corner portion of the recess J 9, electric field concentration occurs at this portion, so that the drain breakdown voltage can be reduced.On the other hand, when the tilted ion implantation is performed, the P-RESURF layer J 10 is formed on the side surface and the corner portion of the recess J 9. Thus, the drain breakdown voltage at the OFF time may be increased to, for example, 1300V. However, since the tilted ion implantation in four directions must be performed sequentially around the transistor cell region where the JFET is formed, ion implantation processing becomes complicated and consumes time. As a result, manufacturing cost of the device increases.In the above explanation, the P-RESURF layer J 10 is formed as an external breakdown resistant structure. However, this is not limited to the P-RESURF layer J 10, and the same applies when a P-type guard ring is formed.US 2010 / 0 025 693 A1 discloses a wide band gap semiconductor device and junction field effect transistor comprising a transistor cell region, a diode formation region, an electric field relaxation region located between the transistor cell region and the diode formation region, and an outer edge region surrounding the transistor cell region and the diode formation region. A junction field effect transistor is disposed in the transistor cell region. A diode is disposed in the diode formation region. In the region of the relaxation of the electric field, an insulating part is provided. The insulating part includes a trench separating the transistor cell region and the diode formation region, a first conductivity type layer disposed on an inner wall of the trench, and a second conductivity type layer disposed on a surface of the first conductivity type layer to fill the trench. The first conductivity type layer and the second conductivity type layer form a PN junction.Further, JP 2009-302 091 A discloses a silicon carbide semiconductor device including a semiconductor substrate including a first conductivity type substrate, a drift layer of a first conductivity type on the first conductivity type substrate, a layer of a second conductivity type on the drift layer, and a layer of a first conductivity type on the layer of a second conductivity type; a transistor formed in a transistor cell region of the semiconductor substrate; An outer breakdown resistant structure formed in an outer breakdown resistant structure region surrounding an outer periphery of the transistor cell region, wherein the outer breakdown resistant structure formed in an outer breakdown resistant structure region includes a first recess surrounding the outer periphery of the transistor cell region, a first trench located on a side surface of the first recess on an inner periphery of the first recess, and an electric field mitigation structure having a second conductivity type embedded layer, the first recess being deeper than the first conductivity type layer and the second conductivity type layer and reaching the drift layer, the first trench surrounding the outer periphery of the transistor cell region, and the second conductivity type embedded layer being embedded in the first trench. Further, JP 2009-302 091 A1 discloses a method for manufacturing the silicon carbide semiconductor device.In addition, JP 2003-273 127 A discloses a semiconductor device made of silicon carbide and a method for manufacturing the same. To provide a silicon carbide semiconductor device capable of improving withstand voltage at the periphery of a cell, an N -- drift layer 2, a first P-type gate layer 3 and an N +- source layer 4 are laminated sequentially on an N +- SiC substrate 1, and a trench 5 is formed by the source layer 4 and the first gate layer 3 to reach the drift layer 2, and an N-type channel layer 6 is formed on the inner wall of the trench 5, and a second P-type gate layer 7 made of SiC is formed within the layer 6. A guard ring structure having the same structures as the trench 5, the channel layer 6, and the second gate layer 7 is formed at the periphery of a cell in which the trench 5 is formed, and the elements 3 a, 3 b, 3 c, 32, and 42 in the structure corresponding to the first gate layer 3 and the second gate layer 7 are in an electrically floating state.In view of the above, an object of the present disclosure is to provide a SiC semiconductor having an external voltage breakdown resistant structure formed without tilted ion implantation and surrounding an outer periphery of a transistor cell region where a JFET or the like is formed to achieve a high drain breakdown voltage.The object is achieved by the features of claims 1, 7, 10 or 17.According to a first aspect of the present disclosure, an outer breakdown resistant structure formed in an outer breakdown resistant structure region includes a first recess, a first trench, and an electric field mitigation structure. The first recess surrounds an outer periphery of a transistor cell region and is deeper than a first conductivity type layer and a second conductivity type layer to reach the drift layer. The first trench is located on a side surface of the first recess on an inner periphery of the first recess and surrounds the outer periphery of the transistor cell region. The electric field mitigation structure has an embedded layer of a second conductivity type. The embedded layer of a second conductivity type is embedded in the first trench and provides the side surface of the first recess.Since the side surface of the first recess is provided by the embedded layer of a second conductivity type to provide the electric field mitigation structure, electric field concentration is mitigated at a corner defining a boundary between the side surface and a bottom surface. Accordingly, a breakdown position is shifted to the drift layer on the bottom surface of the first recess. Thus, an electric field is mitigated, so that a breakdown voltage can be improved. Since the structure is formed by embedding the embedded layer of a second conductivity type in the first trench, tilted ion implantation does not need to be performed. Thus, the external voltage breakdown resistant structure surrounding the outer periphery of the transistor cell region can be formed without the tilted ion implantation and can achieve a high drain breakdown voltage.According to the present aspect, a second recess is further included. The second recess is deeper than a thickness of the first conductivity type layer and surrounds the outer periphery of the transistor cell region. The first well is disposed farther away from the transistor cell region than the second well and deeper than the second well. The first trench is disposed at a boundary between the first recess and the second recess.As described above, when the second recess is formed, it is preferable that the first recess is farther away from the transistor cell region than the second recess.According to another or second aspect of the present disclosure, another second conductivity type layer is formed on a side of a bottom surface of the second recess near the first recess and on a side of the bottom surface of the first recess near the second recess. The further conductivity type layer is merged with the embedded second conductivity type layer to form a RESURF second conductivity type layer providing the electric field mitigation structure.Since the other second conductivity type layer on the side of the bottom surface of the second recess near the first recess and the other second conductivity type layer on the side of the bottom surface of the first recess near the second recess are continuously united to form the P-RESURF layer 20, an ideal drain breakdown voltage at the OFF time can be ensured.According to another or third aspect of the present disclosure, a plurality of first trenches are disposed outward from the boundary between the first trench and the second trench, and the embedded layer of a second conductivity type is formed in each of the first trenches to form a guard ring structure that provides the electric field mitigation structure.As described above, the guard ring structure is formed by the embedded layer of a second conductivity type embedded in each of the first trenches. Even when such a guard ring structure is formed, the second conductivity type embedded layer may be located on the side surface of the first recess by using the first trench and the second conductivity type embedded layer. Thus, the same advantages as the third aspect can be obtained.According to another or fourth aspect of the present disclosure, a plurality of first trenches are disposed inward from the boundary between the first trench and the second trench, and the embedded layer of a second conductivity type is formed in each of the first trenches to form a guard ring structure that provides the electric field mitigation structure.In this way, the guard ring structure can be formed within the boundary between the first recess and the second recess. In this case, when the embedded layer of a second conductivity type is formed on an embedded layer of a first conductivity type in the first trench, the guard ring structure formed in the second recess includes the first trench, the embedded layer of a first conductivity type, and the embedded layer of a second conductivity type. Thus, the second conductivity type layer is located between the first trenches. Not only the embedded layer of a second conductivity type but also the layer of a second conductivity type serves as the guard ring structure, and a distance therebetween becomes equal to only a thickness of the embedded layer of a second conductivity type. As a result, an electric field in the guard ring structure is reduced, so that a stable drain breakdown voltage can be easily secured.According to another or fifth aspect of the present disclosure, the first trenches are arranged in descending order of their width in an outward direction of the transistor cell region.As described above, the first trenches may be arranged in descending order of their width in the outward direction of the transistor cell region. In this case, when an embedded layer of a first or second conductivity type has an impurity concentration lower than that of the embedded layer of a first conductivity type or the embedded layer of a second conductivity type is formed before the embedded layer of a second conductivity type is formed in each of the first trenches, depths of the embedded layer of a second conductivity type may gradually decrease. In such a structure, the electric field at the OFF time is further mitigated. Thus, compared to when the embedded layers of a second conductivity type have the same depth, even if the size of the outer breakdown-resistant pattern region is small, the same or higher breakdown voltage can be ensured.According to another or sixth aspect of the present disclosure, a JFET is formed in the transistor cell region. The JFET includes a first gate region, a source region, a second trench, a channel layer of a first conductivity type, a second gate region of a second conductivity type, a source electrode, and a drain electrode. The first gate region is provided by the second conductivity type layer. The source region is provided by the first conductivity type layer. The second trench reaches the drift layer by penetrating the first conductivity type layer and the second conductivity type layer. The channel layer is formed on an inner wall of the second trench by epitaxial growth. The second gate region is formed on the channel layer. The source electrode is electrically connected to the first conductivity type layer. The drain electrode is electrically connected to the substrate of a first conductivity type. A source-drain current is controlled by controlling a potential of the first gate region and / or the second gate region.As described above, the present disclosure may be applied to a SiC semiconductor device including a JFET in the transistor cell region. In this case, the first trench and the second conductivity type embedded layer may be formed using processes in which the second trench, the channel layer, and the second gate region are formed. In this way, since a manufacturing method is widely used, the electric field mitigation structure can be formed without extending the manufacturing method.According to a seventh aspect of the present disclosure, a silicon carbide semiconductor device includes: a semiconductor substrate including a first conductivity type substrate, a first conductivity type drift layer on the first conductivity type substrate, a second conductivity type layer on the drift layer, and a first conductivity type layer on the second conductivity type layer; a MOSFET formed in a transistor cell region of the semiconductor substrate and including a base region, a source region, a gate insulating layer, a gate electrode, a source electrode, a drain electrode, a second trench, and a second conductivity type deep layer, the base region being provided by the second conductivity type layer, the source region being provided by the first conductivity type layer, the gate insulating layer is formed on a surface of the base region between the source region and the drift layer, the gate electrode is formed on a surface of the gate insulating layer, the source electrode is electrically connected to the first conductivity type layer, the drain electrode is electrically connected to the first conductivity type substrate, the second trench reaches the drift layer by penetrating the first conductivity type layer and the second conductivity type layer, the deep second conductivity type layer is embedded in the second trench, and a source-drain current is controlled by controlling a potential of the gate electrode; and an external voltage breakdown resistant structure formed in an external voltage breakdown resistant structure region surrounding an outer periphery of the transistor cell region, wherein the external voltage breakdown resistant structure, which is formed in the outer breakdown resistant structure region, includes a first recess surrounding the outer periphery of the transistor cell region, a first trench located on a side surface of the first recess on an inner periphery of the first recess, and an electric field mitigation structure having an embedded second conductivity type layer, the first recess being deeper than the first conductivity type layer and the second conductivity type layer and reaching the drift layer, the first trench surrounding the outer periphery of the transistor cell region, the embedded second conductivity type layer being embedded in the first trench and providing the side surface of the first recess, wherein the silicon carbide semiconductor device further includes a second recess deeper than a thickness of the first conductivity type layer and surrounding the outer periphery of the transistor cell region, wherein the first recess is disposed farther away from the transistor cell region than the second recess and deeper than the second recess, and the first trench is disposed at a boundary between the first recess and the second recess.As described above, the present disclosure can be applied to a SiC semiconductor device having a MOSFET in the transistor cell region. In this case, the first trench and the embedded layer of a second conductivity type may be formed using processes in which the second trench and the deep layer are formed. In this way, since a manufacturing method is generally used, the electric field mitigation structure can be formed without extending the manufacturing processing. According to another or eighth aspect of the present disclosure, the first trench and the second trench have the same depth.According to another or ninth aspect of the present disclosure, another trench is formed in the transistor cell region and reaches the drift layer by penetrating the first conductivity type layer and the second conductivity type layer. The gate insulating film and the gate electrode are formed in the other trench, so that the MOSFET has a trench gate structure. The other trench of the trench gate structure is deeper than the second trench.As described above, the MOSFET formed in the transistor cell region may have a trench gate structure. In this case, the second trench in which the deep layer is embedded is deeper than the other trench of the trench gate structure. Thus, the electric field applied to the gate insulating film is reduced at the OFF time, so that breakdown of the gate insulating film can be prevented.In the first aspect to the ninth aspect explained above, the present disclosure is defined as an apparatus. Alternatively, the present disclosure may be defined as a manufacturing method. Tenth to nineteenth aspects correspond to methods of manufacturing the SiC semiconductor devices of the first to ninth aspects.According to another or tenth aspect of the present disclosure, a manufacturing method includes a step of providing the semiconductor substrate, a step of forming a first trench in the outer breakdown resistant structure region such that the first trench surrounds the outer periphery of the transistor cell region, a step of forming an embedded layer of a second conductivity type in the first trench, and a step of forming a first recess deeper than the layer of a first conductivity type and the layer of a second conductivity type and reaching the drift layer such that the first recess surrounds the outer periphery of the transistor cell region. In the first recess forming step, the first trench is located on a side surface of the first recess on an inner periphery of the first recess, so that the side surface of the first recess is provided by the embedded layer of a second conductivity type to form an electric field mitigation structure including the embedded layer of a second conductivity type. By this method, the SiC semiconductor device of the first aspect can be manufactured.According to the present tenth aspect, the manufacturing method further includes a step of forming a second recess deeper than a thickness of the first conductivity type layer such that the second recess surrounds the outer periphery of the transistor cell region. In the first recess forming step, the first trench is disposed at a boundary between the first recess and the second recess so that the side surface of the first recess is provided at the boundary between the first recess and the second recess by the second conductivity type embedded layer to form the electric field mitigation structure including the second conductivity type embedded layer. By this method, the SiC semiconductor device of the second aspect can be manufactured.According to another or eleventh aspect of the present disclosure, the manufacturing method further includes a step of forming a second conductivity type layer on a side of a bottom surface of the second recess near the first recess and on a side of a bottom surface of the first recess near the second recess such that the second conductivity type layer is united with the embedded second conductivity type layer to form a RESURF second conductivity type layer providing the electric field mitigation structure. The second conductivity type layer forming step follows the first recess forming step and the second recess forming step, and includes a step of forming a mask on a surface of the substrate and a step of performing ion implantation of second conductivity type impurities in a normal direction of the substrate using the mask.As described above, the second conductivity type layer is formed by performing ion implantation of second conductivity type impurities in a normal direction of the substrate. By this method, the SiC semiconductor device of the third aspect can be manufactured.According to another or twelfth aspect of the present disclosure, in the first trench forming step, a plurality of first trenches are formed such that the plurality of first trenches are disposed outward from the boundary between the first recess and the second recess, and in the second conductivity type embedded layer forming step, the second conductivity type embedded layer is formed in each of the plurality of first trenches to form a guard ring structure providing the electric field mitigation structure. By this method, the SiC semiconductor device of the fourth aspect can be manufactured.According to another or thirteenth aspect of the present disclosure, in the first trench forming step, a plurality of the first trenches are formed such that the plurality of first trenches are disposed inward from the boundary between the first recess and the second recess, and in the second conductivity type embedded layer forming step, the second conductivity type embedded layer is formed in each of the plurality of first trenches to form a guard ring structure providing the electric field mitigation structure. By this method, the SiC semiconductor device of the fifth aspect can be manufactured.According to another or fourteenth aspect of the present disclosure, in the first trench forming step, the first trenches are formed such that the first trenches are arranged in descending order of their width in an outward direction of the transistor cell region. By this method, the SiC semiconductor device of the sixth aspect can be manufactured.According to another or fifteenth aspect of the present disclosure, the manufacturing method further includes a step of forming a JFET in the transistor cell region. The JFET has a first gate region provided by the second conductivity type layer and a source region provided by the first conductivity type layer. The step of forming the JFET includes a step of forming a second trench that reaches the drift layer by penetrating the first conductivity type layer and the second conductivity type layer, a step of forming a channel layer of a first conductivity type by epitaxial growth on an inner wall of the second trench, a step of forming a second gate region of a second conductivity type on the channel layer, a step of forming a source electrode electrically connected to the first conductivity type layer, and a step of forming a drain electrode electrically connected to the first conductivity type substrate. A source-drain current is controlled by controlling a potential of the first gate region and / or the second gate region. By this method, the SiC semiconductor device of the seventh aspect can be manufactured.According to another or sixteenth aspect of the present disclosure, when the JFET is formed in the transistor cell region, the manufacturing method further includes a step of forming an embedded layer of a first conductivity type in the first trench. The second conductivity type embedded layer forming step is performed after the first conductivity type embedded layer forming step. The first trench forming step and the second trench forming step are performed simultaneously. The first conductivity type embedded layer forming step and the channel layer forming step are performed simultaneously. The second conductivity type embedded layer forming step and the second gate region forming step are simultaneously performed. With such an approach, since a manufacturing method is generally used, the electric field mitigation structure can be formed without extending the manufacturing processing.Another or seventeenth aspect of the present disclosure relates to a method of manufacturing a silicon carbide semiconductor device, the silicon carbide semiconductor device including: a semiconductor substrate including a first conductivity type substrate, a first conductivity type drift layer on the first conductivity type substrate, a second conductivity type layer on the drift layer, and a first conductivity type layer on the second conductivity type layer; a transistor formed in a transistor cell region of the semiconductor substrate; and an external voltage breakdown resistant structure formed in an external voltage breakdown resistant structure region surrounding an outer periphery of the transistor cell region, the method including: a step of providing the semiconductor substrate; a step of forming a first trench in the external breakdown resistant structure region such that the first trench surrounds the outer periphery of the transistor cell region; a step of forming an embedded layer of a second conductivity type in the first trench, and a step of forming a first recess deeper than the layer of a first conductivity type and the layer of a second conductivity type and reaching the drift layer such that the first recess surrounds the outer periphery of the transistor cell region, wherein in the step of forming the first recess, the first trench is located on a side surface of the first recess on an inner periphery of the first recess such that the side surface of the first recess is provided by the embedded layer of a second conductivity type to form an electric field mitigation structure, the embedded layer of a second conductivity type, and the method further includes: a step of forming a second recess deeper than a thickness of the layer of a first conductivity type such that the second recess surrounds the outer periphery of the transistor cell region, wherein in the step of forming the first recess, the first trench is disposed at a boundary between the first recess and the second recess such that the side surface of the first recess at the boundary between the first recess and the second recess is provided by the embedded layer of a second conductivity type to form the electric field mitigation structure including the embedded layer of a second conductivity type, and a step of forming a MOSFET in the transistor cell region, the MOSFET including a base region provided by the layer of a second conductivity type, and a source region provided by the second conductivity type layer, wherein the step of forming the MOSFET includes a step of forming a second trench that reaches the drift layer by penetrating the first conductivity type layer and the second conductivity type layer, a step of forming a deep second conductivity type layer in the second trench, a step of forming a gate insulating layer on a surface of the base region between the source region and the drift layer, a step of forming a gate electrode on a surface of the gate insulating layer, forming a source electrode electrically connected to the first conductivity type layer, and a step of forming a drain electrode electrically connected to the first conductivity type substrate, and a source-drain current is controlled by controlling a potential of the gate electrode.According to another or eighteenth aspect of the present disclosure, when the MOSFET is formed in the transistor cell region, the first trench forming step and the second trench forming step are simultaneously performed, and the second conductivity type embedded layer forming step and the deep layer forming step are simultaneously performed. With such an approach, since manufacturing processing is generally used, the electric field mitigation structure can be formed without extending the manufacturing processing.According to another or nineteenth aspect of the present disclosure, when the MOSFET is formed in the transistor cell region, the manufacturing method further includes a step of forming another trench in the transistor cell region such that the other trench is deeper than the second trench and reaches the drift layer by penetrating the first conductivity type layer and the second conductivity type layer. The gate insulating film and the gate electrode are formed in the other trench, so that the MOSFET has a trench gate structure. By this method, the SiC semiconductor device of the eleventh aspect can be manufactured.The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the drawings.The following are shown: FIG. 1A is a top layout view of a SiC semiconductor device including a JFET according to a first embodiment of the present disclosure, and FIG. 1B is a diagram illustrating a cross-sectional view taken along line IB-IB of FIG. 1A ; FIG. 2 is a graph showing a result of measurement of a relationship between an impurity concentration of a P +- layer 15 and a breakdown voltage; FIGS. 3A, 3B, and 3C are cross-sectional views illustrating processes for manufacturing the SiC semiconductor device illustrated in FIGS. 1A and 1B ; FIGS. 4A, 4B, and 4C are cross-sectional views illustrating processes for manufacturing an SiC semiconductor device subsequent to FIGS. 3A, 3B, and 3C ; FIG. 5 is a cross-sectional view of a SiC semiconductor device including a JFET according to a second embodiment of the present disclosure; FIG. 6 is a cross-sectional view illustrating processing for manufacturing the SiC semiconductor device illustrated in FIG. 5 ; FIG. 7 is a cross-sectional view of a SiC semiconductor device including a JFET according to a third embodiment of the present disclosure; FIG. 8 is a cross-sectional view illustrating processing for manufacturing a SiC semiconductor device illustrated in FIG. 7 ; FIG. 9 is a cross-sectional view of a SiC semiconductor device including a JFET according to a fourth embodiment of the present disclosure; FIG. 10 is a cross-sectional view of a SiC semiconductor device including a MOSFET according to a fifth embodiment of the present disclosure; FIGS. 11A, 11B, and 11C are cross-sectional views illustrating processes for manufacturing the SiC semiconductor device illustrated in FIG. 10 ; FIGS. 12A, 12B, and 12C are cross-sectional views illustrating processes for manufacturing the SiC semiconductor device subsequent to FIGS. 11A, 11B, and 11C ; FIG. 13 is a cross-sectional view of a SiC semiconductor device including a MOSFET according to a sixth embodiment of the present disclosure; FIG. 14 is a cross-sectional view showing processing for manufacturing the SiC semiconductor device shown in FIG. 13; FIG. 15 is a cross-sectional view of a SiC semiconductor device including a MOSFET according to a seventh embodiment of the present disclosure; FIG. 16 is a cross-sectional view illustrating processing for manufacturing the SiC semiconductor device illustrated in FIG. 15 ; FIG. 17 is a cross-sectional view of a SiC semiconductor device including a MOSFET according to an eighth embodiment of the present disclosure; and FIGS. 18A and 18B are cross-sectional views illustrating processes for forming a P-RESURF layer as an external breakdown resistant structure.Embodiments of the present invention will be explained with reference to the drawings, in which like reference numerals indicate the same or equivalent parts.(First Embodiment)A SiC semiconductor device including a JFET will be explained as an example of a SiC semiconductor device according to a first embodiment of the present disclosure. FIGS. 1A and 1B are diagrams illustrating a SiC semiconductor device including a JFET according to the present embodiment. FIG. 1A illustrates an upper side layout view and FIG. 1B illustrates a cross-sectional view taken along line IB-IB in FIG. 1A. A structure of the SiC semiconductor device including the JFET according to the present embodiment will be explained below with reference to these diagrams.As illustrated in FIG. 1A and FIG. 1B, the structure includes a transistor cell region (JFET formation region) R 1 where JFET cells are formed, and an outer breakdown resistant structure region R 2 located around an outer periphery of the transistor cell region R 1. In the transistor cell region R 1, embedded epitaxial regions R 3, which are gate structures formed by filling trenches with epitaxial layers, are arranged in a stripe pattern. The outer breakdown-resistant structure region R 2 surrounds the transistor cell region R 1.The SiC semiconductor device is formed by using a semiconductor substrate 5 having a multilayer structure including an N +- substrate (a first conductivity type substrate) 1, an N -- drift layer 2, a P +- layer 3 (second conductivity type layer), and an N +- layer 4 (first conductivity type layer). For example, the N +- substrate 1 has an N-type impurity concentration of 1×10 19 cm -3 or more. For example, an N-type impurity concentration of the N +- drift layer 2 is smaller than that of the N +- substrate 1 and ranges from 1×10 15 to 1×10 18 cm 3. For example, the P +- layer 3 has a P-type impurity concentration between 1×10 18 to 5×10 19 cm -3. For example, an N-type impurity concentration of the N +- layer 4 is higher than that of the N -- layer 2, and ranges from 1×10 18 to 5×10 20 cm -3. For example, the P +- layer 3 has a P-type impurity concentration between 1×10 18 to 5×10 19 cm -3. For example, an N-type impurity concentration of the N +- layer 4 is higher than that of the N - drift layer 2, and ranges between 1×10 18 to 5×10 20 cm -3.In the SiC semiconductor device, the transistor cell region R 1 in which many JFET cells are formed is located on the center side of the semiconductor substrate 5, and the external breakdown resistant structure region R 2 is disposed to surround the transistor cell region R 1.A trench 6 is formed on a main surface side of the semiconductor substrate 5 and the transistor cell region R 1. The trench 6 reaches the N +- drift layer 2 by penetrating the N +- layer 4 and the P +- layer 3. An N -- channel layer (a fourth semiconductor layer) is formed by epitaxial growth on an inner surface of each trench 6, and a P +- layer 8 (a fifth semiconductor layer) is formed by epitaxial growth on the N -- channel layer 7. For example, the N -- channel layer 7 has a thickness of 1 μm or less and an N-type impurity concentration between 5×10 15 and 1 10 17 cm -3. For example, the P +- layer 8 has a P-type impurity concentration between 1×10 18 to 5×10 20 cm -3. The trench 6 is filled with the N -- channel layer 7 and the P +- layer 8, so that the embedded epitaxial regions R 3 can be formed.In the transistor cell region R 1 in which the JFET cells are formed, a first gate region is provided by the P +- layer 3, a second gate region is provided by the P +- layer 8, and an N +- source region is provided by the N +- layer 4.Although not illustrated in the drawings, the P +- layer 3 providing the first gate region is electrically connected to a first gate electrode, and a gate voltage of the first gate region is controlled by the first gate electrode. Further, the P +- type layer 8 providing the second gate region is electrically connected to a second gate electrode 9, and a gate voltage of the second gate region is controlled by the second gate electrode 9.For example, the first gate electrode is formed on a surface of the P +- layer 3 providing the first gate region such that it appears different in cross section from that shown in FIG. 1. The first gate electrode is formed through a contact hole in contact with the P +- layer 3. The second gate electrode 9 is formed on a surface of the P +- layer 8 providing the second gate electrode. For example, each of the first gate electrode and the second gate electrode 9 is formed by forming an alloy layer of Ti and Al on Ni, which is a material capable of forming ohmic contact with a P +- type semiconductor.Further, a source electrode 10 made of Ni or the like is formed on a surface of the N +- layer 4 providing the N +- source region. The source electrode 10 is electrically insulated from the first gate electrode and the second gate electrode 9 by an interlayer dielectric 11.A drain electrode 12 is formed on a back surface side of the semiconductor substrate 5 and electrically connected to the N +- substrate. In this manner, the JFET cells are formed in the transistor cell region R 1.A trench (first trench) 13 is formed on the main surface side of the semiconductor substrate 5 in the external breakdown resistant structure region R 2. The trench 13 reaches the N -- drift layer 2 by penetrating the N +- layer and the P +- layer 3. An N -- layer (a first conductivity type embedded layer) 14 formed simultaneously with the N -- channel layer and a P +- layer 15 (a second conductivity type embedded layer) formed simultaneously with the P +- layer 8 are provided in the trench 13. Further, a recess 16 and a recess 17 are formed on the main surface side of the semiconductor substrate 5. The recess 16 is deeper than the thickness of the N +- layer 4. the recess 17 is located outside the recess 16 and reaches the N -- drift layer 2 by penetrating the N +- layer and the P +- layer 3. the recess 16 corresponds to a second recess and the recess 17 corresponds to a first recess. In this way, the mesa structure is formed. That is, in the mesa, the recess 17 surrounds the transistor cell region R 1, and the recess 16 is located inside the recess 17 and surrounds the transistor cell region R 1.A P region 18 is formed on an outer edge of a bottom surface of the recess 16, that is, on the near side of the bottom surface of the recess 16 to the recess 17 to surround the transistor cell region R1. For example, the P region 18 has a P-type impurity concentration between 1×10 18 to 5×10 20 cm -3( for example, 5×10 18 cm -3). A P region 19 is formed on the near side of a bottom surface of the recess 17 to a boundary between the bottom surface and a side surface of the recess 17, that is, on the near side of the bottom surface of the recess 17 to the recess 16 to surround the boundary to the cell region R 1. For example, the P region 19 has a P-type impurity concentration between 1×10 18 to 5×10 20 cm -3( for example, 5×10 18 cm -3). The trench 13 is located at the boundary (at a steep height portion) between the bottom surface and the side surface of the recess 17, and the side surface of the recess 17 is provided by the P +- layer 15 in the trench 13. Thus, the P region on the bottom surface of the recess 16, the P +- layer 15 in the trench 13, and the P region 19 on the bottom surface of the recess 17 are united to form a P-RESURF layer 20. This P-RESURF layer 20 provides an electric field mitigation structure.Further, in the external breakdown resistant structure R 2, an N +- layer 21 is formed in a surface portion of the N -- drift layer 2 on the bottom surface of the recess 17. The N +- layer 21 is located outside the P-RESURF layer 20 and is connected to an electrode 22. The N +- layer 21 and the electrode 22 provide a channel stopper (EQR) for separating an electric field.The SiC semiconductor including the JFET according to the present embodiment has a structure described above.In the SiC semiconductor device having the above structure, the JFET formed in the transistor is normally off. An operation of the JFET is controlled by voltages applied to the first gate electrode and the second gate electrode 9 in the following manner.When the first gate electrode and the second gate electrode are electrically connected to each other so that potentials of these electrodes can be controlled to be equal, or when the first gate electrode and the second gate electrode are electrically disconnected from each other so that potentials of these electrodes can be controlled separately, dual gate driving is performed. That is, the amount of extension of a depletion layer extending from the P +- layers 3, 8 providing the first and second gate regions toward the N -- channel layer 7 is controlled based on the potentials of the first gate electrode and the second gate electrode 9. For example, when no voltage is applied to the first gate electrode and the second gate electrode 9, the N -- channel layer 7 is clamped by the depletion layer extending from the P +- layers 3, 8. As a result, a source-drain current is turned off. Then, when a forward bias voltage is applied between the P +- layers 3, 8 and the N -- channel layer 7, the amount of extension of the depletion layer extending to the N -- channel layer is reduced. As a result, a channel region is formed so that a source-drain current can flow.Further, in the SiC semiconductor having the above structure, the P region 18 on the bottom surface of the recess 16, the P +- layer 15 in the trench 13, and the P region 19 on the recess 17 form the P-RESURF layer 20 in the external breakdown-resistant structure region R 2. Since the P-RESURF layer 20 surrounds the periphery of the transistor cell region R 1, electric field concentration at a corner defining the boundary between the side surface and the bottom surface is mitigated. Accordingly, a breakdown position is shifted to the N -- drift layer 2 on the bottom surface of the recess 17. Thus, an electric field is mitigated, so that a drain breakdown voltage can be improved.FIG. 2 is a graph illustrating a result of measurement of a relationship between the impurity concentration of the P +- layer 15 and the drain breakdown voltage when the P +- layer is located at the boundary (the step height portion) between the bottom surface and the side surface of the recess 17. A drain breakdown voltage observed when the P +- layer 15 is not located at a boundary between the bottom surface and the side surface of the recess 17 is also shown in FIG. 2 as a reference.As shown in FIG. 2, when the P +- layer 15 is located at the boundary between the bottom surface and the side surface of the recess 17, the drain breakdown voltage is greatly improved compared to when the P +- layer 15 is not disposed. In particular, when the P impurity (or P-type impurities) is greater than 3×10 17 cm -3 or more, the drain breakdown voltage may be higher than 1100V. Thus, the P impurity of the P +- layer 15 is set to be larger than 3×10 17 cm -3 or more, so that the drain breakdown voltage may be higher than 1100V. Accordingly, in the present embodiment, the P +- layer 15 has the P impurity of 1×10 18 to 5×10 20 cm -3( for example, 5×10 18 cm -3), to ensure a high drain breakdown voltage.Next, a method of manufacturing the SiC semiconductor device illustrated in FIGS. 1A and 1B will be explained with reference to FIGS. 3A, 3B, and 3C, and FIGS. 4A, 4B, and 4C. In FIGS. 3A, 3B, and 3C, and FIGS. 4A, 4B, and 4C, a portion outside the P-RESURF layer 20 illustrated in FIG. 1B is omitted.(Processing shown in FIG. 3A )First, the N +- substrate 1 having the above-mentioned impurity concentration is provided. Then, the N -- drift layer, the P +- layer 3 and the N +- layer 4 are sequentially formed on the surface of the N +- substrate 1 by epitaxial growth. Consequently, the semiconductor substrate 5 is manufactured.(Processing Illustrated in FIG. 3B )By photolithography, the trench 6 reaching the N -- drift layer 2 by penetrating the N +- layer and the P +- layer 3 is formed in the transistor cell region R 1 at the same time as the trench 13 reaching the N -- drift layer 2 by penetrating the N +- layer 4 and the P +- layer 3 is formed in the external breakdown-resistant structure region R 2. According to the present embodiment, each of the trenches 6 and 13 has the same width and the same depth.(Processing Illustrated in FIG. 3C )By epitaxial growth, N -- SiC, and P +- SiC are epitaxially grown on the entire surface of the semiconductor substrate 5 to form the N -- layer 30 and the P +- layer 31, so that the trenches 6 and 7 can be filled with the N -- layer 30 and the P +- layer 31.(Processing shown in FIG. 4A )The surface of the semiconductor substrate 5 is planarized by etch back or chemical mechanical polishing (CMP) so that the N -- layer 30 and the P +- layer 31 can be left only in the trenches 6 and 13. Thus, the N -- channel layer 7 and the P +- layer 8 are formed in the trench 6, and the N -- layer 14 and the P +- layer 15 are formed in the trench 13.(Processing Illustrated in FIG. 4B )By anisotropic etching such as RIE (Reactive Ion Etching), an outer edge of the transistor cell region R 1 is etched to a depth deeper than the N +- layer 4, so that the recess 16 is formed.Specifically, the recess 16 is formed by performing anisotropic etching after a mask having an opening corresponding to a formation region of the recess 16 (the external breakdown voltage resistant pattern region R 2) where the recess 16 is to be formed is placed. Then, by anisotropic etching such as RIE using another mask, the outer edge of the bottom surface of the recess 16 is selectively etched to a depth deeper than the P +- layer 3, so that the recess 17 is formed. Specifically, the recess 17 is formed by performing anisotropic etching after the other mask including an opening corresponding to a formation region of the recess 17 (a region from a first position at which the P-RESURF layer 15 is to be formed to a second position outside the first position) at which the recess 17 is to be formed is placed. In this way, the mesa structure is formed. At this time, the side surface of the recess 17 is provided by the P +- layer 15.(Processing Illustrated in FIG. 4C )After a mask 32 for ion implantation is placed, openings corresponding to formation regions of P regions 18 and 19 are formed. Then, the P regions 18 and 19 are formed by performing ion implantation of P-type impurities in the normal direction of the substrate surface. At this time, since the side surface of the recess 17 is provided by the P +- layer 15 in the processing illustrated in FIG. 4B, the P region 18 on the bottom surface of the recess 16, the P +- layer 15 in the trench 13, and the P region 19 on the bottom surface of the recess 17 are united with each other to form the P-RESURF layer 20.When the openings are formed in the mask 32, some remainder of the mask 32 may be left on the side surface of the recess 17. The rest may block the ion implantation, so that an end of the P region 19 may be slightly separated from the corner of the recess 17. However, since the P +- layer 15 in the trench is also located on the bottom surface of the recess 17, the P +- layer 15 and the P region 19 are continuously united with each other.Although subsequent processings are not illustrated in the drawings, after the mask 32 is removed, ion implantation of N-type impurities is performed using a metal mask or the like. Then, the implanted ions are activated, so that the N +- layer 21 is formed. Then, after the interlayer dielectric 11 is formed on the entire surface of the semiconductor substrate 5, contact holes are formed in predetermined regions of the interlayer dielectric 11 and the N +- layer 4. Then, a wiring layer is formed on the interlayer dielectric 11, and the first gate electrode, the second gate electrode 9, the source electrode 10, and the electrode 22 are formed by patterning the wiring layer. Then, the drain electrode 12 is formed on the back surface side of the semiconductor substrate 5. In this way, the semiconductor device illustrated in FIGS. 1A and 1B is manufactured.As described above, in the SiC semiconductor device according to the present embodiment, the P region 18 on the bottom surface of the recess 16, the P +- layer 15 in the trench 13, and the P region 19 on the bottom surface of the recess 17 form the P-RESURF layer 20 to provide the electric field mitigation structure. Since the P-RESURF layer 20 surrounds the periphery of the transistor cell region R 1, the concentration of an electric field at the corner defining the boundary between the side surface and the bottom surface is alleviated. Accordingly, the breakdown position is shifted to the N -- drift layer 2 on the bottom surface of the recess 17. Thus, the electric field is mitigated, so that the drain breakdown voltage can be improved. Specifically, according to the present embodiment, the P region 18, the P +- layer 15, and the P region 19 are continuously united with each other to form the P-RESURF layer 20. Thus, an ideal drain breakdown voltage at the OFF time can be ensured.The P-RESURF layer 20 can be formed without implanting ions into the side surface of the recess 17 during ion implantation, as long as the P regions 18 and 19 are formed on the bottom surfaces of the recess 16 and the recess 17. Thus, the P-RESURF layer 20 can be formed without performing the tilted ion implantation. Thus, the external voltage breakdown resistant structure surrounding the periphery of the transistor cell region R 1 where the JFET is formed is formed without performing the tilted ion implantation, so that the SiC semiconductor device has a structure for obtaining a high drain breakdown voltage. The trench 13, the N -- layer 14 and the P +- layer 15 for providing the structure are formed simultaneously as the trench 6, the N -- layer 7 and the P +- layer 8 for providing the JFET. Since the manufacturing processing is generally used, the structure can be formed without extending the manufacturing processing.(Second Embodiment)A second embodiment of the present disclosure will be explained. Since the present embodiment is the same as the first embodiment except for a structure of the outer breakdown-resistant structure region R 2, only the difference will be explained.FIG. 5 is a diagram illustrating a cross-sectional view of a SiC semiconductor device including a JFET according to the present embodiment. As illustrated in FIG. 5, a plurality of trenches 13 are formed, and each trench 13 is filled with the N -- layer 14 and the P +- layer 15. The innermost trench 13 closest to the transistor cell region R 1 is located at the boundary (at a step height portion) between the bottom surface and the side surface of the recess 17, and the side surface of the recess 17 is provided by the P +- layer 15 in the innermost trench 13. Although upper portions of the P +- layers 15 in the other trenches 13 located outside the innermost trench 13 are removed by the recess 17, the remaining portions of the P +- layers 15 are arranged at regular intervals to provide a guard ring structure.As described above, according to the present embodiment, the guard ring structure is formed in the external breakdown resistant structure region R 2 instead of the P-RESURF layer of the first embodiment. Even when the guard ring structure is formed, the P +- layer 15 may be located on the side surface of the recess 17 by using the trench 13, the N -- layer 14, and the P +- layer 15. Thus, the same advantages as in the first embodiment can be obtained.A method of manufacturing the SiC semiconductor device according to the present embodiment is almost the same as that described in the first embodiment. As illustrated in FIG. 6, there is a difference in that a plurality of trenches 13 are formed at regular intervals in the processing explained in the first embodiment with reference to FIG. 3. When a plurality of trenches 13 are formed at regular intervals in advance, each trench 13 is filled with the N -- layer and the P +- layer 15. Then, the recess 16 and the recess 17 are formed by performing selective etching so that the innermost trench 13 closest to the transistor cell region R 1 may be located at the boundary between the bottom surface and the side surface of the recess 17. Thus, the SiC semiconductor device according to the present embodiment is manufactured. As explained above, the SiC semiconductor device has the guard ring structure in the external breakdown resistant structure region R 2 instead of the P-RESURF layer 20, and the guard ring structure can be formed without ion implantation processing.(Third Embodiment)A third embodiment of the present disclosure will be explained. Since the present embodiment is the same as the second embodiment except for a shape of the guard ring structure, only the difference will be explained.FIG. 7 is a diagram illustrating a cross-sectional view of the SiC semiconductor device including a JFET according to the present embodiment. As illustrated in FIG. 7, according to the present embodiment, although the guard ring structure is formed using the trench 13, the N -- layer 14, and the P +- layer 15, the trenches are arranged in descending order of their width in an outward direction. Further, since the trench 13 is narrower, the N -- layer 14 is thicker, so that the P +- layer 15 on the N -- layer may be thinner.Further, since depths of the P +- layers 15 continuously decrease, the electric field is mitigated at the OFF time. Thus, even if the size of the outer breakdown resistant structure region R 2 is smaller than that of the second embodiment in which the P +- layers 15 have the same depth, the same or higher drain breakdown voltage can be ensured.A method of manufacturing the SiC semiconductor device according to the present embodiment is almost the same as that described in the second embodiment. As illustrated in FIG. 8, a difference is that in the processing, the trenches 13 are arranged in descending order of their width in the outward direction explained in the first embodiment with reference to FIG. 3B. When the trenches 13 are arranged in descending order of their width in the outward direction in advance, the thickness of the N -- layer 14 formed on the bottom of the trench 13 changes according to the width of the trench 13. In this way, the SiC semiconductor device according to the present embodiment is manufactured.(Fourth Embodiment)A fourth embodiment of the present disclosure will be explained. Since the present embodiment is the same as the second and third embodiments except for a shape of the guard ring structure, only the difference will be explained.FIG. 9 is a diagram illustrating a cross-sectional view of a SiC semiconductor device including a JFET according to the present embodiment. In the second and third embodiments, the innermost trench 13 of a plurality of trenches 13 formed in the outer breakdown-resistant structure region R 2 is located at the boundary (at a step height portion) between the bottom surface and the side surface of the recess 17. For example, as illustrated in FIG. 9, the Nth trench 13 from the innermost trench 13, where N is a positive integer, may be located at the boundary (at a steep height portion) between the bottom surface and the side surface of the recess 17. In other words, at least one trench 13 may be located within the trench 13 located at the boundary between the bottom surface and the side surface of the recess 17.In the guard ring structure, the N -- layer 14 and the N -- drift layer 2 located between P regions with one within the other (the P +- layers 15 in the trenches 13 according to the second and third embodiments of the present embodiments) serve as the electric field mitigation structure. When the innermost trench 13 of a plurality of trenches 13 formed in the outer breakdown-resistant structure region R 2 is located at the boundary (at a step height portion) between the bottom surface and the side surface of the recess 17 as in the second and third embodiments, only the P +- layers 15 in the recess 17 provide the guard ring structure. Thus, a distance between adjacent guard ring structures is equal to the sum of the thicknesses of the N -- layers 14 in adjacent trenches 13 and the width of the N -- drift layer 2 between adjacent trenches 13.In contrast, according to the present embodiment, the guard ring structure formed by the trench 13, the N -- layer 14, and the P +- layer 15 is provided in the recess 16 such that the P +- layer 3 may be located between the trenches 13. Thus, not only the P +- layers 15 but also the P +- layer 3 serve as the guard ring structure, and a distance between adjacent guard ring structures is equal to only the thickness of the N -- layers 14.In Fig. 9, each trench 13 has the same width as in the second embodiment. The same applies when the trenches 13 are arranged in descending order of their width in the outward direction as in the third embodiment.(Fifth Embodiment)A fifth embodiment of the present disclosure will be explained. Since the present embodiment is the same as the first embodiment except for a transistor formed in the transistor cell region R 1, only the difference will be explained.FIG. 10 is a diagram illustrating a cross-sectional view of a SiC semiconductor device in the present embodiment. As illustrated in FIG. 10 according to the present embodiment, the SiC semiconductor device has a MOSFET having a trench gate structure. Specifically, according to the present embodiment, the SiC semiconductor device is formed using a semiconductor substrate 5 having a multilayer structure including an N +- substrate (a first conductivity type substrate), an N -- drift layer 2 (a first conductivity type layer), a P +- layer (a second conductivity type layer), and an N +- layer. The P +- layer 3 serves as a P base region for forming a channel region. A gate insulating film and a gate electrode 41 on a surface of the gate insulating film 40 are formed in the trench 6 in place of the N -- channel layer 7 and the P +- layer 8. The trench 6 is filled with the gate insulating film 40 and the gate electrode 41.Further, a trench (a second trench) 42 reaching the N -- drift layer 2 by penetrating the N +- layer 4 and the P +- layer 3 is formed in the transistor cell region R 1. The trench 42 is deeper than the trench 6 and separated from a side surface of the trench 6 by a predetermined distance. The trench 42 is filled with a deep P +- layer 43. Since the trench 42 is deeper than the trench 6, an electric field applied to the gate insulating film 40 at the OFF time is reduced, so that breakdown of the gate insulating film 40 can be prevented. A P -- or N -- low concentration layer is formed on a bottom of the trench 42 so that a corner of a bottom of the deep P +- layer 43 may be rounded to reduce electric field concentration. Alternatively, it is possible to fill the trench 42 only with the deep P +- layer.The interlayer dielectric 11 covers the gate electrode 41. The source electrode 10 is formed on the interlayer dielectric. The source electrode 10 is electrically connected to the N +- layer 4 providing a source region through the contact hole of the interlayer dielectric 11. The source electrode 10 is also electrically connected to the P +- layer 3 providing the P base region through the contact hole of the interlayer dielectric 11 and the deep P +- layer 43. In this way, the MOSFET having the trench gate structure is formed.A trench (first trench) 45 is formed on the main surface side of the semiconductor substrate 5 in the external breakdown resistant structure region R 2. The trench 45 reaches the N -- drift layer 2 by penetrating the N +- layer 4 and the P +- layer 3. A P +- layer (a second conductivity type embedded layer) 46 formed at the same time as the P +- deep layer 43 and a low concentration layer (a second conductivity type or first conductivity type embedded layer) 47 formed at the same time as the low concentration layer 44 are provided in the trench 45.The trench 45 is located at the boundary (at a step height portion) between the bottom surface and the side surface of the recess 17, and the side surface of the recess 17 is provided by the P +- layer 46 in the trench 45. Thus, the P region 18 on the bottom surface of the recess 16, the P +- layer 46 in the trench 45, and the P region 19 on the bottom surface of the recess 17 are united to form the P-RESURF layer 20.As described above, even when the SiC semiconductor device includes the MOSFET having the trench gate structure, the side surface of the recess 17 can be provided through the P +- layer 46 in the trench 45. Thus, the same advantages as in the first embodiment can be obtained.Next, a method of manufacturing the semiconductor device illustrated in FIG. 10 will be explained with reference to FIGS. 11A, 11B, and 11C, and FIGS. 12A, 12B, and 12C. In FIGS. 11A, 11B, and 11C, and FIGS. 12A, 12B, and 12C, a portion outside the P-RESURF layer 20 illustrated in FIG. 10 is omitted.(Processing Illustrated in FIG. 11A )First, the N +- substrate 1 having the above-mentioned impurity concentration is provided. Then, the N -- drift layer 2, the P +- layer 3 and the N +- layer 4 are sequentially formed on the surface of the N +- substrate 1 by epitaxial growth. Accordingly, the semiconductor substrate 5 is manufactured.(Processing Illustrated in FIG. 11B )By photolithography, the trench 42 reaching the N -- drift layer 2 by penetrating the N +- layer 4 and the P +- layer 3 is formed in the transistor cell region R 1 at the same time as the trench 45 reaching the N -- drift layer 2 by penetrating the N +- layer 4 and the P +- layer 3 is formed in the external breakdown resistant structure region R 2. According to the present embodiment, each of the trenches 42 and 45 has the same width and the same depth.(Processing Illustrated in FIG. 11C )By epitaxial growth, P -- type or N -- type SiC and P +- type SiC are epitaxially grown on the entire surface of a semiconductor substrate 5 to form the low concentration layers 44 and 47, the P +- deep layer 43 and the P +- layer 46, so that the trenches 42 and 45 can be filled with these layers.(Processing Illustrated in FIG. 12A )The surface of the semiconductor substrate 5 is planarized by chemical mechanical polishing (CMP) so that the low concentration layers 44 and 47, the deep P +- layer 43 and the P +- layer 46 can be left only in the trenches 42 and 45.(Processing Illustrated in FIG. 12B )The recesses 16 and 17 are formed by executing the same processing as explained in the first embodiment with reference to FIG. 4B. Thus, the mesa structure is formed. At this time, the side surface of the recess 17 is provided through the P +- layer 46 into the trench 45.(Processing Illustrated in FIG. 12C )The trench 6 is formed by performing trench etching after a trench etching mask (not shown) is placed on the entire surface of the semiconductor substrate 6. Then, the gate insulating film 40 is formed by thermal oxidation. Then, the gate electrode 41 is formed by depositing doped polysilicon or the like. Then, planarization is formed by etching back or the like, so that the gate electrode 41 can be left in the trench 6.Although subsequent processes are not illustrated in the drawings, as in the processing illustrated in FIG. 4C of the first embodiment, after an ion implantation mask having openings corresponding to formation regions of the P regions 18 and 19 is placed, ion implantation of P-type impurities is performed in the normal direction of the substrate surface. Consequently, the P regions 18 and 19 are formed. At this time, since the side surface of the recess 17 is formed by the P +- layer 46 in the trench 45 in the processing illustrated in FIG. 12B, the P region 18 on the bottom surface of the recess 16, the P +- layer 46 in the trench 13, and the P region 19 on the bottom surface of the recess 17 are united to form the P-RESURF layer 20. Then, after the mask is removed, the ion implantation of N-type impurities is performed using a metal mask or the like. Then, the implemented ions are activated, so that the N +- layer 21 is made. Then, after the interlayer dielectric 11 is formed, contact holes are formed in predetermined regions of the interlayer dielectric 11 and the N +- layer 4. Then, a wiring layer is formed on the interlayer dielectric 11, and the source electrode 10 and the electrode 22 are formed by patterning the wiring layer. Then, the drain electrode is formed on the back surface side of the semiconductor substrate 5. In this way, the SiC semiconductor device shown in FIG. 10 is manufactured.As explained above, in the SiC semiconductor device according to the present embodiment, the P region 18 on the bottom surface of the recess 16, the P +- layer 46 in the trench 45, and the P region on the bottom surface of the recess 17 form the P-RESURF layer 20. Thus, as in the first embodiment, the drain breakdown voltage can be improved.The P-RESURF layer 20 can be formed without implanting ions into the side surface of the recess 17 during ion implantation. Thus, the P-RESURF layer 20 can be formed without performing the tilted ion implantation. Thus, the external breakdown resistant structure region is formed around the periphery of the transistor cell region R 1 where the MOSFET is formed without performing the tilted ion implantation, so that the SiC semiconductor device has a structure for obtaining a high drain breakdown voltage. The trench 45 and P +- layer 46 for providing the structure are formed at the same time as the trench 42 and the deep P +- layer 43 for providing the MOSFET. Therefore, the structure can be formed without extending the manufacturing processing.(Sixth Embodiment)A sixth embodiment of the present disclosure will be explained. Since the present disclosure is the same as the fifth embodiment except for a structure of the external breakdown-resistant structure region R 2, only the difference will be explained.FIG. 13 is a diagram illustrating a cross section of the SiC semiconductor device including a MOSFET according to the present embodiment. As illustrated in FIG. 13, a plurality of trenches 45 are formed, and each trench 45 is filled with the low concentration layer 47 and the P +- layer 46. The innermost trench 45 closest to the transistor cell region R 1 is located at the boundary (step height portion) between the bottom surface and the side surface of the recess 17, and the side surface of the recess 17 is provided by the P +- layer 46 in the innermost trench 45. Although upper portions of the P +- layers 46 in the other trenches 45 located outside the innermost trench 45 are removed by the recess 17, the remaining portions of the P +- layers 46 are arranged at regular intervals to provide a guard ring structure.As described above, according to the present embodiment, the guard ring structure is formed in the external breakdown resistant structure region R 2 instead of the P-RESURF layer 20 of the fifth embodiment. Even when the guard ring structure is formed, the P +- layer 46 may be located on the second surface of the recess 17 by using the trench 45 and the P +- layer 46. Thus, the same advantages as the fifth embodiment can be obtained.A method of manufacturing the SiC semiconductor device according to the present embodiment is almost the same as that described in the fifth embodiment. As illustrated in FIG. 14, a difference is that a plurality of trenches are formed at regular intervals in the processing explained in the fifth embodiment with reference to FIG. 11. When a plurality of trenches 45 are formed at regular intervals in advance, each trench 45 is filled with the low concentration layer 47 and the P +- layer 46 by forming the low concentration layer 44 and the P +- deep layer 43. Then, the recess 16 and the recess 17 are formed by performing selective etching, so that the innermost trench 44 closest to the transistor cell region R 1 can be disposed at the boundary between the bottom surface and the side surface of the recess 17. Thus, the SiC semiconductor device according to the present embodiment is manufactured. As explained above, the SiC semiconductor device has the guard ring structure in the external breakdown voltage resistant structure region R 2 instead of the P-RESURF layer 20, and the guard ring structure can be formed without ion implantation processing.(Seventh Embodiment)A seventh embodiment of the present disclosure will be explained. Since the present disclosure is the same as the sixth embodiment except for a shape of the guard ring structure, only the difference will be explained.FIG. 15 is a diagram illustrating a cross-sectional view of a SiC semiconductor device including a MOSFET according to the present embodiment. As illustrated in FIG. 15, according to the present embodiment, although the guard ring structure is formed using the trench 45, the low concentration layer 47, and the P +- layer 46, the trenches 45 are arranged in descending order of their width in the outward direction. Further, since the trench 45 is narrower, the low concentration layer 47 in the trench 45 is thicker, so that the P +- layer 46 on the low concentration layer 47 may be thinner.In this structure, the electric field at the OFF time is further mitigated. Thus, even if the size of the outer breakdown resistant structure region R 2 is smaller than that of the sixth embodiment in which the P +- layers 46 have the same depth, the same or higher drain breakdown voltage can be ensured.A method of manufacturing the SiC semiconductor device according to the present embodiment is almost the same as that explained in the sixth embodiment. As illustrated in FIG. 16, a difference is that the trenches 45 are arranged in descending order of their width in the outward direction in the processing explained in the fifth embodiment with reference to FIG. 11. When the trenches 45 are arranged in advance at intervals of the order of their width in the outward direction, the thickness of the low concentration layer 47 formed on the bottom of the trench 45 changes according to the width of the trench 45. thus, since the trench 45 is narrower, the low concentration layer 47 is thicker, so that the P +- layer 46 on the low concentration layer 47 can be thinner. In this way, the SiC semiconductor device according to the present embodiment is manufactured.(Eighth Embodiment)An eighth embodiment of the present disclosure will be explained. Since the present embodiment is the same as the sixth and seventh embodiments except for a shape of the guard ring structure, only the difference will be explained.FIG. 17 is a diagram illustrating a cross-sectional view of a SiC semiconductor device including a MOSFET according to the present embodiment. In the sixth and seventh embodiments, the height of the bottom surface of the recess 17 formed in the outer breakdown-resistant pattern region R 2 is kept constant. Alternatively, as illustrated in FIG. 17, the height of the bottom surface of the recess 17 may gradually decrease in the outward direction of the transistor cell region R 1. Accordingly, the P +- layers 46 of the guard ring structures are arranged in descending order of height, so that the outermost P +- layer 46 can have the smallest height.When the P +- layer 46 of the guard ring structures are arranged in descending order of their height, the electric field is mitigated more effectively. As a result, breakdown voltage is further improved.(Modifications)While the present disclosure has been explained with reference to embodiments thereof, it is to be understood that the disclosure is not limited to the embodiments. The present disclosure is intended to cover various modifications and equivalent arrangements within the light of the spirit and scope of the present disclosure.In the above embodiments, the electric field mitigation structure is provided by forming the side surface of the recess 17 at the boundary between the recess 16 and the recess 17 using the P +- layer 15 or 46, and the external breakdown resistant structure is provided by forming the P-RESURF layer 20 or the guard ring structure using the same. The minimum requirement for such an external breakdown resistant structure is to include the electric field mitigation structure provided by forming the side surface of the recess 17 at the boundary between the recess 16 and the recess 17 using the P +- layer 15 or 46. The external breakdown resistant structure may be modified in any manner as long as the minimum requirement is satisfied. For example, the external breakdown resistant structure may be the P-RESURF layer 20 using the electric field mitigation structure, the guard ring structure using the electric field mitigation structure, or a combination thereof.In the above embodiments, an N-channel JFET in which a channel region is formed in the N -- channel layer 7 or an N-channel MOSFET in which a channel region is formed in the P +- layer 3 providing the P base region is explained as an example. Alternatively, a P-channel JFET or MOSFET in which a conductivity type of each component is reversed may be applied to the present disclosure. Although a JFET or a MOSFET is explained as an example of a transistor formed in the transistor cell region R 1, another type of transistor may be formed.In the first embodiment, the JFET is driven by dual gate drive in which the source-drain current is controlled by controlling the potential of each of the first and second gate regions. Alternatively, the JFET may be driven by single gate drive in which the source-drain current is controlled by controlling the potential of the first and / or second gate regions.In the above embodiments, the N +- layer 4 providing the source region is formed by epitaxial growth. Alternatively, the N +- layer may be formed by ion implantation of N-type impurities into the first gate region. In this case, when the N +- layer 4 is formed at a position separated from the mesa, there is no need for the recess 16.In the SiC semiconductor device including the JFET in the transistor cell region R 1 according to the first to fourth embodiments, since the trench 13 corresponding to the first trench and the trench 5 corresponding to the second trench can be formed simultaneously, the electric field mitigation structure such as the P-RESURF layer 20 or the guard ring structure is formed using the trench 13 filled with the N -- layers 14 and the P +- layer 15. Similarly, in the SiC semiconductor device including the MOSFET in the transistor cell region R 1 according to the fifth to eighth embodiments, since the trench 45 corresponding to the first trench and the trench 42 corresponding to the second trench can be formed simultaneously, the electric field mitigation structure such as the P-RESURF layer 20 or the guard ring structure is formed using the trench 42 filled with the P +- layer 42. Alternatively, in the SiC semiconductor device including the JFET, the electric field mitigation structure such as the P-RESURF layer 20 or the guard ring structure may be formed using the trench 42 filled with the P +- layer 42 as described in the fifth to eighth embodiments, or in the SiC semiconductor device including the MOSFET, the electric field mitigation structure such as the P-RESURF layer 20 or the guard ring structure may be formed using the trench 13 filled with the N -- layers 14 and the P +- layer 15.

Claims

A silicon carbide semiconductor device, comprising: a semiconductor substrate (5) including a first conductivity type substrate (1), a first conductivity type drift layer (2) on the first conductivity type substrate (1), a second conductivity type layer (3) on the drift layer (2), and a first conductivity type layer (4) on the second conductivity type layer (3); a transistor formed in a transistor cell region (R1) of the semiconductor substrate (5); and an external breakdown resistant structure formed in an external breakdown resistant structure region (R2) surrounding an outer periphery of the transistor cell region (R1), wherein the external breakdown resistant structure formed in the external breakdown resistant structure region (R2) includes a first recess (17), surrounding the outer periphery of the transistor cell region (R1), a first trench (13) located on a side surface of the first recess (17) on an inner periphery of the first recess (17), and including an electric field mitigation structure having a second conductivity type embedded layer (15), the first recess (17) being deeper than the first conductivity type layer (4) and the second conductivity type layer (3) and reaching the drift layer (2), the first trench (13) surrounding the outer periphery of the transistor cell region (R1), the second conductivity type embedded layer (15) being embedded in the first trench (13) and providing the side surface of the first recess (17), the transistor cell region (R1) providing a second trench (6), a channel layer (7) of a first conductivity type and a second gate region (8) of a second conductivity type, the first trench (13) and the second trench (6) have the same depth, and the embedded layer (15) of a second conductivity type is formed over an embedded layer (14) of a first conductivity type in the first trench (13), wherein the silicon carbide semiconductor device further comprises: a second recess (16) that is deeper than a thickness of the layer (4) of a first conductivity type and surrounds the outer periphery of the transistor cell region (R1), wherein the first recess (17) is disposed farther away from the transistor cell region (R1) than the second recess (16) and deeper than the second recess (16), and the first trench (13) is disposed at a boundary between the first recess (17) and the second recess (16).The silicon carbide semiconductor device according to claim 1, wherein a second conductivity type layer (18, 19) is formed on a side of a bottom surface of the second recess (16) near the first recess (17), is formed on a side of a bottom surface of the first recess (17) near the second recess (16), and is united with the second conductivity type embedded layer (15) to form a second conductivity type RESURF layer (20) providing the electric field mitigation structure.The silicon carbide semiconductor device according to claim 1, further comprising a plurality of first trenches (13) including the first trench (13), wherein the plurality of first trenches (13) is disposed outward from the boundary between the first recess (17) and the second recess (16), and the embedded layer (15) of a second conductivity type is embedded in each of the plurality of first trenches (13) to form a guard ring structure providing the electric field mitigation structure.The silicon carbide semiconductor device according to claim 1 or 3, further comprising a plurality of first trenches (13) including the first trench (13), wherein the plurality of first trenches (13) are disposed inward from the boundary between the first recess (17) and the second recess (16), and the second conductivity type embedded layer (15) is embedded in each of the plurality of first trenches (13) to form a guard ring structure providing the electric field mitigation structure.The silicon carbide semiconductor device according to claim 3 or 4, wherein the plurality of first trenches (13) are arranged in descending order of their width in an outward direction of the transistor cell region (R1).The silicon carbide semiconductor device according to any one of claims 1 to 5, wherein a JFET is formed in the transistor cell region (R1), the transistor cell region (R1) includes a first gate region, a source region, a source electrode (10), and a drain electrode (12), the first gate region is provided by the second conductivity type layer (3), the source region is provided by the first conductivity type layer (4), the second trench (6) reaches the drift layer (2) by penetrating the first conductivity type layer (4) and the second conductivity type layer (3), the channel layer (7) is formed by epitaxial growth on an inner wall of the second trench (6), the second gate region (8) is formed on the channel layer (7), the source electrode (10) is electrically connected to the first conductivity type layer (4), the drain electrode (12) is electrically connected to the first conductivity type substrate (1), and a source-drain current is controlled by controlling a potential of the first gate region (3) and / or the second gate region (8).A silicon carbide semiconductor device, comprising: a semiconductor substrate (5) including a first conductivity type substrate (1), a first conductivity type drift layer (2) on the first conductivity type substrate (1), a second conductivity type layer (3) on the drift layer (2), and a first conductivity type layer (4) on the second conductivity type layer (3); a MOSFET formed in a transistor cell region (R1) of the semiconductor substrate (5) and including a base region, a source region, a gate insulating layer (40), a gate electrode (41), a source electrode (10), a drain electrode (12), a second trench (42), and a deep second conductivity type layer (43), the base region being provided by the second conductivity type layer (3), the source region is provided by the first conductivity type layer (4), the gate insulating layer (40) is formed on a surface of the base region between the source region and the drift layer, the gate electrode (41) is formed on a surface of the gate insulating layer (40), the source electrode (10) is electrically connected to the first conductivity type layer (4), the drain electrode (12) is electrically connected to the first conductivity type substrate (1), the second trench (42) reaches the drift layer (2) by penetrating the first conductivity type layer (4) and the second conductivity type layer (3), the second conductivity type deep layer (43) is embedded in the second trench (42), and a source-drain current is controlled by controlling a potential of the gate electrode (41); and an external voltage breakdown resistant structure, which is formed in an outer voltage breakdown resistant structure region (R2) surrounding an outer periphery of the transistor cell region (R1), wherein the outer voltage breakdown resistant structure formed in the outer voltage breakdown resistant structure region (R2) includes a first recess (17) surrounding the outer periphery of the transistor cell region (R1), a first trench (45) located on a side surface of the first recess (17) on an inner periphery of the first recess (17), and an electric field mitigation structure having a second conductivity type embedded layer (46), the first recess (17) being deeper than the first conductivity type layer (4) and the second conductivity type layer (3) and reaching the drift layer (2), the first trench (45) surrounds the outer periphery of the transistor cell region (R1), the embedded second conductivity type layer (46) is embedded in the first trench (45) and provides the side surface of the first recess (17), the silicon carbide semiconductor device further comprising: a second recess (16) deeper than a thickness of the first conductivity type layer (4) and surrounding the outer periphery of the transistor cell region (R1), the first recess (17) is disposed farther away from the transistor cell region (R1) than the second recess (16) and deeper than the second recess (16), and the first trench (45) is disposed at a boundary between the first recess (17) and the second recess (16).The silicon carbide semiconductor device according to claim 7, wherein the first trench (45) and the second trench (42) have the same depth.The silicon carbide semiconductor device according to claim 7 or 8, wherein another trench (6) is formed in the transistor cell region (R1) and reaches the drift layer (2) by penetrating the first conductivity type layer (4) and the second conductivity type layer (3), the gate insulating layer (40) and the gate electrode (41) are formed in the another trench (6) such that the MOSFET has a trench gate structure, and the second trench (42) is deeper than the another trench (6) of the trench gate structure.A method for manufacturing a silicon carbide semiconductor device, the silicon carbide semiconductor device comprising: a semiconductor substrate (5) including a first conductivity type substrate (1), a first conductivity type drift layer (2) on the first conductivity type substrate (1), a second conductivity type layer (3) on the drift layer (2), and a first conductivity type layer (4) on the second conductivity type layer (3); a transistor formed in a transistor cell region (R1) of the semiconductor substrate (5); and an external voltage breakdown resistant structure formed in an external voltage breakdown resistant structure region (R2) surrounding an outer periphery of the transistor cell region (R1), the method comprising: a step of providing the semiconductor substrate (5); a step of forming a first trench (13) in the external breakdown resistant structure region (R2) such that the first trench (13) surrounds the outer periphery of the transistor cell region (R1); a step of forming an embedded second conductivity type layer (15) in the first trench (13), and a step of forming a first recess (17) deeper than the first conductivity type layer (4) and the second conductivity type layer (3) and reaching the drift layer (2) such that the first recess (17) surrounds the outer periphery of the transistor cell region (R1), wherein in the step of forming the first recess (17), the first trench (13) is located on a side surface of the first recess (17) on an inner periphery of the first recess (17), such that the side surface of the first recess (17) is provided by the second conductivity type embedded layer (15) to form an electric field mitigation structure including the second conductivity type embedded layer (15), and the method further comprises: a step of forming a second trench (6), a step of forming a first conductivity type channel layer (7) and a step of forming a second conductivity type gate region (8) in the transistor cell region (R1), respectively, and a step of forming a first conductivity type embedded layer (14) in the first trench (13), the first trench (13) and the second trench (6) having the same depth, and the embedded layer (15) of a second conductivity type is formed over the embedded layer (14) of a first conductivity type in the first trench (13), the method further comprising: a step of forming a second recess (16) deeper than a thickness of the layer (4) of a first conductivity type such that the second recess (16) surrounds the outer periphery of the transistor cell region (R1), wherein in the step of forming the first recess (17), the first trench (13) is disposed at a boundary between the first recess (17) and the second recess (16) such that the side surface of the first recess (17) at the boundary between the first recess (17) and the second recess (16) is provided by the embedded layer (15) of a second conductivity type to form the electric field mitigation structure, which has the embedded layer (15) of a second conductivity type.The method according to claim 10, further comprising: a step of forming a second conductivity type layer (18, 19) on a side of a bottom surface of the second recess (16) near the first recess (17) and on a side of a bottom surface of the first recess (17) near the second recess (16) such that the second conductivity type layer (18, 19) is united with the embedded second conductivity type layer (15) to form a second conductivity type RESURF layer (20) providing the electric field mitigation structure, wherein the step of forming the second conductivity type layer (18, 19) follows the step of forming the first recess (17) and the step of forming the second recess (16), and the step of forming the layer (18, 18, 19) of a second conductivity type includes a step of forming a mask on a surface of the substrate, and a step of performing ion implantation of impurities of a second conductivity type in a normal direction of the substrate using the mask.The method according to claim 10, wherein in the step of forming the first trench (13), a plurality of the first trenches (13) including the first trench (13) is formed such that the plurality of first trenches (13) is disposed outward from the boundary between the first recess (17) and the second recess (16), and in the step of forming the second conductivity type embedded layer (15), the second conductivity type embedded layer (15) is formed in each of the plurality of first trenches (13) to form a guard ring structure providing the electric field mitigation structure.The method according to claim 10 or 12, wherein in the step of forming the first trench (13), a plurality of the first trenches (13) including the first trench (13) is formed such that the plurality of first trenches (13) is disposed inward from the boundary between the first recess (17) and the second recess (16), and in the step of forming the second conductivity type embedded layer (15), the second conductivity type embedded layer (15) is formed in each of the plurality of first trenches (13) to form a guard ring structure providing the electric field mitigation structure.The method according to claim 12 or 13, wherein in the step of forming the first trench (13), the plurality of first trenches (13) is formed such that the plurality of first trenches (13) are arranged in descending order of their width in an outward direction of the transistor cell region (R1).The method according to any one of claims 10 to 14, further comprising: a step of forming a JFET in the transistor cell region (R1), wherein the transistor cell region (R1) has a first gate region provided by the second conductivity type layer (3), a source region provided by the first conductivity type layer (4), a source electrode (10), and a drain electrode (12), the step of forming the JFET includes a step of forming a second trench (6) reaching the drift layer (2) by penetrating the first conductivity type layer (4) and the second conductivity type layer (3), a step of forming a channel layer (7) of a first conductivity type by epitaxial growth on an inner wall of the second trench (6), a step of forming a second conductivity type second gate region (8) on the channel layer (7), a step of forming the source electrode (10) electrically connected to the first conductivity type layer (4), and a step of forming the drain electrode (12) electrically connected to the first conductivity type substrate (1), and a source-drain current is controlled by controlling a potential of the first gate region (3) and / or the second gate region (8).The method according to claim 15, wherein the step of forming the second conductivity type embedded layer (15) is performed after the step of forming the first conductivity type embedded layer (14), the step of forming the first trench (13) and the step of forming the second trench (6) are performed simultaneously, the step of forming the first conductivity type embedded layer (14) and the step of forming the channel layer (7) are performed simultaneously, and the step of forming the second conductivity type embedded layer (15) and the step of forming the second gate region (8) are performed simultaneously.A method for manufacturing a silicon carbide semiconductor device, the silicon carbide semiconductor device comprising: a semiconductor substrate (5) including a first conductivity type substrate (1), a first conductivity type drift layer (2) on the first conductivity type substrate (1), a second conductivity type layer (3) on the drift layer (2), and a first conductivity type layer (4) on the second conductivity type layer (3); a transistor formed in a transistor cell region (R1) of the semiconductor substrate (5); and an external voltage breakdown resistant structure formed in an external voltage breakdown resistant structure region (R2) surrounding an outer periphery of the transistor cell region (R1), the method comprising: a step of providing the semiconductor substrate (5); a step of forming a first trench (45) in the external breakdown resistant structure region (R2) such that the first trench (45) surrounds the outer periphery of the transistor cell region (R1); a step of forming an embedded layer (46) of a second conductivity type in the first trench (45); and a step of forming a first recess (17) deeper than the layer (4) of a first conductivity type and the layer (3) of a second conductivity type and reaching the drift layer (2) such that the first recess (17) surrounds the outer periphery of the transistor cell region (R1), wherein in the step of forming the first recess (17), the first trench (45) is located on a side surface of the first recess (17) on an inner periphery of the first recess (17), such that the side surface of the first recess (17) is provided by the second conductivity type embedded layer (46) to form an electric field mitigation structure including the second conductivity type embedded layer (46), and the method further comprises: a step of forming a second recess (16) deeper than a thickness of the first conductivity type layer (4) such that the second recess (16) surrounds the outer periphery of the transistor cell region (R1), wherein in the step of forming the first recess (17), the first trench (45) is disposed at a boundary between the first recess (17) and the second recess (16) such that the side surface of the first recess (17) is provided at the boundary between the first recess (17) and the second recess (16) by the second conductivity type embedded layer (46), to form the electric field mitigation structure including the embedded second conductivity type layer (46), and a step of forming a MOSFET in the transistor cell region (R1), the MOSFET including a base region provided by the second conductivity type layer (3) and a source region provided by the second conductivity type layer (4), wherein the step of forming the MOSFET includes a step of forming a second trench (42) reaching the drift layer (2) by penetrating the first conductivity type layer (4) and the second conductivity type layer (3), a step of forming a deep second conductivity type layer (43) in the second trench (42), a step of forming a gate insulating film (42) on a surface of the base region between the source region and the drift layer, a step of forming a gate electrode (41) on a surface of the gate insulating film (40), forming a source electrode (10) electrically connected to the first conductivity type film (4), and a step of forming a drain electrode (12) electrically connected to the first conductivity type substrate (1), and a source-drain current is controlled by controlling a potential of the gate electrode (41).The method according to claim 17, wherein the step of forming the first trench (45) and the step of forming the second trench (42) are performed simultaneously, and the step of forming the embedded layer (46) of a second conductivity type and the step of forming the deep layer (43) are performed simultaneously.The method according to claim 17 or 18, further comprising: a step of forming a further trench (6) in the transistor cell region (R1) such that the second trench (42) is deeper than the further trench (6) and reaches the drift layer (2) by penetrating the first conductivity type layer (4) and the second conductivity type layer (3), wherein the gate insulating layer (40) and the gate electrode (41) are formed in the other trench (6) such that the MOSFET has a trench gate structure.

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