Solid-state imaging device and method for controlling the same

Abstract

A solid-state imaging device having a plurality of pixels (10), each pixel (10) comprising: - a photoelectric conversion section (21) of a second conductivity type arranged in a surface layer portion of a surface of a semiconductor substrate (20) of a first conductivity type and converting light incident on the surface into an electric charge; - a charge holding section (22) of a second conductivity type which stores the electric charge generated in the photoelectric conversion section (21) and is arranged in the semiconductor substrate (20); - a multiplication gate electrode (31) capacitively coupled to the charge holding section (22) and disposed on the semiconductor substrate (20) via an insulating film (34); and - a cargo barrier section (26) which: - is arranged between the charge holding section (22) and the insulating film (34) at a position where the multiplication gate electrode (31) and the charge holding section (22) are capacitively coupled, - has a first conductivity type with a higher impurity concentration than the semiconductor substrate (20), - causes the charge holding section (22) to hold the electric charge until an electric field in a depth direction of the semiconductor substrate (20) reaches an electric field capable of avalanche multiplication when a voltage is applied to the multiplication gate electrode (31), and - the avalanche multiplication of the electric charge in the depth direction is generated when a predetermined voltage is applied to the multiplication gate electrode (31).

Description

[Technical field]

[0001] The present invention relates to a solid-state imaging device having a gate electrode for amplifying an electric charge and a method for driving the same. [State of the art]

[0002] Solid-state imaging devices that use semiconductors are known as image sensors, such as CCD image sensors and CMOS image sensors. Image sensors increase the number of pixels to produce higher-resolution images. As a result, reducing the light-receiving area per pixel can reduce sensitivity.

[0003] To solve this problem, for example, JP 2009 - 147 064 A proposes a solid-state imaging device having a gate electrode for avalanche multiplication between a photodiode section for photoelectrically converting the incident light and a floating diffusion section for converting an electric charge into a voltage.

[0004] The solid-state imaging device described in JP 2009-147064 A performs avalanche multiplication on an electric charge and stores the multiplied electrons. The solid-state imaging device thus includes multiple quantum well structures and gate electrodes corresponding to the multiplication and storage. The solid-state imaging device further includes a gate electrode for transferring charges between the quantum wells. At least three gate electrodes are required within a unit pixel to multiply electric charges. This causes a problem in that the pixel size is increased and a large number of pixels are difficult to use. The solid-state imaging device according to this configuration multiplies an electric charge between different quantum wells (different gate electrodes), thus increasing the length of a path for the electric charge.This makes it difficult to reduce a voltage applied to a multiplication gate electrode to detect an electric field that enables avalanche multiplication.

[0005] From JP 2009 - 147 049 A, a solid-state imaging device is also known which comprises a p-type silicon substrate, a gate insulating film, three gate electrodes, a photodiode section, a floating diffusion region composed of an n-type impurity region, and an element isolation region. [Summary of the invention]

[0006] It is an object of the present invention to reduce the size of a pixel in a solid-state imaging device having a multiplying section and to reduce a voltage applied to a multiplying gate electrode.

[0007] The object is achieved by a solid-state imaging device according to claim 1 and a method for controlling such a solid-state imaging device according to claim 13. Advantageous further developments are the subject of the subclaims.

[0008] According to the invention, the charge barrier portion is caused to form a region between the insulating film and the charge holding portion having a potential lower than that of the interface between the semiconductor substrate and the insulating film and the charge holding portion. The charge holding portion provides a higher potential than the charge holding portion and a region opposite the charge barrier portion with respect to the charge holding portion in the direction of arrangement of the insulating film, the charge barrier portion, and the charge holding portion. More specifically, a quantum well is formed. For this reason, the charge holding portion stores an electric charge generated by the photoelectric conversion portion. The insulating film and the charge barrier portion are provided between the multiplication gate electrode and the charge holding portion.When a predetermined voltage is applied to the multiplication gate electrode, the potential toward the insulating film increases in the direction of the arrangement of the insulating film, the charge blocking portion, and the charge holding portion. An electric charge present in the charge holding portion accelerates toward the insulating film and increases in the charge blocking portion due to avalanche multiplication. It is possible to multiply an electric charge while storing the electric charge in the charge holding portion and applying a predetermined voltage to the multiplication gate electrode with respect to an impurity profile according to the present invention in the direction of the arrangement of the insulating film, the charge blocking portion, and the charge holding portion. The same electrode can store and multiply electric charges without forming another charge holding portion and another multiplication gate electrode in other regions.The thickness of the charge barrier portion for accelerating and multiplying an electric charge, i.e., the distance required to accelerate the electric charge, can be reduced compared to a configuration for accelerating and multiplying electric charges between different electrodes. Accordingly, the voltage applied to the multiplication gate electrode can be reduced to ensure an electric field suitable for avalanche multiplication of electric charges.

[0009] The driving method of the present invention applies a low bias voltage to the multiplication gate electrode during the storage period, thus allowing the potential in the charge blocking portion to decrease compared to the charge holding portion. That is, the charge holding portion below the multiplication gate electrode can store an electric charge generated in the photoelectric conversion portion without moving the electric charge toward the surface of the semiconductor substrate. The method applies a high bias voltage to the multiplication gate electrode during the multiplication period, thus allowing the potential for the charge blocking portion to be higher than that of the charge holding portion while increasing the potential toward the insulating film. That is, the electric charge stored in the charge holding portion can be accelerated toward the insulating film.Avalanche multiplication can be used to increase the electrical charge. [Brief description of the drawings]

[0010] The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description with reference to the accompanying drawings. In the drawings: Fig. 1 schematically shows a configuration of a solid-state imaging device according to a first embodiment; Fig. 2 a cross-sectional view of a pixel along the line II-II in the Fig. 3 and schematically a configuration of the pixel; Fig. 3 a top view illustrating a pixel layout; Fig. 4 is a timing chart illustrating timings for driving the solid-state imaging device; Fig. 5 is a potential diagram illustrating electrical potential profiles for the pixel in a direction perpendicular to a thickness direction of a semiconductor substrate; Fig. 6 is a potential diagram illustrating electrical potential profiles for the pixel in the direction perpendicular to a thickness direction of a semiconductor substrate; Fig. 7 is a potential diagram illustrating electrical potential profiles for the pixel in a thickness direction of a semiconductor substrate; Fig. 8 is a potential diagram illustrating electrical potential profiles for the pixel in a thickness direction of a semiconductor substrate; Fig. 9 is a potential diagram illustrating electrical potential profiles for the pixel in a thickness direction of a semiconductor substrate; Fig. 10 is a potential diagram illustrating electrical potential profiles for the pixel in a direction perpendicular to a thickness direction of a semiconductor substrate; Fig. 11 is a potential diagram illustrating electrical potential profiles for the pixel in a direction perpendicular to a thickness direction of a semiconductor substrate; Fig. 12 the dependence of the maximum electric field strength in a charge barrier section on an impurity concentration in the charge barrier section; Fig. 13 is a partially enlarged cross-sectional view taken along the line II-II in the Fig. 2 and a potential diagram; Fig. 14 is a partially enlarged cross-sectional view taken along the line II-II in the Fig. 2 and a potential diagram; Fig. 15 is a cross-sectional view of a pixel according to a modification of the first embodiment; Fig. 16 is a cross-sectional view illustrating a schematic configuration of a pixel according to a second embodiment; Fig. 17 is a cross-sectional view illustrating a schematic configuration according to a third embodiment; Fig. 18 is a cross-sectional view of a pixel according to a fourth embodiment along the line XVIII-XVIII in the Fig. 19 and schematically a configuration of the pixel; Fig. 19 is a plan view illustrating an exemplary pixel layout; Fig. 20 a cross-sectional view of a pixel along the line XX-XX in the Fig. 19 and schematically a configuration of the pixel; Fig. 21 is a potential diagram illustrating electrical potential profiles for the pixel in a direction along a surface of a semiconductor substrate; Fig. 22 is a potential diagram illustrating electrical potential profiles for the pixel according to a fifth embodiment in a thickness direction of a semiconductor substrate; and Fig. 23 is a cross-sectional view of a pixel according to another embodiment; [Embodiments for carrying out the invention]

[0011] Embodiments of the present invention will now be described with reference to the accompanying drawings, in which corresponding parts in the drawings are designated by the same reference numerals. (First embodiment)

[0012] The following is a schematic configuration of the solid-state imaging device of the embodiment with reference to FIG. Fig. 1 described.

[0013] The solid-state imaging device of the embodiment forms a CMOS image sensor. The solid-state imaging device has, as shown in Fig. 1, a sensor array 11, a vertical drive circuit 12, a CDS (correlated double sampling) circuit 13, a horizontal drive circuit 14, an A / D conversion (ADC) circuit 15, and a timing generator (TG) 16. The sensor array 11 includes a plurality of unit pixels (hereinafter referred to simply as pixels) arranged in a two-dimensional matrix.

[0014] The unit pixel 10 includes at least such components as a photoelectric conversion section, a charge holding section, a floating diffusion (FD) section, and a reset drain (RD) section. The photoelectric conversion section photoelectrically converts the incident light to store an electric charge. The charge holding section receives the electric charge from the photoelectric conversion section and temporarily holds the electric charge. The FD section receives the electric charge from the charge holding section and converts the electric charge into a voltage. The RD section resets the amount of electric charge in the FC section. According to the embodiment, the pixel 10 also includes a transfer device that transfers an electric charge from the photoelectric conversion section to the charge holding section and from the charge holding section to the FD section.A specific configuration of the unit pixel 10 is described below.

[0015] A row transmission line 10a and a row selection line 10b connect the vertical drive circuit 12 to each pixel. The vertical drive circuit 12 selects each pixel 10 in the sensor array 11 in units of rows as read rows. The row transmission line 10a includes a plurality of signal lines and supplies the sensor array 11 with a drive signal that transmits or resets a signal generated by the photoelectric conversion section, which will be described later. The row selection line 10b supplies the sensor array 11 with a signal for selecting it as a read row.

[0016] The CDS circuit 13 is arranged for one or more pixel rows in the sensor array 11 and performs CDS processing on a signal read from the row selected by the vertical drive circuit 12. Specifically, the CDS circuit 13 receives a reset level and a signal level from each pixel 10 and determines a difference between the two levels to remove a fixed noise pattern for each pixel 10.

[0017] The horizontal drive circuit 14 is connected to each pixel 10 via the CDS circuit 13 through a column signal line 10c. The horizontal drive circuit 14 sequentially selects signals, which are subjected to CDS processing in the CDS circuit 13 and stored column by column. After the horizontal drive circuit 14 selects signals for the columns, the ADC 15 converts the signals into digital signals and outputs them.

[0018] The TG 16 generates various timing signals to drive the vertical drive circuit 12, the CDS circuit 13, the horizontal drive circuit 14 and the ADC 15.

[0019] The following is a schematic configuration of the unit pixel 10 of the embodiment with reference to FIG. Fig. 2 described.

[0020] The unit pixel 10 has, as in Fig. 2, a photoelectric conversion section 21, a charge holding section 22, an FD section 23, and an RD section 24 are formed on a surface 20a of a p-type (p-) semiconductor substrate 20. According to the embodiment, the sections 21, 22, 23, and 24 are formed separately from each other and adjacent to each other in this order. The embodiment supplies the semiconductor substrate 20 with a ground potential.

[0021] The photoelectric conversion section 21 is available as an n-type (n-) doped with impurities such as phosphorus. The impurity concentration can be set to, for example, 5.0 × 10 16 cm -3 The light incident on the photoelectric conversion section 21 is converted into an electric charge by photoelectric conversion. According to the embodiment, an electric charge generated by photoelectric conversion describes an electron. A hole enhancement layer 25 is formed between the photoelectric conversion section 21 and the surface 20a. The hole enhancement layer 25 is available as a p-type (p+) with a higher impurity concentration than the semiconductor substrate 20. That is, the hole enhancement layer 25 is exposed from the surface 20a. The photoelectric conversion section 21 is formed deeper than the hole enhancement layer 25 in the thickness direction of the semiconductor substrate 20.

[0022] The charge holding section 22 is doped with impurities such as phosphorus, available as n-type (n), with a higher concentration than the photoelectric conversion section 21. The impurity concentration can be set, for example, to 1.0 × 10 17 cm -3be set. Consequently, the charge holding portion 22 exhibits a higher potential than the semiconductor substrate 20 (p-type region) surrounding the charge holding portion 22. According to the embodiment, the charge holding portion 22 is formed separately from the photoelectric conversion portion 21. A transfer device, which will be described later, transfers an electric charge generated in the photoelectric conversion portion 21 to the charge holding portion 22. Then, the charge holding portion 22 temporarily holds the electric charge. A charge barrier portion 26 is formed between the charge holding portion 22 and the surface 20a adjacent to the charge holding portion 22. The charge barrier portion 26 is exposed from the surface 20a. The charge holding portion 22 is formed deeper than the charge barrier portion 26 in the thickness direction of the semiconductor substrate 20.According to the embodiment, an interface between the charge holding portion 22 and the charge blocking portion 26 is formed such that it is approximately 0.2 µm away from the surface 20a. The charge blocking portion 26 is available as a p-type (p) with a higher impurity concentration than the semiconductor substrate 20. The impurity concentration of the charge blocking portion 26 is preferably set to a value greater than or equal to 1.5 × 10 . 17 cm -3 and less than or equal to 3.0 × 10 18 cm -3 According to the embodiment, the impurity concentration is set to 3.0 × 10 17 cm -3The charge-blocking portion 26 is characteristic of the present invention. The charge-blocking portion 26 causes a potential in the thickness direction of the semiconductor substrate 20 to form a quantum well, the base of which corresponds to the charge-holding portion 22. Specific operating effects of the charge-blocking portion 26 will be described below.

[0023] The FD section 23 is doped with impurities such as phosphorus, available as n-type (n+) with a higher concentration than the charge holding section 22. The FD section 23 is provided separately from the photoelectric conversion section 21 and the charge holding section 22. A source follower circuit 27 is connected to the FD section 23. The source follower circuit 27 according to the embodiment includes three transistors Tr1, Tr2, and Tr3 connected in series. The gate of the transistor Tr1 is connected to the FD section 23. The drain is connected to a power supply potential (VDD in the Fig. 2). The row select line 10b connects the gate of the transistor Tr2 to the vertical drive circuit 12. The drain is connected to the source of the transistor Tr1. The row select line 10b, which is connected to the gate of the transistor Tr2, is controlled by a clock pulse (SEL in the Fig. 2), which controls an on / off state of transistor Tr2. The gate of transistor Tr3 is connected to a constant voltage source 28. The drain is connected to the source of transistor Tr2. The source of transistor Tr3 is grounded. That is, transistor Tr3 serves as a constant current source. The column signal line 10c is connected to the source of transistor Tr2, that is, the drain of transistor Tr3.

[0024] An electric charge transferred from the charge holding section 22 changes the electric potential of the FD section 23. The transistor Tr2 turns on when a certain voltage is applied to the row selection line 10b (for reading signals). An electric current corresponding to a change in the electric potential of the FD section 23 flows through the column signal line 10c. The transistor Tr2 turns off when no certain voltage is applied to the row selection line 10b. In this state, there is no change in the current flowing through the column signal line 10c due to a change in the electric potential of the FD section 23.

[0025] The RD section 24, doped with impurities such as phosphorus, is available as n-type (n+) with a concentration approximately equal to the FD section 23. The RD section 24 is provided separately from the photoelectric conversion section 21, the charge holding section 22 and the FD section 23. The RD section 24 is connected to the constant voltage source (VRD in the Fig. 2) to provide a specific electrical potential. According to the embodiment, VRD is supplied from the same power source as VDD. A reset operation, described below, flushes an electrical charge stored in the FD section 23 to the RD section 24. The FD section 23 maintains the same electrical potential as the RD section 24.

[0026] The unit pixel 10 includes a plurality of gate electrodes such that the vertical drive circuit 12 performs an on / off operation at specific timings. Specifically, the unit pixel 10 includes a transfer gate electrode 30, a multiplication gate electrode 31, a read gate (ROG) electrode 32, and a reset gate (RG) electrode 33. According to the embodiment, the gate electrodes 30, 31, 32, and 33 use n-type polycrystalline silicon doped with impurities.

[0027] The transfer gate electrode 30 is formed via an insulating film 34 above a region between the photoelectric conversion section 21 and the charge holding section 22 on the surface 20a of the semiconductor substrate 20. The transfer gate electrode 30 connects to a transfer line 35 included in the series transfer line 10a and is supplied with a clock pulse (Vtr in the Fig. 2) supplied by the vertical control circuit 12.

[0028] The multiplication gate electrode 31 is capacitively coupled to at least partially overlap with the charge holding portion 22 and is formed via the insulating film 34 above the surface 20a of the semiconductor substrate 20. The multiplication gate electrode 31 connects to a multiplication gate line 36 included in the series transmission line 10a and is supplied with a clock pulse (VMG in the Fig. 2) supplied by the vertical control circuit 12.

[0029] The ROG electrode 32 is formed via the insulating film 34 above a region between the charge holding portion 22 and the FD portion 23 on the surface 20a of the semiconductor substrate 20. The ROG electrode 32 connects to a read gate line (ROG line) 37 included in the series transmission line 10a and is supplied with a clock pulse (VROG in the Fig. 2) supplied by the vertical control circuit 12.

[0030] The RG electrode 33 is formed via the insulating film 34 above a region between the FD portion 23 and the RD portion 24 on the surface 20a of the semiconductor substrate 20. The RG electrode 33 connects to a reset gate line (RG line) 38 included in the series transmission line 10a and is supplied with a clock pulse (VRG in the Fig. 2) supplied by the vertical control circuit 12.

[0031] According to the embodiment, the pixel 10 includes a light-shielding film 39 for blocking light. The light-shielding film 39 is formed above a region except the photoelectric conversion portion 21 for photoelectric conversion using the light incident on the surface 20a of the semiconductor substrate 20. The light-shielding film 39 is composed of, for example, aluminum. The light-shielding film 39 is formed to cover the sensor array 11 and has a hole corresponding to the photoelectric conversion portion 21 and the hole enhancement layer 25.

[0032] The unit pixel 10 is electrically isolated from another unit pixel 10 via an element isolation region (not shown). The element isolation region may be provided as an isolation film (such as an oxide film due to LOCOS oxidation) or as a p-type impurity region having a higher concentration than the semiconductor substrate 20 and the charge blocking portion 26.

[0033] A specific layout configuration of the unit pixel 10 of the embodiment is described below with reference to FIG. Fig. 3 and Fig. 4 described.

[0034] The unit pixel 10 has, as in Fig. 3, the transfer gate electrode 30, the multiplication gate electrode 31, the ROG electrode 32, and the RG electrode 33 are arranged adjacent to each other in this order. The series transfer line 10a is formed to supply the gate electrodes 30, 31, 32, and 33 with the clock pulses (Vtr, VMG, VROG, and VRG). Specifically, in the series transfer line 10a, the transfer line 35 is connected to the transfer gate electrode 30 via a contact 35a. The multiplication gate line 36 is connected to the multiplication gate electrode 31 via a contact 36a. The ROG line 37 is connected to the ROG electrode 32 via a contact 37a. The RG line 38 is connected to the RG electrode 33 via a contact 38a.

[0035] A peripheral circuit including the source follower circuit 27 is formed above the semiconductor substrate 20 and connected to the FD section 23 via a contact 27a. The source follower circuit 27 is further connected to the row selection line 10b via a contact 27b. The source follower circuit 27 is also connected to the column signal line 10c and a power supply potential line 40 via a contact 27c and a contact 40a, respectively. According to the embodiment, the power supply potential line 40 is also connected to the RD section 24 via a contact 40b. The RD section 24 is in the Fig. 3 omitted.

[0036] According to the embodiment, the row transmission line 10a and the row selection line 10b are formed to extend in the direction of the adjacent arrangement of the gate electrodes 30, 31, 32, and 33 and connect to the vertical drive circuit 12. The column signal line 10c and the power supply potential line 40 extend in the direction perpendicular to the row transmission line 10a and the row selection line 10b and connect to the horizontal drive circuit 14.

[0037] According to the embodiment, the multiplication gate electrode 31 is as shown in Fig. 2, is formed to overlap only a part of the charge barrier portion 26. Specifically, the multiplication gate electrode 31 is narrower than the charge barrier portion 26 in the direction of the adjacent arrangement of the gate electrodes 30, 31, 32, and 33. The charge barrier portion 26 is exposed to the region between the multiplication gate electrode 31 and the transfer gate electrode 30 and the region between the multiplication gate electrode 31 and the ROG electrode 32 above the surface 20a of the semiconductor substrate 20.

[0038] Hereinafter, a method of driving the solid-state imaging device according to the embodiment will be described with reference to FIG. Fig. 4 to 11.

[0039] Fig. 4 shows an exemplary timing chart for driving the solid-state imaging device of the embodiment. The horizontal axis corresponds to time. The timing chart shows, in chronological order, states of clock pulses (Vtr, VMG, VROG, and VRG) and a clock pulse (SEL) applied to the row select line 10b to control an on / off operation of the transistor Tr2. That is, the timing chart shows that a high bias voltage or a low bias voltage is applied to each gate electrode at a certain timing. According to the embodiment, clock pulses Vtr, VROG, and VRG are applied to the gate electrodes 30, 32, and 33 to transfer electric charges, assumed to range between a high bias voltage of approximately 3.3 V and a low bias voltage of 0 V (ground electric potential).A clock pulse VMG is applied to the multiplication gate electrode 31 for multiplying electric charge, and is assumed to range between a high bias voltage of approximately 5 V and a low bias voltage of 0 V. A clock pulse SEL is assumed to range between a high bias voltage sufficient to turn on the transistor Tr2 of the source follower circuit 27 and a low bias voltage of 0 V. The following describes how the solid-state imaging device is driven at each time point.

[0040] At time t0, as in Fig. 4, clock pulses Vtr, VMG, VROG, and SEL are set to the low bias voltage (hereinafter referred to as low bias), and clock pulse VRG is set to the high bias voltage (hereinafter referred to as high bias). The photoelectric conversion section 21, the charge holding section 22, the FD section 23, and the RD section 24 cause the respective potentials in the direction of the adjacent arrangement of the gate electrodes to be shaped to reflect differences in the impurity concentrations of the sections. The charge holding section 22, as shown in Fig. 5, provides a higher potential (higher electric potential) than the photoelectric conversion section 21. The FD section 23 provides a higher potential than the charge holding section 22. The RD section 24 provides a potential approximately equal to the FD section 23. At time t0, the region immediately below the transfer gate electrode 30 and the ROG electrode 32 causes a potential approximately equal to the ground electric potential. Consequently, the photoelectric conversion section 21 and the charge holding section 22 are electrically separated. In contrast, a potential immediately below the RG electrode 33 is high because VRG is set to high bias. Accordingly, the FD section 23 and the RD section 24 are electrically connected to cause the same electric potential.An electric potential for the region immediately below the transfer gate electrode 30 approaches the ground electric potential, forming a quantum well whose base corresponds to the photoelectric conversion section 21. Consequently, the photoelectric conversion section 21 stores a signal charge 100 generated from photoelectric conversion of the incident light.

[0041] Vtr changes, as in Fig. 4, from low bias to high bias between t1 and t2. In this state, the region immediately below the transfer gate electrode 30 creates a high potential (high electric potential). The signal charge 100 stored in the photoelectric conversion section 21 is transferred to the charge holding section 22 due to edge E-field drift and self-induction drift.

[0042] At time t2, Vtr changes from high bias to low bias. This causes, as shown in Fig. 6, the potential immediately below the transfer gate electrode 30 becomes approximately the ground electrical potential. The photoelectric conversion section 21 and the charge holding section 22 form quantum wells that are electrically isolated from the other sections. The charge holding section 22 holds the signal charge 100 transferred from the photoelectric conversion section 21. The photoelectric conversion section 21 begins storing a new signal charge 200 due to photoelectric conversion of the incident light into an electrical charge. That is, a storage period described in the scope of the claims begins when Vtr changes to low.

[0043] The charge blocking portion 26 is exposed from the surface 20a of the semiconductor substrate 20 between the charge holding portion 22 and the insulating film 34. The potential in the thickness direction of the semiconductor substrate 20 is, as shown in Fig. 7, approximately equal to the ground electric potential corresponding to the insulating film 34 and the charge blocking portion 26. The potential corresponding to the charge holding portion 22 is higher (positive electric potential) than that of the charge blocking portion 26. The potential decreases (approaches the ground electric potential) with increasing distance from the surface 20a in the thickness direction of the semiconductor substrate 20. That is, the potential is formed into a quantum well whose base corresponds to the charge holding portion 22. The charge holding portion 22 also holds the signal charge 100 in the thickness direction of the semiconductor substrate 20. The embodiment uses n-type polycrystalline silicon for the multiplication gate electrode 31. An interface between the insulating film 34 and the multiplication gate electrode 31 causes a slightly positive electric potential.

[0044] A clock pulse VMG is generated as in Fig. 4, is applied between times t3 and t4 to contain multiple high bias voltages. The clock pulse comprises a single pulse that changes to a low-high-low bias. Referring now to the Fig. 7 to 9 describe in more detail how the solid-state imaging device is driven when this pulse is applied to the multiplication gate electrode 31.

[0045] When VMG is low, the charge holding section 22, as described above, holds the signal charge 100 ( Fig. 7).

[0046] When VMG subsequently changes from Low Bias to High Bias, the surface 20a of the semiconductor substrate 20 deepens, as shown in Fig. 8, the potential (to increase the electric potential). The charge barrier portion 26 can hold the potential lower than that of the charge holding portion 22. An electric field suitable for avalanche multiplication of electric charges is more likely to be available in a region toward the surface 20a than a potential barrier formed in the charge barrier portion 26.

[0047] If VMG, as in Fig. 9, the charge blocking section 26 allows the potential to be higher than that of the charge holding section 22. The signal charge 100 stored in the charge holding section 22 accelerates toward the surface 20a. This enables avalanche multiplication at the signal charge 100.

[0048] When VMG subsequently changes from high bias to low bias, the potential of the semiconductor substrate 20 in the thickness direction becomes similar to the transition state ( Fig. 8) is formed, in which VMG changes from low bias to high bias. At this time, the signal charge 100 is present toward the surface 20a rather than the potential barrier formed in the charge barrier section 26.

[0049] When VMG subsequently switches to low bias, the electric potential in the insulating film 34 and the charge-blocking section 26 approaches the ground electric potential and is formed into a quantum well whose base corresponds to the charge-holding section 22, as shown in the Fig. 7. The signal charge 100 is transferred from the region closer to the surface 20a than the charge barrier portion 26 to the charge carrier holding portion 22 due to the edge E-field drift and the self-induction drift.

[0050] A change of VMG from low bias to high bias enables, as described above, avalanche multiplication of the signal charge 100 stored in the charge holding section 22. A change of VMG from high bias to low bias enables the charge holding section 22 to hold the multiplied signal charge 100 in turn.

[0051] Between times t3 and t4, applying multiple high bias voltages as VMG can multiply an electric charge resulting from photoelectric conversion. This period (t4-t3) corresponds to a multiplication period described in the scope of the claims.

[0052] At time t5, VRG changes from high bias to low bias. This reduces, as shown in Fig. 10, the potential in the region immediately below the RG electrode 33 increases, allowing the electric potential to approach the ground electric potential. At time t5, VROG also goes low. The FD section 23 is electrically isolated from the charge-holding section 22 and the RD section 24. That is, the FD section 23 forms a quantum well.

[0053] A clock pulse SEL is applied to the row select line 10b and changes from low bias to high bias between times t5 and t6. This turns on the transistor Tr2 of the source follower circuit 27 and allows the current flowing through the column signal line 10c to change in accordance with a change in the gate voltage for the transistor Tr1 connected to the FD section 23.

[0054] Between times t6 and t7, VROG changes from low bias to high bias. This increases, as shown in Fig. 11, the potential immediately below the ROG electrode 32 transfers the signal charge 100 stored in the charge holding section 22 to the FD section 23. The FD section 23 stores the signal charge 100 to change the gate voltage for the transistor Tr1 connected to the source follower circuit 27. Specifically, the electric potential for the FD section 23, that is, the gate voltage for the transistor Tr1, decreases compared to that before the signal charge 100 is stored. Between times t6 and t7, SEL remains at high bias. A decrease in the electric potential for the FD section 23 decreases the current flowing through the column signal line 10c. A decrease in the current amount depends on the amount of the signal charge 100 transferred to the FD section 23.This shows that the amount of light incident on the pixel 10 is converted to a decrease in the amount of current flowing through the column signal line 10c.

[0055] At time t7, VROG changes to low. The FD section 23 is thus again formed into a quantum well. At time t7, the FD section 23 holds the signal charge 100.

[0056] Between times t7 and t8, SEL switches from high bias to low bias. This prevents a change in the electrical potential of the FD section 23 from affecting the column signal line 10c.

[0057] At time t8, RG changes from low bias to high bias. This drives the signal charge 100 held in the FD section 23 away to the RD section 24. The FD section 23 maintains the same electrical potential (VRD) as the RD section. The potential waveform in the semiconductor substrate 20 at time t8 is the same as that at time t0.

[0058] Repeating the operation from t0 to t8 can sequentially output a voltage signal corresponding to the light incident on the sensor array 11. The photoelectric conversion section 21 converts the light into an electric charge and stores it during a period in which Vtr changes from high bias to low bias at time t2, passes time t8, and changes from low bias to high bias at time t8. This period corresponds to a storage period described in the scope of the claims.

[0059] Working effects of the solid-state imaging device according to the embodiment will be described below.

[0060] According to the embodiment, the charge barrier portion 26 is formed on the surface 20a of the semiconductor substrate 20. The charge holding portion 22 is formed adjacent to and deeper than the charge barrier portion 26 from the surface 20a. The potential in the thickness direction of the semiconductor substrate 20 is formed into a quantum well when the clock pulse VMG, which is set to low bias, is applied to the multiplication gate electrode 31. The base of the quantum well corresponds to the charge holding portion 22. The barrier thereof corresponds to the charge barrier portion 26 and a region of the semiconductor substrate 20 deeper than the charge holding portion 22. When an electric charge is transferred to the charge holding portion 22, the charge holding portion 22 can store the electric charge without moving it toward the surface 20a of the semiconductor substrate 20.When VMG changes from low bias to high bias as described above, the charge barrier portion 26 can form an electric field suitable for avalanche multiplication on the electric charge, while the charge holding portion 22 holds the electric charge. Setting VMG to high bias can accelerate and multiply the electric charge in the thickness direction of the semiconductor substrate 20. That is, the same electrode can store and multiply multiple electric charges. This can reduce the number of gate electrodes compared to the technology described in Patent Document 1 that accelerates an electric charge for multiplication in a direction perpendicular to the thickness direction. More specifically, the surface 20 of the semiconductor substrate 20 can eliminate an area for regions required for an electric charge multiplication operation.This means that the unit pixel 10 can be reduced in size.

[0061] According to the embodiment, the same electrode, that is, the multiplication gate electrode 31, can store and multiply an electric charge. The embodiment can shorten the distance required for accelerating the electric charge compared to the configuration described in Patent Document 1 that accelerates and multiplies an electric charge between different electrodes. The embodiment can increase an electric field even when the electric charge is accelerated using the same electric potential difference. More specifically, it is possible to reduce a voltage (high bias for VMG) applied to the multiplication gate electrode 31 to detect an electric field required for avalanche multiplication compared to the configuration that accelerates and multiplies an electric charge between different electrodes.The configuration of the embodiment can set a high bias voltage for VMG to approximately 5 to 8 V. The embodiment can significantly reduce a voltage (15 V or higher) for the multiplication gate electrode as described in Patent Document 1.

[0062] According to the embodiment, the impurity concentration of the charge blocking portion 26 as described above is preferably determined to be greater than or equal to 1.5 × 10 17 cm -3 and less than or equal to 3.0 × 10 18 cm -3 The inventors have determined the concentration range using a computer simulation. In particular, the inventors have, as described in Fig. 12, a dependence of the E-field (electric field) intensity for the charge-barrier portion 26 of the semiconductor substrate 20 on the impurity concentration is simulated. The E-field intensity along the vertical axis describes a maximum electric field in the thickness direction of the semiconductor substrate 20 including the charge-barrier portion 26. The impurity concentration along the horizontal axis describes the impurity concentration of boron with which the charge-barrier portion 26 is doped. The E-field intensity increases with increasing impurity concentration. An electric field required for the avalanche multiplication of electric charges is greater than or equal to 2 × 10 5 V.cm -1 . An electric field of less than or equal to 1 × 10 8 V cm -1prevents tunnel breakdown from the charge blocking portion 26 to the insulating film 34 formed between the charge blocking portion 26 and the multiplication gate electrode 31. The electric field for the charge blocking portion 26 is preferably set to the above-mentioned range. This E-field range represents a preferred concentration range of greater than or equal to 1.5 × 10 17 cm -3 and less than or equal to 3.0 × 10 18 cm -3ready. The inventors carried out the simulation under the condition that an interface between the charge-holding portion 22 and the charge-barrier portion 26 is formed at a distance of approximately 0.2 µm from the surface 20a. When the charge-barrier portion 26 is strongly inverted, the maximum electric field is almost independent of the distance of the interface between the charge-holding portion 22 and the charge-barrier portion 26 from the surface 20a. The preferred concentration range (greater than or equal to 1.5 × 10 17 cm -3 and less than or equal to 3.0 × 10 18 cm -3 ) is not limited to 0.2 µm distance of the interface between the charge holding portion 22 and the charge blocking portion 26 from the surface 20a.

[0063] According to the embodiment, the photoelectric conversion portion 21 and the charge holding portion 22 are formed separately from each other. The transfer gate electrode 30 is formed via the insulating film 34 corresponding to a region between the photoelectric conversion portion 21 and the charge holding portion 22 formed on the surface 20a of the semiconductor substrate 20.

[0064] A voltage applied to the transfer gate electrode 30 can control the transfer of an electric charge from the photoelectric conversion section 21 to the charge holding section 22. Specifically, when Vtr is applied to the transfer gate electrode 30, setting Vtr to high bias can transfer an electric charge from the photoelectric conversion section 21 to the charge holding section 22. Setting Vtr to low bias can electrically disconnect the charge holding section 22 from the photoelectric conversion section 21. The charge holding section 22 and the FD section 23 are also electrically disconnected when a low bias voltage is applied to the ROG electrode 32 formed between the charge holding section 22 and the FD section 23.This configuration can temporarily store an electric charge photoelectrically converted by the photoelectric conversion section 21 and subsequently output the signal charge 100 as a voltage in a predetermined sequence. The plurality of pixels 10 can be exposed simultaneously to enable comprehensive exposure.

[0065] According to the embodiment, the charge blocking portion 26 is formed such that it only partially overlaps with the multiplication gate electrode 31. More specifically, the charge blocking portion 26 is exposed from the surface 20a of the semiconductor substrate 20, except for the part of the charge blocking portion 26 that overlaps with the multiplication gate electrode 31. That is, at least one edge 31a of the multiplication gate electrode 31 is, as shown in Fig. 13, positioned on the side of the charge blocking portion 26 rather than the boundary between the charge blocking portion 26 and the semiconductor substrate 20. This configuration can prevent the occurrence of a potential well near the interface between the charge blocking portion 26 and the semiconductor substrate 20 during a low bias to high bias transition state for the clock pulse VMG applied to the multiplication gate electrode 31 to multiply an electric charge.

[0066] The effect is described below with reference to the Fig. 13 and Fig. 14. In the Fig. 13 and Fig. In FIG. 14, to show potentials, a dash-double-dotted line A describes a potential for the charge-holding portion 22. A dash-dotted line B describes a potential for the charge-barrier portion 26 when VMG is set to low bias. A solid line C describes a potential for the charge-barrier portion 26 during a transient state in which VMG changes to high bias.

[0067] When a voltage is applied to the multiplication gate electrode 31, an electric field concentrates at the edge 31a of the multiplication gate electrode 31 in contact with the insulating film 34. The edge 31a is, for example, as shown in Fig. 14, flush with the interface between the charge barrier portion 26 and the semiconductor substrate 20. On the surface 20a, the potential for the semiconductor substrate 20 is lower than the charge barrier portion 26 (solid line C in the Fig. 14), while the impurity concentration of the semiconductor substrate 20 is lower than that of the charge blocking portion 26. This configuration creates a potential well at the interface between the charge blocking portion 26 and the semiconductor substrate 20. The electric charge stored in the charge holding portion 22 partially moves to the potential well created on the surface 20a of the semiconductor substrate 20 before VMG changes to high bias. Even when VMG subsequently changes to high bias, a potential difference between the potential well and the charge blocking portion 26 is smaller than a potential difference between the charge holding portion 22 and the charge blocking portion 26. The efficiency of multiplying the electric charge may decrease. In contrast, the multiplying gate electrode 31, as shown in Fig. 13, is formed such that its edge 31a is positioned toward the charge blocking portion 26, away from the interface between the charge blocking portion 26 and the semiconductor substrate 20. This configuration can prevent a potential dip from occurring.

[0068] The embodiment arranges the gate electrodes 30, 31, 32, and 33 in this order. According to this configuration, the multiplication gate electrode 31 is preferably narrower than the charge barrier portion 26 in the arrangement direction. That is, the charge barrier portion 26 is preferably exposed from a region between the multiplication gate electrode 31 and the transfer gate electrode 30 and from a region between the multiplication gate electrode 31 and the ROG electrode 32 on the surface 20a of the semiconductor substrate 20. This is because the region between the multiplication gate electrode 31 and the transfer gate electrode 30 has a lower impurity concentration than the above-described element isolation region (or does not ensure insulating properties equivalent to an insulating film), so that a potential well is easily caused.According to the embodiment, the multiplication gate electrode 31 is narrower in the arrangement direction than the charge blocking portion 26. This can prevent the occurrence of a potential well in the region between the multiplication gate electrode 31 and the transfer gate electrode 30 and the region between the multiplication gate electrode 31 and the ROG electrode 32. Consequently, an electric charge can be effectively multiplied.

[0069] According to the embodiment, during the multiplication period, a high bias voltage as VMG is applied to the multiplication gate electrode 31 twice or more. This can effectively multiply an electric charge compared to one cycle of high bias as VMG. The number of times a high bias voltage is applied can be set (configured). Designers can set (configure) any amount of electric charge multiplication.

[0070] The unit pixel 10 according to the embodiment includes the FD portion 23 and the RD portion 24 connected to the source follower circuit 27. The unit pixel 10 further includes the ROG electrode 32 and the RG electrode 33 for transferring electric charges. The solid-state imaging device according to the embodiment can form a CMOS image sensor as an area sensor with the unit pixels 10 arranged in a two-dimensional matrix. (Modification of the first embodiment)

[0071] According to the embodiment, the semiconductor substrate 20 has the region configured as a conductivity type p (p-) immediately below the transfer gate electrode 30. The region has, as shown in Fig. 15, preferably has a low-concentration region 50 configured as an N (n--) conductivity type with a lower impurity concentration than the photoelectric conversion portion 21. This configuration can deepen the potential for the region immediately below the transfer gate electrode 30 and increase a fringe E-field between the photoelectric conversion portion 21 and the charge holding portion 22. The amount of remaining electric charge to be transferred from the photoelectric conversion portion 21 to the charge holding portion 22 can be reduced. (Second embodiment)

[0072] The first embodiment provides the example of forming the photoelectric conversion section 21 and the charge holding section 22 separately. However, the present invention is not limited to this. The photoelectric conversion section 21 and the charge holding section 22 may be formed, for example, as shown in Fig. 16, may be formed adjacent to each other.

[0073] Such a configuration transfers an electric charge to the charge holding section 22 from the time the photoelectric conversion section 21 generates the electric charge in accordance with the photoelectric conversion. After a predetermined exposure time has elapsed, applying the clock pulse VMG to the multiplication gate electrode 31 multiplies the electric charge. The pixel 10 according to the second embodiment does not have the transfer gate electrode 30, unlike the first embodiment. The second embodiment can reduce the number of gate electrodes in the unit pixel 10 compared to the configuration of the first embodiment. The pixel size can be reduced.Since the transfer gate electrode 30 does not need to be provided, an area for providing the gate electrode of the unit pixel 10 can be reduced and an area for the photoelectric conversion section 21 can be increased to improve sensitivity. The configuration of a logic circuit including the TG 16 can be simplified because it is not necessary to control the clock pulse Vtr applied to the transfer gate electrode 30. (Third embodiment)

[0074] The first and second embodiments provide examples of independently forming the photoelectric conversion section 21 and the charge holding section 22. However, the present invention is not limited thereto. The photoelectric conversion section 21 and the charge holding section 22 may be formed, for example, as shown in Fig. 17, be formed in the same area. More specifically, the photoelectric conversion section 21 is also used as the charge holding section 22. This configuration forms the insulating film 34 and the multiplication gate electrode 31 above the photoelectric conversion section 21.

[0075] In such a configuration, the hole enhancement layer 25 corresponds to the charge blocking portion 26. The potential corresponding to the position related to the photoelectric conversion portion 21 in the thickness direction of the semiconductor substrate 20 is approximately equal to the potential corresponding to the position related to the charge holding portion 22 of the first embodiment. Applying the clock pulse VMG to the multiplication gate electrode 31 can multiply an electric charge.

[0076] Similar to the second embodiment, the pixel 10 according to the third embodiment does not have the transfer gate electrode 30. The third embodiment can reduce the number of gate electrodes in the unit pixel 10 compared to the configuration of the first embodiment. The photoelectric conversion section 21 is also used as the charge holding section 22. The pixel size can be further reduced compared to the second embodiment. An area for providing the gate electrode of the unit pixel 10 can be reduced, and an area for the photoelectric conversion section 21 can be increased to improve sensitivity. The configuration of a logic circuit including the TG 16 can be simplified because it is not necessary to control the clock pulse Vtr applied to the transfer gate electrode 30. (Fourth Embodiment)

[0077] The above-described embodiments provide examples of forming the multiplication gate electrode 31 on the surface 20a of the semiconductor substrate 20 via the insulating film 34. According to the fourth embodiment, the semiconductor substrate, as shown in Fig. 18, the multiplication gate electrode 31 is formed into a trench in the thickness direction of the semiconductor substrate 20.

[0078] According to the fourth embodiment, the photoelectric conversion section 21 and the charge holding section 22 are formed in the same area, similar to the third embodiment. The photoelectric conversion section 21 is also used as the charge holding section 22. That is, the hole accumulation layer 25 is also used as the charge blocking section 26. The multiplication gate electrode 31 of the embodiment is formed such that it is partially exposed from the surface 20a of the semiconductor substrate 20 and is contained in the hole accumulation layer 25. The insulating film 34 is arranged between the multiplication gate electrode 31 and the hole accumulation layer 25. The multiplication gate electrode 31 of the embodiment is, as shown in Fig. 19, formed to enclose the photoelectric conversion section 21 (charge holding section 22). That is, the multiplication gate electrode 31 extends, as shown in Fig. 20, perpendicular to the direction of arrangement of the photoelectric conversion section 21, the FD section 23 and the RD section 24. The multiplication gate electrode 31 arranges the photoelectric conversion section 21 (charge holding section 22) therebetween in the direction along the surface 20a. Fig. 18 shows a cross-sectional view along the line XVIII-XVIII in the Fig. 19. Fig. 20 shows a cross-sectional view along the line XX-XX in the Fig. 19.

[0079] The configuration of the embodiment arranges, as in Fig. 18, the multiplication gate electrode 31, the insulating film 34, the hole accumulation layer 25 (charge blocking portion 26), and the photoelectric conversion portion 21 (charge holding portion 22) are arranged in this order in the direction along the surface 20a. The potential in this arrangement direction is, as shown in Fig. 21, is shaped to form a potential well in the photoelectric conversion section 21 (charge holding section 22). The potential is shaped similarly to the potential corresponding to the position concerning the charge holding section 22 in the thickness direction of the semiconductor substrate 20 of the above-described embodiments. Applying the clock pulse VMG to the multiplication gate electrode 31 can multiply an electric charge. The potential shown in the Fig. 21 corresponds to the potential in the XXI direction in the Fig. 18.

[0080] The trench shape of the multiplication gate electrode 31 can prevent the multiplication gate electrode 31 and the insulating film 34 from interfering with the incident light. This can ensure the amount of light incident on the photoelectric conversion section 21 when the photoelectric conversion section 21 is also used as the charge holding section 22 according to the third and fourth embodiments.

[0081] The embodiment provides the example of forming the multiplication gate electrode 31 such that, as shown in Fig. 19, surrounds the photoelectric conversion section 21 (the charge holding section 22). The charge blocking section 26 and the insulating film 34 may also be disposed only between the trench-shaped multiplication gate electrode 31 and the charge holding section 22. However, increasing the area of the multiplication gate electrode 31 facing the charge holding section 22 can multiply electric charges even more effectively, as described in the embodiment. (Fifth embodiment)

[0082] The above-described embodiments use a low bias of 0 V for the clock pulse VMG applied to the multiplication gate electrode 31. The fifth embodiment uses the low bias below 0 V. An example of setting the low bias to -0.5 V is described below.

[0083] The example of setting the low bias to 0 V uses n-type polycrystalline silicon for the multiplication gate electrode 31, as described in the first embodiment. The interface between the insulating film 34 and the multiplication gate electrode 31 introduces a slightly positive electric potential in the potential including the charge blocking portion 26 and the charge holding portion 22 in the thickness direction of the semiconductor substrate 20. Suppose that VMG applied to the multiplication gate electrode 31 changes from high bias to low bias in the charge holding portion 22. The signal charge 100 moves to the surface 20a side of the semiconductor substrate 20, so that the signal charge 100 is multiplied. In this case, the signal charge 100 may not be partially transferred to the charge holding portion 22 and may remain near the surface 20a.In contrast, the embodiment sets Low Bias to a negative value, such as -0.5 V. The embodiment can, as in . Fig. 22, an electric potential for the interface between the insulating film 34 and the multiplication gate electrode 31 can be brought closer to the ground electric potential. Consequently, the embodiment can transfer the signal charge 100 to the charge holding portion 22 without leaving the signal charge 100 near the surface 20a. (Other embodiments)

[0084] Although the present invention has been described above in connection with its preferred embodiments, it should be understood that it is not limited thereto but may be modified in various ways within its scope.

[0085] The fourth embodiment shows an example in which the pixel 10 has the trench-shaped multiplication gate electrode 31, and the photoelectric conversion section 21 is also used as the charge holding section 22. However, the multiplication gate electrode 31 may be formed in a trench shape even when the photoelectric conversion section 21 and the charge holding section 22 are provided independently. Specifically, the trench-shaped multiplication gate electrode 31 may be formed to sandwich the charge holding section 22 in the direction perpendicular to the arrangement direction of the photoelectric conversion section 21, the charge holding section 22, the FD section 23, and the RD section 24, and in the direction along the surface 20a.

[0086] Alternatively, the multiplication gate electrode 31, as shown in Fig. 23, be embedded in the semiconductor substrate 20. According to this embodiment, the semiconductor substrate 20 is available, for example, as an SOI substrate. An insulating layer included in the SOI substrate can serve as the insulating film 34 described in the above-described embodiments when the insulating layer is provided between the multiplication gate electrode 31 and the charge holding portion 22. The charge blocking portion 26 is formed between the charge holding portion 22 and the insulating film 34. This embodiment can prevent an effect of surface-level noise because the charge blocking portion 26, the FD portion 23, or the RD portion 24 are not exposed from the surface 20a of the semiconductor substrate 20.An electric charge can be multiplied without providing the light-receiving surface with the multiplying gate electrode 31, as required in the third embodiment, even if the photoelectric conversion section 21 is also used as the charge holding section 22. An electric charge can be multiplied without providing a space for forming a trench, as required in the fourth embodiment. The pixel size can be further reduced compared with the third and fourth embodiments. The unit pixel 10 can reduce the area for disposing the gate electrodes and increase the area for the photoelectric conversion section 21 to improve sensitivity. Fig.23 shows the configuration for embedding the transfer gate electrode 30, the ROG electrode 32, and the RG electrode 33 in the semiconductor substrate 20. However, only the multiplication gate electrode 31 may be embedded.

[0087] The above-described embodiments show examples of arranging unit pixels 10 in a two-dimensional array to be used as an area sensor. It is also possible to arrange the unit pixels 10 one-dimensionally to use them as a line sensor.

[0088] The above-described embodiments show the examples of a CMOS image sensor using the unit pixel 10 having the FD portion 23 and the RD portion 24. An electric charge stored in the charge holding portion 22 is transferred to the FD portion 23 (which has the source follower circuit 27). The RD portion 24 resets an electric charge for the FD portion 23. However, the present invention is not limited to this. For example, an electric charge stored in the charge holding portion 22 may be transferred to a CCD image sensor having a vertical register including a charge-coupled device (CCD).

[0089] The above-described embodiments show examples of the semiconductor substrate 20 being placed at the ground electrical potential. However, the present invention is not limited thereto. It should be noted that the clock pulses (Vtr, VMG, VROG, and VRG) are applied to the transfer gate electrode 30, the multiplication gate electrode 31, the ROG electrode 32, and the RG electrode 33, and preferably use low bias voltages equal to or less than the electrical potential for the semiconductor substrate 20.

Claims

[1] A solid-state imaging device comprising a plurality of pixels (10), each pixel (10) comprising: - a photoelectric conversion section (21) of a second conductivity type arranged in a surface layer portion of a surface of a semiconductor substrate (20) of a first conductivity type and converting light incident on the surface into an electric charge; - a charge holding section (22) of a second conductivity type which stores the electric charge generated in the photoelectric conversion section (21) and is arranged in the semiconductor substrate (20); - a multiplication gate electrode (31) capacitively coupled to the charge holding section (22) and disposed on the semiconductor substrate (20) via an insulating film (34); and - a cargo barrier section (26) which: - is arranged between the charge holding section (22) and the insulating film (34) at a position where the multiplication gate electrode (31) and the charge holding section (22) are capacitively coupled, - has a first conductivity type with a higher impurity concentration than the semiconductor substrate (20), - causes the charge holding section (22) to hold the electric charge until an electric field in a depth direction of the semiconductor substrate (20) reaches an electric field capable of avalanche multiplication when a voltage is applied to the multiplication gate electrode (31), and - the avalanche multiplication of the electric charge in the depth direction is generated when a predetermined voltage is applied to the multiplication gate electrode (31). [2] A solid-state imaging device according to claim 1, wherein - at least a part of the multiplication gate electrode (31) is arranged over the insulating film (34) above the surface of the semiconductor substrate (20) to overlap with the charge holding portion (22) in a thickness direction perpendicular to the surface; - the charge barrier portion (26) is arranged in a surface layer portion of the surface of the semiconductor substrate (20); and - at least a part of the charge barrier section (26) overlaps with the multiplication gate electrode (31) in a direction perpendicular to the surface. [3] A solid-state imaging device according to claim 1, wherein - the multiplication gate electrode (31) is arranged in a trench arranged on the surface of the semiconductor substrate (20), in a thickness direction perpendicular to the surface; and - at least a part of the charge barrier section (26) overlaps with the multiplication gate electrode (31) in a horizontal direction parallel to the surface. [4] A solid-state imaging device according to claim 2 or 3, wherein - the photoelectric conversion section (21) and the charge holding section (22) are separated from each other; and - each pixel (10) further comprises a transfer gate electrode (30) arranged above the surface of the semiconductor substrate (20) via the insulating film (34) between the photoelectric conversion section (21) and the charge holding section (22). [5] A solid-state imaging device according to claim 4, wherein each pixel (10) further comprises a low-concentration region (50) of a second conductivity type having a concentration lower than the photoelectric conversion section (21) and the charge holding section (22) and being arranged at a surface layer portion of the semiconductor substrate (20) between the photoelectric conversion section (21) and the charge holding section (22). [6] A solid-state imaging device according to claim 2 or 3, wherein the photoelectric conversion section (21) and the charge holding section (22) are arranged adjacent to each other. [7] A solid-state imaging device according to any one of claims 4 to 6, wherein the charge holding section (22) has a higher impurity concentration than the photoelectric conversion section (21). [8] A solid-state imaging device according to claim 2 or 3, wherein - the charge holding section (22) and the photoelectric conversion section (21) are integrated; and - the photoelectric conversion section (21) is formed integrally with the charge holding section (22). [9] A solid-state imaging device according to any one of claims 1 to 8, wherein only a part of the charge barrier portion (26) overlaps with the multiplication gate electrode (31). [10] A solid-state imaging device according to any one of claims 1 to 9, wherein - each pixel (10) further comprises a floating diffusion portion (23) of the second conductivity type, a reset drain portion (24) of the second conductivity type, an ROG electrode (32) and a reset gate electrode (33); - the floating diffusion section (23) is arranged in a surface layer section of the surface of the semiconductor substrate (20); - the floating diffusion section (23) is separated from the photoelectric conversion section (21), the charge holding section (22) and the charge blocking section (26); - the floating diffusion section (23) is connected to a source follower circuit (27) which converts an electrical charge into a voltage; - the reset drain portion (24) is arranged in a surface layer portion of the surface of the semiconductor substrate (20); - the reset drain section (24) is separated from the photoelectric conversion section (21), the charge holding section (22), the charge blocking section (26) and the floating diffusion section (23); - the ROG electrode (32) is arranged above the surface of the semiconductor substrate (20) via the insulating film (34) between the charge barrier section (26) and the floating diffusion section (23); and - the reset gate electrode (33) is arranged above the surface of the semiconductor substrate (20) via the insulating film (34) between the floating diffusion section (23) and the reset drain section (24). [11] A solid-state imaging device according to any one of claims 1 to 10, wherein the charge barrier portion (26) has an impurity concentration of greater than or equal to 1.5 × 10 17 cm -3 and less than or equal to 3.0 × 10 18 cm -3 has. [12] A solid-state imaging device according to any one of claims 1 to 11, wherein the plurality of pixels (10) are arranged in a two-dimensional matrix. [13] A method for driving the solid-state imaging device according to any one of claims 1 to 12, comprising the steps of: - applying a clock pulse with a high bias voltage and a low bias voltage to the multiplication gate electrode (31); - applying the low bias voltage to the multiplication gate electrode (31) during a storage period to store an electric charge in the charge holding section (22); and - applying at least the high bias voltage to the multiplication gate electrode (31) during a multiplication period to multiply the electric charge stored in the charge holding section (22). [14] A method of driving the solid-state imaging device according to claim 13, further comprising the step of: - applying the high bias voltage at least twice to the multiplication gate electrode (31) during the multiplication period. [15] A method of driving the solid-state imaging device according to claim 13 or 14, wherein the low bias voltage is lower than an electric potential of the semiconductor substrate (20).

Images