Method for constructing a power semiconductor device

Abstract

Method for manufacturing a power semiconductor device comprising the following steps: - Providing a wafer (1) of a first conductivity type, wherein the wafer (1) has a first main surface (11) and a second main surface (15) opposite the first main surface (11), and a portion of this wafer (1) forms a drift layer (10) with an unchanged doping concentration, - Application to the second main surface (15) of at least one dopant of the first conductivity type to form a layer (2') of the first conductivity type, or a dopant of a second conductivity type that differs from the first conductivity type to form a layer (2) of the second conductivity type, - subsequent deposition of a titanium deposition layer (3) on the second main surface (15), - Laser annealing of the titanium deposition layer (3) at a temperature of more than 1200 °C, such that an intermetallic composite layer (35) is simultaneously formed on the interface between the titanium deposition layer (3) and the wafer (1) and at least one dopant is diffused into the wafer (1), wherein by applying such a temperature the titanium deposition layer (3) acts as a light absorber, so that an increased temperature is achieved in the wafer (1) below the titanium deposition layer (3), - Creating a first metal electrode layer (4) on the second side (15), - Removal of the intermetallic composite layer (35) and the titanium deposition layer (3) prior to the formation of the first metal electrode layer (4).

Description

Field of expertise

[0001] The invention relates to the field of power electronics and in particular to a method for manufacturing a power semiconductor device and a power semiconductor device per se. Background of the inventionMethods of carrying out the invention

[0002] A state-of-the-art punch-through insulated-gate bipolar transistor (IGBT) with a four-layer structure includes a collector electrode on a collector side and an emitter electrode on an emitter side opposite the collector side. An (n-) doped drift layer is located between the emitter electrode and the collector electrode. A p-doped base layer is disposed on the emitter side, surrounding an n-doped source region. This source region and the base layer are in electrical contact with the emitter electrode. A gate electrode is also disposed on the emitter side (either a planar gate or a trench gate), which is electrically isolated from all layers by an insulating layer.

[0003] An n-doped buffer layer is located on the collector side between the base layer and the collector electrode. The buffer layer stops an electric field during device operation. A p-doped collector layer is arranged on the buffer layer toward the collector electrode.

[0004] Such devices were previously fabricated by epitaxial growth of the buffer layer.

[0005] Such devices were previously developed as non-punch-through (NPT) devices, in which there is no buffer layer and the p-type collector layer is directly adjacent to the (n-)doped drift layer. Such devices offer several advantages in terms of switching capability and current sharing of such chips, which enabled the use of IGBTs in high-current modules.

[0006] Nevertheless, such devices require a thick wafer structure due to the need to contain the electric field within the drift layer in the NPT concept. Therefore, such NPT devices suffer higher static and dynamic losses.

[0007] To improve the electrical properties of IGBTs, soft-punch-through (SPT) devices were introduced. These devices have thinner, but highly doped buffer layers, resulting in thinner devices than NPT devices, but without the disadvantages known from previous PT devices. Such devices resulted in improvements in losses. Nevertheless, STP concepts require complex processes when the wafer is thin, which is particularly the case with low-voltage IGBTs for forming the backside layers, including the collector and buffer layers. One such method is known, for example, from DE 198 29 614 A1. It describes a manufacturing method for a soft-punch-through insulated-gate bipolar transistor (IGBT) element 180 ( Fig. 1c), based on a PT type, which makes it possible to manufacture relatively thin semiconductor elements without having to use the epitaxial growth process. For this purpose, a buffer layer 13 with a greater thickness than electrically necessary is introduced into a lightly doped wafer, followed by process steps for forming the layers on the emitter-side surface (first main side 11) of the semiconductor element (such as the base layer 5, source regions 6, gate electrode 7' with its electrically conductive layer 75, and insulating layers 72, 74). Afterward, the thickness of the buffer layer on the second main side 15 is reduced by grinding or polishing to the electrically required size (dotted line in Fig. 1a). This makes it possible to perform the emitter-side process steps on a relatively thick wafer, reducing the risk of breakage. Nevertheless, due to the subsequent thinning of the wafer, a semiconductor element with the desired small thickness can be manufactured. The minimum thickness of the finalized semiconductor element is no longer limited by a minimum thickness that can be achieved for its starting material. A p-dopant is then implanted and diffused to form a collector layer 2 ( Fig. 1b) and then a first electrode layer 4 is created on the second main layer 15 ( Fig. 1c).

[0008] US 6,482,681 B1 describes another punch-through (PT) bipolar transistor (IGBT). The device is manufactured using an (n-) doped wafer on which all processes for layer formation on the emitter side, also called the cathode side, are completed—i.e., all connections and metallizations on the emitter side are fabricated. The wafer is then thinned, and hydrogen ions are implanted on the collector side, also called the anode side, of the wafer to form an n+-doped buffer layer. A p-dopant is then implanted to form a collector layer. The wafer is subsequently annealed at 300 to 400°C to activate the hydrogen ions without damaging the structure on the emitter side.Thus, in the case of blocking, the buffer layer abruptly slows down the electric field before it reaches the collector layer and thus keeps the electric field away from the collector layer, since a semiconductor element can be destroyed if the electric field reaches the collector layer.

[0009] After thinning the device, a p-type dopant is implanted to form the p-type collector layer and activated by laser annealing, followed by multiple metal deposition steps. Finally, a sintering process below 400°C is performed in a conventional furnace to activate the anode and form good contact with the collector electrode. This process is limited to achieve good control of the p-type anode collector activation. However, due to the limitation of the collector-side processes to temperatures below 400°C, the ability to control the anode (or cathode) activation levels and form good Si / metal contacts is also severely limited. Furthermore, device optimization for improved static and dynamic performance is required, with several limiting process options.

[0010] By using high-energy laser annealing (e.g. over 1 J / cm2 ) After implantation, higher activation levels are possible. However, this only affects the Si wafer surface and does not improve metal contact, as metallization is performed in a later step. The metallization process and sintering are still required as a separate step.

[0011] Similar challenges arise when designing fast-recovery diodes based on thin wafer processing. In all these cases, the use of an optimized laser annealing technology for creating the p-collector layer is essential.

[0012] US 2008 / 0 076 238 A1 describes a method for creating an IGBT in which phosphorus ions are implanted onto a wafer and laser-annealed to create a buffer layer. Subsequently, boron ions are implanted and laser-annealed to form a collector layer. A nickel film is then deposited onto the collector layer and laser-annealed. All laser-annealing steps are performed separately.

[0013] EP 0 330 122 A1 describes an IGBT with an implanted p-collector layer annealed at a temperature below 600 °C, onto which a platinum layer is subsequently sputtered, which is then heated to 450 to 470 °C to form a Pt-Si composite layer. A multilayer collector electrode is then fabricated from a titanium layer, a nickel layer, and a silver layer.

[0014] US 2008 / 0 102 576 A1 discloses a p-type collector region of an IGBT and an n-type cathode region of a freewheeling diode alternately formed on a second main surface of a semiconductor substrate. A back electrode is formed on the second main surface to contact both the p-type collector region and the n-type cathode region, and includes a titanium layer, a nickel layer, and a gold layer sequentially stacked on the second main surface. In this way, a semiconductor device capable of achieving a satisfactory ON voltage during both conduction of an insulated-gate field-effect transistor and conduction of the freewheeling diode can be obtained, as well as a manufacturing method thereof.

[0015] US 5,623,157 discloses an electronic circuit formed on an insulating substrate and comprising thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layers is less than 1500 Å, e.g., between 100 and 750 Å. A first layer consisting primarily of titanium and nitrogen is formed on the semiconductor layer. A second layer of aluminum is formed on the first layer. The first and second layers are patterned into conductive interconnects. The bottom surface of the second layer is in substantially complete, close contact with the first layer. The conductive traces have good contacts with the semiconductor layer.

[0016] US 6,303,476 B1 describes a method, apparatus, and system for controlling the amount of heat transferred to a process area of ​​a workpiece by exposure to laser radiation, using a thermally induced reflectivity switch layer. The device is a film stack with an absorber layer applied to the workpiece, e.g., a silicon wafer. Part of the absorber layer covers the process area. The absorber layer absorbs the laser radiation and converts the absorbed radiation into heat. A reflective switch layer is applied to the absorber layer. The reflective switch layer can consist of one or more thin-film layers and preferably comprises a thermal insulation layer and a transition layer.The reflectivity of the reflective switch layer changes from a low-reflectivity state to a high-reflectivity state at a critical temperature to limit the amount of radiation absorbed by the absorber layer by reflecting the incident radiation. This, in turn, limits the amount of heat transferred from the absorber layer to the process area.

[0017] US Pat. No. 5,236,865 A describes a method for producing silicides while simultaneously activating the underlying active regions of the silicon substrate, eliminating the need for separate annealing of the active region after ion implantation. The energy required for such simultaneous processing is provided by laser irradiation of the surface of a wafer after it has been coated with a layer of the desired metal in the silicide. Disclosure of the invention

[0018] It is an object of the invention to provide a method for manufacturing a power semiconductor device that provides better contact of the wafer to the electrode with improved processing capabilities and better device performance than current methods.

[0019] This object is achieved by providing a method for manufacturing a power device according to the invention, the device comprising: - providing a wafer of a first conductivity type, the wafer having a first main side and a second main side opposite the first main side, - applying a dopant of a second conductivity type different from the first conductivity type or of the first conductivity type to the second main side to form a layer of the first or second conductivity type, respectively, - the subsequent deposition of a titanium deposition layer, the titanium having a melting point of 1660 °C, i.e. above that of silicon (1410 °C), on the second main side, - annealing the titanium deposition layer so that an intermetallic composite layer is formed at the interface between the titanium deposition layer and the wafer and the dopant is diffused into the wafer, - forming a first metal electrode layer on the second side.

[0020] The invention can be applied, for example, to thin wafers with a maximum thickness of 200 µm, as these are used for low-voltage IGBTs (voltages up to 2000 V) or for low-voltage diodes (also up to 2000 V). Process capability can be improved by the manufacturing method of the invention, and device performance can also be improved compared to previous SPT IGBTs and diodes. By using the method of the invention, the activation of the collector dopant (such as boron or aluminum as p-dopants; or phosphorus or arsenic as n-dopants) can be greatly improved, which is particularly important when processing thin wafers and wafers with large diameters, such as 200 mm or larger diameters.

[0021] The titanium metal deposition layer has a melting point in the high temperature range, as high energies can be produced on the wafer surface depending on the duration and energy of the laser pulse. Even short but high-energy laser pulses generate temperatures well over 1000 °C. For example, laser pulses with an energy of > 1 J / cm 2 used. For example, a very short (e.g. 200 ns) and high-energy (2 J / cm 2) Laser pulses can produce surface temperatures exceeding 1300 °C. For this reason, titanium is used, which has a melting point of 1660 °C, which is thus higher than the temperature produced by the laser, e.g., higher than 1200 °C or even higher than 1300 °C. Titanium is deposited as a thin layer after the dopant of the first and second conductivity types has been applied to form a layer of the first or second conductivity type, and then annealed. Titanium acts as a light absorber in this step. The resulting effect is the increased temperature in the wafer material (e.g., silicon) beneath the titanium deposition layer, which leads to greater activation of the dopant, since more energy is absorbed by the titanium deposition layer for the same laser beam energy density. The thermal conductivity of titanium is low (21.9 W m -1 ·K -1), so there isn't a large heat spread and more heat is used for the underlying wafer material (e.g., silicon). The titanium silicide is generated along with the activation of the dopant. Since it improves contact resistance, it may be advantageous to keep the titanium deposition layer as part of the metal electrode layer.

[0022] A major advantage is the fact that the titanium deposition layer, with a melting point above 1660 °C, absorbs the laser beam (heat) much more strongly than the wafer surface. Therefore, better activation of the dopant is achieved and / or lower laser energies can be applied, as shown in Fig. 11 shown.

[0023] Titanium is capable of providing silicide layers with good contact to a Si wafer. These layers can also be used in addition to backside structures, as required for field charge extraction (FCE) concept diodes or reverse conducting IGBTs that comprise alternating p- and n-type regions on the collector side.

[0024] In the case of the method of the invention, which includes a dopant implantation step to form a layer of the first or second conductivity type, the implantation step and the metal deposition step are performed in two different tools. If deposition is used as the method for applying the dopant, the metal deposition layer can be created in the same device.

[0025] The laser annealing step is performed on the wafer surface (p- or n-type layer) after a metal deposition layer has been deposited on the wafer surface. Thus, a good activation level is achieved with lower laser energies (which is better in terms of process capability and surface damage after laser annealing), and a good contact is formed (through the intermetal bonding layer and / or a sintering step). Fig. Figure 11 shows the doping concentration that can be achieved by sintering according to the prior art, with a prior art laser annealing, and the improvement by adding a Ti deposition layer according to the invention before the laser annealing step. The doping concentration increases from approximately 5 * 10 16 cm -3 to 1 * 10 18 cm -3 for state-of-the-art laser tempering and further to 8 * 10 19 cm -3for a laser annealing according to the invention and a wafer with a Ti deposition layer.

[0026] After the laser annealing step, the final solder metals, such as Ti, Ni, or Ag, can be deposited with a short annealing step. For example, the same metal can be used as a metal deposition layer and as a first metal electrode layer.

[0027] For the method of applying the dopant by deposition, such as evaporation or sputtering, to form the layer of the first or second conductivity type, a single tool can be used for the deposition of the dopant and the deposition of the metal deposition layer. Short description of the drawings

[0028] The subject matter of the invention is described in more detail in the following text, with reference to the accompanying drawings, in which: Fig. 1 shows a method of manufacturing a power semiconductor device according to the prior art; Fig. 2 shows a method according to the invention for manufacturing a power semiconductor device; Fig. 3 an alternative for step a) from Fig. 2 shows; Fig. 4 an alternative for step b) from Fig. 2 shows; Fig. 5 an alternative for step d) from Fig. 2 shows; Fig. 6 an alternative for step d) from Fig. 2 shows; Fig. 7-9 show various IGBTs according to the invention; Fig. 10 shows a diode according to the invention; and Fig. 11 shows a graph illustrating the doping concentration as a function of the depth in the wafer achieved with conventional methods and the method of the invention.

[0029] The reference symbols used in the figures and their meanings are summarized in the list of reference symbols. In general, identical or identically functioning parts are given the same reference symbols. The described embodiments are intended as examples and are not intended to limit the invention. Methods of carrying out the invention

[0030] To manufacture an insulated gate bipolar transistor according to the invention, the following steps are carried out.

[0031] An (n-) doped wafer 1 having a first and a second main side 11, 15, which are opposite to the first main side 11, is provided. The wafer 1 can be manufactured on the basis of a silicon wafer or a wafer with a wide band gap. Such a part of the wafer with an unchanged doping concentration forms a drift layer 10 in the finalized device. For example, wafer 1 has a constantly low doping concentration. Here, the essentially constant doping concentration of the wafer (wherein the part of the wafer with an unchanged doping concentration forms a drift layer 10 in the finalized device) means that the doping concentration is essentially homogeneous throughout the wafer 1 (drift layer 10), but without excluding possible fluctuations in the doping concentration within the wafer 1 (drift layer 10) on the order of a factor of one to five, e.g.due to a process used to manufacture the wafer.

[0032] On the second main side 15, an n-dopant is applied and diffused into the wafer 1 to form the buffer layer 13.

[0033] Alternatively, the following steps are performed directly on an n-doped wafer without forming a buffer layer thereon, i.e., the step of forming a buffer layer is omitted, and a non-punch-through device is fabricated. In this case, the collector layer 2, 2' is formed on the second side 15, as described below, directly adjacent to the n-doped drift layer 10. Subsequently, the following steps are carried out to create layers on the first main side 11. To form a base layer 5, p-dopants are applied to the first main side 11 and diffused into the wafer 1.

[0034] Then, n-type dopants for creating the source regions 6 are implanted and annealed on the first main side 11.

[0035] Subsequently, the wafer is thinned, for example, on the second main side to leave a final portion of the buffer layer if the device includes a buffer layer, or to reduce the thickness of the drift layer to the electrically desired thickness.

[0036] These steps are merely examples for the production of the layers on the first main side 11 of the wafer and the buffer layer 13. Any other sequence (e.g., producing a portion of the layers on the first main side 11 at a later time than previously described) is intended to be covered by the invention. For example, the first and second metal electrode layers 4, 8 can be produced simultaneously.

[0037] The method of the invention disclosed below begins with providing a wafer comprising a first main side 11 and a second main side 15 opposite to the first main side 11, the wafer having an n-doped layer (which later forms the buffer layer) on the second main side 15 ( Fig. 2a). Alternatively, the method according to the invention may begin with the provision of an (n-) doped wafer which does not have a differently doped layer on the second main side 15, as in Fig. 3. In the Fig. Figures 2 to 6 show only the layers on the second main page. The layers on the first main page 11 are not part of these figures for clarity.

[0038] To create the layers on the second main page 15, the following steps are carried out: - applying a dopant of a second conductivity type different from the first conductivity type or of the first conductivity type to the second main layer 15 to form a layer 2 of the second or first conductivity type ( Fig. 2b), - the subsequent deposition of a metal deposition layer 3, wherein the metal is titanium, on the second main side 15 ( Fig. 2c), - annealing the titanium deposition layer 3 so that an intermetallic composite layer 35 is formed on the interface between the metal deposition layer 3 and the wafer 1 and the dopant diffuses into the wafer 1, - producing a first metal electrode layer 4 on the second side 15.

[0039] The dopant for creating the n- or p-doped layer 2, 2' can be applied by deposition or implantation of the dopant onto the second main side 15. Depending on the type of semiconductor, the dopant is n- or p-type. For example, if the semiconductor is a diode, the dopant can be n-type; if the semiconductor is an IGBT, a p-type dopant is used. Pre-doped amorphous silicon (pre-doped with either n- or p-type ions) can also be used as a dopant.

[0040] If the semiconductor is a reverse conducting device, an n-type dopant and another p-type dopant are used to create n- and p-layers alternating in a plane parallel to the second main surface ( Fig. 4).

[0041] Titanium, with its melting point of 1660 °C, which is higher than that of silicon, is used to deposit the metal deposition layer. The thickness of the titanium deposition layer is, for example, between 5 and 200 nm, in particular between 20 and 200 nm, in particular between 10 and 100 nm, in particular between 10 and 50 nm, or in particular between 50 and 100 nm. The annealing of the titanium deposition layer 3 is carried out, for example, by laser annealing.

[0042] The titanium deposition layer 3, which acts as a light absorption layer, and the dopant are then annealed by laser annealing. This is done, for example, using an energy of 1 - 1.5 J / cm 2 , especially 1 J / cm 2, carried out. Through this laser annealing, if the wafer is made of silicon, the titanium forms a silicide layer (intermetallic composite layer) together with the silicon. The intermetallic composite layer 35 formed at the interface between the titanium deposition layer 3 and the wafer 1 means that the titanium diffuses from the titanium deposition layer 3 into the wafer 1 and the silicon into the titanium layer, i.e., the intermetallic composite layer 35 is arranged below the titanium deposition layer 3 and from the second main side 15 of the wafer to a depth. The thickness of the intermetallic composite layer is the depth to which the layer 35 extends into the wafer from the wafer surface (second main side 15). It corresponds, for example, to the thickness of the titanium deposition layer up to four times the thickness of the titanium deposition layer, for example up to three times the thickness.

[0043] The intermetallic composite layer is a layer in which the metal from the metal deposition layer, i.e., titanium, diffuses into the wafer (solid-state diffusion), and the metal forms a bond with the wafer material. In the case of a silicon wafer, silicides are formed. For example, silicon forms TiSi2 with titanium. The term "intermetallic" is used in this patent application to refer to the silicide layer created by the diffusion of the metal (i.e., titanium) from the titanium deposition layer into the silicon wafer. It can also be referred to as a titanium-wafer composite layer or simply a titanium-wafer layer.

[0044] Before producing the first metal electrode layer 4, the intermetal composite layer 35 will be removed together with the titanium deposition layer 3 ( Fig. 6). Alternatively, for example, the intermetallic composite layer 35 may be retained, in which case the titanium deposition layer 3 may also be retained ( Fig. 2d), the IGBT 110 has these layers (e.g. in Fig. 8) or before the first metal electrode layer 4 is formed ( Fig. 5; IGBT with intermetal layer 35 but without titanium deposition layer e.g. Fig. 7 shows IGBT 100, Fig. 9 shows IGBT 120 or Fig. 10 shows a diode 150 of the invention).

[0045] For example, in a case where the same metal is used for the titanium deposition layer 3 and the metal electrode layer 4, at least on the side of the metal electrode layer facing the titanium deposition layer 3, the manufacturing step of removing the titanium deposition layer 3 can be avoided. However, in cases where different metals are used for the titanium deposition layer 3 and the first metal electrode layer 4, the deposition layer 3 can also be retained, so that the titanium deposition layer 3, which is electrically conductive, forms part of the first metal electrode layer 4. Thus, the first metal electrode layer 4 forms a sandwich-like layer.

[0046] After producing the first metal electrode layer 4, the layer 4 can be sintered to further improve reliable contact of the first metal electrode layer 4 with the wafer 1.

[0047] In Fig. 7 shows a power semiconductor device of the invention in the form of an insulated gate bipolar transistor 100, which comprises a second metal electrode layer 4 in the form of an emitter electrode on the first main side 11 and a first metal electrode layer 4 in the form of a collector electrode on the second main side 15, wherein the second main side 15 is arranged opposite the first main side 11. An (n-) doped drift layer 10 is arranged between the first main side 11 and the second main side 15. A p-doped base layer 5 is arranged between the drift layer 10 and the first main side 11. The base layer 5 contacts the second metal electrode layer 8. At least one n-doped source region 6 is arranged on the first main side 11. The device comprises a gate electrode, either in the form of a trench gate electrode 7 ( Fig. 7, Fig. 8) or a planar gate electrode 7' ( Fig. 9).

[0048] Such a trench gate electrode 7 comprises an electrically conductive layer 75 and a first electrically insulating layer 72, which surrounds the electrically conductive layer 75 and thereby separates it from the drift layer 10, the base layer 5, and the at least one source region 6. Typically, a second insulating layer 74 is arranged between the electrically conductive layer 75 and the second metal electrode layer 8. The trench gate electrode 7 is arranged laterally to the base layer 5 in a plane parallel to the first main side 11.

[0049] An IGBT 120 with planar gate electrode 7' is in Fig. 9. The planar gate electrode 7' also includes an electrically conductive layer 75, but in this case, the gate electrode 7' is arranged on the wafer 1 on the first main side 11. A first electrically insulating layer 72 is arranged between the electrically conductive layer 75 and the wafer 1, such that it separates the electrically conductive layer 75 from the drift layer 10, the base layer 5, and the at least one source region 6. Typically, the second insulating layer 74 is arranged between the electrically conductive layer 75 and the second metal electrode layer 8.

[0050] The source region 6 is embedded in the base layer 5 so that the source region 6 contacts the second metal electrode layer 8.

[0051] A p-doped layer 2 in the form of a collector layer is arranged on the second main side 15. An n-doped buffer layer 13 with a higher doping concentration than the drift layer 10 can be arranged between the drift layer 10 and the collector layer, generally between the drift layer 10 and the second main layer 15, with the buffer layer adjacent to the drift layer 10.

[0052] The doping concentration of the source region 6 is higher than that of the base layer 5. Exemplary doping concentrations for the source region 6 are more than 1 * 10 18 cm -3 and less than 1 * 10 21 cm -3 , for example between 1 * 10 19 cm -3 and 1 * 10 20 cm -3 .

[0053] The doping concentration of the base layer 5 and the drift layer 10 can be freely selected based on the application requirements and the doping concentration rules listed above. For devices above 600 V, the doping concentration of the drift layer is typically less than 5 * 10 14 cm -3 . The base layer 5 has, for example, a doping concentration of less than 5 * 10 18 cm -3 on.

[0054] The structures described above form an active cell. The IGBT device may comprise only one active cell, as described above, but it is also possible for the device to comprise at least two or more such active cells, i.e., the active cells may be repeatedly arranged in a wafer.

[0055] In Fig. 10 shows a diode 150 of the invention, which comprises a p-doped anode layer 55 on the first main side. On the second main side 15, an n-doped layer 2' was applied, on which the metal deposition layer 3 was deposited during the manufacture of a diode. Depending on the application, the Fig. 10 present buffer layer 13 between drift layer 10 and first layer 2' can also be omitted. In Fig. 10, the device includes the intermetallic composite layer 35, but as previously noted, this layer may also have been removed or the titanium deposition layer 3 may have been retained.

[0056] In another embodiment, the conductivity types are swapped, ie all layers of the first conductivity type are p-type (e.g., wafer 1) and all layers of the second conductivity type are n-type (e.g., layer 2 if layer 2 consists of a different conductivity type than wafer 1).

[0057] It is noted that the term "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude the plural. Also, elements described in connection with different embodiments may be combined. It is also noted that the reference signs used in the claims are not intended to limit the scope of the claims. Reference list 1 wafer 10 Drift layer 11 first main layer 13 Buffer layer 15 second main layer 100, 110, 120 IGBT according to the invention 150 Diode according to the invention 2, 2' layer of the first or second conductivity type 3 Titanium deposition layer 35 Intermetal composite layer 4 first metal electrode layer 5 Base layer 55 Anode layer 6 Source region 7, 7' gate electrode 72 first insulation layer 74 second insulation layer 75 electrically conductive layer 8 second metal electrode layer

Claims

[1] A method for producing a power semiconductor device, comprising the following steps: - Providing a wafer (1) of a first conductivity type, wherein the wafer (1) has a first main side (11) and a second main side (15) opposite the first main side (11), and a part of this wafer (1) with an unchanged doping concentration forms a drift layer (10), - applying to the second main side (15) at least one dopant of the first conductivity type to form a layer (2') of the first conductivity type, or a dopant of a second conductivity type different from the first conductivity type to form a layer (2) of the second conductivity type, - subsequent deposition of a titanium deposition layer (3) on the second main side (15), - laser annealing the titanium deposition layer (3) at a temperature of more than 1200 °C, so that at the same time an intermetallic composite layer (35) is formed on the interface between the titanium deposition layer (3) and the wafer (1) and the at least one dopant is diffused into the wafer (1), wherein by applying such a temperature the titanium deposition layer (3) acts as a light absorber, so that an increased temperature is achieved in the wafer (1) below the titanium deposition layer (3), - producing a first metal electrode layer (4) on the second side (15), - removing the intermetal composite layer (35) and the titanium deposition layer (3) before producing the first metal electrode layer (4). [2] Method according to claim 1, comprising depositing the titanium deposition layer (3) with a thickness between 5 and 200 nm, in particular between 10 and 50 nm. [3] Method according to one of claims 1 to 2, comprising applying the at least one dopant by implanting or depositing the dopant. [4] Method according to one of claims 1 to 2, comprising applying the at least one dopant by depositing pre-doped amorphous silicon as dopant. [5] Method according to one of claims 1 to 4, comprising sintering the first metal electrode layer (4). [6] A method according to any one of claims 1 to 5, comprising providing a silicon wafer or wide bandgap wafer as the wafer (1). [7] Method according to one of claims 1 to 6, comprising introducing a buffer layer (13) into the wafer (1) before providing the wafer (1), wherein the buffer layer (13) is inserted between the drift layer (10) and the second main side (15), and the buffer layer (13) has a higher doping concentration than the drift layer (10). [8] A method according to any one of claims 1 to 7, comprising laser annealing the titanium deposition layer (3) at a temperature of more than 1300 °C. [9] Method according to one of claims 1 to 8, comprising producing an IGBT, in particular a reverse conducting IGBT, or a diode as the power semiconductor component.

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