Two-sided polishing process

Abstract

A two-side polishing method for simultaneously polishing both surfaces of a wafer by holding the wafer with a carrier including a holding hole configured to hold the wafer and an annular plastic insert arranged along the inner circumference of the holding hole, wherein the plastic insert has an inner circumferential surface and is configured to contact an edge region of the wafer to be held, and wherein the carrier is arranged between upper and lower turntables to which polishing pads are attached, the method comprising: Polishing both surfaces of the wafer, wherein the planarity of the inner circumferential surface is maintained at or below 100 µm and the verticality of the inner circumferential surface is maintained at or below 5°, wherein the planarity is defined as the maximum difference in the elevation of irregularities of the inner circumferential surface of the plastic insert, and the verticality is defined by an angle formed between a straight line perpendicular to the main surface of the carrier and a straight line connecting an upper edge region and a lower edge region of the inner circumferential surface.

Description

Technical area

[0001] The present invention relates to a two-side polishing method for simultaneously polishing both surfaces of a wafer with a two-side polishing carrier. background

[0002] When polishing both surfaces of a wafer simultaneously, such as double-side polishing, the wafer is held with a carrier for use in a double-side polishing device.

[0003] The Fig. Figure 8 is a schematic diagram for explaining wafer double-side polishing with a commonly used double-side polishing machine. As shown in Fig. As shown in Fig. 8, the carrier 102 of the two-side polishing apparatus 101 has a holding hole 104 for holding a wafer W. The carrier 102 has a thickness thinner than that of the wafer W.

[0004] The wafer W is inserted into the holding hole 104 and held there. The upper and lower surfaces of the wafer W are held between polishing pads 107 arranged on opposite sides of an upper turntable 105 and a lower turntable 106.

[0005] The carrier 102 is moved by a (sun) gear 108 and an internal gear 109 and is thereby rotated and turned via the rotation of the (sun) gear 108. The upper turntable 105 and the lower turntable 106 rotate in opposite directions, whereby a polishing agent is applied to the polishing surfaces, so that both surfaces of the wafer W are polished simultaneously by the polishing pads 107 attached to the upper and lower turntables 105, 106.

[0006] The carrier 102 of this type, used in the two-side polishing of the wafer W, is usually made of metal. Accordingly, a plastic insert 103 for protecting an edge portion of the wafer W from damage by the metal carrier 102 is attached along the inner periphery of the holding hole 104 of the carrier 102 (see Patent Document 1, for example). Citation listPatent literature

[0007] Patent Document 1: Japanese Unexamined Patent Publication (Kokai) No. 2011-25322, published under the reference number JP 2011 - 25 322 A

[0008] Further state of the art is known from the following documents: KR 10 2011 0 059 145 A relating to a carrier for a wafer and a device for polishing both sides of the wafer. US 2012 / 0 100 788 A1 relating to a method for double-sided polishing of a wafer. JP 2000 - 210 863 A relating to a method for processing a wafer. Summary of the inventionTechnical problem

[0009] There is a problem when polishing is repeatedly performed with a carrier having a plastic insert as described above, such that the flatness of the wafer is easily degraded: for example, a sag is generated at the outer periphery of the wafer.

[0010] The inventors of the present invention therefore investigated the causes and found that small irregularities formed on the inner circumferential surface of a plastic insert became larger over time due to wear of the carrier and the resulting irregularities then cause the degradation of flatness.

[0011] The present invention was conceived in view of the above-described problem. An object of the present invention is to provide a two-side polishing method that suppresses degradation of wafer flatness, such as sagging on the outer periphery, which results from variations in the shape of the inner periphery surface of a plastic insert of a carrier. Solution to the problem

[0012] To solve the problem, the present invention provides a two-side polishing method for simultaneously polishing both surfaces of a wafer, in which the wafer is held by a carrier having a holding hole configured to hold the wafer, and an annular plastic insert arranged along an inner circumference of the holding hole, the plastic insert having an inner circumferential surface configured to contact an edge region of the wafer to be held, and the carrier being arranged between upper and lower turntables and having polishing pads mounted thereon, the method comprising: polishing both surfaces of the wafer while maintaining the planarity of the inner circumferential surface at or below 100 µm and the verticality of the inner circumferential surface at or below 5°,where planarity is defined by the maximum difference in the elevation of irregularities of the inner circumferential surface of the plastic insert, and verticality is defined by an angle formed between a straight line perpendicular to the main surface of the carrier and a straight line connecting an upper corner region and a lower corner region of the inner circumferential surface.

[0013] The two-side polishing process performed in this way inhibits the degradation of wafer flatness due to a variation in the shape of the inner circumferential surface of the plastic insert of the carrier.

[0014] After polishing both surfaces of the wafer, the inner circumferential surface of the plastic insert can be ground or cut to maintain planarity and verticality.

[0015] In this way, the planarity and verticality can easily be maintained within the ranges specified above.

[0016] In this case, the surfaces of the wafer are preferably polished such that the planarity is maintained at or below 25 µm and the verticality is maintained at or below 2°.

[0017] In this way, the degradation of wafer flatness due to a variation in the shape of the inner circumferential surface of the plastic insert of the carrier can be reliably inhibited.

[0018] In addition, the upper and lower turntables may have a plurality of supports therebetween to simultaneously polish both surfaces of a plurality of wafers.

[0019] In this way, a large number of wafers can be polished simultaneously in a batch process, thereby reducing the processing time.

[0020] In this case, both wafer surfaces are preferably polished such that a difference in the inner diameter among the respective plastic inserts of the plurality of carriers is kept at or below 0.5 mm.

[0021] This method can inhibit the occurrence of a difference in polishing rates between wafers due to an increasing difference in the inner diameter among the plastic inserts when a plurality of wafers are polished simultaneously in a batch process, thereby enabling inhibition of the variation in the processing thickness of the wafers and consequently the degradation of the flatness. Advantageous effects of the invention

[0022] The method for two-side polishing a wafer according to the present invention polishes both surfaces of the wafer while maintaining the planarity of the inner circumferential surface of a plastic insert of the carrier at or below 105 µm and the verticality at or below 5°, thereby making it possible to inhibit the degradation of the flatness of the wafer due to the shape variation of the inner circumferential surface of the plastic insert of the carrier. Short description of the drawings Fig. 1 is a schematic diagram explaining wafer polishing according to the two-side polishing method of the present invention; Fig. 2 is an explanatory diagram of the planarity and verticality of the inner circumferential surface of a plastic insert according to the two-side polishing method of the present invention; Fig. 3 is a graph showing the relationship between the service life of the carrier and the planarity in Example 1 and the Comparative Example; Fig. 4 is a graph showing the relationship between the operating time of a beam and the verticality in Example 1 and a comparative example; Fig. 5 is a graph showing the relationship between ESFQRmax and planarity in Example 1 and Comparative Example; Fig. 6 is a graph showing the relationship between ESFQRmax and verticality in Example 1 and the comparative example; Fig. 7 is a graph showing the relationship between the difference in the inner diameter of the plastic inserts and the processing thickness in Example 2; and Fig. Figure 8 is a schematic diagram explaining the two-side polishing of a wafer with a conventional two-side polishing machine. Description of the embodiments

[0023] Embodiments of the present invention will be described below, but the present invention is not limited to these embodiments.

[0024] As described above, in the double-side polishing of wafers using a carrier having a plastic insert, there is a problem that the inner circumferential surface of the plastic insert is abraded by contact with an edge portion of the wafer due to the use of the carrier over a period of time; the irregularities formed on the inner circumferential surface of the plastic insert gradually become larger; deterioration of the flatness of a wafer to be polished is easily observed, for example, sagging of the outer circumferential surface of the wafer is observed.

[0025] In view of this, the inventors have conducted careful studies to solve the problem and found the following, thereby completing the invention.

[0026] First, planarity and verticality were defined to evaluate the irregularity of the inner peripheral surface of the plastic insert. The planarity of the inner peripheral surface was defined as the maximum difference in the increase of the irregularities of the inner peripheral surface; the verticality of the inner peripheral surface was defined as the angle formed between a straight line perpendicular to the main surface of the substrate and a straight line connecting an upper edge region and a lower edge region of the inner peripheral surface. Two-side polishing, in which the planarity is maintained at or below 100 µm and the verticality at or below 5°, enables the inhibition of the degradation of the flatness of a wafer to be polished.Processing the inner circumferential surface of the plastic insert into a flat surface is sufficient to maintain the planarity and verticality of the inner circumferential surface.

[0027] Furthermore, the inventors found that the following problem arises when both surfaces of multiple wafers are polished simultaneously using multiple carriers (multiple plastic inserts) in a batch process: with repeated processing of the inner circumferential surface, the difference in the inner diameter among the plastic inserts increases; thus, the polishing rate varies for each carrier, and the variation in the processing thickness of the wafer polished in the same batch process increases. In two-side polishing, the difference between the carrier thickness and the wafer processing thickness, a gap, affects wafer flatness. The increase in the processing thickness variation accordingly reduces the flatness.

[0028] If the difference in inner diameter is kept within a prescribed range, the variation in processing thickness and consequently the degradation of flatness can be more effectively suppressed.

[0029] The two-side polishing method according to the invention will now be described in detail with reference to Fig. 1 described.

[0030] As in Fig. 1, the carrier 2 of the two-side polishing apparatus 1 has a holding hole 4 for holding a wafer W. The carrier 2 is formed with a thickness thinner than that of the wafer W.

[0031] In the carrier 2, an annular plastic insert 3 is arranged along the inner circumference of the holding hole 4. The inner circumferential surface of the plastic insert 3 is configured to contact an edge region of the wafer, thus protecting the wafer from damage by the carrier 2.

[0032] The carrier W is inserted into the holding hole 4 and held there. The upper and lower surfaces of the wafer W are arranged between polishing pads 7 arranged on opposite sides of an upper turntable 5 and a lower turntable 6.

[0033] The carrier 2 is driven by a (sun) wheel 8 and an internal wheel 9 and is thereby rotated and turned by rotation via the (sun) wheel 8.

[0034] The two-side polishing method according to the invention is a method for simultaneously polishing both surfaces of a wafer with a two-side polishing device of this type.

[0035] First, the flatness and verticality of the inner circumferential surface of the plastic insert 3 are measured. The measurement can be performed, for example, using a two-dimensional displacement measuring device. Then, it is recorded whether the flatness is 100 µm or less and the verticality is 5° or less.

[0036] The planarity and verticality are now discussed with reference to Fig. 2 described at (A) and (B).

[0037] As in Fig. 2 at (A), there are minor irregularities on the inner circumferential surface 10 of the plastic insert 3. The "planarity of the inner circumferential surface" according to the present invention means the difference in elevation between the most-depressed area 'a' and the most-protruded area 'b' of the inner circumferential surface 10, which is the maximum difference (t) in elevation in the irregularities.

[0038] As in Fig. 2 at (B), "verticality of the inner circumferential surface" according to the present invention refers to the angle (θ) formed between a straight line 'd' perpendicular to the main surface of the substrate and a straight line 'c' connecting an upper corner portion and a lower corner portion of the inner circumferential surface 10.

[0039] If the inspection reveals that the flatness is greater than 100 µm or the verticality is greater than 5°, the inner circumferential surface of the plastic insert 3 is machined to achieve a planarity of 100 µm or less and a verticality of 5° or less. This process can be a milling process or a cutting process using a processing machine such as an NC milling machine.

[0040] Subsequently, the wafer W is held in the holding hole 4 of the carrier 2 with the plastic insert 3, in which the planarity of the inner circumferential surface 10 is maintained at or below 100 µm and the verticality of the inner circumferential surface 10 is maintained at or below 5°. The carrier 2, which holds the wafer W, is arranged between the upper turntable 5 and the lower turntable 6.

[0041] The upper and lower polishing surfaces of the wafer W are then placed between the polishing pads 7, which are respectively attached to the upper turntable 5 and the lower turntable 6. The upper turntable 5 and the lower turntable 6 are rotated in opposite directions, and a polishing agent is supplied to the polishing surfaces so that both surfaces of the wafer W are polished simultaneously by the polishing pads 7.

[0042] During polishing, the further polishing conditions can be the same as in a conventional two-side polishing process.

[0043] After the wafer W has been polished and before another wafer W is polished, the planarity and verticality of the inner circumferential surface are measured and examined so that polishing is carried out with a planarity always maintained at or below 100 µm and a verticality at or below 5°.

[0044] The two-side polishing method according to the invention, performed in this way, enables the inhibition of flatness degradation, for example, sagging of the outer periphery of a wafer, which typically occurs due to shape variation caused by abrasion of the inner circumferential surface 10 of the plastic insert 3. The method thus enables a wafer in which the degradation of ESFQRmax is inhibited.

[0045] In the above embodiment, the measurement of the planarity and verticality and the processing of the inner circumferential surface are performed each time before polishing a wafer W or after polishing a wafer W. However, the present invention is not limited to this embodiment.

[0046] The time intervals at which the measurement of the planarity and verticality and the machining of the inner orbital surface are carried out can be periodic: for example, the relationship between the service life of the carrier (plastic insert) and a change with the passage of time in the planarity and verticality of the inner orbital surface is first determined to calculate the service life of the carrier after which the inner orbital surface must be machined, and this service time of the carrier can be used to determine the above-mentioned time intervals.

[0047] As previously described, it is sufficient to maintain the planarity and verticality at or below 100 µm and at or below 5°, respectively. In particular, the planarity is preferably maintained at or below 25 µm and the verticality at or below 2°. In this way, the degradation of the flatness of a wafer to be polished can be reliably prevented.

[0048] In addition, in a batch process with two-side polishing, the upper and lower turntables 5, 6 can accommodate the carriers 2 between them, each holding wafers W therebetween, in order to simultaneously polish both surfaces of the wafers.

[0049] In this way, polishing processing time can be reduced and productivity can be improved.

[0050] In this case, both surfaces of the wafer W are preferably polished such that the difference in inner diameters between the different plastic inserts 3 of the carrier is kept at or below 0.5 mm.

[0051] The "inner diameter" described here is represented by a diameter of an approximate circle, after fitting a round shape, according to the least squares method, obtained by measuring the circumferential position along the inner circumferential surface of the plastic insert with an offset meter.

[0052] The “inner diameter difference” is represented by the difference between the maximum and minimum inner diameters among the plastic inserts of the carriers used simultaneously in a batch process for two-side polishing.

[0053] Taking into account the differences in inner diameter between the plastic pieces in this way allows the processing thickness of the wafers polished in the same polishing batch to be uniform, resulting in a reduction in the variation in wafer flatness.

[0054] It should be noted that the double-side polishing method according to the present invention can utilize a double-side polishing apparatus of the type in which multiple holding holes and plastic inserts are provided in a carrier. As in the aforementioned embodiment, a preferred aspect in this case is that both surfaces of the wafers are polished, keeping the difference in the inner diameter of the plastic inserts respectively disposed in the holding holes at or below 0.5 mm. Examples

[0055] The present invention will be described specifically below with reference to Examples and Comparative Examples, but the present invention is not limited to these Examples. (Example 1 and comparison example)

[0056] Silicon wafers with a diameter of 300 mm were double-sided polished. This time, five wafers were polished simultaneously in a batch process using a double-side polishing machine (DSP-20B, manufactured by Fujikoshi Machinery Corp.) with five carriers, each configured to hold a single wafer. Urethane foam polishing pads were used. A polishing compound containing colloidal silica in an alkaline solution was used.

[0057] First, the inner circumferential surfaces of the plastic inserts of all carriers were cut to a flatness of 25 µm or less and a verticality of 2° or less. After cutting, the inner circumferential surfaces and the inner diameters of the plastic inserts of all carriers were measured using a two-dimensional offset meter manufactured by Keyence Corp. The results showed that the planarity of the inner circumferential surfaces of all plastic inserts ranged from 12.91 µm to 22.73 µm; the verticality ranged from 0.86° to 1.9°. The minimum value of the inner diameter of the plastic inserts was 301.069 mm; the maximum value was 301.510 mm; and the difference in the inner diameter was 0.441 mm.

[0058] Using these carriers, two-side polishing was repeated continuously for 31,000 minutes to measure the planarity and verticality of the inner circumferential surface and the ESFQRmax (the maximum edge side front least squares range) of the polished wafers. ESFQRmax was measured using a wafer sight manufactured by KLA-Tencor Co., Ltd.

[0059] The measurement result for planarity is shown in Fig. 3 and the measurement result for verticality in Fig. 4. As in the Fig. 3 and Fig. As shown in Figure 4, it was found that both the planarity and verticality deteriorated over time during the use of the carriers. In addition, it was found that when the carrier was used for 10,000 minutes or less, the planarity and verticality were maintained at or below 100 μm or at or below 5°, respectively (Example 1). The measurement results regarding the planarity and verticality of the inner circumferential surface of the plastic insert just before the use of the carriers exceeded 10,000 minutes were that the planarity was in a range of 83.74 μm to 93.27 μm and the verticality was in a range of 4.6° to 4.9°, with each value being the average value of five carriers.

[0060] When the carrier usage time exceeded 10000 minutes, the planarity of the inner orbital surface was above 100 µm; the verticality exceeded 5° (comparative example).

[0061] These results showed that under the above conditions, if the upper limit of the use time of the carrier is 10000 minutes and the inner circumferential surface of the plastic insert is periodically machined, the planarity and the verticality of the inner circumferential surface of the plastic insert are maintained at or below 100 µm and at or below 5°, respectively.

[0062] The results of ESFQRmax show the Fig. 5 and Fig. 6. As in the Fig. 5 and Fig. As shown in Figure 6, by maintaining planarity at or below 100 µm and verticality at or below 5°, a good result was obtained for ESFQRmax. The flatness of all double-side polished wafers was measured from the beginning of polishing to the eleventh batch process; the average ESFQRmax was a good value at 0.050 µm (N=55). Furthermore, the average ESFQRmax value until the carriers reached 10,000 minutes of use was 0.048 µm (N=2,000). This value was almost as good as the flatness of a wafer immediately after 11 batch processes of double-side polishing with a carrier, immediately after the plastic insert was processed.

[0063] In contrast, the average value for ESFQRmax after the wear times of the carriers exceeded 10,000 minutes was 0.090 µm (N=20), which was significantly worse than 0.048 µm, the result of Example 1.

[0064] This result confirmed that since the two-side polishing method of the present invention polishes both surfaces of a wafer while maintaining the planarity of the inner circumferential surface of a plastic insert at or below 100 µm and the verticality at or below 5°, the degradation of wafer flatness due to the variation in the shape of the inner circumferential surface of the plastic insert of the carrier can be inhibited. (Example 2)

[0065] Silicon wafers were double-sided polished under the same conditions as in Example 1, and the inner diameter difference between the plastic inserts and the variation in wafer processing thickness were measured in the same batch process. Wafers with a thickness ranging from 791.2 µm to 791.3 µm were used in the double-side polishing. The wafer thickness was measured using a wafer sight manufactured by KLA-Tencor Co., Ltd.

[0066] The result will be Fig. 7. As shown in Fig. As shown in Figure 7, when the inner diameter difference is 0.5 mm or less, a good value of 0.107 µm is obtained as the average value of the variation in wafer processing thickness. In addition, no significant difference in the variation in wafer processing thickness was observed among all four cases with the inner diameter difference of 0.5 mm or less. In particular, the variation in wafer processing thickness did not increase due to the inner diameter difference.

[0067] It should be noted that the present invention is not limited to the above-described embodiments. The embodiment is merely exemplary, and any example having substantially the same features and exhibiting the same functions and effects according to the technical concept described in the claims of the present invention is encompassed within the technical scope of the present invention.

Claims

[1] A two-side polishing method for simultaneously polishing both surfaces of a wafer by holding the wafer with a carrier including a holding hole configured to hold the wafer and an annular plastic insert arranged along the inner circumference of the holding hole, the plastic insert having an inner circumferential surface and being configured to contact an edge portion of the wafer to be held, and the carrier being arranged between upper and lower turntables to which polishing pads are attached, the method comprising: Polishing both surfaces of the wafer, wherein the planarity of the inner circumferential surface is maintained at or below 100 µm and the verticality of the inner circumferential surface is maintained at or below 5°, wherein the planarity is defined as the maximum difference in the elevation of irregularities of the inner circumferential surface of the plastic insert, and the verticality is defined by an angle formed between a straight line perpendicular to the main surface of the carrier and a straight line connecting an upper edge region and a lower edge region of the inner circumferential surface. [2] The two-side polishing method according to claim 1, wherein after polishing both surfaces of the wafer, the inner circumferential surface of the plastic insert is ground or cut to maintain planarity and verticality. [3] The two-side polishing method according to claim 1 or claim 2, wherein both surfaces of the wafer are polished while maintaining the planarity at or below 25 µm and the verticality at or below 2°. [4] The two-side polishing method according to any one of claims 1 to 3, wherein the upper and lower turntables interpose a plurality of carriers to simultaneously polish both surfaces of a plurality of wafers. [5] The two-side polishing method according to claim 4, wherein both surfaces of the wafer are polished while maintaining a difference in inner diameter among the respective plastic inserts of the plurality of supports at or below 0.5 mm.

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