Silicon carbide semiconductor device

Abstract

Silicon carbide semiconductor device (1) comprising: an element area (IR) in which a semiconductor element (7) is provided; and a guard ring area (5) having a second conductivity type and surrounding the element area (IR) in a plan view, wherein the semiconductor element (7) comprises a silicon carbide substrate (10) of hexagonal silicon carbide and has a principal surface (10a) corresponding to a plane offset by 8° relative to a {0001} plane, the semiconductor element (7) contains a drift region (12) with a first conductivity type that is different from the second conductivity type, the protective ring area (5) contains a linear area (B) and a curved area (A) which is continuously connected to the linear area (B), a value obtained by dividing a radius of curvature (R) of an inner circumferential section (2c) of the curvature region (A) by a thickness (T1) of the drift region (12), is not less than 5 and not greater than 10.

Description

Technical field

[0001] The present invention relates to a silicon carbide semiconductor device and in particular to a silicon carbide semiconductor device with a guard ring area. Technical background

[0002] A guard ring region can be formed in a semiconductor device, such as a MOSFET (metal oxide semiconductor field-effect transistor), so that it surrounds a region in which a semiconductor element is provided in order to suppress the semiconductor element from breaking due to the concentration of an electric field.

[0003] For example, Japanese Patent Application No. JP 2008-004 643 A (Patent Document 1) describes a silicon MOSFET structure, wherein the MOSFET comprises an elemental region and a termination region formed to surround the elemental region, with a guard ring formed on the termination region. According to the MOSFET described in Japanese Patent Application No. JP 2008-004 643 A, a guard ring layer and an embedded guard ring layer are formed such that they exhibit curvatures in a corner section of the outermost base region, making them concentric with each other. To suppress the concentration of the electric field in the corner section of the outermost base region, the outermost base region is configured to have a radius of curvature approximately two to four times the thickness of the guard ring layer.

[0004] Document US 2010 / 0 200 936 A1 relates to a semiconductor device with a semiconductor layer of first conductivity type, on the main surface of which a first semiconductor column region of the same conductivity type and an adjacent second semiconductor column region of opposite conductivity type are provided. Both column regions form a periodic structure parallel to the main surface. The device further comprises a first main electrode, a first semiconductor region of second conductivity type, a second semiconductor region of first conductivity type, a second main electrode, a control electrode, and a high-resistance semiconductor layer in the edge termination section surrounding the column regions. The semiconductor layer is less densely doped than the first semiconductor column region, with the depth of the column regions decreasing stepwise towards the edge termination section.

[0005] Document US 2004 / 0 173 820 A1 relates to a high-voltage-strength semiconductor device that retains its performance even under variations in the impurity concentration of the RESURF layer or under the influence of solid electrical charges. It is formed by placing an annular boundary layer with a high impurity concentration and a concentric RESURF layer with a low impurity concentration of the second conductivity type on a semiconductor layer of first conductivity type with electrodes on opposite faces along the outer edge of an electrode. Outside the RESURF layer, an outer annular layer with a similarly low impurity concentration is located in an intervening gap, and inside is an inner annular layer with a concentration similarly high to that of the boundary layer. Summary of the invention: Technical problem

[0006] However, if a MOSFET is manufactured using silicon carbide, which has a band gap larger than that of silicon, such that the radius of curvature of the outermost base region (in other words, the radius of curvature of the guard ring formed in contact with an end section of the outermost base region) is about two to four times the thickness of the drift layer, an electric field is concentrated in the corner section of the guard ring, with the result that the MOSFET may break.

[0007] To increase the concentration of the electric field in the corner section of the guard ring, consideration is being given to increasing the radius of curvature of this section. However, a larger radius of curvature results in a smaller area of ​​the element region, leading to a reduced current in the forward state.

[0008] In view of this, the present invention aims to provide a silicon carbide semiconductor device that can improve the breakdown voltage while suppressing a decrease in current in the forward state. The solution to the problem

[0009] Because silicon has a cubic crystal structure, silicon carbide can have a hexagonal crystal structure. Silicon with a cubic crystal structure does not exhibit anisotropy in electric field strength, but silicon carbide with a hexagonal crystal structure does. Specifically, the electric field strength of silicon carbide with a hexagonal crystal structure is approximately 1.6 times greater in a direction parallel to the c-axis than in a direction perpendicular to the c-axis. Consequently, a simple ratio of the radius of curvature of the guard ring to the thickness of the drift layer in silicon is not applicable to silicon carbide.As a result of careful study, the inventors have arrived at the present invention by finding that the breakdown voltage can be improved while suppressing the decrease in current in the forward state of the silicon carbide semiconductor device by configuring it to a value determined by dividing a radius of curvature of an inner circumferential section of a curvature region by a thickness of a drift region such that it is not less than 5 and not greater than 10.

[0010] A silicon carbide semiconductor device according to the present invention comprises an element region and a guard ring region. A semiconductor element is provided in the element region. The guard ring region has a second conductivity type and surrounds the element region in plan view. The semiconductor element comprises a silicon carbide substrate of hexagonal silicon carbide and has a main surface corresponding to a plane offset by 8° with respect to a plane {0001}. The semiconductor element includes a drift region with a first conductivity type that differs from the second conductivity type. The guard ring region comprises a linear region and a curved region that is continuously connected to the linear region. A value obtained by dividing a radius of curvature of an inner circumferential section of the curved region by a thickness of the drift region is not less than 5 and not greater than 10.

[0011] In accordance with the silicon carbide semiconductor device according to the present invention, the value obtained by dividing the radius of curvature of the inner circumferential section of the curvature region by the thickness of the drift region is not less than 5 and not greater than 10. Accordingly, the breakdown voltage can be improved while suppressing the decrease in current in the forward state.

[0012] Preferably, in the silicon carbide semiconductor device described above, the semiconductor element includes a body region that is in contact with the drift region and exhibits the second conductivity type. The thickness of the body region is greater than the thickness of the guard ring region. Accordingly, a concentration of the electric field at the corner section of the body region can be efficiently suppressed.

[0013] Preferably, in the silicon carbide semiconductor device described above, the guard ring region includes a JTE region which is in contact with the body region and exhibits the second conductivity type. Accordingly, the breakdown voltage can be improved by the JTE region, which establishes contact with the body region 13.

[0014] Preferably, in the silicon carbide semiconductor device described above, the semiconductor element comprises a source region, which is in contact with the body region and exhibits the first conductivity type, and a source electrode, which is in contact with the source region. The JTE region is in contact with the source electrode. Accordingly, the source region can extract electrons from the JTE region at a high rate, thereby enabling the formation of a depletion layer, even during high-frequency operation.

[0015] Preferably, in the silicon carbide semiconductor device described above, the guard ring region includes a guard ring that is not in contact with the element region. Accordingly, the breakdown voltage can be improved by the guard ring, which does not make contact with the element region.

[0016] Preferably, the silicon carbide semiconductor device described above incorporates multiple guard rings. The value obtained by dividing the radius of curvature of an inner circumferential section of a curvature region of the innermost guard ring by the thickness of the drift region is not less than 5 and not greater than 10. In cases where multiple guard rings are present, the radius of curvature of the innermost guard ring is smaller than the radii of curvature of the other guard rings. Because the value obtained by dividing the radius of curvature of the inner circumferential section of the curvature region of the innermost guard ring by the thickness of the drift region is not less than 5 and not greater than 10, the breakdown voltage can be improved while suppressing the current drop in the on-state.

[0017] Preferably, the silicon carbide semiconductor device described above further comprises a field-stop region having a first conductivity type and surrounding the guard ring region in plan view. Accordingly, the breakdown voltage of the silicon carbide semiconductor device can be further improved.

[0018] Preferably, in the silicon carbide semiconductor device described above, the distance between an outer circumferential section of the guard ring area and an inner circumferential section of the field stop area is constant in every position of the outer circumferential section of the guard ring area in a plan view. Accordingly, the local concentration of an electric field can be suppressed. The advantageous effects of the invention

[0019] As is evident from the above description, according to the present invention a silicon carbide semiconductor device can be created which can improve the breakdown voltage while suppressing the decrease in current in the forward state. Brief description of the drawings Fig. Figure 1 is a schematic cross-sectional view showing a configuration of a silicon carbide semiconductor device in an embodiment of the present invention. Fig. Figure 2 is a schematic plan showing the configuration of the silicon carbide semiconductor device in the embodiment of the present invention. Fig. Figure 3 is a schematic cross-sectional view showing a configuration of a first modification of the silicon carbide semiconductor device in the embodiment of the present invention. Fig. Figure 4 is a schematic cross-sectional view showing a configuration of a second modification of the silicon carbide semiconductor device in the embodiment of the present invention. Fig. Figure 5 is a schematic cross-sectional view showing a configuration of a third modification of the silicon carbide semiconductor device in the embodiment of the present invention. Fig. Figure 6 is a schematic plan showing the configuration of the third modification of the silicon carbide semiconductor device in the embodiment of the present invention. Fig. Figure 7 is a flowchart that schematically shows a method for manufacturing the silicon carbide semiconductor device in the embodiment of the present invention. Fig. Figure 8 is a schematic cross-sectional view showing a first step of the method for manufacturing the silicon carbide semiconductor device in the embodiment of the present invention. Fig. Figure 9 is a schematic cross-sectional view showing a second step of the method for manufacturing the silicon carbide semiconductor device in the embodiment of the present invention. Fig. Figure 10 is a schematic cross-sectional view showing a third step of the method for manufacturing the silicon carbide semiconductor device in the embodiment of the present invention. Fig. Figure 11 shows a relationship between the on-resistance and a breakdown voltage. Description of the embodiments

[0020] The following describes the embodiments of the present invention with reference to the figures. It should be noted that in the figures mentioned below, the same or corresponding sections are given the same reference numerals and the same or corresponding sections are not described repeatedly. With regard to the crystallographic information in this description, a single orientation is represented by [], a group orientation is represented by <>, a single plane is represented by (), and a group plane is represented by {}. Furthermore, a negative index is expected to be indicated crystallographically by placing a '-' (hyphen) over a number, but in this description it is indicated by placing the negative sign before the number. For the description of an angle, a system is used in which an undirected angle is 360°.

[0021] First, the following describes a configuration of a MOSFET as a silicon carbide semiconductor device in an embodiment of the present invention.

[0022] In the Fig. 1 and Fig. 2. The MOSFET 1 has an element region IR (an activation region) and a termination region OR (an invalid region) that surrounds the element region IR. The termination region OR contains a guard ring region 5. In other words, the element region IR is surrounded by the guard ring region 5. A semiconductor element 7, such as a transistor or a diode, is provided in the element region IR.

[0023] The semiconductor element 7 contains, for example, mainly a silicon carbide substrate 10 made of hexagonal silicon carbide, a gate insulating layer 15, a gate electrode 17, a source electrode 16, and a drain electrode 20. The silicon carbide substrate 10 mainly contains an n+ substrate 11, a drift region 12, a p-body region 13, an n+ source region 14, and a p+ region 18. The silicon carbide substrate 10 is, for example, made of hexagonal silicon carbide. The silicon carbide substrate 10 can have a principal surface 10a corresponding to a plane that is, for example, no more than 8° away from a {0001} plane.

[0024] An N+ substrate is a substrate made from hexagonal silicon carbide and exhibits n-type conductivity (a first conductivity type).

[0025] The N+ substrate 11 contains an n-type impurity, such as N (nitrogen), in a high concentration. The concentration of the impurity, such as nitrogen, in the n+ substrate 11 is, for example, approximately 1.0 × 10 18 cm -3 .

[0026] The drift region 12 is an epitaxial layer made of silicon carbide and exhibits n-type conductivity. The drift region 15 has, for example, a thickness T1 of approximately 15 µm. Preferably, the thickness T1 of the drift region 12 is not less than 14.5 µm and not greater than 15.5 µm. The n-type defect in the drift region 12 is, for example, nitrogen and is present therein at a defect concentration that is lower than that of the n-type defect in the n+ substrate 11. The concentration of the defect, such as nitrogen, in the drift region 12 is, for example, approximately 7.5 × 10⁻⁶. 15 cm -2 .

[0027] The p-body region 13 exhibits p-type conductivity. The p-body region 13 is formed within the drift region 12, such that it contains the main area 10a of the silicon carbide substrate 10. The p-body region 13 contains a p-type defect, such as Al (aluminum) or B (boron). The concentration of the defect, such as aluminum, in the p-body region 13 is, for example, approximately 1 × 10⁻⁶. 17 cm -2 .

[0028] The N+ source region 14 has an n-type conductivity. The N+ source region 14 contains the main area 10a and is formed within the p-body region 13, such that it is surrounded by the p-body region 13. The N+ source region 14 contains an n-type defect, such as P (phosphorus), in a concentration higher than that of the n-type defect in the drift region 12, e.g., in a concentration of approximately 1 × 10 20 cm -2 .

[0029] The P+ region 18 exhibits p-type conductivity. The P+ region 18 is in contact with the main surface 10a and the p-body region 13, such that it extends through the vicinity of the center of the n+-source region 14. The P+ region 18 contains a p-type defect, such as aluminum or boron, at a concentration higher than that of the p-type defect in the p-body region 13, e.g., at a concentration of approximately 1 × 10⁻⁶. 20 cm -2 .

[0030] The gate insulating layer 15 is formed in contact with the drift region 12, such that it extends from above the top surface of one n+ source region 14 to above the top surface of the other n+ source region 14. The gate insulating layer 15 is made, for example, of silicon dioxide.

[0031] The gate electrode 17 is arranged on and in contact with the gate insulating layer 15, such that it extends from above one n+ source region 14 to above the other n+ source region 14. The gate electrode 17 is made, for example, of a conductor such as polysilicon or aluminum.

[0032] On the main surface 10a, a source electrode 16 is arranged in contact with the n+ source region 14 and the p+ region 18. The source electrode 16 also contains, for example, titanium atoms (Ti atoms), aluminum atoms (Al atoms), and silicon atoms (Si atoms). The source electrode 16, which is therefore an ohmic contact electrode containing Ti, Al, and Si, exhibits low contact resistance with respect to both the p-type silicon carbide region and the n-type silicon carbide region.

[0033] The drain electrode 20 is located opposite the main surface on which the drift area 12 is formed and is in contact with the main surface of the n+ substrate 11. This drain electrode 20 can have the same configuration as the source electrode 16 or can be made of a different material, such as nickel, which, for example, enables an ohmic contact with the n+ substrate 11. Accordingly, the drain electrode 20 is electrically connected to the n+ substrate 11.

[0034] The guard ring region 5 has an annular shape and is arranged in the termination region OR of the silicon carbide substrate 10, such that it surrounds the element region IR in which the semiconductor element 7 is provided. The guard ring region 5 has p-type conductivity (a second conductivity type). The guard ring region 5 is an electrically conductive region that serves as a guard ring. The guard ring region 5 includes, for example: a JTE region 2 that is in contact with the p-body region 13; and several guard rings 3 that are not in contact with the p-body region 13. Preferably, the p-body region 13 of the semiconductor element 7 has a thickness T1 that is greater than the thickness T2 of the guard ring region 5.

[0035] The multiple guard rings 3 of the guard ring region 5 contain an impurity, such as boron or aluminum. The impurity concentration in each of the multiple guard rings 3 is lower than the impurity concentration of the p-body region 13. The impurity concentration in each of the multiple guard rings 3 is, for example, 1.3 × 10 13 cm -2 and is preferably not smaller than approximately 8 × 10 12 cm -2 and not larger than about 1.4 × 10 13 cm -2 .

[0036] As in Fig. As shown in Figure 2, the guard ring region 5 has linear regions B and curvature regions A, which are continuously connected to the linear regions B. Specifically, the linear regions B and the curvature regions A are arranged alternately to form an annular guard ring region 5 that surrounds the element region IR. The curvature region A has an inner circumferential section 2c, which is formed along the arc of a circle with a center C. The curvature region A of the guard ring region 5 has a radius of curvature R. The radius of curvature R is, for example, not less than 50 µm and not greater than 1260 µm.

[0037] A value obtained by dividing the radius of curvature R of the inner circumferential section 2c of the guard ring region 5 by the thickness T1 of the drift region 12 of the semiconductor element 7 is not less than 5 and not greater than 10. For example, the thickness T1 of the drift region 12 is 15 µm, while the radius of curvature of the inner circumferential section 2c of the guard ring region 5 is 125 µm. In the above case, the value obtained by dividing the radius of curvature R of the inner circumferential section 2c of the guard ring region 5 by the thickness T1 of the drift region 12 of the semiconductor element 7 is approximately 8.3. If the guard ring region 5 contains several guard rings 3, the inner circumferential section 2c of the guard ring region 5 refers to the inner circumferential section 2c of the guard ring 3 that is located closest to the semiconductor element 7 (in other words, to the innermost guard ring 3).

[0038] If the guard ring area 5 contains multiple guard rings 3, the multiple guard rings 3 are arranged with a gap between them. Specifically, each of the multiple guard rings 3 has linear regions B and curvature regions A. The linear regions B of the multiple guard rings 3 are arranged parallel to each other in plan view. Meanwhile, the curvature regions A of the multiple guard rings 3 are arranged along the arcs of concentric circles that have center C and different radii. The respective concentrations of p-type defects in the multiple guard rings 3 can be the same or different. Of the multiple guard rings 3, one guard ring 3 preferably has a defect concentration on its outer circumferential side that is lower than the defect concentration of a guard ring 3 on its inner circumferential side.

[0039] The guard ring region 5 can have a JTE region (junction termination extension region) 2, which, for example, establishes contact with the p-body region 13 of the semiconductor element 7 and exhibits p-type conductivity. The JTE region 2 can have the same defect as the defect of the guard ring 3, with the same defect concentration as the defect concentration of the guard ring 3. The impurity concentration of the JTE region 2 is lower than the impurity concentration of the p-body region 13. Preferably, the thickness T1 of the p-body region 13 of the semiconductor element 7 is greater than the thickness T2 of the JTE region 2. It is stated that, if the guard ring region 5 contains the JTE region 2 and the guard rings 3, the guard ring region 5 refers to a region between the inner circumferential section 2c of the JTE region 2 and the outer circumferential section 3d of the outermost guard ring 3 in a plan view.

[0040] In Fig. 3. A guard ring region 5 of the MOSFET 1 may not have a JTE region 2 that is in contact with the p-body region 13, and may instead have a guard ring 3 that is not in contact with the p-body region 13. The defect and defect concentration of the guard ring 13 are the same as those of the preceding guard ring 3. One guard ring 3 or several guard rings 3 may be provided. Preferably, several guard rings 3 are arranged with a gap between them.

[0041] In Fig. 4. The MOSFET 1 can have a JTE region 2 that is in contact with the p-body region 13, and a source electrode 16a can be formed in contact with the JTE region 2. The source electrode 16a is electrically connected to the source electrode 16, which is in contact with the source region 14, which is surrounded by a p-body region 13, and a p+ region 18, which is surrounded by the source region 14.

[0042] In Fig. 5 and in Fig. 6. The MOSFET 1 can further include a field stop region 4, which has an n-type conductivity, such that it surrounds the guard ring region 5, which has a p-type conductivity. The field stop region 4 has the same conductivity type (n-type) as that of the drift region 12. The field stop region 4 has a defect concentration that is higher than the defect concentration of the drift region 12. The defect concentration in the field stop region 4 is, for example, approximately 1.0 × 10⁻⁶. 18 cm -3Preferably, the shortest distance D between the outer circumferential section 3d of the guard ring area 5 and the inner circumferential section 4c of the field stop area 4 is constant in every position of the outer circumferential section 3d of the guard ring area 5. If the guard ring area 5 has multiple guard rings 3, the shortest distance D refers to the shortest distance between the outer circumferential section 3d of the outermost guard ring 3 and the inner circumferential section 4c of the field stop area 4.

[0043] The following describes an operation of MOSFET 1. When a voltage not exceeding a threshold value is applied to the gate electrode 17, i.e., during the OFF state, the p-body region 13 and the drift region 12 just beneath the gate insulating layer 15 are reverse-biased, resulting in MOSFET 1 being in a non-conductive state. Conversely, when a positive voltage is applied to the gate electrode 17, an inversion layer forms in a channel region near the point where the p-body region 13 makes contact with the gate insulating layer 15. Consequently, the n+ source region 14 and the drift region 12 are electrically connected, causing a current to flow between the source electrode 22 and the drain electrode 20.

[0044] The following describes a method for manufacturing the MOSFET 1 according to the embodiment of the present invention.

[0045] In Fig. 8 First, a silicon carbide substrate 10 is prepared in a substrate preparation step (S10: Fig. 7) prepared. Specifically, the drift region 12 is formed by epitaxial growth on a major surface of the n+ substrate 11 made of hexagonal silicon carbide. The epitaxial growth can be carried out, for example, using a mixed gas of SiH4 (silane) and C3H8 (propane) as a source material gas. In this case, nitrogen is incorporated, for example, as an n-type defect. In this way, the drift region 12 is formed, which contains the n-type defect at a concentration lower than that of the n-type defect in the n+ substrate 11.

[0046] Next, a silicon dioxide oxide film is formed on the main surface 10a of the silicon carbide substrate 10, e.g., by CVD (chemical vapor deposition). Then, a resist is applied to the oxide film, followed by exposure and development, forming a resist film with an opening in a region corresponding to the shape of the desired p-body region 13. The oxide film is then partially removed by RIE (reactive ion etching) using the resist film as a mask, forming, for example, a mask layer composed of the oxide film with an opening pattern in the drift region 12.

[0047] In Fig. 9 will be an ion implantation step (S20: Fig. 7) is carried out. In the ion implantation step, ions are implanted into the silicon carbide substrate 10, thereby forming the p-body region 13, the n+ source region 14, and the guard ring region 5. Specifically, after removal of the masking film described above, ions of the p-type defect, such as Al, are implanted into the drift region 12 using the mask layer as a mask, thereby forming the p-body region 13 and the guard ring region 5. Furthermore, after removal of the oxide layer used as the mask, a mask layer is formed that has an opening in a region corresponding to the shape of the desired n+ source region 14.

[0048] Next, the mask layer is used as a mask to introduce an n-type defect, such as P (phosphorus), into the drift region 12 by ion implantation, thereby forming the n+ source region 14. Next, a mask layer with an opening in a region conforming to the shape of the desired p+ region 18 is formed, this mask layer being used as a mask to introduce a p-type defect, such as Al or B, into the drift region 12 by ion implantation, thereby forming the p+ region 18. It is noted that the p-body region 13 of the semiconductor element 7 can be formed before / after the formation of the guard ring region 5. The formation of the protective ring area 5 specifically refers to the formation of the JTE area 2 and the protective ring 3. It should be noted that the implantation depth of the p-body area 13 is preferably greater than the implantation depth of the protective ring area 5.Furthermore, a field stop area 4 can be formed so that it surrounds the protective ring area 5 in a plan view.

[0049] Next, a heat treatment is performed to activate the defects introduced by the ion implantations described above. Specifically, for example, the silicon carbide substrate 10 with the incorporated ions is heated to approximately 1700 °C in an argon atmosphere and held at this temperature for about 30 minutes.

[0050] In Fig. Step 10 will be a gate insulating layer formation step (step S30: Fig. 7) carried out. Specifically, the silicon carbide substrate 10 is first thermally oxidized, whereby the desired ion implantation areas are created by the step described above (S20: Fig. 7) are formed. Thermal oxidation can be carried out, for example, by heating to approximately 1300 °C in an oxygen atmosphere for about 40 minutes. Accordingly, the gate insulating layer 15 of silicon dioxide is formed on the main surface 10a of the silicon carbide substrate 10.

[0051] Next, a gate electrode formation step (S40: Fig. 7) is carried out. In this step, the gate electrode 17, which is made of a conductor such as polysilicon or aluminum, is formed in contact with the gate insulating layer 15, such that it extends from above one n+ source region 14 to above the other n+ source region 14. If polysilicon is used as the material of the gate electrode 17, the polysilicon can be configured to contain phosphorus in a high concentration of more than 1 × 10 20 cm -3contains. Then an insulating layer, e.g. made of silicon dioxide, is formed to cover the gate electrode 17.

[0052] Next, a step of forming an ohmic electrode (S50: Fig. 7) is carried out. Specifically, for example, a masking pattern is formed to expose the p+ region 18 and a section of the n+ source region 14, whereby a metal layer containing, for example, Si atoms, Ti atoms, and Al atoms is completely formed on the surface of the substrate, for example, by sputtering. Then, for example, by removing the masking pattern, the metal layer 50 is formed in contact with the gate insulating layer 15 and in contact with the p+ region 18 and the n+ source region 14. Then, for example, by heating the metal layer to about 1000 °C, the source electrode 16 is formed in ohmic contact with the silicon carbide substrate 10. Furthermore, the drain electrode 20 is formed in contact with the n+ substrate 11 of the silicon carbide substrate 10. The in Fig. MOSFET 1 shown is completed.

[0053] It should be noted that a configuration can be used in which the n-type and p-type conductances can be interchanged in the embodiment. Furthermore, in the present embodiment, a planar-type MOSFET is described as an example of the silicon carbide semiconductor device, wherein the silicon carbide semiconductor device can be a trench-type MOSFET. Alternatively, the silicon carbide semiconductor device can be an IGBT (an insulated-gate bipolar transistor) or the like.

[0054] Next, the following describes the function and effect of the method for manufacturing the MOSFET 1 according to the present embodiment.

[0055] In accordance with the MOSFET 1 according to the present embodiment, the value obtained by dividing the radius of curvature R of the inner circumferential section 2c of the curvature region A of the guard ring region 5 by the thickness of the drift region 12 is not less than 5 and not greater than 10. Because the value obtained by dividing the radius of curvature R of the inner circumferential section 2c of the curvature region A of the guard ring region 5 by the thickness of the drift region 12 is not less than 5 and not greater than 10, the breakdown voltage can be improved while suppressing a decrease in the current during forward conduction.

[0056] Furthermore, in accordance with the MOSFET 1 according to the present embodiment, the semiconductor element 7 includes a body region 13 which is in contact with the drift region 12 and has the second conductivity type. The thickness T2 of the body region 13 is greater than the thickness T3 of the guard ring region 5. Accordingly, a concentration of the electric field at the corner section 13c of the body region 13 can be effectively suppressed.

[0057] Furthermore, in accordance with the MOSFET 1 according to the present embodiment, the guard ring area 5 includes a JTE area 2 which is in contact with the body area 13 and has the second conductivity type. Accordingly, the breakdown voltage can be improved by the JTE area 2, which establishes contact with the body area 13.

[0058] Furthermore, in accordance with the MOSFET 1 according to the present embodiment, the semiconductor element 7 comprises a source region 14, which is in contact with the body region 13 and has the first conductivity type, and a source electrode 16, which is in contact with the source region 14. The JTE region 2 is in contact with the source electrode 16. Accordingly, the source region 14 can pull electrons from the JTE region 2 at a high speed, thereby also forming a depletion layer in high-speed operation.

[0059] Furthermore, in accordance with the MOSFET 1 according to the present embodiment, the guard ring region 5 includes a guard ring 3 which is not in contact with the IR element region. Accordingly, the breakdown voltage can be improved by the guard ring 3, which does not make contact with the IR element region.

[0060] Furthermore, in accordance with the MOSFET 1 according to the present embodiment, several guard rings 3 are provided. The value obtained by dividing the radius of curvature R of an inner circumferential section 2c of a curvature region A of the innermost guard ring 3 of the multiple guard rings 3 by the thickness T1 of the drift region 12 is not less than 5 and not greater than 10. In the case where there are multiple guard rings 3, the radius of curvature R of the innermost guard ring 3 is smaller than the radii of curvature R of the other guard rings 3. Because the value obtained by dividing the radius of curvature R of the inner circumferential section of the curvature region A of the innermost guard ring 3 by the thickness T1 of the drift region 12 is not less than 5 and not greater than 10, the breakdown voltage can be improved while suppressing a decrease in the current during the on-state condition.

[0061] The MOSFET 1 according to the present embodiment further comprises a field-stop region 4, which has the first conductivity type and surrounds the guard ring region 5 in plan view. Accordingly, the breakdown voltage of the silicon carbide semiconductor device can be further improved.

[0062] Furthermore, in accordance with the MOSFET 1 according to the present embodiment, a distance d between an outer circumferential section 3d of the guard ring area 5 and an inner circumferential section 4c of the field stop area 4 is constant in every position of the outer circumferential section 3d of the guard ring area 5 in a plan view. Accordingly, the locally concentrated electric field can be suppressed. [An example]

[0063] In the present example, a relationship between the forward current and the breakdown voltage was investigated by changing the value obtained by dividing the radius of curvature R of the inner circumferential section of the guard ring 3 by the thickness T1 of the drift region 12 (hereinafter referred to as the "drift layer ratio"). First, three types of MOSFETs 1, each made of silicon carbide and containing a drift region 12 with a thickness T1 of 15 µm, were prepared using the fabrication method illustrated in the embodiment. The n-type impurity concentration of the drift region 12 was set to 7.5 × 10⁻⁵. 15 cm -2 The MOSFET 1 chip was a square with each side measuring 3 mm.

[0064] A guard ring region 5 was provided in MOSFET 1 so that it surrounds the IR element region. The impurity concentration of guard ring region 5 was set to 1.3 × 10⁻⁶.13 cm -2 The radii of curvature R of the inner circumferential sections 2c of the curvature regions A of the guard ring regions 5 of the MOSFETs 1 were set to 50 µm, 125 µm, and 1260 µm, respectively. This means that three types of MOSFETs 1 were prepared, with drift layer ratios of 3.3, 8.3, and 84.3. The on-state current and breakdown voltage were measured for each of the MOSFETs 1. It should be noted that the shape of the element region IR of the MOSFET 1 with a drift ratio of 84.3 is circular in plan view.

[0065] The breakdown voltage was determined by applying a reverse voltage to each of the MOSFETs and measuring the reverse current. The breakdown voltage was defined as a voltage such that the reverse current rapidly increases with increasing reverse voltage. The resulting broken section was specified using an emission microscope. When MOSFET 1, with a drift layer ratio of 3.3, was observed using an emission microscope and the reverse voltage was 1200 V, strong light emission was observed in curvature region A of guard ring region 5. This confirmed that a breakdown had occurred in curvature region A of guard ring region 5.

[0066] In Fig. Section 11 describes the following relationship between the on-state current of MOSFET 1 and the breakdown voltage. When the radius of curvature R of the bent region A of the guard ring region 5 becomes small, an electric field is likely to be concentrated in the bent region A, resulting in a reduced breakdown voltage. For example, a target breakdown voltage specification for MOSFET 1 is 1200 V. If the drift layer ratio is 3.3, the on-state current will be high, at 13.6 A, but the breakdown voltage will be approximately 1100 V, which does not meet the specification. A drift layer ratio that allows a breakdown voltage of at least 1200 V is considered to be 5 or greater.

[0067] On the other hand, if the radius of curvature R of the curvature region A of the guard ring region 5 becomes large, the concentration of the electric field is weakened, resulting in an increased breakdown voltage. However, if the area of ​​the curvature region A is increased, the area of ​​the element region IR is decreased, resulting in a small current flowing in the semiconductor element 7 in the forward state. The MOSFET 1 ideally possesses a high breakdown voltage and a high on-resistance (i.e., it has the properties shown in the upper right of the diagram). Fig.(as specified in Figure 11). For example, a target specification for the on-resistance in MOSFET 1 is 12 A. If the drift layer ratio is 8.3, the breakdown voltage is 1800 V and the on-state current is 12.8 A. If the drift layer ratio is 84.3, the breakdown voltage is high, i.e., 1900 V, but the breakdown voltage is approximately 10 A, which does not meet the specification. If the drift layer ratio exceeds 8.3, the breakdown voltage is not increased as much, but the on-state current decreases rapidly. A drift layer ratio that allows a breakdown voltage of less than 12 A is considered to be 10 or less. Consequently, a drift layer ratio that meets both the on-state current and breakdown voltage specifications is assumed to be no less than 5 and no greater than 10.

[0068] The embodiments and examples disclosed herein are in every respect illustrative and non-limiting. The scope of protection of the present invention is defined by the terms of the claims rather than by the embodiments described above, and it is intended that it includes all modifications within the scope of protection and the meaning of the equivalent terms of the claims. LIST OF REFERENCE MARKS

[0069] 1: MOSFET; 2: JTE region; 2a: Curvature region; 2b: Linear region; 2c: Inner circumferential section; 3: Guard ring; 3a: Curvature region; 3b: Linear region; 5: Guard ring region; 7: Semiconductor element; 10: Silicon carbide substrate; 10a: Main area; 11: n+ substrate; 12: Drift region; 13: p-body region; 14: n+ source region; 15: Gate insulating layer; 16: Source electrode; 17: Gate electrode; 18: p+ region; 20: Drain electrode; A: Curvature region; B: Linear region; IR: Element region; OR: Termination region.

Claims

[1] Silicon carbide semiconductor device (1) comprising: an element area (IR) in which a semiconductor element (7) is provided; and a guard ring area (5) having a second conductivity type and surrounding the element area (IR) in a plan view, wherein the semiconductor element (7) comprises a silicon carbide substrate (10) of hexagonal silicon carbide and has a principal surface (10a) corresponding to a plane offset by 8° relative to a {0001} plane, the semiconductor element (7) contains a drift region (12) with a first conductivity type that is different from the second conductivity type, the protective ring area (5) contains a linear area (B) and a curved area (A) which is continuously connected to the linear area (B), a value obtained by dividing a radius of curvature (R) of an inner circumferential section (2c) of the curvature region (A) by a thickness (T1) of the drift region (12), is not less than 5 and not greater than 10. [2] Silicon carbide semiconductor device according to claim 1, wherein the semiconductor element (7) contains a body region (13) which is in contact with the drift region (12) and has the second conductivity type, and a thickness (T2) of the body area is greater than a thickness of the protective ring area (5). [3] Silicon carbide semiconductor device according to claim 2, wherein the guard ring area (5) contains a JTE area (2) which is in contact with the body area (13) and has the second conductivity type. [4] Silicon carbide semiconductor device according to claim 3, wherein the semiconductor element (7) includes a source region (14) which is in contact with the body region (13) and has the first conductivity type, and a source electrode (16) which is in contact with the source region (14), and the JTE area (2) is in contact with the source electrode (16). [5] Silicon carbide semiconductor device according to any one of claims 1 to 4, wherein the guard ring area (5) includes a guard ring (3) which is not in contact with the element area (IR). [6] Silicon carbide semiconductor device according to claim 5, wherein several protective rings (3) are provided, and a value obtained by dividing a radius of curvature (R) of an inner circumferential section (2c) of a curvature region (A) of an innermost guard ring (3) of the multiple guard rings (3) by the thickness (T1) of the drift region (12), is not less than 5 and not greater than 10. [7] Silicon carbide semiconductor device according to any one of claims 1 to 6, further comprising a field stop region (4) having the first conductivity type and surrounding the guard ring region (5) in plan view. [8] Silicon carbide semiconductor device according to claim 7, wherein a distance (D) between an outer circumferential section (3d) of the guard ring area (5) and an inner circumferential section (4c) of the field stop area (4) is constant in every position of the outer circumferential section (3d) of the guard ring area (5) in a plan view.

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