Reducing the overhead associated with processor frequency changes

Abstract

Procedure that includes: Determining (16) whether a processor is operating at its minimum supply voltage and, if so, changing (18) a processor clock frequency by compressing a clock edge, and if the processor is in a scaled voltage range, Changing (20) the processor clock frequency using a phase-locked loop, wherein changing the processor clock frequency by compressing the clock edge comprises calculating the ratio of the target frequency to the base frequency and multiplying this ratio by an integer value to achieve a finer granularity in the frequency adjustment, and compressing one or more clock edges to achieve a frequency adjustment to the target frequency according to the granularity.

Description

background

[0001] This applies to processors in general and in particular to processors that implement a mode in which the frequency of the processor can change.

[0002] Typically, processors can change their operating frequency in a number of different cases. For example, some processors can share power between different components of a platform that includes a processor. If the processor's power requirements are reduced, the processor can use less power by reducing its frequency and lowering its supply voltage by a corresponding amount. However, even if the supply voltage has been reduced below a minimum voltage, additional power savings can be achieved by continuing to reduce its frequency.

[0003] Each time a frequency is changed, execution of a particular workload is halted to allow a phase-locked loop to lock on to a new frequency. The phase-locked loop is used by the processor to adjust the output clock to a desired frequency. Phase-locked loop time is an overhead, like other handshaking protocols, and is a trade-off between the rate of change of current and the rate of change of time. These overheads can cause different logic sections to engage on a staggered basis.

[0004] As a result, the overhead associated with frequency changes can result in a significant time delay. If frequency changes occur frequently enough, significant power overhead can occur. Not only is there a power loss, but there may also be a power consumption cost, as the devices consume power during the time spent changing the frequency.

[0005] US 2009 / 0 125 293 A1 describes a method and system for real-time prediction of power consumption during a transition to a different power state, providing input data for energy management decision-making processes or for display to system operators. The unit(s) for which power consumption is predicted can be a single processor in a single-processor system or extend down to the level of devices within a complex of processing devices. The method and system collect real-time data on the power consumption of the unit(s) and create a model, e.g., a regression model, for the relationship between power consumption and performance.A resulting change in power consumption, required by an anticipated change in the nominal power state, is presented as display data or transmitted to a power budget controller to inform the controller of possible changes that may improve system operation, such as managing power trade-offs between different subunits of a processing system.

[0006] US 2008 / 0 284 476 A1 describes a processor comprising a clock source, a central processing unit (CPU), and a clock generator. The clock source comprises an output for providing a periodic clock signal. The CPU comprises an input for receiving a CPU clock signal. The clock generator comprises a first input coupled to the output of the clock source, a second input for receiving a mode signal indicative of an output frequency, and an output coupled to the input of the CPU. The clock generator provides the CPU clock signal using periodic pulse skipping such that the CPU clock signal has a number of transitions over a unit time corresponding to the output frequency.

[0007] The invention is defined in the independent claims. Embodiments of the invention are specified in the dependent claims. Brief description of the drawings

[0008] Some embodiments are described with reference to the following figures: Fig. 1 is an illustration of a plurality of bars before and after squashing, according to some embodiments; Fig. 2 is a flowchart for a compression sequence according to one embodiment; Fig. 3 is an illustration of a processor for one embodiment; Fig. 4 is a system diagram for one embodiment and Fig. 5 is a front view of a system. Fig. Figure 6 is a representation of two clock signals running at a 5:4 ratio. Fig. 7 is a series of clock signals with different ratios. Detailed description

[0009] In many cases, processors may change frequency so frequently that suboptimal performance and power consumption can result. These performance and power losses can be mitigated by changing the frequency using a squeezing technique instead of a phase-locked loop technique. The squeezing technique may involve eliminating clock pulses to reduce the frequency. This can be done more quickly, resulting in less overhead in some cases.

[0010] As an example of an application for some embodiments of the present invention, a Turbo embodiment may include a processor that periodically changes its frequency. This enables the processor to share power with other platform components. Specifically, in a system-on-a-chip (SOC) Turbo implementation, a frequency change may be requested approximately every millisecond, with each frequency change costing approximately 40 microseconds.

[0011] Frequency scaling may be necessary if the supply voltage Vcc is already at its minimum voltage. Once the supply voltage is at its minimum, the frequency can be reduced by eliminating the number of clock edges seen during a period.

[0012] Fig. Figure 1 above shows a series of clocks labeled CZ, GFraw, and GSraw. While the clocks in question can be any clock, in some embodiments the CZ clock range is a system agent clock that happens to run at 1 / 4 the system memory clock rate. Other generic and non-generic clock ranges may be used. GF and GS clocks may be the graphics clocks, running in a ratio relative to each other. For example, a 2:1 ratio between GF, or graphics-fast, and GS, or graphics-slow, clocks may be used. GF and GS may be generated using one phase-locked loop, and CZ may be generated using another phase-locked loop. However, there are also modes where they both originate from the same phase-locked loop.

[0013] Links in Fig. 1 is an area labeled a non-squeeze area, marked with the first two alignment marks, where none of the pulses are squeezed or eliminated. To the right is an area labeled a squeeze area, where one or more pulses may be eliminated. For the top three signals, no squeeze occurs at GF or GS, which is why they are labeled CZ, GFraw, and GSraw. Then, a value (Val) and an NxtVAL value (explained below) are shown. This specification requires that a Time Slot Valid (TSV) goes to zero at the end of the squeeze area. This results in squeezing or elimination of pulses in both the graphics slow (GS) and graphics fast (GF) clocks.

[0014] The GSraw value can be a running clock. A TSV algorithm examines this free-running clock GSraw and generates a clock gate value known as a TSV. When TSV equals one, the clocks can run, and when TSV equals zero (e.g., at the end of the compression window), the clock is masked in one embodiment. The TSV algorithm can be applied to GSraw and masks the last GS and GF clocks, as the ratio should be maintained at the endpoints.

[0015] Window and Allow can change when the two measures come to match, which is Fig. 1 is marked by the dashes on the "align" signal. Masking can be implemented using a bubble generator, either first-in, first-out, or BGF. An algorithm for performing the squeezing can be as follows: Val = Init = -2 If(Window=Allow) ClockEn=1 NxtVal = Init elsif (Val >= 0) NxtVal = Val - Allow else NxtVal = CurrentValue + (Window - Allow) endif If (NxtVal < 0) ClockEn=1 else ClockEn=0

[0016] As another, in Fig. In the example shown in Figure 6, two clocks run at a 5:4 ratio, where CZ equals 200 MHz, GF equals 320 MHz, and GS equals 160 MHz. By compressing one of the four target edges, a new average achieved frequency has a 5:3 ratio, where CZ equals 200, GF equals 240, and GS equals 120 MHz.

[0017] This example illustrates an increment of 80 MHz achieved by squeezing edges together. Finer granularities can be achieved by multiplying the ratio by an integer value. For example, instead of starting with a 5:4 ratio, the ratio can be 10:8. By squeezing one of the eight target edges, an increment of 40 MHz can be achieved. The following illustrates how the granularity can be reduced by increasing the ratio and the ability to eliminate one clock per ratio: 5:3 CZ=200, GF=240, GS=120, GF granularity = 80 MHz 10:7 CZ=200, GF=280, GS=140, GF granularity = 40 MHz 20:15 CZ=200, GF=300, GS=150, GF granularity = 20 MHz 40:31 CZ=200, GF=310, GS=155, GF granularity = 10 MHz 80:63 CZ=200, GF=315, GS=157.5, GF granularity = 5 MHz

[0018] In the above example, if CZ is equal to 200 megahertz and the ratio is 5:4, and this frequency change is to occur once every millisecond, the ratio can be increased to 2000 to 1600. In this example, a granularity of 1 / 1600, or 0.000625 megahertz, can be achieved.

[0019] The Fig. The diagrams included in Figure 7 show that the deterministic synchronous nature of the various clocks involved is maintained throughout the frequency change: The CZ clock is the clock that must continue to run at a fixed frequency. CFclk_von_PLL is the graphics clock supplied to the logic by the PLL. CFclk is the clock received by the logic. GSclk is the clock pulse received by the logic. In this example, GF = 2*GS. COMclk is an imaginary clock pulse that indicates when both clock pulses share a rising edge. CZ = 200 MHz, GFclk_of_PLL = 1000 MHz, GFclk = 1000 MHz, GSclk = 500 MHz, ratio = 2:5

[0020] With reference to Fig. 2: A pulse compression sequence according to one embodiment may be implemented in software, firmware, and / or hardware. In software and firmware embodiments, it may be implemented using computer-executed instructions stored on one or more non-transitory computer-readable media, such as magnetic, optical, or semiconductor memory. For example, in one embodiment, a graphics subsystem (see graphics subsystem 715c in Fig. 4) execute the sequence.

[0021] In one embodiment, the compression sequence 10 begins Fig. 2, with determining whether a new clock frequency has been requested, as shown in diamond 12. In one embodiment, this may be done as part of a turbo implementation, where reducing the clock signal frequency supplied to a processor is desired to conserve power and make power available to other system components. If a new required frequency is present, a new clock frequency may be received at block 14. This may indicate the desired final ratio and how fine a granularity of steps may be used to achieve that ratio.

[0022] If there is a desire to change the clock frequency, a check at diamond 16 determines whether the processor is already operating at its minimum supply voltage. If so, the frequency can be changed using clock compression. The granularity of the compression and the steps, if any, to achieve the compression frequency can be received at block 14.

[0023] However, if the processor is not yet operating at its minimum supply voltage, and particularly if it is operating in the scaled voltage region, the frequency can be changed by changing the frequency of the phase-locked loop, as shown in block 20. Therefore, in some embodiments, clock squeezing is only used when the processor is already at its minimum supply voltage, and otherwise, conventional frequency-changing techniques can be used. However, in other embodiments, clock squeezing can be used in other cases.

[0024] In some embodiments, squeezing may be used instead of changing the phase-locked loop, as it has zero frequency change overhead. Furthermore, finer frequency granularities can be achieved, and lower frequencies may be possible.

[0025] Of course, clock frequencies can also be increased by reducing or eliminating compression at one stroke, or by increasing or decreasing it gradually over time.

[0026] Fig. 3 illustrates a system according to one embodiment. In some embodiments, a system on a chip may be illustrated. In Fig. 3, a multi-core processor 400 may include a core zero 406 and a core one 408. The two sites 402 and 404 may each include a single processor core 406 or 408. In other embodiments, the number of cores per site may be more than one. For example, in other embodiments, there may be two or four cores per site, or more. Each site includes a phase-locked loop (PLL) 116 or 118.

[0027] Location 402 may be a higher-level location that controls the voltage supplied to the processor by sending a voltage information signal 410 to voltage regulator 412. Voltage regulator 412 receives a power supply from a power source 414 and regulates the voltage supplied specifically to processor 416. Logic at location zero 402 may continuously modify the supplied voltage 416 by sending new voltage information signals 410 to voltage regulator 412 at any given time.

[0028] Furthermore, the system may include an input / output complex 424. This complex may include one or more integrated input / output host controllers for controlling data transfer between the multi-core processor 400 and one or more peripheral devices, such as a mass storage device 426 (e.g., a hard disk drive), non-volatile memory 428, and a network port 430 that provides access between the computer system and the network 432. One or more different input / output interfaces, such as a USB (universal serial bus interface), the PCI Express ® -interface (peripheral component interconnect express interface) or the IEEE 1394 Firewire interface of the Institute of Electrical and Electronic Engineers or one or more other input / output interfaces can be used.

[0029] In various embodiments not shown, a graphics processing unit may be coupled to or integrated with the multi-core processor 400 to provide information to a display device, such as a monitor, for viewing by a user.

[0030] Fig. 4 illustrates one embodiment of a system 700. In embodiments, the system 700 may be a media system, although the system 700 is not limited to this context. For example, the system 700 may be incorporated into a personal computer (PC), a laptop computer, an ultra-laptop computer, a tablet, a touchpad, a portable computer, a handheld computer, a palmtop computer, a personal digital assistant (PDA), a mobile phone, a mobile phone / PDA combination, a television, a smart device (e.g., smartphone, smart tablet, or smart TV), a mobile internet device (MID), a messaging device, a data transmission device, and so on.

[0031] In embodiments, system 700 includes a platform 702 coupled to a display 720. Platform 702 may receive content from a content device, such as content service device(s) 730 or content delivery device(s) 740, or other similar content sources. A navigation controller 750 having one or more navigation features may be used, for example, to interact with platform 702 and / or display 720. Each of these components is described in more detail below.

[0032] In embodiments, platform 702 may include any combination of a chipset 705, a processor 710, memory 712, storage 714, a graphics subsystem 715, applications 716, a global positioning system (GPS) 721, a camera 723, and / or a radio 718. Chipset 705 may provide for data exchange between processor 710, memory 712, storage 714, graphics subsystem 715, applications 716, and / or radio 718. For example, chipset 705 may include a memory adapter (not shown) capable of providing data exchange with memory 714.

[0033] Furthermore, the platform 702 may include an operating system 770. An interface to the processor 772 may serve as an interface between the operating system and the processor 710.

[0034] Firmware 790 may be provided to implement functions such as the boot sequence. An update module may be provided to enable the firmware to be updated from outside of the platform 702. For example, the update module may include code to determine whether the update attempt is authentic and to identify the most recent update to firmware 790 to facilitate determining when updates are needed.

[0035] In some embodiments, the platform 702 may be powered by an external power supply. In some cases, the platform 702 may also include an internal battery 780 that serves as a power source in embodiments not adapted for an external power supply, or in embodiments that allow power from either a battery or an external source.

[0036] The Fig. The sequence shown in Figure 2 may be implemented in software and firmware embodiments, to name a few examples, by incorporating it into memory 714 or into a random access memory in processor 710 or graphics subsystem 715. Graphics subsystem 715 may include the graphics processing unit, and processor 710 may be a central processing unit in one embodiment.

[0037] Processor 710 may be implemented as a complex instruction set computer processor (CISC) or reduced instruction set computer processor (RISC), an x86 instruction set compatible processor, a multi-core processor, or any other microprocessor or central processing unit (CPU). In embodiments, processor 710 may be dual-core processor(s), mobile dual-core processor(s), and so on.

[0038] The memory 712 may be implemented as a volatile memory device, such as, but not limited to, random access memory (RAM), dynamic random access memory (DRAM), or static RAM (SRAM).

[0039] Memory 714 may be implemented as a non-volatile storage device, such as, but not limited to, a magnetic disk drive, optical disk drive, tape drive, internal storage device, attached storage device, flash memory, battery-backed SDRAM (synchronous DRAM), and / or a network-accessible storage device. In embodiments, memory 714 may include technology for increasing storage performance-enhanced protection for valuable digital media, for example, when multiple hard drives are included.

[0040] The graphics subsystem 715 may perform processing of images, such as still or video images, for display. The graphics subsystem 715 may be, for example, a graphics processing unit (GPU) or a visual processing unit (VPU). An analog or digital interface may be used to communicatively connect the graphics subsystem 715 and the display 720. For example, the interface may be a high-definition multimedia interface (HDMI), a DisplayPort interface, wireless HDMI, and / or wireless HD-compliant technologies. The graphics subsystem 715 may be integrated with the processor 710 or the chipset 705. The graphics subsystem 715 may be a standalone card communicatively connected to the chipset 705.

[0041] The graphics and / or video processing techniques described herein may be implemented in various hardware architectures. For example, graphics and / or video functionality may be integrated into a chipset. Alternatively, a discrete graphics and / or video processor may be used. As yet another embodiment, the graphics and / or video functions may be implemented by a general-purpose processor, including a multi-core processor. In yet another embodiment, the functions may be implemented in a consumer electronics device.

[0042] The radio 718 may be one or more radio devices capable of transmitting and receiving signals using various suitable wireless data transmission technologies. Such technologies may include data transmissions over one or more wireless networks. Example wireless networks include (but are not limited to) wireless local area networks (WLANs), wireless personal area networks (WPANs), wireless metropolitan area networks (WMANs), cellular networks, and satellite networks. When transmitting data over such networks, the radio 718 may operate in accordance with one or more applicable standards in any version.

[0043] In embodiments, display 720 may be any monitor or television-like display. For example, display 720 may be a computer display screen, a touchscreen display, a video monitor, a television-like device, and / or a television. Display 720 may be digital and / or analog. In embodiments, display 720 may be a holographic display. Additionally, display 720 may be a transparent surface capable of receiving a visual projection. Various forms of information, images, and / or objects may be conveyed through such projections. For example, such projections may be a visual overlay for a mobile augmented reality (MAR) application.Controlled by one or more software applications 716, the platform 702 may display the user interface 722 on the display 720.

[0044] In embodiments, the content service device(s) 730 may be hosted by any national, international, and / or independent service and thus accessible to the platform 702, for example, via the Internet. The content service device(s) 730 may be connected to the platform 702 and / or the display 720. The platform 702 and / or the content service device(s) 730 may be connected to a network 760 to transmit (e.g., send and / or receive) media information to and from the network 760. The content delivery device(s) 740 may also be connected to the platform 702 and / or the display 720.

[0045] In embodiments, the content service device(s) 730 may be a cable television box, a personal computer, a network, a telephone, internet-enabled devices or appliances capable of delivering digital information and / or content, as well as any other similar device capable of unidirectionally or bidirectionally transferring content between content providers and the platform 702 and / or the display 720 via the network 760 or directly. It should be noted that the content may be transferred unidirectionally and / or bidirectionally to and from any of the components in the system 700 and a content provider via the network 760. Examples of content may include any media information, including, for example, video, music, medical, and gaming information, and so on.

[0046] The content service device(s) 730 receive(s) content such as cable television programming, including media information, digital information, and / or other content. Examples of content providers may include any cable or satellite television, radio, or internet content provider. The listed examples are not intended to limit embodiments of the invention.

[0047] In embodiments, platform 702 may receive control signals from navigation controller 750, which has one or more navigation features. The navigation features of controller 750 may be used, for example, to interact with user interface 722. In embodiments, navigation controller 750 may be a pointing device, which may be a computer hardware component (particularly a human interface device) that enables a user to input spatial (e.g., continuous and multi-dimensional) data into a computer. Numerous systems, such as graphical user interfaces (GUIs), televisions, and monitors, allow the user to control and input data to the computer or television using physical gestures.

[0048] Movements of the navigation features of controller 750 may be rendered on a display (e.g., display 720) by movements of a pointer, cursor, focus ring, or other visual pointers displayed on the display. For example, under the control of software applications 716, features located on navigation controller 750 may be mapped to virtual navigation features displayed, for example, on user interface 722. However, in embodiments, controller 750 may not be a separate component, but may be integrated into platform 702 and / or display 720. However, embodiments are not limited to the elements or context shown or described herein.

[0049] For example, in embodiments, drivers (not shown) may include technology to, when enabled, enable users to instantly turn platform 702 on and off like a television by touching a button after initial boot-up. Program logic may enable platform 702 to stream content to media adapters or other content service device(s) 730 or content delivery device(s) 740 when the platform is "off." Furthermore, chipset 705 may include, for example, hardware and / or software support for 5.1 surround sound audio and / or high-resolution 7.1 surround sound audio. Drivers may include a graphics driver for integrated graphics platforms. In embodiments, the graphics driver may include a peripheral component interconnect express (PCI Express) graphics card.

[0050] In various embodiments, any one or more of the components shown in system 700 may be integrated. For example, platform 702 and content service device(s) 730 may be integrated, or platform 702 and content delivery device(s) 740 may be integrated, or platform 702, content service device(s) 730, and content delivery device(s) 740 may be integrated, for example. In various embodiments, platform 702 and display 720 may be an integrated unit. Display 720 and content service device(s) 730 may be integrated, or display 720 and content delivery device(s) 740 may be integrated, for example. These examples are not intended to limit the invention.

[0051] In various embodiments, system 700 may be implemented as a wireless system, a wired system, or a combination of both. When implemented as a wireless system, system 700 may include components and interfaces suitable for transmitting data over a wireless shared medium, such as one or more antennas, transmitters, receivers, transceivers, amplifiers, filters, control logic, and so forth. Examples of wireless shared media may include, but are not limited to, portions of a radio spectrum, such as the RF spectrum, and so forth.When implemented as a wired system, the system 700 may include components and interfaces suitable for transmitting data over wired data transmission media, such as input / output adapters (I / O adapters), physical connectors for connecting the I / O adapter to a corresponding wired data transmission medium, a network interface card (NIC), a disk controller, a video controller, an audio controller, and so on. Examples of wired data transmission media may include a wire, a cable, metal leads, a printed circuit board (PCB), a backplane, a switching fabric, semiconductor material, a twisted pair, coaxial cable, fiber optic cable, and so on.

[0052] Platform 702 may establish one or more logical or physical channels to transmit information. The information may include media information and control information. "Media information" may refer to any data that represents content intended for a user. Examples of content may include, for example, data from a voice conversation, a video conference, a streamed video, an electronic mail message, a voice message, alphanumeric symbols, graphics, images, video, text, and so on. Data from a voice conversation may include, for example, speech information, periods of silence, background noise, comfort noise, tones, and so on. "Control information" may refer to any data that represents commands, instructions, or control words intended for an automated system.For example, control information may be used to route media information through a system or to instruct a node to process the media information in a predetermined manner. However, embodiments are not limited to the elements or context described in . Fig. 4 are shown or described.

[0053] As described above, the system 700 can be embodied in different physical styles or form factors. Fig. Figure 4 illustrates embodiments of a small form factor device 800 in which system 700 may be embodied. In embodiments, device 800 may be embodied, for example, as a mobile computing device with wireless capabilities. "A mobile computing device" may refer to any device with a processing system and a mobile power source or supply, such as one or more batteries.

[0054] As described above, examples of a mobile computing device may include a personal computer (PC), a laptop computer, an ultra-laptop computer, a tablet, a touchpad, a portable computer, a handheld computer, a palmtop computer, a personal digital assistant (PDA), a mobile phone, a mobile phone / PDA combination, a television, a smart device (e.g., smartphone, smart tablet, or smart TV), a mobile internet device (MID), a messaging device, a data transmission device, and so on.

[0055] Examples of a mobile computing device may also include computers configured to be worn by a person, such as a wrist computer, a finger computer, a ring computer, a glasses computer, a belt clip computer, a wristband computer, shoe computers, clothing computers, and other wearable computers. In embodiments, a mobile computing device may be implemented, for example, as a smartphone capable of executing computer applications as well as voice transmissions and / or data transmissions. Although some embodiments may be described, by way of example, with a mobile computing device implemented as a smartphone, it should be noted that other embodiments may also be implemented using other wireless mobile computing devices. The embodiments are not limited in this context.

[0056] As in Fig.5, device 800 may include a housing 802, a display 804, an input / output device (I / O device) 806, and an antenna 808. Device 800 may also include navigation features 812. Display 804 may be any suitable display device for displaying information appropriate for a mobile computing device. I / O device 806 may be any suitable I / O device for inputting information to a mobile computing device. Examples of I / O device 806 may include an alphanumeric keypad, a numeric keypad, a touchpad, input keys, buttons, switches, toggle switches, microphones, speakers, a voice recognition device and software, and so on. Information may also be input to device 800 using a microphone.Such information can be digitized using a speech recognition device. The embodiments are not limited in this context.

[0057] Various embodiments may be implemented using hardware elements, software elements, or a combination of both. Examples of hardware elements may include processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so on), integrated circuits, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs), logic gates, registers, semiconductor devices, chips, microchips, chipsets, and so on.Examples of software may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces (APIs), instruction sets, computational code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an embodiment is implemented using hardware elements and / or software elements may vary according to any number of factors, such as a desired computational rate, performance levels, thermal tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds, and other design or performance constraints.

[0058] One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium representing various logic within the processor that, when read by a machine, causes the machine to manufacture logic for performing the techniques described herein. Such representations, known as "IP cores," may be stored on a physical machine-readable medium and delivered to various customers or manufacturing facilities for loading into the manufacturing machines that actually manufacture the logic or processor.

[0059] Various embodiments may be implemented using hardware elements, software elements, or a combination of both. Examples of hardware elements may include processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so on), integrated circuits, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs), logic gates, registers, semiconductor devices, chips, microchips, chipsets, and so on.Examples of software may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces (APIs), instruction sets, computational code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an embodiment is implemented using hardware elements and / or software elements may vary according to any number of factors, such as a desired computational rate, performance levels, thermal tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds, and other design or performance constraints.

[0060] One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium representing various logic within the processor that, when read by a machine, causes the machine to manufacture logic for performing the techniques described herein. Such representations, known as "IP cores," may be stored on a physical machine-readable medium and delivered to various customers or manufacturing facilities for loading into the manufacturing machines that actually manufacture the logic or processor.

[0061] The graphics processing techniques described herein can be implemented in various hardware architectures. For example, graphics functionality can be integrated into a chipset. Alternatively, a discrete graphics processor can be used. As yet another embodiment, the graphics functions can be implemented by a general-purpose processor, including a multi-core processor.

[0062] The following sentence parts and / or examples refer to further embodiments: In an exemplary embodiment, it may be changing a processor clock frequency by squeezing a clock edge. The method may include selecting a desired frequency and squeezing at least one clock edge to achieve the frequency. The method may further include achieving the frequency by incrementally squeezing clock edges. The method may further include determining how many edges to squeeze to achieve a target frequency. The method may further include implementing a system-on-chip turbo. The method may further include using squeezing to adjust the frequency ratio between two clocks.

[0063] Another example embodiment may include storing on at least one non-transitory computer-readable medium instructions for changing a processor clock frequency by squeezing a clock edge. The medium may further include storing instructions for selecting a desired frequency and squeezing at least one clock edge to achieve the frequency. The medium may further include storing instructions for achieving the frequency by incrementally squeezing clock edges. The medium may further include storing instructions for determining how many edges to squeeze to achieve a target frequency. The medium may further include storing instructions for implementing a system-on-chip turbo. The medium may further include storing instructions for applying squeezing to adjust the frequency relationship between two clocks.

[0064] Another example embodiment may include a processor having a core for switching to a processor clock frequency by squeezing clock edges, and a phase-locked loop connected to the core. The processor may include the core selecting a desired frequency and squeezing at least one clock edge to achieve that frequency. The processor may further include the core achieving the frequency by squeezing clock edges incrementally. The processor may further include the core determining how many edges to squeeze to achieve a target frequency. The processor may further include the core implementing a system-on-chip turbo. The processor may further include the core applying squeezing to adjust the frequency ratio between two clocks.

[0065] Yet another example embodiment may include a processor having a core for switching to a processor clock frequency by squeezing clock edges, a phase-locked loop coupled to the core, and memory coupled to the processor. The system may further include the processor selecting a desired frequency and squeezing at least one clock edge to achieve that frequency. The system may further include the processor achieving the frequency by squeezing clock edges incrementally. The system may further include the processor determining how many edges to squeeze to achieve a target frequency. The system may further include the processor implementing a system-on-chip turbo. The system may further include the processor applying squeezing to adjust the frequency ratio between two clocks.The system may also include an operating system, a battery and firmware, as well as a module for updating the firmware.

[0066] When reference is made in this specification to "a single embodiment" or "an embodiment," it means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation included in the present invention. Therefore, phrases such as "a single embodiment" or "in an embodiment" do not necessarily refer to the same embodiment. Moreover, the particular features, structures, or characteristics may be introduced in other suitable forms than the particular embodiment illustrated, and all such forms may be included within the claims of the present invention.

[0067] Although the present invention will be described with reference to a limited number of embodiments, those skilled in the art will recognize numerous modifications and variations therein. It is intended that the appended claims cover all such modifications and variations that fall within the true spirit and scope of this present invention.

Claims

[1] Procedure which includes: Determining (16) whether a processor is operating at its minimum supply voltage and, if so, changing (18) a processor clock frequency by compressing a clock edge, and if the processor is in a scaled voltage range, Changing (20) the processor clock frequency using a phase-locked loop, wherein changing the processor clock frequency by compressing the clock edge comprises calculating the ratio of the target frequency to the base frequency and multiplying this ratio by an integer value to achieve a finer granularity in the frequency adjustment, and compressing one or more clock edges to achieve a frequency adjustment to the target frequency according to the granularity. [2] A method according to claim 1, which includes achieving the frequency by gradually compressing clock edges. [3] The method of claim 1, including determining how many edges are to be compressed to achieve a target frequency. [4] The method of claim 1, including applying compression to adjust the frequency ratio between two clocks. [5] At least one non-transitory computer-readable medium having stored thereon instructions that, when executed by a processor, cause the processor to change a processor clock frequency by squeezing a clock edge, wherein changing (18) the processor clock frequency by squeezing the clock edge comprises calculating the ratio of the target frequency to the base frequency and multiplying this ratio by an integer value to achieve a finer granularity in the frequency adjustment, and squeezing one or more clock edges to achieve a frequency adjustment to the target frequency according to the granularity. [6] A medium according to claim 5, further storing instructions for selecting a desired frequency. [7] The medium of claim 6, further storing instructions for achieving the frequency by squeezing clock edges in steps. [8] The medium of claim 6, further storing instructions for determining how many edges are to be compressed to achieve a target frequency. [9] The medium of claim 7, further storing instructions to apply compression to adjust the frequency ratio between two clocks. [10] The medium of claim 5, further comprising instructions for determining (16) whether the processor is operating at its minimum supply voltage. [11] The medium of claim 10, further storing instructions to apply clock squashing when the processor is operating at its minimum supply voltage. [12] The medium of claim 10, further storing instructions to use a phase-locked loop to change a clock frequency when the processor is not operating at its minimum supply voltage. [13] Processor comprising: a core configured to switch to a processor clock frequency, wherein the core is to cause clock edge compression to switch, and a phase-locked loop connected to the core, wherein changing (18) the processor clock frequency by compressing the clock edge comprises calculating the ratio of the target frequency to the base frequency and multiplying this ratio by an integer value to achieve finer granularity in the frequency adjustment, and compressing (18) one or more clock edges to achieve a frequency adaptation to the target frequency according to the granularity. [14] The processor of claim 13, wherein the core is to select a desired frequency and compress at least one clock edge to achieve that frequency. [15] The processor of claim 14, wherein to achieve the frequency, the core is to compress clock edges in stages. [16] The processor of claim 13, wherein the core is to determine how many edges to compress to achieve a target frequency. [17] The processor of claim 13, wherein the core is to implement a system on a chip turbo. [18] The processor of claim 13, wherein the core is to compress to adjust the frequency ratio between two clocks. [19] The processor of claim 13, wherein the core is to apply clock squashing when the processor is operating at its minimum supply voltage. [20] The processor of claim 13, wherein the core is to use the phase-locked loop to change a clock frequency when the processor is not operating at its minimum supply voltage. [21] System that includes: a processor having a core for switching to a processor clock frequency and for squeezing clock edges, and a phase-locked loop connected to the core, and a display connected to the processor, the processor being configured to determine (16) whether the processor is operating at its minimum supply voltage, and if this is the case, changing (18) the processor clock frequency by squeezing a clock edge, and if the processor is in a scaled voltage range, Changing (20) the processor clock frequency using the phase-locked loop, wherein changing (18) the processor clock frequency by compressing the clock edge comprises calculating the ratio of the target frequency to the base frequency and multiplying this ratio by an integer value to achieve a finer granularity in the frequency adjustment, and compressing one or more clock edges to achieve a frequency adjustment to the target frequency according to the granularity. [22] The system of claim 21, wherein the processor is to select a desired frequency and compress at least one clock edge to achieve that frequency. [23] The system of claim 22, wherein the processor is to gradually reach the frequency and compress clock edges. [24] The system of claim 22, wherein the processor is to determine how many edges are to be compressed to achieve a target frequency. [25] The system of claim 21, wherein the processor is to apply compression to adjust the frequency ratio between two clocks.

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