Improvements to an interconnect retimer

Abstract

Device (650, 660, 665, 655) comprising: Control logic for: Generating a test mode signal (670a, ..., 670f) comprising a test pattern (620) and an error reporting sequence (625); and Send logic for: Transmitting the test mode signal on a data link comprising one or more expansion devices (660, 665) and two or more sub-data links (675a, 675b, 675c), wherein the test mode signal is to be transmitted on a particular one of the sub-data links, the test pattern is to be used by a receiving device to identify errors on the particular sub-data link, and the error report sequence is to be encoded with error information to describe error statuses of sub-data links in the plurality of sub-data links.

Description

FIELD OF EXPERTISE

[0001] This disclosure relates to a computer system and particularly (but not exclusively) to point-to-point interconnections. BACKGROUND

[0002] Advances in semiconductor processing and logic design have enabled an increase in the amount of logic that can be present on integrated circuit devices. As a logical consequence, computer system configurations have evolved from single or multiple integrated circuits within a system to multiple cores, multiple hardware threads, and multiple logic processors residing on single integrated circuits, as well as other interfaces integrated within such processors. A processor or integrated circuit typically comprises a single physical processor die, with the processor die comprising any number of cores, hardware threads, logic processors, interfaces, memory, controller hubs, etc.

[0003] As a result of the greater ability to pack more processing power into smaller packages, smaller computing devices have gained popularity. Smartphones, tablets, ultra-thin notebooks, and other user devices have grown exponentially. However, these smaller devices rely on servers for both data storage and complex processing that exceeds the form factor. Subsequently, the demand in the high-performance computing market (i.e., server space) has also increased. For example, modern servers typically have not only a single processor with multiple cores, but also multiple physical processors (also known as multi-socket sockets) to increase computing power. However, as processing power grows along with the number of devices in a computing system, communication between sockets and other devices becomes more important.

[0004] Indeed, interconnects have evolved from the more traditional multidrop buses that primarily performed electrical transfers to fully-fledged interconnect architectures capable of rapid transfers. Unfortunately, as future processors are required to consume at even higher rates, the demand for the capabilities of existing interconnect architectures increases accordingly.

[0005] Document US 2013 / 0 173 974 A1 shows a method and apparatus for a computer memory test structure. Document US 2008 / 0 037 526 A1 shows methods for error detection, reporting, and maintenance negotiation control of a pseudo-segment line. Document PCI-SIG: PCI Express Base Specification; Revision 3.0; 2010 shows an overview of the PCI Express architecture and key concepts. BRIEF DESCRIPTION OF THE DRAWINGS Fig.1 illustrates one embodiment of a computing system including an interconnect architecture. Fig. 2 illustrates one embodiment of an interconnect architecture including a layered stack. Fig. 3 illustrates one embodiment of a request or packet to be generated or received within an interconnect architecture. Fig. 4 illustrates one embodiment of a transmitter-receiver pair for an interconnect architecture. Fig. 5A-5B illustrate simplified block diagrams of example data connections including one or more expansion devices. Fig. 6A-6E illustrate simplified block diagrams of example implementations of a test mode for determining faults in one or more subdata links of a data link. Fig.Figure 7 illustrates a representation of an example ordered sentence. Fig. Figure 8 illustrates simplified block diagrams showing an example of disconnection and reconnection on a data link. Fig. 9 is a flowchart showing an example technique for providing a multi-mode retimer. Fig. 10 illustrates a simplified block diagram of an example physical layer logic of a retimer. Fig. 11A-11E are flow diagrams illustrating example techniques associated with a data connection implemented using an expansion device. Fig. 12 illustrates one embodiment of a block diagram for a computer system including a multi-core processor. Fig.13 illustrates another embodiment of a block diagram for a computer system including a multi-core processor. Fig. 14 illustrates one embodiment of a block diagram for a processor. Fig. 15 illustrates another embodiment of a block diagram for a computer system including a processor. Fig. 16 illustrates one embodiment of a block for a computer system including multiple processors. Fig. Figure 17 illustrates an example system implemented as a system-on-chip (SoC). DETAILED DESCRIPTION

[0006] In the following description, numerous specific details are set forth, such as examples of various types of processors and system configurations, specific hardware structures, specific architectural and microarchitectural details, specific register configurations, specific instruction types, specific dimensions / heights, specific processor pipeline stages and operations, etc., in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that these specific details need not be employed to practice the present invention.In other instances, well-known components or methods, such as specific and alternative processor architectures, specific logic circuits / code for described algorithms, specific firmware code, specific interconnect operations, specific logic configurations, specific manufacturing methods and materials, specific compiler implementations, specific expression of algorithms in code, specific shutdown and clocking methods / logic, and other specific operating details of a computer system have not been described in detail to avoid unnecessarily obscuring the present invention.

[0007] Although the following embodiments may be described with reference to power conservation and energy efficiency in specific integrated circuits, such as computing platforms or microprocessors, other embodiments are applicable to other types of integrated circuits and logic devices. Similar methods and teachings of embodiments described herein may be applied to other types of circuits or semiconductor devices that could also benefit from improved energy efficiency and energy conservation. For example, the disclosed embodiments are not limited to desktop computing systems or Ultrabooks™ and may also be used in other devices, such as handheld devices, tablets, other thin notebooks, system-on-chip (SOC) devices, and embedded applications.Some examples of handheld devices include mobile phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include a microcontroller, a digital signal processor (DSP), a system on a chip, network computers (NetPCs), set-top boxes, network hubs, wide-area network (WAN) switches, or any other system capable of performing the functions and operations taught below. Furthermore, the methods and systems of the device described herein are not limited to physical computing devices but may also address software optimizations for power conservation and efficiency.As will be readily apparent from the following description, the embodiments of methods, apparatus, and systems described herein (whether with respect to hardware, firmware, software, or a combination thereof) are essential to future balancing of 'green technology' and performance considerations.

[0008] As computer systems advance, the components they contain become more complex. As a result, the complexity of the interconnect architecture used to couple these components and enable communication between them also increases, ensuring that the necessary bandwidths for optimal component operation are achieved. Furthermore, different market segments require different aspects of interconnect architectures to meet market needs. For example, servers require higher performance, while the mobile ecosystem is sometimes able to sacrifice overall performance for power savings. Nevertheless, a singular purpose of most structures is to provide the highest possible performance with maximum power savings. Discussed below are several interconnects that would potentially benefit from aspects of the invention described herein.

[0009] One interconnect architecture includes the Peripheral Component Interconnect (PCI) Express (PCIe) architecture. A primary goal of PCIe is to enable the interoperability of components and devices from different vendors in an open architecture spanning multiple market segments: clients (desktop and mobile), servers (standard and enterprise), and embedded and communications devices. PCI Express is a high-performance, general-purpose I / O interconnect defined for a wide variety of future computing and communications platforms. Some PCI attributes, such as its usage model, load-store architecture, and software interfaces, have been retained through its revisions, while previous parallel bus implementations have been replaced by a highly scalable, fully serial interface.The newer versions of PCI Express leverage the advantages of point-to-point interconnects, switch-based technology, and a packetized protocol to deliver new levels of performance and features. Power management, Quality of Service (QoS), hot-plug / hot-swap support, data integrity, and error handling are among the advanced features supported by PCI Express.

[0010] Referring to Fig.Figure 1 illustrates one embodiment of a structure consisting of point-to-point data links interconnecting a set of components. System 100 includes a processor 105 and system memory 110 coupled to a controller hub 115. Processor 105 includes any processing element, such as a microprocessor, a host processor, an embedded processor, a coprocessor, or another processor. Processor 105 is coupled to controller hub 115 by a front side bus (FSB) 106. In one embodiment, FSB 106 is a point-to-point serial interconnect as described below. In another embodiment, data link 106 includes a serial, differential interconnect architecture compatible with another interconnect standard.

[0011] System memory 110 includes any memory device, such as random access memory (RAM), non-volatile (NV) memory, or other memory accessible to the devices in system 100. System memory 110 is coupled to controller hub 115 through a memory interface 116. Examples of a memory interface include a double data rate (DDR) memory interface, a dual-channel DDR memory interface, and a dynamic random access memory (DRAM) interface.

[0012] In one embodiment, controller hub 115 is a root hub, root complex, or root controller in a Peripheral Component Interconnect Express (PCIe or PCIE) interconnect hierarchy. Examples of controller hub 115 include a chipset, a memory controller hub (MCH), a northbridge, an interconnect controller hub (ICH), a southbridge, and a root controller / hub. Often, the term chipset refers to two physically separate controller hubs, i.e., a memory controller hub (MCH) coupled to an interconnect controller hub (ICH). It is noted that current systems often include the MCH integrated with processor 105, while controller 115 is intended to communicate with I / O devices in a manner similar to that described below. In some embodiments, peer-to-peer routing is optionally supported by root complex 115.

[0013] Here, the controller hub 115 is coupled to a switch / bridge 120 through a serial connection 119. Input / output modules 117 and 121, which may also be referred to as interfaces / ports 117 and 121, comprise / implement a layered protocol stack to provide transmission between the controller hub 115 and the switch 120. In one embodiment, multiple devices may be coupled to the switch 120.

[0014] The switch / bridge 120 routes packets / messages from a device 125 upstream, ie, upward in a hierarchy toward a root complex, to the controller hub 115 and downstream, ie, downward in a hierarchy away from a root controller, from the processor 105 or system memory 110 to the device 125. The switch 120, in one embodiment, is referred to as a logical arrangement of multiple virtual PCI-to-PCI bridge devices.Device 125 includes any internal or external device or component to be coupled to an electronic system, such as an I / O device, a network interface controller (NIC), an add-in card, an audio processor, a network processor, a hard disk, a storage device, a CD / DVD-ROM, a display, a printer, a mouse, a keyboard, a router, a portable storage device, a FireWire device, a Universal Serial Bus (USB) device, a scanner, and other input / output devices. For example, in PCIe terminology, a device is often referred to as an endpoint. Although not specifically shown, device 125 may include a PCIe-to-PCI / PCI-X bridge to support older or other versions of PCI devices. Endpoint devices are often classified within PCIe as legacy, PCIe, or root complex integrated endpoints.

[0015] A graphics accelerator 130 is also coupled to the controller hub 115 through a serial connection 132. In one embodiment, the graphics accelerator 130 is coupled to an MCH, which is coupled to an ICH. The switch 120, and accordingly, the I / O device 125, is then coupled to the ICH. The I / O modules 131 and 118 are also intended to implement a layered protocol stack to communicate between the graphics accelerator 130 and the controller hub 115. Similar to the MCH discussion above, a graphics controller or the graphics accelerator 130 may be integrated into the processor 105. Furthermore, one or more data connections (e.g., 123) of the system may include one or more extension devices (e.g., 150), such as retimers, repeaters, etc.

[0016] Referring to Fig.2 illustrates one embodiment of a layered protocol stack. A layered protocol stack 200 includes any form of layered communication stack, such as a QuickPath Interconnect (QPI) stack, a PCIe stack, a next-generation high-performance computing interconnect stack, or another layered stack. Although the discussion immediately below will be with reference to the Fig. 1-4 refer to a PCIe stack, the same concepts can be applied to other interconnect stacks. In one embodiment, protocol stack 200 is a PCIe protocol stack that includes a transaction layer 205, a data link layer 210, and a physical layer 220. An interface, such as interfaces 117, 118, 121, 122, 126, and 131 in Fig.1, can be represented as a communication protocol stack 200. The representation as a communication protocol stack can be referred to as a module or interface that implements / includes a protocol stack.

[0017] PCI Express uses packets to send information between components. Packets are formed in the transaction layer 205 and the data link layer 210 to carry information from the sending component to the receiving component. As the transmitted packets flow through the other layers, they are augmented with additional information necessary to process the packets at those layers. On the receiving side, the reverse process occurs, and the packets are converted from their physical layer 220 representation to the data link layer 210 representation, and finally (for transaction layer packets) to the form that can be processed by the transaction layer 205 of the receiving device. Transaction layer

[0018] In one embodiment, the transaction layer 205 is intended to provide an interface between the processing core and the interconnect architecture, such as the data link layer 210 and the physical layer 220. In this regard, a primary task of the transaction layer 205 is the packetization and depacketization of packets (i.e., transaction layer packets, or TLPs). The transaction layer 205 typically manages credit-based flow control for TLPs. PCIe implements split transactions, i.e., transactions where the request and response are separated in time, allowing a data link to carry other traffic while the device gathers data for the response.

[0019] In addition, PCIe uses credit-based flow control. In this scheme, an initial amount of credits is announced for each of the receiver buffers in the transaction layer 205. An external device at the opposite end of the data link, such as the controller hub 115 in Fig. 1, counts the number of credits consumed by each TLP. A transaction can be committed if the transaction does not exceed a credit limit. Upon receipt of a response, a credit amount is restored. One advantage of a credit scheme is that the latency of credit return does not affect performance, provided the credit limit is not reached.

[0020] In one embodiment, four transaction address spaces include a configuration address space, a memory address space, an input / output address space, and a message address space. Memory space transactions include one or more read requests and write requests to transfer data to / from a memory-mapped location. In one embodiment, memory space transactions are capable of using two different address formats, e.g., a short address format, such as a 32-bit address, or a long address format, such as a 64-bit address. Configuration space transactions are used to access the configuration space of PCIe devices. Configuration space transactions include read requests and write requests. Message space transactions (or simply messages) are defined to support in-band communication between PCIe agents.

[0021] Thus, in one embodiment, the transaction layer 205 packetizes a packet header / payload 206. The current packet header / payload format can be found in the PCIe specification on the PCIe specification website.

[0022] Briefly on Fig. Referring to Figure 3, an embodiment of a PCIe transaction descriptor is illustrated. In one embodiment, a transaction descriptor 300 is a mechanism for carrying transaction information. In this regard, the transaction descriptor 300 supports the identification of transactions in a system. Other potential uses include tracking modifications to the default transaction order and the mapping of transactions to channels.

[0023] The transaction descriptor 300 includes a global identifier field 302, an attribute field 304, and a channel identifier field 306. In the illustrated example, the global identifier field 302 is shown as comprising a local transaction identifier field 308 and a source identifier field 310. In one embodiment, the global transaction identifier 302 is unique for all outstanding requests.

[0024] According to one embodiment, the local transaction identifier field 308 is a field generated by a requesting agent and is unique for all outstanding requests requiring completion for that requesting agent. Furthermore, in this example, the source identifier 310 uniquely identifies the requesting agent within a PCIe hierarchy. Accordingly, the local transaction identifier field 308, together with the source ID 310, provides a global identification of a transaction within a hierarchy domain.

[0025] The attribute field 304 specifies properties and relationships of the transaction. In this regard, the attribute field 304 is optionally used to provide additional information that allows modification of the standard processing of transactions. In one embodiment, the attribute field 304 includes a priority field 312, a reserved field 314, an ordering field 316, and a non-snoop field 318. Here, the priority subfield 312 can be modified by an initiator to assign a priority to the transaction. The reserved attribute field 314 remains reserved for future or provider-defined use. Possible usage models using priority or security attributes can be implemented using the reserved attribute field.

[0026] In this example, ordering attribute field 316 is used to provide additional information conveying the ordering type, which may modify the default ordering rules. According to an example implementation, an ordering attribute of "0" means that the default ordering rules apply, while an ordering attribute of "1" means relaxed ordering, where writes can pass other writes in the same direction and read completions can pass writes in the same direction. Snoop attribute field 318 is used to determine whether transactions are being snooped. As shown, channel ID field 306 identifies a channel to which a transaction is associated. connection layer

[0027] The link layer 210, also referred to as the data link layer 210, acts as an intermediate layer between the transaction layer 205 and the physical layer 220. In one embodiment, the function of the data link layer 210 is to provide a reliable mechanism for exchanging transaction layer packets (TLPs) between two components of a data link. One side of the data link layer 210 accepts TLPs packetized from the transaction layer 205, uses packet sequence identifiers 211 (i.e., an identification number or packet number), calculates and uses an error detection code (CRC) 212, and presents the modified TLPs to the physical layer 220 for transmission over a physical device to an external device. Physical layer

[0028] In one embodiment, physical layer 220 includes a logical subblock 221 and an electrical subblock 222 for physically transmitting a packet to an external device. Here, logical subblock 221 is responsible for the "digital" functions of physical layer 221. In this regard, the logical subblock includes a transmitter section for preparing outgoing information for transmission by physical subblock 222 and a receiver section for identifying and preparing received information before passing it to data link layer 210.

[0029] The physical block 222 includes a transmitter and a receiver. The transmitter is supplied with symbols from the logical subblock 221, which the transmitter serializes and transmits to an external device. The receiver is supplied with serialized symbols from an external device and converts the received signals into a bit stream. The bit stream is deserialized and provided to the logical subblock 221. In one embodiment, an 8b / 10b transmission code is used, in which 10-bit symbols are transmitted / received. Here, special symbols are used to form a packet with frames 223. In addition, in one example, the receiver also provides a symbol clock obtained from the incoming serial stream.

[0030] As mentioned above, although the transaction layer 205, the data link layer 210, and the physical layer 220 are discussed with reference to a specific embodiment of a PCIe protocol stack, a layered protocol stack is not so limited. Indeed, any layered protocol may be included / implemented. As an example, a port / interface represented as a layered protocol includes: (1) a first layer to packetize packets, i.e., a transaction layer; a second layer to sequence packets, i.e., a data link layer; and a third layer to send the packets, i.e., a physical layer. As a specific example, a Common Standard Interface (CSI) layered protocol is used.

[0031] Next on Fig.4, an embodiment of a PCIe point-to-point structure is illustrated. Although an embodiment of a PCIe point-to-point data link is illustrated, a serial point-to-point data link is not limited to including any transmission path for transmitting serial data. In the embodiment shown, a basic PCIe data link includes two differently controlled low-voltage signal pairs: a transmit pair 406 / 411 and a receive pair 412 / 407. Accordingly, device 405 includes transmit logic 406 to send data to device 410 and receiver logic 407 to receive data from device 410. In other words, two transmit paths, i.e., paths 416 and 417, and two receive paths, i.e., paths 418 and 419, are included in a PCIe data link.

[0032] A transmit path refers to any path for transmitting data, such as a transmission line, a copper line, an optical line, a wireless communication channel, an infrared communication data link, or another communication path. A connection between two devices, such as device 405 and device 410, is referred to as a data link, such as data link 415. A data link may support one lane—each lane representing a set of differential signal pairs (one pair for transmitting, one pair for receiving). To scale bandwidth, a data link may combine multiple lanes denoted by xN, where N is any supported data link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider.

[0033] A differential pair refers to two transmission paths, such as lines 416 and 417, for transmitting differential signals. For example, when line 416 transitions from a low voltage level to a high voltage level, i.e., a rising edge, line 417 transitions from a high logic level to a low logic level, i.e., a falling edge. Differential signals may exhibit better electrical characteristics, such as better signal integrity, i.e., crosstalk, overshoot / undershoot, ringing, etc. This allows for a better timing window, which allows for faster transmission frequencies.

[0034] In some implementations, a data link, such as a PCIe-compliant data link, may include one or more retimers or other extension devices, such as a repeater. A retimer device (or simply "retimer") may include active electronics and receive and retransmit (reclock) digital I / O signals. Retimers may be used to extend the length of a channel usable with a digital I / O bus. Retimers may be protocol-aware, software-transparent, and capable of performing a data link balancing technique, such as PCIe's data link balancing technique. A data link incorporating one or more retimers may form two or more separate electrical subdata links whose data rates are comparable to the data rates of data links employing similar protocols but not including retimers.For example, a data link comprising a single retimer may form a data link with two separate sub-data links, each operating at 8.0 GT / s or more.

[0035] Other extension devices exist, but some have compatibility issues with certain communication protocols. For example, some repeaters may not support the PCIe 3.0 data link balancing protocol. Furthermore, some applications tend to use channels with longer physical lengths, which require extension devices to implement such channel lengths. These and other trends have made retimers increasingly important in many systems.

[0036] Fig. 5A-5B illustrate simplified block diagrams 500a-b of example data connections including one or more retimers. For example, in Fig.5A, a data connection connecting a first component 505 (e.g., an upstream component) to a second component 510 (e.g., a downstream component) may include a single retimer 515a. A first subdata connection 520a may connect the first component 505 to the retimer 515a, and the second subdata connection 520b may connect the retimer 515a to the second component. As shown in Fig. As shown in Figure 5B, multiple retimers 515a, 515b can be used to extend a data connection. Three subdata connections 520a-cf can be defined by two retimers 515a, 515b, where a first subdata connection 515a connects the first component to the first retimer 515a, a second subdata connection 515c connects the first retimer 515a to the second retimer 515b, and the third subdata connection 515c connects the second retimer 515b to the second component.

[0037] As in the examples of Fig.As shown in Figures 5A-5B, a retimer may include two pseudo-ports, and the pseudo-ports may dynamically determine their corresponding downstream / upstream orientation. Each retimer 515a, 515b may support operating modes including a forwarding mode and an execution mode. Further, the retimers 515a, 515b may support operating modes including a forwarding mode and an execution mode. A retimer 515a, 515b may, in some cases, decode data received over the sub-data connection and re-encode the data it is to send downstream over its other sub-data connection. In some cases, the retimer may modify some values ​​in the data it receives, such as when processing and forwarding ordered set data. In addition, a retimer may optionally support any width option as the maximum width, such as a set of width options defined by a specification such as PCIe.

[0038] In some cases, errors may occur on a channel. When using one or more retimers, a data link spans multiple subdata links, and a failure on one of the subdata links may result in a failure being detected for the entire data link. A test mode may be provided that allows the determination of a system-internal fault finding at the subdata link level, so that the specific subdata link error is identified in a data link spanning one or more retimers. The identification of the affected subdata link may be used in a troubleshooting procedure performed for the data link.

[0039] The Fig.6A-6E illustrate example block diagrams 600a-e, which show example implementations of a test mode for determining which of the electrical sub-data connections in a channel are generating errors in the channel. In the example of Fig. 6A, test mode may be entered, and the test mode may define a standardized signal to be sent over a channel between a downstream port 605 (e.g., a first endpoint) and an upstream port 610 (e.g., another endpoint) and via a retimer 615. A first endpoint (e.g., 605) (such as a trunk port) may send a signal including a defined data sequence 620a followed by an error reporting sequence 625a. The retimer 615 receives the signal 630 and determines whether the sequence 620a matches the expected sequence. If the sequence 625a does not match the sequence defined for the test mode, the retimer 615 shall identify the deviation as an error.

[0040] After receiving signal 630, retimer 615 may in turn generate another signal 635 associated with the test mode. In one implementation, retimer 615 is intended to reproduce the same defined sequence (at 620b) in signal 635. Retimer 615 does not reproduce sequence 620a as received in signal 630, but rather generates the sequence anew (e.g., 620b) as defined for the test mode. This can serve to isolate sub-data link errors so that the error-containing sequence is not transmitted over the channel, making it difficult to identify the source of the error (e.g., which sub-data link). However, the information encoded in the error reporting sequence (e.g., 625a, 625b) is intended to be retained in each signal sent in test mode so that the error detection results are passed from device to device within the test mode. In addition, the information encoded in each error reporting sequence (e.g.,625a, 625b) may be updated as further errors are detected within subdata links of the channel. For example, after receiving and analyzing sequence 620a for errors, retimer 615 may encode at least a portion of error report sequence 625b to identify whether one or more errors were detected at retimer 615 for a subdata link connecting endpoint 605 and retimer 615. This information may be in addition to other information described in the previously received error report sequence 625a.

[0041] Continuing with the example of Fig.6A, the retimer 615 may send signal 635, which includes the updated error reporting sequence 625b and the newly generated sequence 620b. A second endpoint 610 may receive signal 635 and analyze sequence 620b for discrepancies (e.g., one or more incorrect bits that deviate from the sequence defined for the test mode), thereby identifying an error or fault condition on the subdata link between the retimer 615 and the endpoint 610 based on any identified discrepancies. The second endpoint may further decode the error reporting sequence 625b to identify which (if any) of the subdata links generated an error during the test. Errors may, in some cases, be captured in one or more registers for, among other things, later processing and analysis by data link testing and management tools.

[0042] Now to the example in Fig.6B, in some implementations, a loopback state may be used to implement a test mode. In some cases, the use of a loopback test mode may help overcome potential backward compatibility issues. In many cases, the endpoints and / or retimers on a channel may be provided by different manufacturers, vendors, etc. One or more of the endpoint devices may not have the logic to support the test mode (e.g., detect errors in a test sequence, update error report sequence data, update subdata link error registers, etc.), while nevertheless supporting a loopback mode, such as a loopback mode defined according to an interconnect protocol used by devices in the channel (e.g., PCIe).Among other example implementations, a particular endpoint that does not support test mode can return error report sequences generated and received by upstream components (e.g., the other endpoint and the retimer), allowing one or more of these components to observe and process test mode results even though that particular endpoint does not fully support test mode.

[0043] In Fig. 6B, signals 630 and 635 are sent from a first endpoint 605 to a retimer 615 and from the retimer 615 to the second endpoint 610, respectively, for example as in the example of Fig.6A. The test mode may be implemented in a loopback state such that when the signal 635 reaches the second endpoint 610, the signal is looped back by a signal 640 sent from the second endpoint 610 to the retimer 615. The signal 640 may include the regeneration of the sequence 620c and an error reporting sequence 625c that includes error detection information from the analysis of the sequences 620a and 620b in the signal. The retimer 615 may analyze the sequence 620c for errors. The error status of the subdata connection between endpoint 610 and retimer 615, as detected by retimer 615 from received sequence 620c, may be communicated in an updated error report sequence 625d included in signal 645, which may also be another instance of sequence 620d as generated by retimer 615 and sent to endpoint 605.

[0044] In the example of Fig.6B, endpoint 605 may perform final error analysis in the test loopback by analyzing sequence 620d received in test mode signal 645. Furthermore, endpoint 605 may interpret error reporting sequence 625d to identify the results of analyses of sequences 620a, 620b, 620c, 620d during the loopback. Error conditions in the specific subdata links between endpoints 605 and 610 and retimer 615 may be identified from the information contained in error reporting sequence 625d. Among other things, additional logic at endpoint 605 (and optionally also (or alternatively) at endpoint 610 or retimer 615) may report the subdata link error status to a register (e.g., corresponding to the channel) or other data structure or logic for use in data link analysis and error recovery.

[0045] Referring to Fig.6C, error report sequences (e.g., 625a-d) may, in some implementations, comprise a series of error report data records (or "segments"), where each error report segment corresponds to at least one of the sub-data connections in a channel that connects one or more retimers (e.g., 615) and two endpoints 605, 610. For example, in the example of Fig. 6B error conditions are reported three times (e.g., at 625b, 625c, 625d, the analysis of sequences 620a, 620b, 620c is summarized). Accordingly, at least three segments may be provided in each of the error report sequences 625a-b. For example, as in the example of Fig.6C illustrates that the results of the analysis of sequence 620a are reflected by encoding the results in segment "Err1" included in error report sequence 625b. The encoding of the error report segment Err1 (by retimer 615) and the error status information described by the encoding can effectively be passed by endpoint 610 in error report sequence 625c. For example, endpoint 610 can re-encode Errl of error report sequence 625c with the same encoding included in Errl of error report sequence 625b. Furthermore, endpoint 610 can identify that the results of its analysis (e.g., of the received sequence 620b) are to be encoded in a different segment of the error report sequence, in this example, "Err2" in error report sequence 625c. Among other things, the next error report sequence 625d (e.g.,generated by the retimer 615) may equally comprise the same encodings of Errl and Err2 as comprised in the error report sequence 625c, in order to transmit the reported analysis results to the endpoint 605, together with the results of the analysis of the sequence 620c performed by the retimer 615, which were described in the encoding of the retimer of a corresponding error report segment “Err3”.

[0046] Error report sequences or other error report data can be formatted and encoded in a variety of ways to progressively document the error status of subdata links of a channel during a test mode. As in the example of Fig.6C, error reporting data may be segmented in some implementations, with each segment dedicated to describing the error status information of a particular subdata link of the channel. In some implementations, error reporting sequences may be preconfigured based on the structure of the data links they are to describe. For example, if a loopback test mode is to be provided for a data link using two retimers (and thus three subdata links in each direction), at least five error reporting segments may be defined. On the other hand, for a data link using a single retimer (and two subdata links), an error reporting sequence comprising at least three segments for testing the data link may be defined, and so on.In some cases, a common error reporting sequence may be defined that includes a set of segments corresponding to a maximum number of subdata links supported for test mode. In still further examples, the segmentation and structure of error reporting sequences may be determined dynamically, for example, by analyzing the data link for a set of expansion devices and subdata links, among other things.

[0047] As in some of the previous examples, an error reporting sequence may in some cases be implemented as a sequence of segments, where each of the segments corresponds to an error detection for a respective sub-data connection in a channel. Furthermore, separate segments may be statically assigned to an upstream part of the channel associated with the sub-data connection and to the downstream part of the channel associated with the same sub-data connection. In other cases, the error reporting sequence segments may be dynamically mapped or assigned to sub-data connection error reporting results. For example, segments may be assigned based on arrival order, with the error reporting results of a first evaluation occupying the first segment, results of a second evaluation occupying the second segment, etc. In some implementations, a test mode may be used in both directions of the data connection, so that the test mode sequence (e.g.620) is sent upstream first on the data connection in some cases and downstream first on the same data connection in other cases. In such cases, it may be, among other things, that the error score of the first subdata connection is reported first in some tests (e.g., and reported in the Errl segment), and in other cases, the score of another subdata connection may be reported first instead (e.g., in the Errl segment).

[0048] In some implementations, an ordered set, training sequence, or other defined data sequence of an existing protocol, such as PCIe, PCI, QPI, etc., may be leveraged for use in a test mode. For example, the defined test mode sequence (e.g., 620) transmitted over each sub-data link may be defined as including a defined sequence of an interconnect protocol. For example, in some implementations, a PCIe electrical idle ordered set (EIOS), an electrical idle output sequence ordered set (EIEOS), a modified compliance pattern, or other pattern or ordered set may be used or included in the defined test mode sequence. In some cases, defined ordered sets or other sequences may be modified or extended for use in or as the error reporting data (e.g., 625).Leveraging a defined, existing ordered set or other sequence for error reporting can help achieve high interoperability, allowing legacy devices to accept and validate signals in some cases, even if the device lacks the logic contained in the known ordered set to accurately interpret specific error encodings. For example, an implementation might use PCIe-SKP ordered sets (SKP-OS) or another ordered set. For example, as shown in the examples in [ ]. Fig. 6D and Fig. As shown in Figure 6E, a sequence of ordered records (e.g., OS1-OS6) can be used as the segments in an exemplary error report sequence (e.g., 625). Each ordered record can provide one or more fields, symbols, bytes, etc., in which error report results can be encoded.

[0049] In the example of Fig.6D, an exemplary data connection connects a root port 650 to a particular endpoint 655 and includes two retimers 660, 665. Three subdata connections 675a, 675b, 675c may connect the root port 650 to the first retimer 660, the first retimer 660 to the second retimer 665, and the second retimer 665 to the endpoint device 655. In the example in the Fig. 6D and Fig.6E may include a register of data defining which of the ordered sets (e.g., OS1-OS6) corresponds to which subdata link channel within a test mode. The fixed test mode sequence / pattern (e.g., 620) to be included in each test mode signal (e.g., 670a-670f) may also be preassigned such that each device (e.g., 650, 655, 660, 665) on the data link, upon entering a test mode, is configured to evaluate whether pattern 620 was successfully transmitted over each subdata link channel. As in previous examples, if the received pattern deviates from the expected pattern, the receiving / evaluating device may encode the error report segment (e.g., OS1-OS6) corresponding to the subdata link with information describing the errors.Such information may include, for example, the number of errors received over the subdata link, the block and / or bit in which the first error was detected, and the lane of the subdata link in which the error was detected. This ordered set containing the error report may be forwarded by subsequent devices on the data link to preserve the error evaluation results of the respective subdata link, as provided by the device on the receiving side of the respective subdata link.

[0050] To illustrate, in the example of Fig.6D, a first signal 670a is transmitted, comprising the test mode pattern 620 and segments of an error report sequence 625 associated with a test mode implemented using a loopback state of the system. Since the initial signal 670a is transmitted before an error has been evaluated, the portions of the segments (e.g., OS1-OS6) of an error report sequence 625 to be encoded with error results may be transmitted empty (or encoded to indicate that an error report from each sub-data link channel remains to be completed). A first retimer 660 may receive the signal 670a and evaluate whether the test mode pattern deviates from what is expected. In this example, the test mode pattern 620 is transmitted error-free over the downstream channel of the first sub-data link 675a.The retimer 660 may identify that a first ordered set OS1 is to be used for documenting errors for the downstream channel of the first sub-data connection 675a ​​and encode the error report sequence segment OS1 accordingly to indicate that no errors were detected on the downstream channel of the first sub-data connection 675a. The loopback test mode may continue by the retimer 660 re-forming the test mode pattern and including it in the signal 670b along with the error report sequence data comprising the encoded results of the evaluation of the first sub-data connection 675a ​​in OS1 (e.g., showing "no" errors).

[0051] As in the example of Fig.6D, in the case of signal 670b, the pattern as received by second retimer 665 includes an error. The error may be evidenced by one or more bits of the received pattern deviating from the expected value of the pattern. Such errors may be caused by a variety of potential disturbances on the sub-data link, including the transmitting device (e.g., 660), the receiving device (e.g., 665), or traces of the sub-data link itself (e.g., 675b). Accordingly, in this example, second retimer 665, upon generating and transmitting subsequent test mode signal 670c, may identify that error results for the downstream channel of second sub-data link 675b are to be encoded in ordered set OS2 of the error report sequence included in signal 670c. Accordingly, the second retimer 665 may encode OS2 in signal 670c to describe the errors detected for the downstream channel of the second sub-data connection 675b.Additionally, the retimer 665 may ensure that the encoding of the ordered set OS1 in the error reporting sequence of the signal 670c is re-encoded / repeated to include the same encoding as that received in OS1 of the test mode signal 670b. The test mode signal 670c may then be sent to the endpoint 655 via the downstream channel of the sub-data link 675c, and the endpoint 655 may evaluate the fixed test mode pattern included in the signal 670c to identify that the pattern was received error-free via the downstream channel of the sub-data link 675c.

[0052] Continuing with the previous example, subsequent test mode signals (e.g., 670d-670e) may be transmitted over upstream channels of subdata links 675c, 675b, 675a ​​in accordance with a loopback of the test mode signal sequence. In this example, the only other identified errors are in the pattern of the test mode signal 670d transmitted on the upstream channel of subdata link 675c. Accordingly, subsequent test mode signals (e.g., 670e, 670f) may reflect the earlier detection of this error in the error report segment (e.g., OS4) corresponding to the downstream channel of the third subdata link 675c.

[0053] Upon receiving the loopback test mode sequence (at signal 670f), the parent port or another component may identify the error information documented in the error reporting sequence segments OS1-OS6 to identify where and what errors occurred on a subdata link-by-subdata link basis. In an example implementation, one or more control status registers may be maintained for the devices (e.g., 650, 655, 660, 665), subdata links (e.g., 675a-675c), and / or subdata link channels, as well as (or alternatively) for the data link as a whole. Error information included in the error reporting sequence segments OS1-OS6 may be used to populate the registers with error information.The error information in these registers can be tracked to perform evaluations of the subdata links and the devices attached to each subdata link to identify fault conditions or other problems on the data link.

[0054] In an example implementation, one or more control status registers may be defined. A data link resource register may be provided, which includes one or more bits to identify whether loopback test mode is supported for a sub-data link channel (or a device on a sub-data link), and one or more bits may also identify which level of error detection resources are available in the channel (e.g., block-level, bit-level, trace-level, etc.). A data link control register may be provided, which includes fields that can be set to indicate that a test mode has been entered and how a particular device should function during the test mode (e.g., regenerating a particular specified test mode sequence followed by a particular number of error reporting segments, etc.).An error log register may also be provided for use in conjunction with error report sequence data generated during a test. The error log register may, in one example, include the following fields: . TABLE 1 Field Description LFSR Seed [22:0] LFSR value in lane 0 at the beginning of the data block (SKP-OS or SDS) in which the first error occurred First Error Location[16:0] {Block No. [8:0], Bit No. [7:0]}, in which the first error was detected First Error Lane[3:0] Track ID in which the first error occurred First Error SubLink[3:0] Subdata connection ID in which the first error occurred Error SubLink(5:0] Subdata connections identified as containing an error Lane_Error_Status[15:0] A register used to track further errors after the first error

[0055] In some implementations, a loopback test mode (or test mode) may be supported in both directions of a data link that includes one or more retimers (or other extension devices). For example, as in the example of Fig.6E, a loopback test mode may alternatively begin at endpoint 655 and loop back to the trunk port 650 to endpoint 655. For example, endpoint 655 may transmit a first signal 680a under test that includes test mode pattern 620 and an error report sequence that includes six segments of ordered sets (e.g., OS1-OS6). In this example, the error report segments OS1-OS6 may have the same subdata link channel assignments as in the example of Fig.6D. For example, the retimer 665 can report the error evaluation performed on the pattern of the first signal 680a in the loopback by encoding the error report segment assigned to the upstream channel of the sub-data link 675c (e.g., OS4) and transmitting the signal 680b containing the encoded segment. Next, the retimer 660 receives the signal 680b and evaluates whether the pattern contains errors. The retimer 660 encodes its test results in the error report segment assigned to the upstream error report segment of the sub-data link 675b (e.g., OS5) and adds the encoded error report segment to the error report sequence included in the test mode signal 680c. As in the example of Fig.6D, this test sequence continues using signals 680d-680f to test (and report the results for) the remaining subdata link channel(s). The results of the test can ultimately be passed to endpoint 655 via signal 680f. In addition, as in the example of Fig.6D, the final subdata link test may be performed on the device receiving the final test mode signal (e.g., 670f, 680f), although the results of that test may not be included in any of the test mode signals. Accordingly, in some cases, the error report segment assigned to the last subdata link channel under test may remain empty in the test mode sequence (since the results are obtained directly from the device (e.g., 650, 655) performing the test on the final test mode signal (e.g., 670f, 680f). In some cases, unused error report segments may be encoded for purposes other than error reporting, such as, among other things, to maintain DC uniformity across the series of error report segments.

[0056] As in the examples in Fig. 6D and Fig.6E, each upstream and downstream channel of the subdata connections to be tested (e.g. 675a-c) can be assigned a corresponding error report sequence segment (e.g. OS1-OS6), which (in the Fig. 6D and Fig. 6E) results in a six-segment error reporting sequence. In some implementations, each subdata link may be assigned multiple error reporting sequence segments, further extending the length of the test mode signals. For example, each subdata link channel may be assigned two or more error reporting segments (e.g., to enable the encoding of more detailed error status information associated with the test of each subdata link channel).

[0057] Alternative embodiments may, instead of statically assigning specific ordered sets in the error reporting sequence to sub-data link channels, provide a set of segments that can be assigned or used when entering test mode according to the parameters of the test. For example, in one example, the error reporting segments provided in the test mode signals may be used according to the order in which the sub-data link channels are tested. For example, regardless of which sub-data link is to be tested first during the loopback test mode, the results would be encoded into a segment designated for the first-performed test results (e.g., OS1). For example, using such an approach in the example of Fig.6E, the error evaluation results for the first test mode pattern in signal 680a would be encoded in OS1, the second error evaluation of signal 680b would be encoded in OS2, and so on. However, if the loopback test mode is performed starting with a test of the subdata connection 675a, as in the example of Fig. 6D, the test results for the pattern in sequence 670a would be encoded in OS1, the test results for the pattern in sequence 670b would be encoded in OS2, and so on. In such an alternative implementation, among other things, instead of providing dedicated error reporting segments for each sub-data link channel, the error reporting sequence may provide error reporting segments according to the number of reported test results to be generated (e.g., using five instead of six segments to support a data link with two expansion devices).

[0058] In one illustrative example, a test mode may be provided in a PCIe-compliant system, and may be entered by performing a PCIe loopback entry. In some implementations, a control signal may be sent to place the data link (including one or more expansion devices) into a loopback and also indicate that the loopback is a test mode loopback. In other cases, one or more bits of training sequences and / or framing tokens may be used to manage entry into the test mode loopback state.In some cases, one or more bits of training sequences used to transition to the loopback state may include one or more bits encoded to indicate that the loopback state is a test mode loopback state, such as one that implements the principles of the example test modes described herein. Furthermore, the test mode loopback signaling may begin with the transmission of an EIEOS, followed by a start of data, followed by a start of data stream (SDS) ordered sentence, indicating a Loopback.Active state. The EIEOS-SDS sequence may, in one example, serve as the specified test mode pattern to be evaluated for each subdata connection. The test mode may be defined such that the only patterns allowed in the data block are data_in = 0 (e.g.,The LFSR standard output includes a sequence of SKP-OS-containing segments of the error reporting sequence included in each test mode signal sent from subdata link to subdata link. In an embodiment where a series of six consecutive SKP-OSs is defined, the sequence of SKP-OSs may be sent at exactly the 370 block interval. Each device on the data link may be aware of the test mode signals and expect to proceed accordingly (except for some devices that are not equipped with the logic to decode error reporting information encoded in the SKP-OS variants used in the test mode signals). Architectures may support different timing architectures, and some of them may require SKP-OSs to be transmitted at different nominal rates.For example, in the case of a Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) architecture, the six SKP OSs can be scheduled after 37 data blocks.

[0059] Fig.Figure 7 illustrates a representation of an exemplary PCIe SKP ordered set 700 that has been extended to support the loopback test mode described above. For example, symbols 0 through (4*N-1) may correspond to the standard SKP symbol. The symbol 4*N may be the standard SKP_END symbol, which warns that only three more symbols are included in the present SKP OS. The last three symbols 705, 710, 715 may be reserved for encoding information corresponding to a specific use case of the SKP OS. In some cases, the standard SKP symbols preceding SKP symbols 705, 710, 715 (along with the test mode pattern) may be tested for errors. These standard SKP symbols may be considered part of the test mode pattern in such cases. In some cases, the correct format of symbols 705, 710, 715 (e.g.,4*N+1, 4*N+2, 4*N+3) based on the data link training state (LTSSM) of the data link. In one example, the SKP symbols 705, 710, 715 may be defined to be encoded for reporting sub-data link test results when the data link state is in a loopback. In one example, the 24 data bits included in the SKP symbols 705, 710, 715 may implement an error reporting segment for a sub-data link and may be adapted for encoding error reporting results according to the following format: . TABLE 2 Bit [0] Set to 1b to indicate that the subdata connection "owns" this SKP Bits[9:1] Number of the block in which the first error occurred: all 1s indicate no error. The block number can be counted from the ordered set after the SDS or the last SKP-OS that claimed the subdata connection. Bits[17:10] Bit number in which the first error occurred: No error is 8'h03 Bits[21:18] Total number of bit errors (error count) (>0 if Bit[1]=1b, a value of 15 indicates >= 15 errors were received in this sequence) Bit

[22] 1b, if the subdata connection has lost the block arrangement Bit

[23] Even-numbered check bit (e.g., XOR of bits [22:0])

[0060] It should be understood that the implementations described above are provided as non-limiting examples, presented merely to conveniently illustrate some of the features disclosed herein. For example, a test mode may be provided that conforms to an interconnect protocol other than PCIe (e.g., QPI, IDI, PCI, etc.) and that leverages some of the features defined in the protocol (e.g., ordered sets, training sequences, data link states, etc.). Furthermore, it should be understood that, although retimers were frequently cited in the above examples, some of the principles and features described herein are equally applicable to systems employing other types of expansion devices.In addition, other test mode signals, fixed test mode patterns, and error reporting sequences, among others, may be implemented beyond the specific examples provided herein without departing from the scope of the concepts disclosed in this description. In-band separation detection

[0061] Retimers and other extension devices may be used in a variety of different systems employing a variety of different features and form factors. For example, some systems may allow hot-plugging of devices on a data link comprising one or more retimers. In some examples, retimers may be used in cables, and such cables may be designed to support hot-plugging and other uses. In some cases, retimers may be implemented in some applications that do not provide sideband signals and / or other support logic that provides out-of-band data connect / disconnect signaling. In addition, retimers may be poorly or incapable of handling disconnection and reconnection on a data link of which they are a part, thereby limiting the use of such retimers. Accordingly, less robust extension devices (e.g.,which are more tolerant to surprise disconnections / reconnections) are often replaced by retimers and other extension devices that may better match the interconnect protocol characteristics and requirements and may also be a better extension solution for other reasons.

[0062] In some implementations, in-band disconnect / reconnect detection may be supported by an exemplary retimer. Such solutions may, among other things, address at least some of the problems mentioned above. Among other features and uses, a retimer equipped with in-band disconnect / reconnect detection logic may detect and support unexpected disconnects and reconnects (such as a hot plug). Detection of a disconnect (and / or reconnect) may be enabled by such logic through analysis of signals received at the retimer's terminals. Accordingly, the retimer may infer a disconnect / reconnect sequence on the data link from in-band data and without corresponding sideband signaling.Indeed, in some implementations, a retimer may forego supporting such sideband signaling and rely entirely on in-band disconnect / reconnect detection. Furthermore, implementing such in-band disconnect / reconnect detection logic can enable a variety of new use cases for retimers, including expanding the use of such retimers within certain interconnect protocols, such as PCIe.

[0063] Referring to the example of Fig.8 shows a series of simplified block diagrams 800a-d illustrating an example of a surprise disconnect and reconnect on a data link comprising at least one retimer 805. In illustration 800a, the data link may connect a downstream port 810 / 9 (e.g., of a first endpoint) and an upstream port 815 (e.g., of a second endpoint). If a surprise disconnect of the second endpoint 815 occurs, as illustrated in illustration 800b, the retimer may not have been warned or may not immediately detect that the second endpoint 815 is no longer connected. Overhead and ambient signals may occur at the downstream port of the retimer even though the retimer 805 is not connected to any device on the port.The retimer 805 may nevertheless forward some of the meaningless signals to the other endpoint 810 before inferring or detecting that an idle condition exists on the downstream port of the retimer 805. Furthermore, the endpoint 810 may similarly detect a problem on the data link (e.g., based on nonsense signals forwarded by the retimer to the endpoint 810 after the disconnection from the other endpoint 815) and begin data link training to correct the problem. As shown in diagram 800c, data link training data 820, such as training sets, predefined training sequences (e.g., including ordered sets and other similar data), and other data, may be sent from the connected endpoint 610 to the retimer 805. In some cases, the data link training data 820 may be used in connection with an attempt to reestablish the data link (e.g.,initiated by endpoint 810). Based on detecting both the idle condition (e.g., 825) on the downstream port and the data link training data 820 on the retimer's upstream port, the retimer's in-band disconnect / reconnect detection logic may infer that a disconnect has occurred. Furthermore, in response, the retimer may trigger a detect state 830 in which the retimer logic attempts to detect if and when a new connection to another upstream port 835 (of a different endpoint, such as a hot-plugged device) has been completed. For example, upon detecting the disconnection, the retimer's in-band disconnect / reconnect detection logic may remove its connections (e.g., 50-ohm connections) and attempt to discover new terminations (e.g., 50-ohm terminations), such as shown in diagram 800d. Multi-mode retimer

[0064] The use of extension devices, such as retimers, is sometimes limited to certain types of applications and systems. For example, many systems and applications cannot tolerate I / O bus latency introduced by components such as retimers and similar extension devices. However, in some systems, to support all aspects of the protocols employed by the system, retimers may be configured to decode and re-encode signals sent by the retimer. For example, some signals may require the retimer to modify fields in some types of signals, such as training sequences, ordered sentences, and other examples. Accordingly, conventional retimers decode and re-encode all signals sent over the retimer(s) on the data link. For example, retimers in PCIe can decode and re-encode data according to, among other things, 8b / 10b or 128b / 130b encoding schemes.Such decoding and re-encoding may be the source of at least some of the latency introduced by conventional retimers.

[0065] In some implementations, enhanced retimers may be provided that address at least some of the issues introduced above, including, among others, minimizing retimer latency. For example, a retimer may be provided that includes the functionality to implement multiple modes, including one or more low-latency modes that can be selectively employed to forgo the conventional decoding and re-encoding of data on the data link and instead forward only the data as received on the subdata link. One or more additional modes may also be provided by the retimer that encodes / re-encodes the data prior to forwarding it along the data link.

[0066] Fig.9 illustrates an example flowchart 900 providing an example method and algorithm for providing a multi-mode retimer. Signals may be received 905 on a port (e.g., an upstream port) of the retimer, and logic within the retimer may determine 905 a signal type and / or data link state applicable to the received signals. Conditions may be predefined to utilize any of a variety of operating modes of the retimer. The modes may include a low-latency mode that forwards the data received on the upstream port directly for transmission on the transmit port (e.g., a downstream port) of the retimer.At least one other mode may be provided that at least partially decodes and / or re-encodes signals received on the upstream port or modifies the encoding of the received signal before the signal is transmitted on the downstream port of the retimer. In some implementations, when data link training (or data link training data) is identified by the retimer, it may be determined (or preconfigured) that a higher touch (and higher latency) mode is employed by the retimer, allowing the retimer to modify some fields in training sets transmitted by the retimer. Some data link states may be identified as being based on decoding and / or re-encoding at the retimer (e.g., in a register of the retimer), and identifying that the data link is in one of these states may enable the use of a signal encoding / decoding mode (e.g.,at 920) at the retimer (e.g., at 915). In another example, if the retimer identifies that the data connection is in a test mode, such as in the above examples of . Fig.5-7, the retimer may employ a mode that allows the retimer to perform decoding (e.g., error detection), field modification (e.g., error report data encoding), and other tasks corresponding to the defined test mode. Other data link states and data types may be properly forwarded by the retimer without decoding / reencoding. For example, data sent in an active data link state (e.g., an L0 state) may be defined as suitable for simple forwarding by the retimer. Accordingly, upon identifying such data link states (or data types) (e.g., at 910, 915), the retimer may employ a low-latency mode (e.g., at 925) to simply pass the data through the retimer without further (or at most minimal) processing of the data by the retimer.The retimer can conveniently, dynamically, and automatically switch between the multiple modes it provides in response to detected signal types, data link states, and other conditions to which one or more of the modes correspond. PHY layer velocity detection

[0067] Modern interconnect structures can support numerous different link speeds and, in some cases, support switching between two or more of the link speeds during operation. A retimer is intended to support the link speed present on a data link of which it is a part. Conventional retimers employ physical layer logic, sometimes including complex and unreliable data link state detection logic, to detect or infer data link state transitions and, thereby, the likely link speed used within the detected data link state.Because the data link state detection logic processes information to determine the current data link state, significant delays may occur before the retimer's transmission rate is adjusted (and readjusted) until the correct transmission rate is achieved and the retimer is able to begin forwarding received data at the appropriate link rate. Furthermore, because the data link state detection logic can sometimes infer incorrect data link rates, an incorrect link rate may be inferred from the data link state detection logic, causing, among other things, errors on the data links and further transmission delays.

[0068] In some implementations, a retimer may be provided that includes speed detection logic and is implemented at least partially using hardware at the electrical physical layer (or PHY) level to accurately detect the actual speed of incoming data on the data link. Instead of using logical physical layer logic to "guess" the data link's link speed, the actual transmission speed may be detected using PHY-level speed detection logic. Indeed, the logical physical layer state detection logic may be simplified or even omitted for use in determining the data link's transmission speed in some implementations.The PHY layer speed detection module can communicate the detected speed to the logical physical layer to allow the retimer to support the detected speed quickly and accurately.

[0069] Fig.10 is a simplified block diagram 1000 illustrating exemplary physical layer logic of an exemplary retimer. In some implementations, a retimer may include a physical layer including an electrical PHY sublayer 1005 and a logical physical sublayer 1010. In some cases, the logical physical sublayer 1010 may further include, among other things, media access control (MAC) and physical coding (PCS) sublayers. An interface 1015 may be provided between the PHY sublayer 1005 and the logical physical sublayer 1010. In some embodiments, such as in PCIe-compliant retimer implementations, the interface 1015 may be implemented as, among other things, a PHY interface for PCI Express (PIPE).The PHY sublayer 1005 may also include a speed detection module 1020 that can detect the transmission speed of data on the data link. The PHY subdata link 1005 may communicate the detected speed to the logical physical sublayer 1010 using the interface 1015. In some implementations, the interface 1015 (e.g., a PIPE-based interface) may be extended to support the communication of the speed (detected at the speed detection module 1020) to the logical physical layer 1010. In some implementations, the speed detection module 1020 may be an analog speed detection module.

[0070] In some implementations, the speed detection module 1020 may automatically perform speed detection once the bus leaves the electrical IDLE state. For example, data link training signals sent to re-establish the data link or to transition the data link state after IDLE may be used by the speed detection module 1020 to detect the transmission rate to be used for data on the data link. In some cases, an intermediate link may support one of multiple link speeds. For example, in one implementation, an incoming signal may be at one of a 2.5, 5.0, 8.0, or 16.0 GT / s rate, and the speed detection module may detect which of the supported rates is currently being used on the data link. The use of such speed detection circuitry (e.g.,1020) can, in some implementations, improve the accuracy and speed with which the retimer detects and adjusts to the transmission speed of the data connection.

[0071] Fig. 11A-11E are flowcharts 1100a-e illustrating example methods associated with a data connection implemented using an extension device, such as a retimer. For example, in Fig.11A identifies 1105 entry into a test mode for a data link comprising one or more subdata links based on the inclusion of one or more retimers (or other extension devices). In association with the test mode, a test mode signal is generated 1110, wherein the test mode signal comprises a test pattern and an error reporting sequence. The test mode signal is transmitted 1115 over a particular subdata link. The test pattern included in the test mode signal may be used (e.g., by the receiver of the signal) to test the particular subdata link for errors. The error reporting sequence is intended to progressively report the error status of each subdata link tested during the test mode. Errors identified on a previous subdata link may be added to and identified in the error reporting sequence included in the generated 1110 test mode signal.

[0072] Referring to Fig.11B, a test mode signal may be received 1120 during a test mode on a data link over a particular sub-data link in a data link comprising one or more extension devices and two or more sub-data links. The received test mode signal may comprise a test mode and an error reporting sequence. The test pattern is evaluated to determine the error status of the respective sub-data link 1130. Another test mode signal is generated 1135 to be transmitted in test mode, comprising a newly generated instance of the test pattern (e.g., newly generated to ensure that errors are not propagated over the data link during the series of test mode signals) and an error reporting sequence containing error status information from sub-data links previously tested during the test mode, as well as the error status of the respective sub-data link determined (at 1130). In the examples of Fig.11A and 11B, the test mode can be implemented using, among other things, a loopback mode.

[0073] In the example of Fig.11C, data is forwarded 1140 on a data link using a retimer. The retimer logic may detect 1145 an idle condition on a first port (e.g., located downstream or upstream) of the retimer. In some cases, the idle condition may be inferred. While the idle condition is being detected, data link training data may be received or otherwise detected 1150 on the second port (e.g., located upstream or downstream) of the retimer. Based on detecting 1145 the idle condition on the first port along with the data link training data (at 1150) on the second port, the retimer may determine that a device previously connected to the retimer using the first port has been disconnected.The retimer may then enter a detection state to identify, among other things, when another device replaces the disconnected device on the data link.

[0074] Referring to the example of Fig.11D, a multi-mode extension device, such as a multi-mode retimer, may be provided. A condition of a data connection on which the extension device is included may be determined 1160. For example, a data connection state or data type may be determined based on the data received on the data connection. A corresponding operating mode of the extension device may be selected 1165 based on the condition. The modes may include, among other things, at least one mode that allows decoding / decoding / modifying the data forwarded via the extension device and another mode that forgoes decoding / encoding in favor of lower latency processing. The selected operating mode is applied 1170 to transmit data over the data connection while the condition is applicable (e.g.,including switching between modes again when a transition in the data connection state is identified).

[0075] In the example of Fig.11E, data is received 1140 at an expansion device, such as a retimer, and hardware speed detection circuitry of the expansion device is used to detect 1145 a transmission speed corresponding to the received data. The expansion device may include a logical physical sublayer and an electrical physical sublayer, and the speed detection module may be implemented using the electrical physical sublayer. The detected transmission speed result may be communicated 1150 from the electrical physical sublayer to the logical physical sublayer. The expansion device may configure itself to process and transmit the data according to the detected speed 1155.

[0076] It is noted that the devices, methods, and systems described above, as previously mentioned, can be implemented in any electronic device or system. As specific illustrations, the following figures provide exemplary systems for using the invention as described herein. As the following systems are described in more detail, a number of different interconnections are disclosed, described, and recalled from the above discussion. And it will be readily apparent that the advances described herein can be applied to any of these interconnections, structures, or architectures.

[0077] Referring to Fig.Figure 12 depicts one embodiment of a block diagram for a computer system including a multi-core processor. Processor 1200 includes any processor or processor device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a co-processor, a system-on-chip (SOC), or other device for executing code. Processor 1200, in one embodiment, includes at least two cores—cores 1201 and 1202—which may include asymmetric cores or symmetric cores (the illustrated embodiment). However, processor 1200 may include any number of processor elements, which may be symmetric or asymmetric.

[0078] In one embodiment, a processing element refers to hardware or logic to support a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a processing unit, a context, a context unit, a logical processor, a hardware thread, a core, and / or any other element capable of maintaining state for a processor, such as execution state or architectural state. In other words, a processing element, in one embodiment, refers to any hardware capable of being independently associated with code, such as a software thread, an operating system, an application, or other code.A physical processor (or processor socket) typically refers to an integrated circuit that may or may not include any number of other processing elements, such as cores or hardware threads.

[0079] A core often refers to logic located on an integrated circuit capable of maintaining an independent architectural state, where each independently maintained architectural state is associated with at least multiple dedicated execution resources. In contrast to cores, a hardware thread typically refers to any logic located on an integrated circuit capable of maintaining an independent architectural state, where the independently maintained architectural states share access to execution resources. As can be seen, the boundary between the nomenclature of a hardware thread and core overlaps when certain resources are shared and others are dedicated to an architectural state.However, a core and a hardware thread are often viewed by an operating system as individual logical processors, with the operating system being able to specify operations on each logical processor individually.

[0080] A physical processor 1200, as in Fig.12, comprises two cores—core 1201 and core 1202. Here, cores 1201 and 1202 are considered symmetric cores, i.e., cores with the same configurations, functional units, and / or logic. In another embodiment, core 1201 comprises an out-of-order processor core, while core 1202 comprises an in-order processor core. However, cores 1201 and 1202 may be individually selected from any type of core, such as a native core, a software-managed core, a core adapted to execute a native instruction set architecture (ISA), a core adapted to execute a translated instruction set architecture (ISA), a co-engineered core, or any other known core. In a heterogeneous core environment (i.e., asymmetric cores), some form of translation, such as binary translation, may be used to schedule or execute code on one or both cores.To further the discussion, the functional units illustrated in core 1201 are described in more detail below, since the units in core 1202 operate in a similar manner in the illustrated embodiment.

[0081] As illustrated, core 1201 includes two hardware threads 1201a and 1201b, which may also be referred to as hardware thread slots 1201a and 1201b. Therefore, in one embodiment, software entities such as an operating system may view processor 1200 as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads concurrently. As noted above, a first thread is associated with architectural state registers 1201a, a second thread is associated with architectural state registers 1201b, a third thread may be associated with architectural state registers 1202a, and a fourth thread may be associated with architectural state registers 1202b. Here, each of the architectural state registers (1201a, 1201b, 1202a, and 1202b) may be referred to as processing elements, thread slots, or thread units, as described above.As illustrated, architectural state registers 1201a are replicated in architectural state registers 1201b, thus enabling individual architectural states / contexts to be stored for logical processor 1201a and logical processor 1201b. In core 1201, other minor resources, such as instruction pointers and rename logic in dispatcher and rename block 1230, may also be replicated for threads 1201a and 1201b. Some resources, such as reorder buffers in reorder / reorder unit 1235, ILTB 1220, load / store buffers, and queues, may be shared through partitioning. Other resources, such as general-purpose internal registers, page table base registers, low-level data cache and data TLB 1215, execution unit(s) 1240, and portions of out-of-order unit 1235, may be fully shared.

[0082] Processor 1200 often includes additional resources that may be fully shared, shared through partitioning, or dedicated by / to processing elements. In Fig. 12 illustrates one embodiment of a purely exemplary processor with illustrative logic units / resources of a processor. It should be noted that a processor may include or omit any of these functional units, as well as any other known functional units, logic, or firmware not shown. As illustrated, core 1201 includes a simplified, representative out-of-order (OOO) processor core. However, an in-order processor may be used in other embodiments. The OOO core includes a branch target buffer 1220 to predict branches to be executed / taken and an instruction translation buffer (I-TLB) 1220 to store address translation entries for instructions.

[0083] Core 1201 further includes decode module 1225 coupled to fetch unit 1220 to decode fetched elements. Fetch logic, in one embodiment, includes individual sequencers associated with thread slots 1201a and 1201b, respectively. Typically, core 1201 is associated with a first ISA that defines / specifies instructions executable on processor 1200. Often, machine code instructions that are part of the first ISA include a portion of the instruction (referred to as an opcode) that references / specifies an instruction or operation to be performed. Decode logic 1225 includes circuitry that recognizes these instructions by their opcodes and forwards the decoded instructions down the pipeline for processing as defined by the first ISA.For example, in one embodiment, as detailed below, decoders 1225 include logic configured or adapted to recognize specific instructions, such as transaction instructions. Based on the recognition by decoders 1225, architecture or core 1201 takes specific, predefined actions to perform tasks associated with the respective instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of which may be new or old instructions. Note that decoders 1226, in one embodiment, recognize the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, decoders 1226 recognize a second ISA (either a subset of the first ISA or a separate ISA).

[0084] In one example, dispatcher and renamer block 1230 includes an dispatcher to reserve resources such as register files for storing instruction processing results. However, threads 1201a and 1201b may be capable of out-of-order execution, with dispatcher and renamer block 1230 also reserving other resources such as reorder buffers to track instruction results. Unit 1230 may also include a register renamer to rename program / instruction reference registers to other registers within processor 1200. Reorder / reorder unit 1235 includes components such as the aforementioned reorder buffers, load buffers, and store buffers to support out-of-order execution and later in-order reordering of out-of-order instructions.

[0085] Scheduler and execution unit(s) block 1240, in one embodiment, includes a scheduler unit for scheduling instructions / operations onto execution units. For example, a floating-point instruction is scheduled onto a port of an execution unit that has an available floating-point execution unit. Register files associated with the execution units are also included to store information about instruction processing results. Example execution units include a floating-point execution unit, an integer execution unit, a branch instruction execution unit, a load execution unit, a store execution unit, and other known execution units.

[0086] Lower-level data cache and data translation buffer (D-TLB) 1250 are coupled to execution unit(s) 1240. The data cache is intended to store recently used or operated-on elements, such as data operands, which may be held in memory coherence states. The D-TLB is intended to store recently performed virtual / linear to physical address translations. As a specific example, a processor may include a page table structure to divide physical memory into a plurality of virtual pages.

[0087] Here, cores 1201 and 1202 share access to higher-level or further-out cache, such as second-level cache, associated with the interface on chip 1210. Note that higher-level or further-out refers to cache levels that increase or move away from the execution unit(s). In one embodiment, a higher-level cache is a last-level data cache—the last cache in the memory hierarchy on processor 1200—such as a second- or third-level data cache. However, a higher-level cache is not so limited, as it may be associated with or include an instruction cache. A trace cache—one type of instruction cache—may instead be coupled after decoder 1225 to store recently decoded traces. Here, an instruction may refer to a macroinstruction (i.e.,a general instruction recognized by the decoders) that can decode into a number of microinstructions (microoperations).

[0088] In the illustrated configuration, the processor 1200 includes an on-chip interface module 1210. Historically, a memory controller, described in more detail below, was included in a computing system external to the processor 1200. In this scenario, the on-chip interface 1210 is intended to communicate with devices external to the processor 1200, such as system memory 1275, a chipset (often including a memory controller hub for connecting to memory 1275 and an I / O controller hub for connecting peripherals), a memory controller hub, a northbridge, or another integrated circuit. And in this scenario, the bus 1205 may include any known interconnect, such as a multi-drop bus, a point-to-point interconnect, a series interconnect, a parallel bus, a coherent (e.g.,cache-coherent) bus, a layered protocol architecture, a differential bus, and a GTL bus.

[0089] Memory 1275 may be dedicated to processor 1200 or shared with other devices in a system. Common examples of memory 1275 types include DRAM, SRAM, non-volatile memory (NV RAM), and other known memory devices. Note that device 1280 may include a graphics accelerator, processor, or card coupled to a memory controller hub, data storage coupled to an I / O controller hub, a wireless transceiver, a flash device, an audio controller, a network controller, or other known device.

[0090] Recently, however, each of these devices may be incorporated on the processor 1200 as more and more logic and devices are integrated onto a single die such as a SOC. For example, in one embodiment, a memory controller hub is located on the same package and / or die with the processor 1200. Here, a portion of the core (an on-core portion) 1210 includes one or more controllers for connecting to other devices, such as the memory 1275 or a graphics device 1280. The configuration including an interconnect and controllers for connecting to such devices is often referred to as an on-core (or uncore) configuration. As one example, the on-chip interface 1210 includes a ring interconnect for on-chip communication and a high-speed serial point-to-point data link 1205 for off-chip communication.However, in the SOC environment, more devices, such as the network interface, co-processors, memory 1275, graphics processor 1280, and any other known computing devices / interfaces may be integrated on a single die or integrated circuit to provide the small form factor with high functionality and low power consumption.

[0091] In one embodiment, processor 1200 is capable of executing compilation, optimization, and / or translation code 1277 to compile, translate, and / or optimize application code 1276 to support or interfere with the devices and methods described herein. A compiler often includes a program or set of programs for translating source text / code into target text / code. Typically, compilation of program / application code with a compiler is performed in multiple phases and passes to translate high-level programming language code into low-level machine or assembly language code. However, single-pass compilers can still be used for simple compilation.A compiler can use any known compilation techniques and any known compilation operations, such as lexical analysis, preprocessing, parsing, semantic analysis, code generation, code conversion, and code optimization.

[0092] Larger compilers often include multiple phases, but these phases are usually contained within two general phases: (1) a front-end, i.e., where syntactic processing, semantic processing, and some conversion / optimization can generally take place, and (2) a back-end, i.e., where analysis, conversions, optimizations, and code generation generally take place. Some compilers refer to a middle, illustrating the blurring of the distinction between a front-end and a back-end of a compiler. Consequently, a reference to insertion, allocation, generation, or any other operation of a compiler can occur in any of the aforementioned phases or passes of a compiler. As an illustrative example, a compiler may insert operations, calls, functions, etc.in one or more compilation phases, such as inserting calls / operations in a front-end compilation phase and then converting the calls / operations into lower-level code during a conversion phase. Note that during dynamic compilation, compiler code or dynamic optimization code can insert such operations / calls and optimize the code for execution at runtime. As a specific illustrative example, binary code (already compiled code) can be dynamically optimized at runtime. Here, the program code can include the dynamic optimization code, the binary code, or a combination thereof.

[0093] Similar to a compiler, a translator, such as a binary translator, translates code either statically or dynamically to optimize and / or translate code. Therefore, a reference to the execution of code, application code, program code, or other software environment may refer to: (1) execution of one or more compiler programs, an optimization code optimizer, or translator, either dynamically or statically, to compile program code, maintain software structures, perform other operations, optimize code, or translate code; (2) execution of main program code, including operations / calls such as application code that has been optimized / compiled; (3) execution of other program code, such as libraries associated with the main program code, to maintain software structures, perform other software-related operations, or optimize code; or (4) a combination thereof.

[0094] With reference now to Fig. 13 is a block diagram of one embodiment of a multi-core processor. As in the embodiment of Fig. As shown in Figure 13, processor 1300 includes multiple domains. Specifically, a core domain 1330 includes a plurality of cores 1330A-1330N, a graphics domain 1360 includes one or more graphics engines including a media engine 1365, and a system agent domain 1310.

[0095] In various embodiments, system agent domain 1310 handles power control operations and power management such that individual units of domains 1330 and 1360 (e.g., cores and / or graphics engines) are independently controllable to dynamically operate at an appropriate power mode / level (e.g., Active, Turbo, Sleep, Hibernation, Deep Sleep, or another Advance Configuration Power Interface-like state) in light of the activity (or inactivity) occurring in the given unit. Each of domains 1330 and 1360 may operate at different voltage and / or power, and furthermore, the individual units within the domains may each operate at an independent frequency and voltage. It should be noted that although only three domains are illustrated, the scope of the present invention is not limited in this regard, and additional domains may be present in other embodiments.

[0096] As shown, each core 1330 further includes low-level caches in addition to various execution units and additional processing elements. Here, the various cores are coupled to each other and to a shared cache memory formed from a plurality of units or slices of a last-level cache (LLC) 1340A-1340N. These LLCs often include memory and cache controller functionality and are shared among the cores and, where appropriate, among the graphics engines.

[0097] As can be seen, a ring interconnect 1350 connects the cores together and provides an interconnect between the core domain 1330, the graphics domain 1360, and the system agent circuitry 1310 via a plurality of ring stops 1352A-1352N, each at a core-to-LLC slice coupling. As can be seen from Fig.As can be seen in Figure 13, interconnect 1350 is used to transmit various information, including address information, data information, acknowledgment information, and snoop / invalidation information. Although a ring interconnect is illustrated, any known on-die interconnect or structure may be used. As an illustrative example, some of the structures discussed above (e.g., another on-die interconnect, On-chip System Fabric (OSF), an Advance Microcontroller Bus Architecture (AMBA) interconnect, a multidimensional mesh structure, or another interconnect architecture) may be used in a similar manner.

[0098] As further illustrated, the system agent domain 1310 includes a display engine 1312 to provide control of and connection to an associated display. The system agent domain 1310 may include other devices such as an integrated memory controller 1320 that provides an interface to system memory (e.g., DRAM implemented with multiple DIMMs; coherency logic 1322 for performing memory coherency operations). Multiple interfaces may be provided to enable interconnection between the processor and other circuitry. For example, in one embodiment, at least one Direct Media Interface (DMI) interface 1316 and one or more PCIe™ interfaces 1314 are provided. The display engine and these interfaces are coupled to memory, typically via a PCIe™ bridge 1318.To further enable transfers between other agents, such as additional processors or other circuitry, one or more interfaces may be provided.

[0099] With reference now to Fig. 14 is a block diagram of a representative core; in particular, logic blocks of a backend of a core such as core 1330 of Fig. 13. In general, the Fig. 14 illustrates an out-of-order processor having a front-end unit 1470 used to fetch incoming instructions, perform various processing operations (e.g., caching, decoding, branch prediction, etc.), and forward instructions / operations to an out-of-order (OOO) engine 1480. The OOO engine 1480 performs further processing on decoded instructions.

[0100] Specifically, the out-of-order engine 1480 in the embodiment of Fig. 14, an allocation unit 1482 for receiving decoded instructions in the form of one or more micro-operations, or µ-ops, from the front-end unit 1470 and allocating them to appropriate resources such as registers, etc. Next, the instructions are provided to a reservation station 1484, which reserves resources and schedules them for execution on one or a plurality of execution units 1486A-1486N. Various types of execution units may be present, including, for example, arithmetic logic units (ALUs), load and store units, vector processing units (VPUs), and floating-point execution units. Results from these various execution units are provided to a reorder buffer (ROB) 1488, which receives out-of-order results and returns them in the correct program order.

[0101] With further reference to Fig. 14, it should be noted that both the front-end unit 1470 and the out-of-order engine 1480 are coupled to different levels of a memory hierarchy. Specifically, an instruction-level cache 1472 is shown, which in turn is coupled to a mid-level cache 1476, which in turn is coupled to a last-level cache 1495. In one embodiment, the last-level cache 1495 is implemented in an on-chip unit (sometimes referred to as an uncore) 1490. As an example, the unit 1490 is associated with the system agent 1310 of Fig.13. As stated above, the uncore 1490 communicates with the system memory 1499, which in the illustrated embodiment is implemented via ED-RAM. It should also be noted that the various execution units 1486 within the out-of-order engine 1480 are in communication with a first-level cache 1474, which is also in communication with the mid-level cache 1476. It should also be noted that the additional cores 1430N-2-1430N may be coupled to LLC 1495. Despite the illustration in the embodiment of Fig. 14 At this high level, it is understood that various variations and additional components may be present.

[0102] With reference now to Fig.15 illustrates a block diagram of an exemplary computer system configured with a processor including execution units for executing an instruction, wherein one or more of the interconnections implement one or more features according to an embodiment of the present invention. System 1500 includes a component such as a processor 1502 for employing execution units including logic for executing algorithms on process data according to embodiments of the present invention, such as the embodiment described herein. System 1500 is representative of processing systems based on the PENTIUM III™, PENTIUM 4™, Xeon™, Itanium, XScale™, and / or StrongARM™ microprocessors, although other systems (including PCs including other microprocessors, engineering workstations, set-top boxes, and the like) may be used.In one embodiment, example system 1500 executes a version of the WINDOWS™ operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may be used. Therefore, embodiments of the present invention are not limited to any specific combination of hardware circuitry and software.

[0103] Embodiments are not limited to computer systems. Alternative embodiments of the present invention may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications may include a microcontroller, a digital signal processor (DSP), a system on a chip, a network computer (NetPC), set-top boxes, network hubs, wide-area network (WAN) switches, or any other system capable of executing one or more instructions according to at least one embodiment.

[0104] In this illustrated embodiment, processor 1502 includes one or more execution units 1508 to implement an algorithm to execute at least one instruction. One embodiment may be described in the context of a single-processor desktop or server system, but alternative embodiments may be included in a multiprocessor system. System 1500 is an example of a "hub" system architecture. Computer system 1500 includes a processor 1502 to process data signals. Processor 1502 includes, as an illustrative example, a complex instruction set computer (CO) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor.Processor 1502 is coupled to a processor bus 1510, which communicates data signals between processor 1502 and other components in system 1500. The elements of system 1500 (e.g., graphics accelerator 1512, memory controller hub 1516, memory 1520, I / O controller hub 1524, wireless transceiver 1526, flash BIOS 1528, network controller 1534, audio controller 1536, serial expansion interface 1538, I / O controller 1540, etc.) perform their usual functions well known to those skilled in the art.

[0105] In one embodiment, processor 1502 includes a Level 1 (L1) internal cache memory 1504. Depending on the architecture, processor 1502 may include a single primary cache or multiple levels of primary caches. Other embodiments include a combination of both primary and external caches, depending on the specific implementation and requirements. Register file 1506 is intended to store various types of data in various registers, including integer registers, floating-point registers, vector registers, banked registers, shadow registers, checkpoint registers, status registers, and instruction pointer registers.

[0106] Execution unit 1508, including logic for performing integer and floating-point operations, is also located in processor 1502. Processor 1502, in one embodiment, includes a microcode (uCode) ROM to store microcode that, when executed, is designed to execute algorithms for specific macroinstructions or handle complex scenarios. Here, microcode is updatable as needed to address logic bugs / fixes for processor 1502. For one embodiment, execution unit 1508 includes logic to process a packed instruction set 1509. By including packed instruction set 1509 in the instruction set of a general-purpose processor 1502, along with associated circuitry for executing the instructions, the operations used by many multimedia applications can be performed using packed data in a general-purpose processor 1502.Therefore, many multimedia applications are accelerated and executed more efficiently when the full width of a processor's data bus is used to perform operations on packed data. This may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations on one data element each.

[0107] Alternative embodiments of an execution unit 1508 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. System 1500 includes a memory 1520. Memory 1520 includes a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, or another memory device. Memory 1520 stores instructions and / or data represented by data signals to be executed by processor 1502.

[0108] It should be noted that any of the aforementioned features or aspects of the invention are based on one or more Fig.15 may be used. For example, an on-die interconnect (ODI) not shown for coupling internal units of processor 1502 implements one or more aspects of the invention described above. Or, the invention is associated with one of the following: a processor bus 1510 (e.g., another known high-performance computing interconnect), a high-bandwidth memory path 1518 to memory 1520, a point-to-point data connection to a graphics accelerator 1512 (e.g., a Peripheral Component Interconnect Express (PCIe)-compliant fabric), a controller hub interconnect 1522, an I / O or other interconnect (e.g., USB, PCI, PCIe) for connecting the other illustrated components.Some examples of such components include audio controller 1536, firmware hub (flash BIOS) 1528, wireless transceiver 1526, data storage 1524, legacy I / O controller 1510 containing user input and keyboard interfaces 1542, serial expansion interface 1538 such as a Universal Serial Bus (USB), and network controller 1534. Data storage device 1524 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0109] With reference now to Fig. 16 is a block diagram of a second system 1600 according to an embodiment of the present invention. As shown in Fig.As shown in Figure 16, multiprocessor system 1600 is a point-to-point interconnect system and includes a first processor 1670 and a second processor 1680 coupled together via a point-to-point interconnect 1650. Each of processors 1670 and 1680 may be a particular version of a processor. In one embodiment, 1652 and 1654 are part of a serial, point-to-point coherent interconnect structure, such as a high-performance architecture. Thus, the invention may be implemented within the QPI architecture.

[0110] Although illustrated with only two processors 1670, 1680, it should be understood that the scope of the present invention is not so limited. In other embodiments, one or more additional processors may be present in a given processor.

[0111] Processors 1670 and 1680 are shown as including integrated memory controller units 1672 and 1682, respectively. Processor 1670 also includes point-to-point (PP) interfaces 1676 and 1678 as part of its bus controller units; likewise, second processor 1680 includes PP interfaces 1686 and 1688. Processors 1670, 1680 may exchange information via a point-to-point (PP) interface 1650 using PP interface circuits 1678, 1688. As shown in Fig. 16, IMCs 1672 and 1682 couple the processors to respective memories, namely a memory 1632 and a memory 1634, which may be parts of a main memory attached to the respective processors.

[0112] The processors 1670, 1680 each exchange information with a chipset 1690 via individual PP interfaces 1652, 1654 using point-to-point interface circuits 1676, 1694, 1686, 1698. The chipset 1690 also exchanges information with a high-performance graphics circuit 1638 via an interface circuit 1692 along a high-performance graphics interconnect 1639.

[0113] A shared cache (not shown) may be included in either processor or external to both processors; however, it is connected to the processors via a PP interconnect such that the local cache information of either or both processors may be stored in the shared cache when one processor is placed in a low-power mode.

[0114] Chipset 1690 may be coupled to a first bus 1616 via an interface 1696. In one embodiment, first bus 1616 may be a Peripheral Component Interconnect (PCI) bus or a bus such as a PCI Express bus or other third-generation I / O interconnect bus, although the scope of the present invention is not so limited.

[0115] As in Fig.16, various I / O devices 1614 are coupled to the first bus 1616 along with a bus bridge 1618 that couples the first bus 1616 to a second bus 1620. In one embodiment, the second bus 1620 comprises a low-pin-count (LPC) bus. Various devices are coupled to the second bus 1620, including, for example, a keyboard and / or mouse 1622, communication devices 1627, and a memory unit 1628, such as a disk drive or other mass storage device, which often includes instructions / code and data 1630, in one embodiment. Further, an audio I / O 1624 is shown coupled to the second bus 1620. It should be noted that other architectures are possible, with the included components and interconnections varying. For example, instead of the point-to-point architecture of Fig. 16 implement a multipoint bus or other such architecture.

[0116] With reference now to Fig. Figure 17 illustrates an embodiment of a system-on-chip (SOC) design in accordance with the inventions. As a specific illustrative example, SOC 1700 is included in user-premises equipment (UE). In one embodiment, UE refers to any device intended to be used by an end user for communication, such as a handheld phone, smartphone, tablet, ultra-thin notebook, notebook with a broadband adapter, or any other similar communication device. A UE often connects to a base station or node, which may be similar in nature to a mobile station (MS) in a GSM network.

[0117] Here, the SOC 1700 includes two cores—1706 and 1707. Similar to the discussion above, cores 1706 and 1707 may correspond to an instruction set architecture such as an Intel® Architecture Core™-based processor, an Advanced Micro Devices, Inc. (AMD) processor, a MIPS-based processor, an ARM-based processor design, or a customer thereof, as well as their licensees or users. Cores 1706 and 1707 are coupled to a cache controller 1708 associated with a bus interface unit 1709 and an L2 cache 1711 for communicating with other parts of the system 1700. Interconnect 1710 includes an on-chip interconnect such as an IOSF, AMBA, or other interconnect discussed above, optionally implementing one or more aspects described herein.

[0118] The interface 1710 provides communication channels to the other components, such as a subscriber identity module (SIM) 1730 for connecting to a SIM card, a boot ROM 1735 for holding boot code for execution by cores 1706 and 1707 to initialize and boot SOC 1700, an SDRAM controller 1740 for connecting to external memory (e.g., DRAM 1760), a flash controller 1745 for connecting to non-volatile memory (e.g., flash 1765), a peripheral controller 1750 (e.g., serial peripheral interface) for connecting to peripherals, video codes 1720 and video interface 1725 for displaying and receiving inputs (e.g., touch-enabled inputs), GPU 1715 for performing graphics-related computations, etc. Any of these interfaces may incorporate aspects of the invention described herein.

[0119] Additionally, the system illustrates peripheral communication devices, such as a Bluetooth module 1770, a 3G modem 1775, a GPS 1785, and a Wi-Fi 1785. It should be noted that, as stated above, a UE includes a radio for communication. Consequently, not all of these peripheral communication modules are required. However, a UE must include some form of radio for external communication.

[0120] While the present invention has been described with respect to a limited number of embodiments, numerous modifications and variations thereof will be apparent to those skilled in the art. It is intended that the appended claims cover all such modifications and variations that fall within the true spirit and scope of the present invention.

[0121] A design can go through various stages, from generation to simulation to manufacturing. Data representing a design can represent the design in several ways. First, the hardware, as is useful in simulations, may be represented using a hardware description language or other functional description language. In addition, a circuit-level model with logic and / or transistor gates may be created at some stages of the design process. In addition, at some stage, most designs reach a level of data representing the physical placement of various devices in the hardware model.In a case where conventional semiconductor manufacturing processes are used, the data representing the hardware model may be the data specifying the presence or absence of various features on different mask layers for masks used to fabricate integrated circuits. In any representation of the design, the data may be stored in any form on a machine-readable medium. A random access memory or a magnetic or optical storage device such as a disk may be the machine-readable medium for storing information transmitted via optical or electrical waves that are modulated or otherwise generated to transmit such information. When an electrical carrier wave indicating or carrying the code is transmitted to the extent that copying, buffering, or retransmission of the electrical signal is performed, a new copy is created.Therefore, a communications provider or network provider may at least temporarily store on a tangible, machine-readable medium an article, such as information encoded in a carrier wave, that includes methods of embodiments of the present invention.

[0122] A module, as used herein, refers to any combination of hardware, software, and / or firmware. As one example, a module includes hardware, such as a microcontroller, associated with a non-transitory medium for storing code adapted for execution by a microcontroller. Therefore, in one embodiment, reference to a module refers to the hardware specifically configured to recognize and / or execute the code to be held on a non-transitory medium. Furthermore, in another embodiment, the use of a module refers to the non-transitory medium including the code specifically adapted to be executed by the microcontroller to perform predetermined operations. And, as can be appreciated, in yet another embodiment, the term module (in this example) may refer to the combination of the microcontroller and the non-transitory medium.Module boundaries depicted as separate typically vary and may overlap. For example, a first and a second module may share hardware, software, firmware, or a combination thereof, while possibly retaining some independent hardware, software, or firmware. In one embodiment, the use of the term "logic" includes hardware such as transistors, registers, or other hardware such as programmable logic devices.

[0123] The use of the term "configured to," in one embodiment, refers to arranging, assembling, manufacturing, offering for sale, importing, and / or engineering a device, hardware, logic, or element to perform a designated or specified task. In this example, a device or element thereof that is not operating is nevertheless "configured to" perform a designated task if it is designed, coupled, and / or interconnected to perform the designated task. As a purely illustrative example, a logic gate may provide a 0 or a 1 during operation. However, a logic gate "configured to" provide an enable signal to a clock does not include every potential logic gate that can provide a 1 or 0.Instead, the logic gate is one that is coupled in a specific way so that the 1 or 0 output during operation is intended to activate the clock. Again, the use of the term "configured to" does not require operation, but instead refers to the latent state of a device, hardware, and / or element, where the device, hardware, and / or element in the latent state is configured to perform a specific output when the device, hardware, and / or element is operating.

[0124] Furthermore, the use of the terms "to," "capable of," and / or "operable to" in one embodiment refers to a particular device, logic, hardware, and / or element designed to enable use of the device, logic, hardware, and / or element in a particular manner. As above, the use of "to," "capable of," or "operable to" in one embodiment refers to the latent state of a device, hardware, and / or element, where the device, hardware, and / or element is not operational but is designed to enable use of a device in a particular manner.

[0125] A value, as used herein, includes any known representation of a number, a state, a logic state, or a binary logic state. Often, the use of logic levels, logic values, or logical values ​​is also referred to as 1s or 0s, simply representing binary logic states. For example, a 1 refers to a high logic level, and a 0 refers to a low logic level. In one embodiment, a memory cell, such as a transistor or flash cell, may be capable of holding a single logical value or multiple logical values. However, other representations of values ​​have been used in computer systems. For example, the decimal number 10 may also be represented by a binary value of 1010 and a hexadecimal character A. Therefore, a value includes any representation of information capable of being held in a computer system.

[0126] Furthermore, states can be represented by values ​​or portions of values. As an example, a first value, such as a logical one, can represent a default or initial state, while a second value, such as a logical zero, can represent a non-default state. Additionally, in one embodiment, the terms Reset and Set refer to a default and an updated value or state, respectively. For example, a default value may include a high logical value, i.e., Reset, while an updated value may include a low logical value, i.e., Set. It should be noted that any combination of values ​​can be used to represent any number of states.

[0127] The embodiments of the above-described methods, hardware, software, firmware, or code may be implemented via instructions or code stored on a machine-accessible, machine-readable, computer-accessible, or computer-readable medium that is executable by a processing element. A non-transitory machine-accessible / readable medium includes any mechanism that provides (i.e., stores and / or transmits) information in a form readable by a machine, such as a computer or electronic system.For example, a non-transitory machine-accessible medium includes random access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; a magnetic or optical storage medium; flash memory devices; electrical storage devices; optical storage devices; acoustic storage devices; another form of storage device for holding information received from transient (transmitted) signals (e.g., carrier waves, infrared signals, digital signals); etc., which are to be distinguished from the non-transitory media that can receive information therefrom.

[0128] Instructions used to program logic to carry out embodiments of the invention may be stored within a memory in the system, such as DRAM, cache, flash memory, or other memory. Furthermore, the instructions may be distributed over a network or by means of other computer-readable media. Therefore, a machine-readable medium may be any mechanism for storing or transmitting information in a format readable by a machine (e.g.,a computer) readable form, but is not limited to, floppy disks, optical disks, compact disc read-only memories (CD-ROMs) and magneto-optical disks, read-only memories (ROMs), random access memories (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic or optical cards, flash memory, or any tangible machine-readable memory used in the transmission of information over the Internet via electrical, optical, acoustic, or other forms of transmitted signals (e.g., carrier waves, infrared signals, digital signals, etc.). Accordingly, the computer-readable medium includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

[0129] The following examples relate to embodiments according to this description. One or more embodiments may include an apparatus, a system, a machine-readable memory, a machine-readable medium, hardware and / or software-based logic, and a method for generating a test mode signal to include a test pattern and an error reporting sequence and transmitting the test mode signal on a data link to include one or more expansion devices and two or more sub-data links, wherein the test mode signal is to be transmitted on a particular one of the sub-data links, the test pattern is to be used by a receiving device to identify errors on the particular sub-data link, and the error reporting sequence is to be encoded with error information to describe error statuses of sub-data links in the plurality of sub-data links.

[0130] In at least one example, the test mode signal is transmitted within a loopback test mode, and instances of the test mode signal are to be transmitted from a first device on the data link to a second device via the one or more extension devices and transmitted from the second device back to the first device via the at least one or more extension devices.

[0131] In at least one example, at least one of the instances of the test mode signal is received from another device on another of the sub-data links of the data link, wherein each instance of the test mode signal comprises an instance of the test pattern and an instance of the error reporting sequence.

[0132] In at least one example, fault detection logic is provided to determine one or more faults on the other sub-data connection based on the instance of the test pattern.

[0133] In at least one example, errors for a sub-data link are determined based on an identification that an instance of the test pattern included in a test mode signal received over the sub-data link deviates from a value expected for the test pattern.

[0134] In at least one example, the extension device comprises a retimer.

[0135] In at least one example, the device includes the retimer.

[0136] In at least one example, the error reporting sequence comprises a plurality of segments, and each segment describes an error status of a respective one of the sub-data connections.

[0137] In at least one example, each segment describes one of a downstream channel and one upstream channel of a respective subconnection.

[0138] In at least one example, each segment comprises one or more ordered sentences, and at least a portion of each of the ordered sentences is encoded to identify error statuses of at least one of the sub-data connections.

[0139] In at least one example, each ordered sentence comprises a respective SKP-ordered sentence.

[0140] In at least one example, the one or more expansion devices comprise at least two expansion devices, the two or more sub-data links comprise three sub-data links, and the plurality of segments comprises at least five segments.

[0141] In at least one example, error information detected for a previous sub-data connection is encoded in the error reporting sequence, and error information is maintained in the error reporting sequence for previously detected error statuses of other sub-data connections in the two or more sub-data connections.

[0142] In at least one example, the error information includes one or more of the following: a number of errors detected for a sub-data link, a trajectory of the data link on which an error occurred, and a location of errors detected in a received test pattern.

[0143] In at least one example, the test pattern comprises a predefined pattern to be regenerated at each subdata connection during a test.

[0144] In at least one example, the test pattern comprises one or more ordered sentences.

[0145] In at least one example, the one or more ordered sets are Electrical Idle Exit Sequence Ordered Sets (EIEOS).

[0146] In at least one example, the control logic is to identify that the data link is in a test mode, and the test mode signal is sent according to the test mode.

[0147] In at least one example, the test pattern is a fixed test pattern defined for the test mode.

[0148] One or more embodiments may provide an apparatus, a system, a machine-readable memory, a machine-readable medium, hardware and / or software-based logic, and a method for receiving a test mode signal on a data link in a test mode, wherein the data link comprises at least one expansion device and two or more sub-data links, the test mode signal comprises a test pattern and an error reporting sequence, the test mode signal is transmitted on a particular one of the sub-data links, and the error reporting sequence is to be encoded with error information to describe error statuses of sub-data links in the plurality of sub-data links and to evaluate the test pattern in the test mode signal to identify an error status of the particular sub-data link.

[0149] In at least one example, the test pattern is evaluated to determine whether the test pattern deviates from an expected test pattern.

[0150] In at least one example, the test pattern is defined for a test mode, the test mode includes a test of each sub-data connection of the connection, and a respective instance of the test pattern is to be generated and sent in each of the tests of the sub-data connections to determine whether the respective instance of the test pattern received at the end of the respective sub-data connection deviates from the defined test pattern.

[0151] In at least one example, each sub-data connection comprises a respective upstream channel and downstream channel, and an instance of the test pattern is to be transmitted on each of the upstream channel and the downstream channel of each of the sub-data connections.

[0152] In at least one example, the error status indicates one or more errors detected on the respective subdata connection based on the test pattern.

[0153] In at least one example, the error status identifies a number of errors detected on the respective subdata connection.

[0154] In at least one example, the error status identifies lanes of the data connection on which the one or more errors occur.

[0155] In at least one example, the error status identifies the location within the test pattern where the one or more errors were detected.

[0156] In at least one example, the control logic is to generate another instance of the test mode signal, where the other instance of the test mode signal comprises an error reporting sequence encoded to indicate the error status of the particular sub-data link, the apparatus further comprising transmit logic to transmit the other instance of the test mode signal on another one of the sub-data links.

[0157] In at least one example, the error reporting sequence in the other instance of the test mode signal retains error status information for previously determined error states from other subdata links of the data link.

[0158] In at least one example, the error reporting sequence comprises a plurality of segments, and each segment describes an error status of a respective one of the sub-data connections.

[0159] In at least one example, the control logic is to identify a particular one of the plurality of segments into which the error status of the particular subdata connection is to be encoded.

[0160] In at least one example, the particular segment is identified as pre-assigned to the respective subdata connection.

[0161] In at least one example, the particular segment is identified as a next unencoded one of the plurality of segments.

[0162] In at least one example, the other instance of the test mode signal comprises an instance of the test pattern.

[0163] In at least one example, the test pattern included in the received test mode signal includes one or more errors, and the instance of the test pattern included in the other instance of the test mode signal is transmitted without the one or more errors.

[0164] In at least one example, a first of a plurality of operating modes of the expansion device is to be used to process the test signal, the plurality of operating modes includes another low latency mode, and the first mode is to enable decoding of the test signal.

[0165] In at least one example, the extension device comprises a retimer.

[0166] In at least one example, the error reporting sequence describes error status of each of the two or more sub-data links of the data link, and the apparatus further comprises logic to interpret the error reporting sequence and record error results for the data link in at least one data structure.

[0167] In at least one example, the data structure includes one or more registers to correspond to the data connection.

[0168] In at least one example, the expansion device comprises at least two retimers.

[0169] In at least one example, a trunk connection device is connected to the data connection.

[0170] One or more embodiments may provide an apparatus, a system, a machine-readable storage, a machine-readable medium, hardware and / or software-based logic, and a method for receiving data link training data from an endpoint device at a first port of the expansion device, indicating an idle data link condition at a second port of an expansion device where the expansion device is included on a data link, and determining that another device has been disconnected based on the idle data link condition and the data link training data where the other device was previously connected to the data link.

[0171] In at least one example, the data link connects the endpoint device to other devices, and the extension device is disposed between the endpoint and the other devices on the data link.

[0172] In at least one example, the first port is connected to the endpoint device via a first sub-data connection of the data connection and the second port is connected to a second sub-data connection of the data connection, and the other device was previously connected to the second port through the second sub-data connection.

[0173] In at least one example, the extension device comprises a retimer.

[0174] In at least one example, the retimer lacks sideband logic to determine disconnection on the data link.

[0175] In at least one example, the disconnection of the other device comprises an unexpected disconnection.

[0176] In at least one example, disconnecting corresponds to hot-plugging a device on the data link.

[0177] In at least one example, switching to a detection mode based on determining that another device has been disconnected.

[0178] In at least one example, transition points of the second port are to be removed to search for and establish a new connection (e.g., with a third device) on the second sub-data link in the detection mode.

[0179] In at least one example, the data link training data comprises one or more training sequences.

[0180] In at least one example, the data connection training data corresponds to an attempt to reestablish the data connection.

[0181] In at least one example, the idle data link condition is inferred based on a level of activity detected at the second port.

[0182] In at least one example, the data link training data is received while the idle data link condition is detected.

[0183] In at least one example, the first port comprises an upstream port and the second port comprises a downstream port.

[0184] In at least one example, the data connection comprises a connection cable.

[0185] One or more embodiments may provide an apparatus, a system, a machine-readable memory, a machine-readable medium, hardware and / or software-based logic, and a method for providing a retimer to support at least two modes of operation and to selectively employ the modes based on conditions on a data link, wherein the modes of operation are to include at least a latency mode and a particulate mode, data received in the low-latency mode is forwarded, and data is decoded and re-encoded in the particulate mode.

[0186] In at least one example, data received by the retimer in low latency mode is not decoded and is forwarded as received.

[0187] In at least one example, the particular mode allows modification of data received by the retimer on the data link.

[0188] In at least one example, the conditions include at least one of a type of data transmitted on the data connection and a data connection state of the data connection.

[0189] In at least one example, the retimer is to detect a particular one of the conditions and use one or more modes of operation based on the particular condition detected.

[0190] In at least one example, the low latency mode is to be used when the data connection is detected as being in an active data connection state.

[0191] In at least one example, the active data link state comprises an L0 state.

[0192] In at least one example, the particular mode is to be used for the training sequence and ordered sentence data.

[0193] In at least one example, the particulate mode is to be used in a data link training link line state.

[0194] In at least one example, the particulate mode is to be used in a test mode.

[0195] In at least one example, the test mode is used to determine error statuses of each of a plurality of sub-data connections of the data connection.

[0196] In at least one example, the data connection uses a PCIe-based protocol.

[0197] One or more embodiments may provide an apparatus, a system, a machine-readable memory, a machine-readable medium, hardware and / or software-based logic, and a method for providing an extension device to comprise physical layer logic, wherein the physical logic comprises a logical physical sublayer and an electrical physical sublayer, the extension device is included on a data link, the electrical physical sublayer comprises a speed detection module for detecting a transmission speed of data on the data link, and the electrical physical sublayer is to communicate the detected transmission speed of the data link to the logical physical sublayer.

[0198] In at least one example, the extension device comprises a retimer device.

[0199] In at least one example, the transmission speed is to be detected as being one of a predetermined set of speeds for the data connection.

[0200] In at least one example, the set of speeds includes a 2.5 GT / s speed, a 5 GT / s speed, and an 8 GT / s speed.

[0201] In at least one example, the speed detection module comprises an analog speed detection module.

[0202] In at least one example, the speed detection module is at least partially implemented in hardware.

[0203] In at least one example, the data connection comprises a PCIe-compliant data connection.

[0204] One or more embodiments may include an apparatus, a system, a machine-readable storage, a machine-readable medium, hardware and / or software-based logic, and a method for receiving data at an expansion device on a data link connecting a first endpoint to a second endpoint, the expansion device being located between the first and second endpoints on the data link, detecting a transmission rate of data using speed detection circuitry implemented in hardware on the expansion device, communicating the detected transmission rate to physical layer logic of the expansion device, and using the expansion device to transmit the data at the transmission rate over the data link from a first device to a second device.

[0205] In at least one example, the detected transmission rate is communicated to the physical layer logic using a physical layer interface between an electrical physical sublayer and a logical physical sublayer of the expansion device.

[0206] In at least one example, the physical layer interface comprises a PHY Interface for PCI Express (PIPE) interface.

[0207] In at least one example, detecting the transmission speed comprises detecting that the transmission speed is one of a set of predetermined speeds supported for the data connection.

[0208] In at least one example, an idle condition on the data link is identified and the transmission rate is to be detected following the idle condition.

[0209] In at least one example, the data comprises data link training data, and the transmission speed is to be detected from the data link training data.

[0210] Reference in this specification to "one embodiment" means that a feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the present invention. Therefore, the appearances of the phrase "in one embodiment" in various places throughout this specification do not necessarily all refer to the same embodiment. Moreover, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0211] In the foregoing specification, a detailed description has been given with reference to specific exemplary embodiments. However, it will be apparent that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The description and drawings are accordingly to be regarded in an illustrative rather than a restrictive sense. Furthermore, the foregoing use of embodiment and other exemplary terms do not necessarily refer to the same embodiment or example, but may refer to different and distinct embodiments, as well as to the same embodiment at times.

Claims

[1] Device (650, 660, 665, 655) comprising: Control logic for: Generating a test mode signal (670a, ..., 670f) comprising a test pattern (620) and an error reporting sequence (625); and Send logic for: Transmitting the test mode signal on a data link comprising one or more expansion devices (660, 665) and two or more sub-data links (675a, 675b, 675c), wherein the test mode signal is to be transmitted on a particular one of the sub-data links, the test pattern is to be used by a receiving device to identify errors on the particular sub-data link, and the error report sequence is to be encoded with error information to describe error statuses of sub-data links in the plurality of sub-data links. [2] The apparatus of claim 1, wherein the test mode signal is transmitted within a loopback test mode and instances of the test mode signal are to be transmitted from a first device on the data link to a second device via the one or more extension devices and further at least one is to be transmitted from the second device back to the first device via the one or more extension devices. [3] The apparatus of claim 2, further comprising receiver logic for receiving at least one of the instances of the test mode signal from another device on another of the sub-data links of the data link, wherein each instance of the test mode signal comprises an instance of the test pattern and an instance of the error reporting sequence. [4] The apparatus of claim 3, further comprising error detection logic for determining one or more errors on the other sub-data link based on the instance of the test pattern, wherein errors for a sub-data link are determined based on an identification that an instance of the test pattern included in a test mode signal received over the sub-data link deviates from an expected value for the test pattern. [5] The apparatus of claim 1, wherein the extension device comprises a retimer. [6] The apparatus of claim 5, wherein the apparatus comprises the retimer. [7] The apparatus of claim 1, wherein the error reporting sequence comprises a plurality of segments, each segment describing error status of a respective one of the sub-data links. [8] Apparatus according to claim 7, wherein each segment describes one of a downstream channel and an upstream channel of a respective sub-data connection. [9] Apparatus according to claim 7, wherein each segment comprises one or more ordered sets and at least a portion of each of the ordered sets is provided to be coded to identify error status of at least one of the sub-data links. [10] The apparatus of claim 9, wherein each ordered set comprises a respective SKP-ordered set. [11] The apparatus of claim 7, wherein the one or more expansion devices comprise at least two expansion devices, the two or more sub-data links comprise three sub-data links, and the plurality of segments comprises at least five segments. [12] The apparatus of claim 1, wherein the control logic is arranged to encode error information detected for a previous sub-data link in the error reporting sequence and to maintain error information in the error reporting sequence for previously detected error statuses of other sub-data links in the two or more sub-data links. [13] The apparatus of claim 12, wherein the error information comprises one or more of the following: a number of errors detected for a sub-data link, a trace of the data link on which an error occurred, and a location of errors detected in a received test pattern. [14] The apparatus of claim 1, wherein the test pattern comprises a predetermined pattern to be newly generated at each sub-data connection during a test. [15] The apparatus of claim 14, wherein the test pattern comprises one or more ordered sets. [16] The apparatus of claim 1, wherein the control logic is to identify that the data link is in a test mode, and the test mode signal is sent according to the test mode. [17] Procedure (1100a), which includes: Identifying (1105) that a data connection is to enter a test mode, wherein the data connection comprises one or more extension devices (660, 665) and two or more sub-data connections (675a, 675b, 675c); Generating (1110) a test mode signal (670a, ..., 670f), wherein the test mode signal comprises a test pattern (620) and an error report sequence (625), and the error report sequence is to be encoded with error information to describe error statuses of sub-data links in the plurality of sub-data links; and Sending (1115) the test mode signal within the test mode on a specific one of the subdata connections. [18] The method of claim 17, wherein the error reporting sequence comprises a plurality of segments, each segment describing error status of a respective one of the sub-data links, and generating the test mode signal comprises: Identifying an error status determined for a previous subdata connection in the data connection; and Identifying a specific one of the segments in which the error status of the preceding subdata connection is to be encoded; and Encoding the error status in the specific segment. [19] Device (650, 660, 665, 655) comprising: Receiver logic for: Receiving a test mode signal (670a, ..., 670f) on a data link in a test mode, wherein the data link comprises at least one extension device (660, 665) and two or more sub-data links (675a, 675b, 675c), the test mode signal comprises a test pattern and an error reporting sequence, the test mode signal is transmitted on a particular one of the sub-data links, and the error reporting sequence is to be encoded with error information to describe error statuses of sub-data links in the plurality of sub-data links; and Control logic for: Evaluating the test pattern in the test mode signal to identify a fault status of the particular sub-data link. [20] The apparatus of claim 19, wherein the test pattern is evaluated to determine whether the test pattern deviates from an expected test pattern. [21] Apparatus according to claim 20, wherein the test pattern is defined for a test mode, the test mode comprises a test of each sub-data connection of the data connection, and a respective instance of the test pattern is to be generated and transmitted in each of the tests of the sub-data connections to determine whether the respective instance of the test pattern received at the end of the respective sub-data connection deviates from the defined test pattern. [22] The apparatus of claim 19, wherein the control logic is arranged to generate another instance of the test mode signal, wherein the another instance of the test mode signal comprises an error reporting sequence encoded to identify the error status of the particular sub-data link, the apparatus further comprising transmit logic for transmitting the another instance of the test mode signal on another one of the sub-data links. [23] The apparatus of claim 22, wherein the error reporting sequence in the other instance of the test mode signal retains error status information for previously determined error statuses of other sub-data links of the data link. [24] The apparatus of claim 22, wherein the error reporting sequence comprises a plurality of segments, each segment describing error status of a respective one of the sub-data links. [25] Apparatus according to claim 24, wherein the control logic is to identify a particular one of the plurality of segments in which the error status of the respective sub-data connection is to be encoded. [26] Procedure (1100b), which includes: Receiving (1120) a test mode signal (670a, ..., 670f) on a data link in a test mode, wherein the data link comprises at least one expansion device (660, 665) and two or more sub-data links (675a, 675b, 675c), the test mode signal comprises a test pattern and an error reporting sequence, and the error reporting sequence is to be encoded with error information to describe error statuses of sub-data links in the plurality of sub-data links, and the test mode signal is transmitted on a particular one of the sub-data links; Evaluating the test pattern in the test mode signal to identify whether the test pattern substantially corresponds to an expected test pattern; and Determining an error status of the particular sub-data connection based on evaluating the test pattern. [27] The method of claim 26, wherein the test mode signal comprises a first test mode signal, and the method further comprises: Generating a second test mode signal, wherein the second test mode signal comprises an instance of the test pattern according to the expected test pattern and an instance of the error reporting sequence adding the error status specified for the particular sub-data connection; and Transmitting the second test mode signal on another of the two or more subdata links. [28] System (600a, ..., 600e) comprising: a first device (650, 655); a second device (650, 655) communicatively coupled to the first device by means of a data connection; one or more extension devices (660, 665) included on the data link, wherein data is to be sent between the first and second devices via the extension devices; and a test mode logic to: Sending test mode signals (670a, ..., 670f) within a test mode of the data connection, wherein the data connection comprises a plurality of sub-data connections (675a, 675b, 675c), each instance of the test mode signal corresponds to a test of a respective one of the sub-data connections and comprises a test pattern and an error reporting sequence, the test pattern is to be used by a device receiving the test mode signal to identify errors on the corresponding data connection, and the error reporting sequence is to be encoded with error information to describe an error status determined for the sub-data connections. [29] The system of claim 28, wherein the test mode logic is further to: Receiving test mode signals and evaluating the test pattern in the test mode signal to identify a fault status of the sub-data link corresponding to the test mode signal. [30] The system of claim 29, wherein each of the expansion devices and the first device comprise a respective instance of the test mode logic. [31] The system of claim 30, wherein the second device also includes an instance of the test mode logic. [32] The system of claim 28, further comprising one or more registers and reporting logic for recording error status information for the plurality of sub-data links determined by the test mode signals and included in the error reporting sequences in the one or more registers corresponding to the data link. [33] The system of claim 28, wherein the first device comprises a trunk connection device.

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