Optoelectronic component and method for its manufacture

Abstract

Method for producing an optoelectronic component (10) comprising the following steps: - Providing a housing (100) having a first surface (101) and a second surface (102), wherein an electrically conductive chip carrier (110) and a contact (120) are embedded in the housing (100) and are accessible at least in places on the first surface (101) and on the second surface (102); - applying an insulation layer (130) to the second surface (102) of the housing (100) by means of aerosol deposition, wherein - the insulation layer (130) has a first opening (131) and a second opening (132), - an underside (112) of the chip carrier (110) is accessible through the first opening (131), and - a bottom side (122) of the contact (120) is accessible through the second opening (132); and - applying a metallization (140) to portions of the insulation layer (130) and the second surface (102).

Description

[0001] The present invention relates to a method for producing an optoelectronic component according to claim 1 and to an optoelectronic component according to claim 12.

[0002] The following publications describe optoelectronic components: JP 2011- 91 259 A, DE 10 2010 021 791 A1, DE 10 2012 207 519 A1.

[0003] Optoelectronic components with high power consumption, such as high-performance light-emitting diodes, are known to generate high levels of waste heat. It is common practice to equip such optoelectronic components with thermal contact surfaces to dissipate the waste heat. Such thermal contact surfaces consist of an electrically conductive material and are often electrically connected to a potential of an optoelectronic semiconductor chip of the optoelectronic component. For many applications, however, it would be more advantageous to design the thermal contact surface of an optoelectronic component as potential-free.

[0004] It is known to form optoelectronic components with ceramic packages to provide a potential-free thermal contact surface. However, such ceramic packages are associated with high costs.

[0005] A process for aerosol deposition of ceramics is known from the prior art. In this process, ceramics are applied in the form of powder with particle sizes of, for example, a few micrometers in a gas stream with a particle velocity of, for example, 100 m / s to 500 m / s.

[0006] An object of the present invention is to provide a method for producing an optoelectronic component. A further object of the present invention is to provide an optoelectronic component.

[0007] The objects are achieved by the method according to claim 1 and the optoelectronic component of claim 12.

[0008] In a method for producing an optoelectronic component, steps are carried out to provide a housing with a first surface and a second surface, wherein an electrically conductive chip carrier is embedded in the housing and is accessible at the first surface and at the second surface. The term "embedded" can mean here and below that the housing has a recess in which the electrically conductive chip carrier is located. In other words, the electrically conductive chip carrier is enclosed by the housing on at least two sides. Furthermore, the term "accessible" can mean here and below that the first and the second surface are each at least partially free of an electrically insulating material, for example of the housing. Electrical contact can be made with the first and / or the second surface at these locations.

[0009] Furthermore, steps are carried out for applying an insulating layer to the second surface of the housing using the aerosol deposition method. A layer applied using the aerosol deposition method can, in particular, comprise an electrically insulating material deposited in the form of particles. In particular, a layer applied using the aerosol deposition method can be a highly dense yet thin ceramic layer. Using the aerosol deposition method, it is thus possible to provide a thin, electrically insulating insulating layer which, due to its small thickness, only marginally increases the thermal resistance of the optoelectronic component.

[0010] The aerosol deposition process allows the insulation layer to be produced with the desired properties through the targeted selection of the particle material(s), the particle size distribution, and the process conditions. Compared to conventional coating processes such as vacuum deposition, chemical vapor deposition, sputtering, or ion plating, the aerosol deposition process enables qualitatively and quantitatively efficient application of the material of the electrically insulating insulation layer in the form of an unstructured or structured layer. Unlike sintering processes, which typically involve applying dispersant-containing pastes containing the desired material particles, the aerosol deposition process eliminates the need for liquid dispersants.The aerosol deposition process can therefore offer higher efficiency and higher process compatibility for the production of the electrically insulating insulation layer compared to processes commonly used in semiconductor technology.

[0011] Advantageously, in an optoelectronic component produced using this method, a thermal contact surface can be electrically insulated from the electrically conductive chip carrier by the insulation layer, thereby rendering the thermal contact surface potential-free. The insulation layer can advantageously cause only a minimal increase in thermal resistance. The method is advantageously cost-effective. In particular, the application of the insulation layer can be carried out cost-effectively using aerosol deposition. The application of the insulation layer can advantageously be carried out at a high process speed, enabling mass production.

[0012] In one embodiment of the method, the insulating layer comprises a ceramic. Advantageously, the insulating layer can thus be applied with high electrical breakdown strength and good thermal conductivity.

[0013] In one embodiment of the method, the insulation layer comprises Al 2 O 3 (aluminum oxide). Advantageously, Al 2 O 3 available at low cost and has favorable mechanical, thermal and electrical properties.

[0014] In one embodiment of the method, a shadow mask or a stencil is used when applying the insulation layer. This advantageously allows the insulation layer to be applied with openings that enable electrical contact with the second surface of the housing of the optoelectronic component. Advantageously, no further process steps are required to create the openings, making the method simple and cost-effective.

[0015] In one embodiment of the method, the insulation layer is applied with a thickness between 1 µm and 20 µm. The insulation layer can preferably have a thickness of at most 10 µm. Advantageously, the insulation layer then has sufficient breakdown strength. A further advantage is that such a thin insulation layer can be applied within a very short processing time. A further advantage is that such a thin insulation layer only causes a slight increase in thermal resistance.

[0016] The method comprises an additional step of applying a metallization to sections of the insulation layer and the second surface. The metallization can serve to create electrical and thermal contact surfaces. Advantageously, in an optoelectronic component produced according to this method, a thermal contact surface formed by a section of the metallization can be electrically insulated from the electrically conductive chip carrier by the insulation layer, thereby rendering the thermal contact surface potential-free.

[0017] In one embodiment of the method, a seed layer is applied to the insulation layer and the second surface to apply the metallization. The metallization is then electroplated onto the seed layer. This advantageously allows for rapid and cost-effective application of the metallization.

[0018] In one embodiment of the method, the metallization is structured by partially removing the metallization. Advantageously, the metallization can thereby be divided into different surface sections that are electrically insulated from one another.

[0019] In one embodiment of the method, this comprises an additional step of arranging an optoelectronic semiconductor chip on the first surface of the housing such that an electrically conductive connection exists between the optoelectronic semiconductor chip and the chip carrier. Advantageously, the optoelectronic semiconductor chip arranged on the first surface can then be electrically contacted via the chip carrier.

[0020] The package is provided with an electrically conductive contact embedded in the package, which is accessible at the first surface and at the second surface. Advantageously, the electrically conductive contact embedded in the package can then provide a further electrically conductive connection to the optoelectronic semiconductor chip.

[0021] In one embodiment of the method, this comprises an additional step of establishing an electrically conductive connection between the optoelectronic semiconductor chip and the contact. Advantageously, the optoelectronic semiconductor chip can then be electrically contacted to the second surface of the housing of the optoelectronic component via the embedded contact.

[0022] An optoelectronic component comprises a housing with a first surface and a second surface. An electrically conductive chip carrier is embedded in the housing and accessible at the first surface and the second surface. An optoelectronic semiconductor chip is arranged on the first surface of the housing. An electrically conductive connection exists between the optoelectronic semiconductor chip and the chip carrier. A ceramic insulation layer is arranged on the second surface of the housing. Advantageously, in this optoelectronic component, a thermal contact surface can be electrically insulated by the insulation layer from the chip carrier embedded in the housing and thus also from the optoelectronic semiconductor chip of the optoelectronic component, which is electrically conductively connected to the chip carrier. As a result, the thermal contact surface is potential-free.Due to the high electrical breakdown strength of ceramics, the ceramic insulation layer can advantageously have a thin layer thickness while still maintaining a sufficiently high electrical breakdown strength. The ceramic insulation layer only slightly increases thermal resistance.

[0023] The insulation layer has a thickness between 1 µm and 20 µm. Preferably, the insulation layer can have a thickness of at most 10 µm. Advantageously, the insulation layer then has a high electrical breakdown strength and high thermal conductivity.

[0024] In the optoelectronic component, metallization is arranged on sections of the insulation layer and the second surface. Advantageously, in this optoelectronic component, a thermal contact surface can be formed by a section of the metallization. The thermal contact surface is electrically insulated by the ceramic insulation layer from the chip carrier embedded in the housing and thus also from the optoelectronic semiconductor chip of the optoelectronic component, which is electrically conductively connected to the chip carrier. As a result, the thermal contact surface formed in the metallization is potential-free. Furthermore, electrical contact surfaces of the optoelectronic component can also be formed by sections of the metallization.

[0025] In one embodiment of the optoelectronic component, a first surface section of the metallization is in electrically conductive connection with the chip carrier. A second surface section of the metallization is insulated from the chip carrier by the insulation layer. The first surface section and the second surface section are electrically insulated from one another. Advantageously, the first surface section of the metallization can then serve to electrically contact the optoelectronic semiconductor chip of the optoelectronic component. The second surface section of the metallization can serve as a thermal contact surface for dissipating waste heat generated by the optoelectronic semiconductor chip from the optoelectronic component. The thermal contact surface is advantageously potential-free.

[0026] An electrically conductive contact is embedded in the housing and accessible at the first surface and the second surface. An electrically conductive connection exists between the optoelectronic semiconductor chip and the contact. Furthermore, a third surface section of the metallization is in electrically conductive connection with the contact. Advantageously, the third surface section of the metallization can then also serve to electrically contact the optoelectronic semiconductor chip of the optoelectronic component.

[0027] In one embodiment of the optoelectronic component, a recess is formed on the first surface of the housing. The optoelectronic semiconductor chip is arranged at the bottom of the recess. Advantageously, the optoelectronic semiconductor chip is protected from mechanical damage at the bottom of the recess. Furthermore, walls of the recess can advantageously serve as an optical reflector of the optoelectronic component. The recess can also advantageously serve to accommodate a converter material for wavelength conversion or to attach an optical lens.

[0028] The above-described properties, features, and advantages of this invention, as well as the manner in which they are achieved, will become clearer and more readily understood in connection with the following description of the exemplary embodiments, which are explained in more detail in conjunction with the drawings. In each case, in a schematic representation: Fig. 1 shows a section through a housing of an optoelectronic component in a first processing stage; Fig. 2 a section through the housing of the optoelectronic component in a second processing stage; Fig. 3 a section through the housing of the optoelectronic component in a third processing stage; Fig. 4 a section through the housing of the optoelectronic component in a fourth processing stage; and Fig. 5 a section through the optoelectronic component in a fifth processing stage.

[0029] Fig. Figure 1 shows a schematic sectional view of a housing 100 of an optoelectronic component in a first processing stage during production of the optoelectronic component. The optoelectronic component can be, for example, a light-emitting diode component, in particular a high-power light-emitting diode component.

[0030] The housing 100 has a first surface 101 and a second surface 102 opposite the first surface 101. The housing 100 is partially made of an electrically insulating material, for example, a molding material, such as an epoxy. The housing 100 is preferably manufactured by injection molding or transfer molding or another molding process.

[0031] A chip carrier 110 is embedded in the housing 100. The chip carrier 110 can also be referred to as a first leadframe. The chip carrier 110 comprises a material with good electrical and thermal conductivity, preferably a metal. For example, the chip carrier 110 can comprise copper. The chip carrier 110 has a top side 111 and a bottom side 112 opposite the top side 111. The chip carrier 110 is embedded in the housing 100 such that the top side 111 of the chip carrier 110 is accessible at the first surface 101 of the housing 100. At the same time, the bottom side 112 of the chip carrier 110 is accessible at the second surface 102 of the housing 100. The embedding of the chip carrier 110 in the housing 100 preferably takes place during the manufacture of the housing 100 by overmolding or casting the chip carrier 110 with the material of the housing 100.

[0032] The underside 112 of the chip carrier 110 has a first section 113 and a second section 114. The first section 113 and the second section 114 lie side by side in the lateral direction. The first section 113 and the second section 114 can be delimited from one another by structuring the underside 112 of the chip carrier 110 such that a section of the material of the housing 100 is arranged between the first section 113 and the second section 114. However, the first section 113 and the second section 114 can also be formed as directly connected over a large area. In any case, the first section 113 and the second section 114 are electrically and thermally connected to one another by further parts of the chip carrier 110. The chip carrier 110 can have a simple cylindrical geometry, such as a circular cylindrical geometry, or a more complex geometry.

[0033] Furthermore, a contact 120 is embedded in the housing 100. The contact 120 can also be referred to as a second leadframe. The contact 120 comprises an electrically conductive material. The contact 120 can, for example, comprise the same material as the chip carrier 110. The contact 120 has a top side 121 and a bottom side 122 opposite the top side 121. The contact 120 is embedded in the housing 100 such that the top side 121 of the contact 120 is accessible at the first surface 101 of the housing 100. At the same time, the bottom side 122 of the contact 120 is accessible at the second surface 102 of the housing 100. The embedding of the contact 120 into the housing 100 preferably takes place simultaneously with the embedding of the chip carrier 110 into the housing 100. The contact 120 may have a cylindrical, such as a circular cylindrical, geometry or another geometry.

[0034] The housing 100 has a recess 160 on its first surface 101. The recess 160 is bowl-shaped or crater-shaped. The recess 160 has a substantially flat bottom 161 in its central region, at which the top side 111 of the chip carrier 110 and the top side 121 of the contact 120 are accessible. The bottom 161 of the recess 160 is delimited on the outside by a circumferential wall 162, which is raised relative to the bottom 161. The wall 162 can be beveled such that the recess 160 increasingly widens from the bottom 161. In the plane of the first surface 101 of the housing 100, the recess 160 can be circular or rectangular, for example.

[0035] Fig. 2 shows a schematic sectional view of the housing 100 in a second processing state, which corresponds to the first processing state of the Fig. 1 follows chronologically.

[0036] To achieve the second processing stage, a structured insulation layer 130 is applied to the second surface 102 of the housing 100. The insulation layer 130 is flat and essentially completely covers the second surface 102 of the housing 100. However, the insulation layer 130 has a first opening 131 and a second opening 132. The first opening 131 of the insulation layer 130 is arranged in the region of the second section 114 of the underside 112 of the chip carrier 110 embedded in the housing 100. Thus, the second section 114 of the underside 112 of the chip carrier 110 is accessible through the first opening 131 of the insulation layer 130. The second opening 132 is arranged in the region of the second surface 102 of the housing in which the underside 122 of the contact 120 is accessible. Thus, the underside 122 of the contact 120 is accessible through the second opening 132 of the insulation layer 130.The first section 113 of the bottom side 112 of the chip carrier 110 is covered by the insulation layer 130.

[0037] The insulation layer 130 comprises a ceramic material that is electrically insulating. At the same time, the material of the insulation layer 130 preferably has high thermal conductivity. The insulation layer 130 can, for example, be made of Al 2 O 3 (aluminum oxide). The thermal conductivity of the insulation layer 130 can be, for example, 25 W / mK.

[0038] The insulation layer 130 is applied to the second surface 102 of the housing 100 by aerosol deposition. The material of the insulation layer 130 is applied in the form of a powder with an average particle size of, for example, 2 µm in a gas stream with a particle velocity of, for example, 100 m / s to 500 m / s. The aerosol deposition process allows deposition rates of several µm / min. The aerosol deposition process allows the deposition of a layer with a thickness of up to 0.1 mm or more.

[0039] The insulation layer 130 is preferably deposited using a shadow mask or a stencil. The shadow mask or stencil shades those regions of the second surface 102 of the housing 100 in which the first opening 131 and the second opening 132 of the insulation layer 130 are to be formed. As a result, the insulation layer 130 is applied to all regions of the second surface 102 of the housing 100, except for the regions of the first opening 131 and the second opening 132.

[0040] The insulation layer 130 has a thickness of between 1 µm and 20 µm in the growth direction, i.e., in the direction perpendicular to the second surface 102. Due to the high electrical breakdown strength of the ceramic material of the insulation layer 130, the insulation layer 130 provides sufficient electrical insulation at this thickness. Due to its small thickness, the insulation layer 130 also has only a low thermal resistance.

[0041] Fig. 3 shows a schematic sectional view of the housing 100 in a third processing state, which corresponds to the second processing state of the Fig. 2 follows chronologically.

[0042] To achieve the third processing stage, a metallization 140 is applied to the insulating layer 130 and the parts of the second surface 102 not covered by the insulating layer 130. The parts of the second surface 102 not covered by the insulating layer 130 are located in the region of the first opening 131 of the insulating layer 130 and the second opening 132 of the insulating layer 130.

[0043] The metallization 140 comprises an electrically conductive material, for example, a metal. Preferably, the metallization 140 comprises a material that is well suited for producing solder connections.

[0044] To apply the metallization, a seed layer can first be applied to the insulation layer 130 and the second surface 102 of the housing 100. The seed layer can be applied, for example, by sputtering. The seed layer can then be thickened by electroplating to form the metallization 140. However, the metallization 140 can also be applied using another method.

[0045] Fig. 4 shows a schematic sectional view of the housing 100 in a fourth processing state, which corresponds to the third processing state of the Fig. 3 follows chronologically.

[0046] To reach the fourth processing stage, the metallization 140 is structured. The structuring of the metallization can be performed, for example, using lithographic methods and etching processes. During the structuring of the metallization 140, parts of the metallization 140 are removed. This divides the metallization 140 into laterally spaced-apart surface sections. The metallization 140 is removed in the separation areas between the surface sections.

[0047] A first section 141 of the metallization 140 remains in the region of the second section 114 of the underside 112 of the chip carrier 110. The first section 141 of the metallization 140 is arranged in the region of the first opening 131 of the insulating layer 130. The first section 141 of the metallization 140 is in electrically conductive connection with the chip carrier 110. A second section 142 of the metallization 140 remains in the region of the underside 122 of the contact 120 embedded in the housing 100. The second section 142 of the metallization 140 is arranged in the region of the second opening 132 of the insulating layer 130. The second section 142 of the metallization 140 is in electrically conductive connection with the contact 120. A third section 143 of the metallization 140 remains in the region of the section 113 of the underside 112 of the chip carrier 110.In this case, the insulation layer 130 is arranged between the third section 143 of the metallization 140 and the underside 112 of the chip carrier 110, which provides electrical insulation of the third section 143 of the metallization 140 from the chip carrier 110. The first section 141, the second section 142, and the third section 143 of the metallization 140 are each electrically insulated from one another.

[0048] Fig. Figure 5 shows a schematic sectional view of the housing 100 in a fifth processing stage, which corresponds to the fourth processing stage of Fig. 4 follows chronologically.

[0049] To achieve the Fig.In the fifth processing stage shown in FIG. 5, an optoelectronic semiconductor chip 150 is arranged on the first surface 101 of the housing 100. The housing 100 and the optoelectronic semiconductor chip 150 together form an optoelectronic component 10. The optoelectronic semiconductor chip 150 can be, for example, a light-emitting diode (LED) chip. The optoelectronic component 10 is then a light-emitting diode component. In particular, the optoelectronic semiconductor chip 150 can be an LED chip with high power consumption. The optoelectronic component 10 is then a high-performance light-emitting diode component.

[0050] The optoelectronic semiconductor chip 150 has a first surface 151 and a second surface 152 opposite the first surface 151. A first electrical contact area 153 is arranged on the first surface 151 of the optoelectronic semiconductor chip 150. A second electrical contact area 154 is arranged on the second surface 152 of the optoelectronic semiconductor chip 150. An electrical voltage can be applied to the optoelectronic semiconductor chip 150 between the first electrical contact area 153 and the second electrical contact area 154 in order to operate the optoelectronic semiconductor chip 150.

[0051] If the optoelectronic semiconductor chip 150 is an LED chip, the first surface 151 can form a radiation emission surface of the optoelectronic semiconductor chip 150. If an electrical voltage is applied to the optoelectronic semiconductor chip 150 between the first electrical contact surface 153 and the second electrical contact surface 154, electromagnetic radiation, for example visible light, is generated in the optoelectronic semiconductor chip 150 and emitted through the radiation emission surface formed by the first surface 151.

[0052] The optoelectronic semiconductor chip 150 is arranged on the first surface 101 of the housing 100 such that the second surface 152 of the optoelectronic semiconductor chip 150 faces the first surface 101 of the housing 100. The optoelectronic semiconductor chip 150 is arranged in the region of the upper side 111 of the chip carrier 110, which is accessible on the first surface 101 of the housing 100, so that an electrically conductive connection exists between the second electrical contact area 154 arranged on the second surface 152 of the optoelectronic semiconductor chip 150 and the chip carrier 110.

[0053] An electrical conductive connection 170 is established between the first electrical contact surface 153 arranged on the first surface 151 of the optoelectronic semiconductor chip 150 and the top side 121 of the contact 120. The electrical conductive connection 170 can be, for example, a bonding connection by means of a thin wire (bond wire).

[0054] Thus, the first section 141 of the metallization 140 is electrically conductively connected to the second electrical contact area 154 of the optoelectronic semiconductor chip 150 via the chip carrier 110. The second section 142 of the metallization 140 is electrically conductively connected to the first electrical contact area 153 of the optoelectronic semiconductor chip 150 via the contact 120 and the electrically conductive connection 170. Voltage can be applied to the optoelectronic semiconductor chip 150 via the first section 141 and the second section 142 of the metallization 140 on the underside 102 of the housing 100.

[0055] If the optoelectronic semiconductor chip 150 is operated by applying electrical voltage, the optoelectronic semiconductor chip 150 produces waste heat, which must be dissipated from the optoelectronic semiconductor chip 150 and the remaining parts of the optoelectronic component 10. The waste heat produced by the optoelectronic semiconductor chip 150 can flow into the chip carrier 110 and be conducted from there via the insulation layer 130 into the third section 143 of the metallization 140. The waste heat of the optoelectronic semiconductor chip 150 can be further transported away from the third section 143 of the metallization 140.

[0056] Due to its small thickness, the insulation layer 130 between the chip carrier 110 and the third section 143 of the metallization 140 contributes only a small portion to the thermal resistance. If the insulation layer 130 is made of Al, for example, 2 O 3with a thermal conductivity of 25 W / mK and a thickness of 5 µm, the insulation layer 130 increases the thermal resistance for an optoelectronic semiconductor chip 150, whose second surface 152 has an edge length of, for example, 1 mm, by only approximately 0.2 K / W. With a thickness of the insulation layer 130 of 2.5 µm, the additive contribution of the insulation layer 130 to the thermal resistance is reduced to approximately 0.1 K / W.

[0057] The first section 141, the second section 142, and the third section 143 of the metallization 140 of the optoelectronic component 10 can be attached to a carrier, for example, by means of a soldering process. For example, the sections 141, 142, 143 of the metallization 140 of the optoelectronic component 10 can be contacted by reflow soldering using a surface mount method (SMT method).

[0058] Because of the insulation layer 130 arranged between the third section 143 of the metallization 140 and the chip carrier 110, the third section 143 of the metallization 140 is electrically insulated from the chip carrier 110 and is therefore advantageously not at the electrical potential of the chip carrier 110.

[0059] The optoelectronic semiconductor chip 150 is arranged in the region of the bottom 161 of the recess 160 on the top side 101 of the housing 100. The wall 162 of the housing 100 can serve, for example, as an optical reflector of the optoelectronic component 10. In this case, the wall 162 is preferably formed from an optically reflective material or coated with such a material. The wall 162 of the recess 160 can then serve to reflect radiation emitted by the first surface 151 of the optoelectronic semiconductor chip 150 in the direction of the wall 162 of the recess 160 and thereby to focus the radiation emitted by the optoelectronic semiconductor chip 150.

[0060] The recess 160 of the optoelectronic component 10 can also serve to accommodate a wavelength-converting material intended to convert a wavelength of radiation emitted by the optoelectronic semiconductor chip 150. The wavelength-converting material can, for example, be embedded in a filler material, such as silicone, arranged in the recess 160. Alternatively, a filler material without wavelength-converting material can also be arranged in the recess 160.

[0061] The recess 160 can also serve to attach an optical lens to the housing 100 of the optoelectronic component 10.

[0062] In a simplified variant of the optoelectronic component 10 and the explained method for its production, the application and structuring of the metallization 140 can be omitted. In this variant, the optoelectronic component 10 can be arranged on a carrier having thermal and electrical contact surfaces. The optoelectronic component 10 is arranged on the carrier such that the thermal contact surface of the carrier comes into contact with the insulation layer 130 in the region of the first section 113 of the chip carrier 110. At the same time, the optoelectronic component 10 is arranged such that a first electrical contact surface of the carrier is in electrically conductive connection with the chip carrier 110 through the first opening 131 of the insulation layer 130.In addition, a second electrical contact surface of the carrier is in electrically conductive connection with the contact 120 through the second opening 132 of the insulation layer 130.

Claims

[1] Method for producing an optoelectronic component (10) comprising the following steps: - Providing a housing (100) having a first surface (101) and a second surface (102), wherein an electrically conductive chip carrier (110) and a contact (120) are embedded in the housing (100) and are accessible at least in places on the first surface (101) and on the second surface (102); - applying an insulation layer (130) to the second surface (102) of the housing (100) by means of aerosol deposition, wherein - the insulation layer (130) has a first opening (131) and a second opening (132), - an underside (112) of the chip carrier (110) is accessible through the first opening (131), and - a bottom side (122) of the contact (120) is accessible through the second opening (132); and - applying a metallization (140) to portions of the insulation layer (130) and the second surface (102). [2] Method according to the preceding claim, wherein the insulating layer (130) comprises a ceramic. [3] Method according to one of the preceding claims, wherein the insulation layer (130) Al 2 O 3 has. [4] Method according to the preceding claim, wherein the thermal resistance of the optoelectronic component is increased by at most 0.2 K / W by the insulation layer (130). [5] Method according to one of the preceding claims, wherein a shadow mask or a stencil is used when applying the insulation layer (130). [6] Method according to one of the preceding claims, wherein for applying the metallization (140) a seed layer is applied on the insulation layer (130) and the second surface (102), wherein the metallization (140) is galvanically deposited on the seed layer. [7] Method according to one of the preceding claims, wherein the metallization (140) is structured by partially removing the metallization (140). [8] A method according to any one of the preceding claims, wherein the method comprises the following further step: - Arranging an optoelectronic semiconductor chip (150) on the first surface (101) of the housing (100) such that an electrically conductive connection exists between the optoelectronic semiconductor chip (150) and the chip carrier (110). [9] Method according to one of the preceding claims, wherein the insulation layer (130) partially covers the underside (121) of the chip carrier (110) and the underside (122) of the contact (120). [10] A method according to any one of the preceding claims, wherein the method comprises the following further step: - Producing an electrically conductive connection (170) between the optoelectronic semiconductor chip (150) and the contact (120). [11] Method according to one of the preceding claims, wherein the chip carrier (110) is a leadframe, the housing (100) consists partly of an electrically insulating material, and the embedding of the chip carrier (110) in the housing (100) is carried out by overmolding and / or casting the chip carrier (110) with the material of the housing (100). [12] Optoelectronic component (10) with a housing (100) with a first surface (101) and a second surface (102), wherein an electrically conductive chip carrier (110) and a contact (120) are embedded in the housing (100) and are accessible at least in places on the first surface (101), wherein the electrically conductive chip carrier (110) can be electrically contacted from the outside on the second surface (102), wherein an optoelectronic semiconductor chip (150) is arranged on the first surface (101) of the housing (100), wherein an electrically conductive connection exists between the optoelectronic semiconductor chip (150) and the chip carrier (110), wherein a ceramic insulation layer (130) is arranged on the second surface (102) of the housing (100), wherein the insulation layer (130) has a thickness between 1 µm and 20 µm, wherein the insulation layer (130) has a first opening (131) and a second opening (132), wherein an underside (112) of the chip carrier (110) is accessible through the first opening (131), wherein a bottom side (122) of the contact (120) is accessible through the second opening (132), and wherein a metallization (140) is arranged on portions of the insulation layer (130) and the second surface (102). [13] Optoelectronic component (10) according to the preceding claim, wherein the insulation layer (130) has a thickness between 1 µm and 10 µm. [14] Optoelectronic component (10) according to one of the two preceding claims, wherein the thermal resistance of the optoelectronic component (10) is increased by at most 0.2 K / W by the insulation layer (130). [15] Optoelectronic component (10) according to one of claims 12-14, wherein a first surface portion (141) of the metallization (140) in the region of the first opening (131) is in electrically conductive connection with the chip carrier, wherein a second surface portion (143) of the metallization (140) is insulated from the chip carrier (110) by the insulation layer (130), wherein the first surface portion (141) and the second surface portion (143) are electrically insulated from each other. [16] Optoelectronic component (10) according to one of the two preceding claims, wherein an electrically conductive connection (170) exists between the optoelectronic semiconductor chip (150) and the contact (120), wherein a third surface portion (142) of the metallization (140) in the region of the second opening (132) is in electrically conductive connection with the contact (120). [17] Optoelectronic component (10) according to one of claims 12-16, wherein the metallization (140) covers the insulation layer (130) in the region of the first opening (131) and in the region of the second opening (132) on a side opposite the housing (100). [18] Optoelectronic component according to one of claims 12-17, wherein the chip carrier (110) is a leadframe, the housing (100) consists partly of an electrically insulating material, and the chip carrier (110) is completely enclosed by the housing (100) on at least two sides.

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