High-voltage field-effect transistor with multiple implanted layers and method for its fabrication

Abstract

Method for manufacturing a high-voltage field-effect transistor (100; 800), the method comprising: Forming a body region (106) in a semiconductor substrate (102); Forming a source region (108) in the semiconductor substrate (102); Forming a drain region (104) in the semiconductor substrate (102) which is separated from the source region (108) by the body region (106), wherein the formation of the drain region (104) comprises the following: Forming a first oxide layer (122) on a surface (118) of the semiconductor substrate (102) over the drain region (104) using a thermal oxidation process, wherein the first oxide layer (122) has a thickness of 20 - 500 nanometers, as well as Performing a plurality of ion implantation processes through the oxide layer (122) while simultaneously tilting the semiconductor substrate (102) such that the ion beams strike the oxide layer (122) at an angle that deviates from the perpendicular, wherein the plurality of ion implantation processes forms a corresponding plurality of separate implanted layers (110; 810) within the drain region (104), and wherein each of the implanted layers (110; 810) is formed at a different depth in the drain region (104); and Deposition of a second oxide layer (126) on the first oxide layer (122) using a low-temperature oxide deposition process.

Description

BACKGROUND INFORMATIONArea of ​​Revelation

[0001] The disclosure relates to the manufacture of field-effect transistors, more specifically, to the manufacture of high-voltage field-effect transistors. Background of the invention

[0002] High-voltage field-effect transistors (HVFETs) can be used in a wide variety of circuit applications, such as power converter circuits. For example, an HVFET can be used as a current switch in a power converter circuit. Examples of power converter topologies, such as HVFET current switches, can include non-isolated power conversion topologies (e.g., buck converters or inverting converters) and isolated power conversion topologies (e.g., flyback converters).

[0003] An HVFET may be exposed to high voltages and currents during operation in a power conversion unit. HVFETs may be exposed to several hundred volts (e.g., 700–800 V) during operation. Accordingly, HVFETs may be designed for high breakdown voltages. HVFETs may also be designed for relatively low on-resistance to minimize conductivity losses during operation of the power converter circuit.

[0004] US Pat. No. 6,773,997 B2 describes a high-voltage MOSFET device featuring an n-well region with a p-top layer of opposite conductivity to improve device properties. The p-top layer is implanted through a thin gate oxide and later diffused into the silicon during the source / drain annealing process. No field oxide is grown on top of the extended drain region, except for two islands of field oxide near the source and drain diffusion regions. This eliminates the possibility of the p-tip being consumed by the field oxide and enables a shallow p-tip with a highly controlled and predictable p-tip to achieve a low on-state resistance while maintaining the desired breakdown voltage. US Pat. No. 5,270,226 A describes that electrically symmetrical transistor properties are achieved by forming the source and drain regions symmetrically with respect to the gate electrodes. After forming the first source and drain regions by ion implantation with a large tilt angle, without a sidewall in the gate electrode, or after forming a sidewall shorter than the distance in the lateral direction of the second source and drain regions from the end of the ion implantation mask, the diffusion of the second source and drain regions in the lateral direction is limited to the maximum extent by a short-term heat treatment, and then the end of the gate electrode and the end of the second source and drain regions are aligned, or their overlap region is formed. As a result, the MOS transistor manufacturing process results in both high performance and high reliability. US Pat. No. 6,429,077 B1 describes a method for fabricating a lateral diffused metal-oxide-semiconductor transistor (LDMOS) on a semiconductor wafer. An ion implantation process is performed on a predetermined region of the silicon substrate to form a p-well adjacent to an n-well. Subsequently, an insulating layer is formed on a predetermined region of the n-well. A gate layer is formed on a portion of the p-well and the n-well, and one side of the gate layer is positioned on the surface of the insulating layer. Finally, an ion implantation process is performed to form two n-doped regions on the p-well and the n-well. The two doped regions are used as the source and drain of the LDMOS transistor. US Pat. No. 4,454,648 A describes a combined process that allows both MNOS and CMOS devices to be fabricated on the same wafer in very large integration systems. Conventional trench isolation techniques are replaced by low-temperature ion implantation processes to achieve substrate isolation. Both n- and p-channel MOS transistor diffusions and field oxidation are processed simultaneously. Furthermore, this process no longer uses epitaxial wafer material as the substrate, but rather bulk silicon. The document US 7 008 865 B2 describes that a semiconductor device includes a semiconductor substrate of a first conductivity type in which an extended drain region of a second conductivity type and a source region of the second conductivity type are formed with a distance therebetween, wherein the extended drain region includes a plurality of buried layers each formed by burying an impurity layer of the first conductivity type, wherein the plurality of buried layers extend substantially parallel to a substrate surface and with a distance therebetween in a depth direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Non-limiting and non-exhaustive embodiments of the subject disclosure are described with reference to the following figures, wherein like reference numerals may refer to like parts throughout the several views. Fig. is a side view of a high-voltage field-effect transistor (HVFET). Fig. is a flow chart showing the manufacturing of the HVFET from Fig. described. Fig. is a side sectional view of a substrate including a drain region and a body region of the HVFET of Fig. . Fig. is a side view of a substrate including a thin oxide layer. Fig. is a side view of ion implantation procedures used for implanting implanted layers of the HVFET of Fig. be performed. Fig. is a side view of a substrate enclosing a thick oxide layer. Fig. is a side cross-sectional view of a substrate including an etched thick oxide layer and an etched thin oxide layer. Fig. is a side view of an alternative HVFET.

[0006] Throughout the several views of the drawings, corresponding reference numerals may refer to corresponding components. Those skilled in the art will appreciate that elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to actual size. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to aid in better understanding various embodiments of the subject disclosure. DETAILED DESCRIPTION

[0007] A high-voltage field-effect transistor (HVFET) of the present disclosure can be fabricated on a substrate (e.g., on a doped silicon substrate). Generally, the processing operations used to form the HVFET can be performed on the surface of the substrate. For example, the doping, patterning, and layering operations used to fabricate the HVFET can be performed on the surface of the substrate.

[0008] The HVFET includes a drain region (e.g. drain region 104 of Fig. ), a source area (e.g. source area 108 of Fig. ) and a body area (e.g. body area 106 of Fig. ) formed in the substrate. The drain region and the source region are optionally separated from each other by the body region. The drain region may comprise a doped region (e.g., an n-well) formed in the substrate. The body region may be a doped region (e.g., a p-well) formed in the substrate adjacent to the drain region. The source region may be a doped region (e.g., P+ and N+ doped regions) formed within the body region such that a portion of the body region is disposed between the source region and the drain region.

[0009] A variety of different layers can be formed over the surface of the substrate. A gate oxide layer and a gate electrode can be formed over the upper side of the portion of the body region located between the source and drain regions. The portion of the body region below the gate electrode and gate oxide can form a channel region of the HVFET. Source and drain electrodes can also be formed to provide contacts for the source and drain regions.

[0010] The HVFET of the present disclosure may also include a thin oxide layer formed over the drain region. The thin oxide layer may be present during the fabrication of the features included in the drain region (e.g., implanted layers 110). The thin oxide layer may also be present in the final HVFET, as shown in Fig. The structure and fabrication of the drain region are described below.

[0011] The drain region of the HVFET comprises a plurality of implanted layers (e.g., implanted layers 110-1, 110-2, 110-3 of Fig. ). As described in this document, the implanted layers may be p-doped regions within the n-well of the drain region. Each implanted layer may have a planar geometry approximately parallel to the surface of the substrate. Accordingly, the implanted layers may be approximately parallel to each other. The implanted layers may be formed at different depths within the drain region such that the implanted layers are stacked on top of or below each other. The p-type implanted layers may be separated from each other by the n-type regions of the drain region.

[0012] The three implanted layers may be referred to as a top implanted layer, a middle implanted layer, and a bottom implanted layer. In some examples, the top implanted layer may be formed on the surface of the substrate (see, for example, Fig. ). In other examples (see e.g. Fig. ), the topmost implanted layer may be formed at a distance below the surface of the substrate such that an n-type portion of the drain region is disposed between the topmost implanted layer and the surface of the substrate. The middle implanted layer may be formed below the topmost implanted layer and separated from the topmost implanted layer by a region of the n-well. The bottommost implanted layer may be formed below the middle implanted layer and separated from the middle layer by a region of the n-well.

[0013] The three implanted layers can be implanted into the drain region using ion implantation processes. In general, an ion implantation process is performed by emitting an ion beam of selected energy onto the substrate to implant one of the implanted layers. As described later in this document (e.g., with respect to Fig. ), the three implanted layers may be implanted through a thin oxide layer formed on the surface of the substrate. Implantation through the thin oxide layer may assist in creating implanted layers with a doping profile conforming to a Gaussian distribution. In some examples, the substrate may be tilted during an ion implantation process such that the ion beam impinges on the thin oxide layer at a non-perpendicular angle. For example, the substrate may be tilted such that the ion beam impinges on the thin oxide layer at an angle approximately 3-10 degrees from perpendicular. Implantation while the substrate is tilted may also assist in creating implanted layers with a doping profile conforming to a Gaussian distribution.

[0014] The thin oxide layer over the top of the drain region may remain over the drain region during subsequent processing operations. For example, additional layers (e.g., insulators and electrodes) may be built over the top of the thin oxide layer during subsequent processing operations. In some examples, the thin oxide layer may be present in a finished HVFET device, as shown in Fig. and Fig. shown.

[0015] Examples of HVFETs and the fabrication of the example HVFETs are described below with reference to Fig. described. In Fig. and Fig. Example HVFETs are shown. Fig. shows an example process for manufacturing HVFETs. Fig. show different phases of HVFET manufacturing, as in the process of Fig. described.

[0016] Fig. is a side cross-sectional view of an HVFET 100 of the subject disclosure. The HVFET 100 can be used in a variety of different electronic applications. For example, the HVFET 100 can be used as a current switch in a switched power circuit. In one example, the HVFET 100 can be used for applications with a voltage rating of 700 volts, a current rating of 5 amperes, and a resistance R DSON of 1 ohm.

[0017] The HVFET 100 includes a p-type semiconductor substrate 102. The p-type semiconductor substrate 102 may be a p-doped silicon wafer. The p-type semiconductor substrate 102 may be referred to as "substrate 102" hereinafter in this document. Substrate 102 includes a drain region 104, a body region 106, and a source region 108. Source region 108 may refer to the combination of P+ region 108-1 and N+ region 108-2. A portion of the body region 106 is disposed between the drain region 104 and the source region 108.

[0018] Drain region 104 is formed within substrate 102. For example, drain region 104 may be an n-well formed within substrate 102. Drain region 104 includes three implanted layers 110-1, 110-2, and 110-3 (collectively, "implanted layers 110"). Drain region 104 may also include a drain contact region 112. Drain contact region 112 may be a heavily n-doped (N+) region within drain region 104. Drain contact region 112 may be in contact with a drain electrode 114. Drain electrode 114 may serve as a drain terminal of HVFET 100, connected to circuitry external to HVFET 100. In some examples, drain electrode 114 may be a metallic electrode.

[0019] Body region 106 is formed in substrate 102 adjacent to drain region 104. For example, body region 106 may be a doped region (e.g., a p-well) formed in substrate 102 adjacent to drain region 104. In some examples, body region 106 may abut (e.g., form an interface with) drain region 104.

[0020] Source region 108 may include one or more doped regions within body region 106. For example, source region 108 may include a heavily p-doped (P+) region 108-1 formed within body region 106 and a heavily n-doped (N+) region 108-2. Source region 108 is separated from drain region 104 by body region 106. For example, source region 108 is formed within body region 106 such that a portion of body region 106 is disposed between source region 108 and drain region 104. The portion of body region 106 disposed between source region 108 and drain region 104 may include a portion of the "channel region" of HVFET 100. Source region 108 may be in contact with a source electrode 116. Source electrode 116 may serve as the source terminal of HVFET 100, connected to circuitry external to HVFET 100. In some examples, source electrode 116 may be a metallic electrode.

[0021] As described above, drain region 104 may include three implanted layers 110. Although three implanted layers 110 are illustrated and described herein, it is contemplated that additional implanted layers may be formed in drain region 104 according to the techniques of the subject disclosure. Implanted layer 110-1 may be referred to in this document as the "topmost implanted layer 110-1." Implanted layer 110-2 may be referred to in this document as the "middle implanted layer 110-2." Implanted layer 110-3 may be referred to in this document as the "bottommost implanted layer 110-3."

[0022] Implanted layers 110 may be p-doped layers (e.g., using boron) within the drain region 104. Implanted layers 110 may be implanted into the drain region 104 using the ion implantation processes described herein. Each of the implanted layers 110 may have nearly planar geometries extending within the drain region 104 approximately parallel to surface 118. Accordingly, implanted layers 110 can be thought of as p-doped regions within the drain region 104 that are approximately parallel to surface 118 and parallel to each other.

[0023] Implanted layers 110 may be formed at different depths within drain region 104 such that the implanted layers 110 are stacked on top of and below each other. Implanted layers 110 may be separated from each other by regions of the n-well that are not p-doped by the ion implantation processes. In other words, implanted layers 110 may be formed in drain region 104 such that implanted layers 110 are separated from drain region 104 by n-doped regions 120-1, 120-2.

[0024] The uppermost implanted layer 110-1 is optionally separated from the middle implanted layer 110-2 by the n-doped region 120-1. In other words, the n-doped region 120-1 can be arranged between the uppermost implanted layer 110-1 and the middle implanted layer 110-2 and can optionally extend along the longitudinal axes of the uppermost implanted layer 110-1 and the middle implanted layer 110-2. The middle implanted layer 110-2 is optionally separated from the lowermost implanted layer 110-3 by the n-doped region 120-2. In other words, the n-doped region 120-2 can be arranged between the middle implanted layer 110-2 and the lowermost implanted layer 110-3 and can optionally extend along the longitudinal axes of the middle implanted layer 110-2 and the lowermost implanted layer 110-3.

[0025] In the HVFET 100 from Fig. the top implanted layer 110-1 may be formed on surface 118. In other examples, e.g., with respect to Fig. , the top implanted layer 810-1 may be formed below surface 118 of substrate 102 such that an n-doped region 820-1 is disposed between the top implanted layer 810-1 and surface 118.

[0026] The implanted layers 110 may extend in a direction parallel to surface 118. As illustrated in this document, in some examples, the implanted layers 110 may extend from a portion of the drain region 104 that is close to the drain contact region 112 to a portion of the drain region 104 that is close to the body region 106. However, as illustrated in Fig. As shown, in some examples, the implanted layers 110 do not make contact with the drain contact region 112 and the body region 106. Rather, in these examples, an n-doped region of the drain region 104 may separate the implanted layers 110 from the drain contact region 112. Similarly, an n-doped region of the drain region 104 may separate the implanted layers 110 from the body region 106. In other words, edges of the implanted layers 110 close to the drain contact region 112 are separated from the drain contact region 112 by an n-doped region of the drain region 104. Similarly, edges of the implanted layers 110 close to the body region 106 are separated from the body region 106 by an n-doped region of the drain region 104.

[0027] In the example HVFET 100 from Fig. The middle implanted layer 110-2 and the bottom implanted layer 110-3 may be surrounded by n-doped regions of drain region 104. The top implanted layer 110-1 is surrounded on all sides by n-doped regions of drain region 104, except on the side of the top implanted layer 110 at surface 118. The side of the top implanted layer 110-1 at surface 118 may abut the thin oxide layer 122. In the example HVFET 800 of Fig. Each of the implanted layers 810 may be surrounded by n-doped regions of the drain region 104.

[0028] The HVFET 100 includes a thin oxide layer 122, a gate oxide layer 124, and a thick oxide layer 126. The thin oxide layer 122 may be formed on surface 118 above the top of implanted layers 110. For example, the thin oxide layer 122 may completely cover the portion of surface 118 above the top of the implanted layers 110. As described further below, the thin oxide layer 122 may be formed on surface 118 prior to implanting the implanted layers 110. After the thin oxide layer 122 is formed, the implanted layers 110 may be implanted through the thin oxide layer 122 into the drain region 104 during ion implantation processes.

[0029] Gate oxide layer 124 may be formed on surface 118 over the upper side of body region 106. For example, gate oxide layer 124 may cover the portion of body region 106 that is located between drain region 104 and source region 108. As shown in Fig. As shown, the gate oxide layer 124 may be formed adjacent to the thin oxide layer 122 such that the gate oxide layer 124 and the thin oxide layer 122 form a continuous oxide layer covering the surface 118.

[0030] A gate electrode 128 may be formed on top of gate oxide layer 124 above the upper side of body region 106. The portion of body region 106 and drain region 104 below gate oxide layer 124 and gate electrode 128 may form a channel region of HVFET 100. Accordingly, in some examples, the channel region of HVFET 100 may extend from the edges of implanted layers 110 to source region 108. Gate electrode 128 may serve as a gate terminal of HVFET 100, optionally connected to circuitry external to HVFET 100. In some examples, gate electrode 128 may be a heavily doped polycrystalline silicon material. Modulating a gate voltage applied to gate electrode 128 may modulate the conductivity of the portion of body region 106 (e.g., the channel region) underlying gate electrode 128 and gate oxide layer 124.

[0031] The thick oxide layer 126 may be formed over the top of the thin oxide layer 122 after the implanted layers 110 are formed using ion implantation processes. An edge of the thick oxide layer 126 may be adjacent to an edge of the gate oxide layer 124, if desired. For example, an interface may be present at an edge of the gate oxide layer 124 and an edge of the thick oxide layer 126.

[0032] As described above, gate electrode 128 is formed over the top of gate oxide layer 124. In some examples, as in Fig. As shown, gate electrode 128 may be a continuous layer formed over both gate oxide layer 124 and a portion of thick oxide layer 126. For example, gate electrode 128 may attach to the interface between gate oxide layer 124 and thick oxide layer 126 such that a continuous gate electrode 128 is deposited on top of gate oxide layer 124 and on top of a portion of thick oxide layer 126. As shown in Fig. As shown, gate electrode 128 may be formed on top of thick oxide layer 126 over the top of the edges of implanted layers 110 that are near body region 106. In some examples, a drain polysilicon extension 130 may be deposited on top of thick oxide layer 126 over the top of the edges of implanted layers 110 that are near drain contact region 112. Drain polysilicon extension 130 and the portion of gate electrode 128 over the top of implanted layers 110 may alter the peak field in the underlying drain region 104.

[0033] The HVFET 100 may include an interlayer dielectric layer 132 formed over the top of the gate oxide layer 124, the gate electrode 128, and the thick oxide layer 126. The interlayer dielectric layer 132 may be an insulating material that serves to prevent electrodes (e.g., 114, 116, 128) from touching each other.

[0034] Some of the structure and operation of HVFET 100 is summarized below. Drain region 104 and source region 108 are separated by body region 106. Drain region 104 includes a drain contact region 112 that can be contacted by drain electrode 114. Body region 106 includes source region 108, which can be contacted by source electrode 116. A portion of body region 106 and a portion of drain region 104 are disposed between source region 108 and drain contact region 112. In other words, drain contact region 112 and source region 108 can be disposed at separate ends of HVFET 100 such that portions of body region 106 and portions of drain region 104, including implanted layers 110, are located between drain contact region 112 and source region 108.During operation, once the HVFET 100 is driven into the on state by a gate voltage, current may flow between the drain contact region 112 and the source region 108 (e.g., between implanted layers 110) in response to the application of a drain to the source voltage.

[0035] The fabrication of the HVFET 100 is described below. A method 200 for fabricating the HVFET 100 is described with respect to Fig. The manufacturing of the HVFET 100 in different phases is described in Fig. The method 200 for manufacturing the HVFET 100 will now be described with reference to Fig. described.

[0036] Fig. is an illustration of a method 200 for fabricating the HVFET 100. As illustrated and described in this document, the HVFET 100 may be fabricated on a p-type semiconductor substrate 102 (e.g., on a p-doped silicon wafer). In one example, a lightly p-doped (5×10 13cm -3 up to 5×10 14 cm -3 ) silicon wafers are used.

[0037] What Fig. As is concerned, substrate 102 may include a surface 118 on which processing operations are performed to fabricate HVFET 100. For example, doping operations, patterning operations, and layering operations used to fabricate HVFET 100 may be performed on surface 118, as described below.

[0038] First, drain region 104 and body region 106 may be formed in substrate 102 in block 202 and block 204, respectively. Drain region 104 may be an n-well formed in a portion of substrate 102. Body region 106 may be a p-well formed in a portion of substrate 102 adjacent to drain region 104.

[0039] Drain region 104 and body region 106 may be doped regions extending from surface 118 into substrate 102. In some examples, drain region 104 may have a depth of approximately 5-10 µm and a length of approximately 20-150 µm. In some examples, body region 106 may have a depth of approximately 1-8 µm.

[0040] If we now refer to Fig. , the thin oxide layer 122 may be formed on the surface 118 in block 206. As illustrated, the thin oxide layer 122 may be formed over both the body region 106 and the drain region 104. A thermal oxidation process may be used to build up the thin oxide layer 122. In some examples, the thin oxide layer 122 may have a thickness of approximately 20-500 nm.

[0041] If we now refer to Fig. , a masking layer 134 may be formed over the top of the thin oxide layer 122 in block 208. The masking layer 134 may define an opening 136 over the top of a portion of the thin oxide layer 122 located above the drain region 104. Subsequent ion implantation operations may be performed through opening 136. The masking layer 134 may, in some examples, be implemented as a photoresist layer. The masking layer 134 may have a sufficient thickness to prevent ions from penetrating portions of the substrate 102 masked by the masking layer 134.

[0042] A plurality of ion implantation processes are then performed through the thin oxide layer 122 in blocks 210-214 to form implanted layers 110. The plurality of ion implantation processes is represented by arrows 138 impinging on the thin oxide layer 122. For example, arrows 138 may represent an ion beam impinging on the thin oxide layer 122. The angle of arrows 138 may optionally represent the angle of the ion beam relative to the thin oxide layer 122. The angle at which the ion beam impinges on the thin oxide layer 122 may be controlled by tilting the substrate 102 relative to the ion beam. While the substrate 102 may be tilted during an ion implantation process such that the ion beam impinges on the thin oxide layer 122 at an angle that is not 90 degrees (i.e., the normal to the thin oxide layer 122), however, in some examples, the substrate 102 may be tilted such that the ion beam impinges on the thin oxide layer 122 at an angle of 90 degrees. The arrows 138 are shown in . Fig. shown as striking the thin oxide layer 122 at an angle approximately five degrees from the vertical.

[0043] A single ion implantation process may be used to implant a single one of the implanted layers 110. Accordingly, three separate ion implantation processes may be performed to implant the three separate implanted layers 110. Each of these ion implantation processes may employ various different parameters (e.g., implantation angle and implantation energy). Example parameters for the three implantation processes are described below.

[0044] To implant the bottommost implanted layer 110-3 in block 210, a first ion implantation process may be performed through the thin oxide layer 122. In some examples, the first ion implantation process may be performed while the substrate 102 is tilted such that the ion beam impinges on the thin oxide layer 122 at an angle that is not 90 degrees, i.e., not perpendicular. For example, the substrate 102 may be tilted such that the ion beam impinges on the thin oxide layer 122 at an angle that deviates from perpendicular by approximately 3-10 degrees. The first ion implantation process may, in some examples, be performed using an ion implantation energy of approximately 2 MeV-5 MeV.Performing ion implantation through the thin oxide layer 122 with the substrate 102 tilted, as described above, may result in the bottommost implanted layer 110-3 having a doping profile approximately corresponding to the Gaussian distribution.

[0045] The bottom implanted layer 110-3 may be implanted into substrate 102 (i.e., drain region 104) approximately 2-5 µm below the surface 118. The thickness of the bottom implanted layer 110-3 may be approximately 0.5-2 µm. The distance between the bottom implanted layer 110-3 and the middle implanted layer 110-2 (i.e., the n-doped region 120-2) may be approximately 0.5-3 µm in some examples.

[0046] To implant the middle implanted layer 110-2 in block 212, a second ion implantation process may be performed through the thin oxide layer 122. In some examples, the second ion implantation process may be performed while the substrate 102 is tilted such that the ion beam impinges on the thin oxide layer 122 at an angle that is not 90 degrees, i.e., not perpendicular. For example, the substrate 102 may be tilted such that the ion beam impinges on the thin oxide layer 122 at an angle that deviates from perpendicular by approximately 3-10 degrees. The second ion implantation process may, in some examples, be performed using an ion implantation energy of approximately 0.5 MeV-3 MeV.Performing ion implantation through the thin oxide layer 122 with the substrate 102 tilted, as described above, may result in the middle implanted layer 110-2 having a doping profile approximately corresponding to the Gaussian distribution.

[0047] The middle implanted layer 110-2 may be implanted into substrate 102 (i.e., drain region 104) approximately 0.5-3 µm below the surface 118. The thickness of the bottom implanted layer 110-2 may be approximately 0.3-1.5 µm. The distance between the middle implanted layer 110-2 and the top implanted layer 110-1 (i.e., the n-doped region 120-1) may be approximately 0.5-3 µm in some examples.

[0048] To implant the topmost implanted layer 110-1 in block 214, a third ion implantation process may be performed through the thin oxide layer 122. In some examples, the third ion implantation process may be performed while the substrate 102 is tilted such that the ion beam impinges on the thin oxide layer 122 at an angle that is not 90 degrees, i.e., not perpendicular. For example, the substrate 102 may be tilted such that the ion beam impinges on the thin oxide layer 122 at an angle that deviates from perpendicular by approximately 3-10 degrees. The third ion implantation process may, in some examples, be performed using an ion implantation energy of approximately 50-500 keV.Performing an ion implantation through the thin oxide layer 122 with the substrate 102 tilted as described above may result in the topmost implanted layer 110-1 having a doping profile approximately corresponding to a Gaussian distribution. The thickness of the topmost implanted layer 110-1 may be approximately 0.1-1 µm. Accordingly, the topmost implanted layer 110-1 may extend from the surface 118 approximately 0.1-1 µm down into the substrate 102 (i.e., into the drain region 104).

[0049] If we now refer to Fig. , the masking layer 134 may be removed from the thin oxide layer 122. Then, in block 216, the thick oxide layer 126 may be formed over the top of the thin oxide layer 122. In some examples, the thick oxide layer 126 may be formed using a low-temperature oxide formation process, such as chemical vapor deposition. Using a low-temperature process may prevent the diffusion of implanted layers 110. In some examples, the thick oxide layer 126 may have a thickness of approximately 0.1-2 µm.

[0050] If we now refer to Fig. , the thick oxide layer 126 and the thin oxide layer 122 may be etched to expose the regions 140-1, 140-2 of surface 118 in block 218. The exposed region 140-1 may be located above the upper side of body region 106. The exposed region 140-2 may be located above the upper side of drain region 104. The fabrication of further features of the HVFET 100 is now with respect to Fig. described.

[0051] Referring again to Fig. , source region 108 and drain contact region 112 may be fabricated in block 224. Source region 108 may be formed using two doping processes. For example, P+ region 108-1 and N+ region 108-2 may be formed by applying a p-type doping process and an n-type doping process, respectively. Drain contact region 112 may be formed using an N+ doping process.

[0052] Gate oxide layer 124 may be formed over body region 106 in block 220. Gate oxide layer 124 may be formed using a thermal oxidation process. In some examples, gate oxide layer 124 may have a thickness of approximately 10-100 nm.

[0053] Gate electrode 128 and drain polysilicon extension 130 may be formed in block 222 using a low-pressure chemical vapor deposition (LPCVD) process. Gate electrode 128 and drain polysilicon extension 130 may, in some examples, include doped polysilicon. Gate electrode 128 may have a thickness of approximately 0.1-1 µm. Drain polysilicon extension 130 may have a thickness of approximately 0.1-1 µm.

[0054] The dielectric interlayer 132 may then be formed in block 226 using a chemical vapor deposition (CVD) process, which is a low-temperature process. The dielectric interlayer 132 may, in some examples, have a thickness of approximately 0.3-2 µm. The drain electrode 114 and the source electrode 116 may be formed in block 228. In some examples, the drain electrode 114 and the source electrode 116 may be metallic electrodes.

[0055] Although some examples are described in detail above, other modifications are possible. For example, the Fig. The flowchart shown does not require the particular arrangement or sequence shown to achieve the desired result. Other steps may be included in the described flowchart, or steps may be omitted. For example, the various regions of substrate 102 (e.g., 104, 106, 108, 110, 112) and various layers (e.g., 114, 116, 122, 124, 126, 128, 130, 132) of the HVFET 100 may be arranged in an arrangement other than that shown with respect to Fig. described. In addition, it is contemplated that regions and / or layers may be added to or removed from substrate 102 to form an HVFET. Other embodiments may be within the scope of the claims.

[0056] Fig.1 is an illustration of an alternative HVFET 800 including implanted layers 810-1, 810-2, 810-3 (collectively, "implanted layers 810"). The alternative HVFET 800 differs from HVFET 100 in that the implanted layers 810 are implanted at depths in drain region 104 that are different from those of the implanted layers 110. For example, the topmost implanted layer 810-1 may be implanted at a distance from surface 118 such that an n-doped region 820-1 is present between the implanted layer 810-1 and surface 118.

[0057] Implanted layers 810 may be p-doped layers (e.g., using boron) within drain region 104. Implanted layers 810 may be implanted into drain region 104 using the ion implantation processes described above for the ion implantation of implanted layers 110. Each of the implanted layers 810 may have nearly planar geometries extending within drain region 104 approximately parallel to surface 118.

[0058] Implanted layers 810 may be formed at different depths within drain region 104 such that the implanted layers 810 are stacked on top of and below each other. Implanted layers 810 may be separated from each other by regions of the n-well that are not p-doped by the ion implantation processes. In other words, implanted layers 810 may be formed in drain region 104 such that implanted layers 810 are separated from drain region 104 by n-doped regions 820-2, 820-3. In HVFET 800, each of the implanted layers 810 is surrounded by n-doped material of drain region 104.

Claims

[1] Method for manufacturing a high-voltage field-effect transistor (100; 800), the method comprising: Forming a body region (106) in a semiconductor substrate (102); Forming a source region (108) in the semiconductor substrate (102); Forming a drain region (104) in the semiconductor substrate (102) separated from the source region (108) by the body region (106), wherein forming the drain region (104) comprises: Forming a first oxide layer (122) on a surface (118) of the semiconductor substrate (102) over the drain region (104) using a thermal oxidation process, the first oxide layer (122) having a thickness of 20 - 500 nanometers, and Performing a plurality of ion implantation processes through the oxide layer (122) while simultaneously tilting the semiconductor substrate (102) such that the ion beams impinge on the oxide layer (122) at an angle that deviates from the vertical, wherein the plurality of ion implantation processes form a corresponding plurality of separate implanted layers (110; 810) within the drain region (104), and wherein each of the implanted layers (110; 810) is formed at a different depth in the drain region (104); and Depositing a second oxide layer (126) on the first oxide layer (122) using a low-temperature oxide deposition process. [2] The method of claim 1, wherein the drain region (104) comprises a doped n-well region. [3] The method of any preceding claim, wherein tilting the semiconductor substrate (102) comprises tilting the semiconductor substrate (102) such that the ion beams impinge on the first oxide layer (122) at an angle that deviates from the perpendicular by three to ten degrees. [4] The method of any preceding claim, wherein the second oxide layer (126) has a thickness of 0.1 - 2 micrometers. [5] The method of claim 4, further comprising: performing an etching process to expose the surface (118) of the semiconductor substrate (102) above the upper side of the body region (106); Forming a gate oxide layer (124) over the upper side of the body region (106), the gate oxide layer (124) abutting the first oxide layer (122) and the second oxide layer (126), and Forming a gate electrode (128) over the upper side of the gate oxide layer (124) and a portion of the second oxide layer (126), wherein a portion of the gate electrode (128) overlying the portion of the second oxide layer (126) is over the upper side of portions of the implanted layers near the body region (106). [6] The method of any preceding claim, wherein each implanted layer of the plurality of separate implanted layers (110; 810) has a thickness of 0.1 - 2 micrometers. [7] The method of any preceding claim, wherein the drain region (104) comprises an n-type well, wherein performing the plurality of ion implantation operations comprises performing three ion implantation operations to form three separate p-type implanted layers (110), wherein a first (110-1) of the p-type implanted layers is formed at the surface (118) of the semiconductor substrate (102) abutting the first oxide layer (122), wherein a second (110-2) of the p-type implanted layers is formed beneath the first (110-1) of the p-type implanted layers, and wherein a third (110-3) of the p-type implanted layers is formed beneath the second (110-2) of the p-type implanted layers. [8] The method of claim 7, wherein the first and second p-type implanted layers (110-1, 110-2) are separated by a first n-type region (120-1) of the n-type well having a thickness of 0.5 - 3 micrometers, and wherein the second and third p-type implanted layers (110-2, 110-3) are separated by a second n-type region (120-2) of the n-type well having a thickness of 0.5 - 3 micrometers. [9] The method of any preceding claim, wherein the drain region (104) comprises an n-type well, wherein performing the plurality of ion implantation operations comprises performing three ion implantation operations to form three separate p-type implanted layers (810) within the n-type well, wherein a first (810-1) of the p-type implanted layers is buried beneath the surface (118) of the substrate (102) such that an n-type region (820-1) of the n-type well is disposed between the first oxide layer (122) and the first p-type implanted layer (810-1), wherein a second (810-2) of the p-type implanted layers is formed beneath the first (810-1) of the p-type implanted layers, and wherein a third (810-3) of the implanted layers of the p-type is formed below the second (810-2) of the implanted p-type layers. [10] The method of claim 9, wherein the first p-type implanted layer (810-1) is separated from the first oxide layer (122) by a first n-type region (820-1) of the n-type well having a thickness of 0.05 - 2 micrometers, the first and second p-type implanted layers (810-1, 810-2) are separated by a second n-type region (820-2) of the n-type well having a thickness of 0.5 - 3 micrometers, and the second and third p-type implanted layers (810-2, 810-3) are separated by a third n-type region (820-3) of the n-type well having a thickness of 0.5 - 3 micrometers. [11] The method of claim 1, wherein performing a plurality of ion implantation operations comprises performing three ion implantation operations through the first oxide layer (122) to form three separate implanted layers (110) within the drain region (104), each of the implanted layers (110) being deposited at a different depth in the drain region (104), and wherein a first (110-1) of the three implanted layers is located at the surface (118) of the semiconductor substrate (102) adjacent the first oxide layer (122). [12] The method of claim 11, wherein the second oxide layer (126) has a thickness of 0.1 - 2 micrometers. [13] The method of claim 12, further comprising: performing an etching process to expose the surface (118) of the semiconductor substrate (102) above the upper side of the body region (106); Forming a gate oxide layer (124) over the upper side of the body region (106), the gate oxide layer (124) abutting the first oxide layer (122) and the second oxide layer (126), and Forming a gate electrode (128) over the top side of the gate oxide layer (124). [14] The method of any one of claims 11-13, wherein each of the three implanted layers (110) has a thickness of 0.1-2 micrometers. [15] The method of any one of claims 11-14, wherein the drain region (104) comprises an n-type well, wherein the three implanted layers (110) are p-type implanted layers, wherein a second (110-2) of the p-type implanted layers is formed beneath the first (110-1) of the p-type implanted layers, and wherein a third (110-3) of the p-type implanted layers is formed beneath the second (110-2) of the p-type implanted layers. [16] The method of claim 15, wherein the first and second p-type implanted layers (110-1, 110-2) are separated by a first n-type region (120-1) of the n-type well having a thickness of 0.5 - 3 micrometers, and wherein the second and third p-type implanted layers (110-2, 110-3) are separated by a second n-type region (120-2) of the n-type well having a thickness of 0.5 - 3 micrometers. [17] High-voltage field-effect transistor (HVFET) (100), comprising: a body region (106) in a semiconductor substrate (102); a source region (108) in the semiconductor substrate (102); a drain region (104) in the semiconductor substrate (102) separated from the source region (108) by the body region (106), wherein the drain region (104) comprises three separate implanted layers (110-1, 110-2, 110-3), each of the implanted layers being located at a different depth in the drain region (104), and wherein a first (110-1) of the three implanted layers is located at the surface (118) of the semiconductor substrate (102); a first oxide layer (122) on the surface (118) of the semiconductor substrate (102) above the drain region (104) abutting the first implanted layer in the drain region (104), the first oxide layer (122) having a thickness of 20 - 500 nanometers; a second oxide layer (126) over the first oxide layer (122), the second oxide layer (126) having a thickness of 0.1 - 2 micrometers; and a gate electrode (128) on the upper side of the second oxide layer (126) above the upper side of the edges of the implanted layers (110). [18] The HVFET (100) of claim 17, further comprising: a gate oxide layer (124) on top of the surface (118) over the top of the body region (106), the gate oxide layer (124) abutting the first oxide layer (122) and the second oxide layer (126), the gate electrode (128) being disposed over the top of the gate oxide layer (124). [19] HVFET (100) of any one of claims 17-18, wherein each of the three implanted layers (110) has a thickness of 0.1 - 2 micrometers. [20] The HVFET (100) of any one of claims 17-19, wherein the drain region (104) comprises an n-type well, wherein the three implanted layers (110) are p-type implanted layers, wherein a second (110-2) of the p-type implanted layers is located below the first (110-1) of the p-type implanted layers, and wherein a third (110-3) of the p-type implanted layers is located below the second of the p-type implanted layers. [21] The HVFET (100) of claim 20, wherein the first and second p-type implanted layers (110-1, 110-2) are separated by a first n-type region (120-1) of the n-type well having a thickness of 0.5 - 3 micrometers, and wherein the second and third p-type implanted layers (110-2, 110-3) are separated by a second n-type region (120-2) of the n-type well having a thickness of 0.5 - 3 micrometers.

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