Power semiconductor device

Abstract

Power semiconductor device (800B to 800E, 900G to 900J) comprising an active region (AR1), a transition region (AR2) provided around a periphery of the active region, and an edge termination region (AR3) provided around a periphery of the transition region, wherein the power semiconductor device comprises: a semiconductor substrate (SB) having a first surface (S1) and a second surface (S2) opposite the first surface, wherein the first surface and the second surface are each arranged over the active region, the transition region and the edge termination region, wherein the semiconductor substrate has: a drift area (1) provided above the active area, the transition area and the edge termination area and having a first conductivity type, a trough area (9a) provided on the first surface, is at least partially contained in the transition area, has an end part on the first surface between the transition area and the edge termination area and has a second conductivity type that differs from the first conductivity type, an extension area (9j) that extends outwards from the trough area on the first surface, is flatter than the trough area and has the second conductivity type, and a plurality of field-limiting rings (9g) provided on the first surface outside the expansion area in the edge termination area and having the second conductivity type, wherein the drift area is arranged on the inside of each of the field-limiting rings on the first surface, each of the field-limiting rings together with the drift area arranged on the inside forming at least one unit structure (U1 to U6), wherein the field-limiting ring located closer to the outside has a smaller proportion of a width to a width of the unit structure on the first surface, wherein the unit structure closer to the outside has a lower average dosage; a first electrode (13a) which is provided in the active region and contacts the first surface of the semiconductor substrate; and a second electrode (4) which touches the second surface of the semiconductor substrate, wherein each of the unit structures on the first surface of the semiconductor substrate has a fixed width (W cellpitch ) and the field restriction ring (9g) located closer to the outside has a shallower depth.

Description

Technical field

[0001] The present invention relates to a power semiconductor device. State of the art

[0002] According to published Japanese patent application No. 2012-231011 (Patent Document 1), an extraction region is arranged between a transistor region and a termination region surrounding the transistor region in an insulated-gate bipolar transistor (IGBT). A p-type layer is deposited on an n -A p-type drift layer is provided in the extraction region. The p-type layer is connected to an emitter electrode. A dummy gate electrode is provided on the p-type layer with an insulating layer between it and the emitter electrode. The dummy gate electrode is connected to a gate electrode. A current density increases slightly at a boundary between the extraction region and the termination region, specifically at the outer end of the p-type layer, during the IGBT turn-off process. As a consequence, a thermal defect can occur. This phenomenon limits the current interruptibility during the turn-off process.

[0003] As described in the aforementioned patent document 1, a lattice defect is introduced in the termination region. This enables charge carrier annihilation in the termination region, reducing the charge carrier concentration in the extraction region during the IGBT turn-off process. Consequently, depletion from the p-type layer towards the collector is accelerated, and the electric field strength decreases. As a result, the current interruptibility during the IGBT turn-off process is improved. Conversely, no lattice defect is introduced in the extraction region. This is intended to prevent an increase in the on-state voltage (ELN). As described above, the technology in the aforementioned patent document 1 aims to improve the interruptibility during the turn-off process without adversely affecting the on-state voltage of the IGBT.

[0004] US 2006 / 0113613A1 describes a semiconductor device comprising: a first base region of a first conductivity type; a second base region of a second conductivity type selectively formed on a major surface of the first base region; a stopper region of a first conductivity type formed on the major surface of the first base region, wherein the stopper region is at a predetermined distance from the second base region and surrounds the second base region; and an annular region of a second conductivity type formed on the major surface of the first base region between the second base region and the stopper region, wherein the annular region spirals around the second base region and is electrically connected to the second base.

[0005] DE 11 2012 005 981 T5 describes a semiconductor device comprising a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed in the active region, and a first to fourth P-layer formed in a region extending from an edge section of the active region to the edge termination region on the surface of the semiconductor substrate.

[0006] DE 10 2012 219 644 A1 describes a semiconductor device comprising a semiconductor substrate with a main surface and an insulating layer formed on the main surface, which continuously covers an upper surface of a first boundary region and an upper surface of a second boundary region, wherein the first boundary region comprises a boundary between a trough layer and a RESURF layer, and wherein the second boundary region comprises a boundary between the RESURF layer and a first defect region. Furthermore, the semiconductor device comprises several lower field plates formed in the insulating layer such that the several lower field plates are not directly above the first and second boundary regions, and several upper field plates formed in the insulating layer such that the several upper field plates are not directly above the first and second boundary regions.

[0007] US 8,330,233 B2 describes a semiconductor device comprising a cell region formed by a semiconductor element and a peripheral region formed at the periphery of the cell region. The semiconductor region consists of an n-drift region formed within the cell region and a peripheral region, multiple p-type columnar regions formed within the n-drift region of the cell region, a plurality of p-type columnar resistance enhancement regions formed within the n-type drift region of the peripheral region, and a plurality of electric field buffer regions formed in an upper portion of the p-type columnar region. State of the art document Patent document

[0008] Patent Document 1: Published Japanese patent application JP 2012-231 011 A Summary of the invention Problems to be solved by the invention

[0009] Both low on-state voltage and high interruptibility can be achieved to some extent using the aforementioned technology. However, achieving a balanced ratio between the two in an IGBT requires further improvements and necessitates additional technologies. Other power semiconductor devices face similar challenges; for example, diodes require improvements in the balance between low on-state voltage and high interruptibility during recovery operation. Additionally, reducing the manufacturing costs of the semiconductor device is urgently needed while ensuring the aforementioned basic performance. If the chip size of the semiconductor device can be reduced without sacrificing performance, the number of chips fabricated from a single wafer increases, thus enabling a reduction in manufacturing costs.

[0010] The present invention was developed in view of the aforementioned problems, and one object of the invention is to provide a power semiconductor device that has both a small size and a high interruptibility capability. Measures to solve the problems

[0011] This problem is solved by the features of the independent claim. The dependent claims contain advantageous embodiments of the invention. Effects of the invention

[0012] In the power semiconductor device according to one aspect of the present invention, the unit structure formed by the field-limiting ring provided in the edge termination region, which is located closer to the outer surface, exhibits a lower average dosage. This arrangement can keep the electric field strength sufficiently low in a smaller edge termination region. Thus, the chip size of the power semiconductor device can be reduced without sacrificing the area of ​​the active region. Furthermore, the local temperature rise at the boundary between the interface region and the edge termination region can be reduced. In other words, both the small chip size and the high static and dynamic interruptibility can be maintained.

[0013] These and other tasks, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when considered in conjunction with the accompanying drawings. Brief description of the drawings Fig. Figure 1 is a top view schematically showing a structure B of an IGBT as a power semiconductor device in a first embodiment of the present invention. Fig. Figure 2 is a schematic partial cross-sectional view, taken along a line II-II in Fig. 1 (IGBT 900B, Structure B). FIG: 3 is a top view schematically showing an arrangement of a second surface of a semiconductor substrate in Fig. 2 shows. Fig. Figure 4 is a partial cross-sectional view showing a structure A of an IGBT in a comparative example, when viewed similarly to Fig. 2 (IGBT 900A, Structure A). Fig. Figure 5 is a partial cross-sectional view schematically showing a structure C of an IGBT as a power semiconductor device in the first embodiment of the present invention, when viewed similarly to Fig. 2 (IGBT 900C, Structure C). Fig. Figure 6 is a partial cross-sectional view schematically showing a structure D of an IGBT as a power semiconductor device in the first embodiment of the present invention, when viewed similarly to Fig. 2 (IGBT 900D, Structure D). Fig. Figure 7 is a diagram of a circuit used to simulate the shutdown process of an IGBT. Fig. Figure 8 is a graphical representation showing shutdown waveforms obtained from the simulation running the circuit in Fig. 7 used. Fig. Figure 9 is a graphical representation showing a temperature distribution of an upper surface S1 of a device in a line DD' in both structure A (dashed line) of the comparative example and structure C (solid line) of the embodiment. Fig. 10 is a graphical representation that shows a relationship between a maximum temperature T max in Fig. 9 and a load resistance range width (L EEBR ) shows. Fig. Figure 11 is a graphical representation that shows each turn-off waveform of a collector-emitter voltage V. CE and a collector current I C in the comparative example (dashed line) with structure A and in the embodiment (solid line) with structure D. Fig. 12A is a distribution chart showing a current potential and hole concentration when t = t ON ( Fig. 11) in structure A as the comparative example. Fig. Figure 12B is a distribution chart showing the current potential and hole concentration when t = t peak ( Fig. 11) in structure A as the comparative example. Fig. 13A is a distribution chart showing the current potential and hole concentration when t = t ON ( Fig. 11) in structure D as the embodiment. Fig. Figure 13B is a distribution chart showing the current potential and hole concentration when t = t peak ( Fig. 11) in structure D as the embodiment. Fig. Figure 14A is a distribution chart showing a charge carrier concentration in the device when t = t ON ( Fig. 11) in structure A as the comparative example. Fig. Figure 14B is a distribution chart showing the charge carrier concentration in the device when t = t ON ( Fig. 11) in structure D as the embodiment. Fig. Figure 15A is a distribution chart showing the charge carrier concentration in the device when t = t peak ( Fig. 11) in structure A as the comparative example. Fig. Figure 15B is a distribution chart showing the charge carrier concentration in the device when t = t peak ( Fig. 11) in structure D as the embodiment. Fig. Figure 16A is a distribution chart showing the charge carrier concentration in the device when t = t tail ( Fig. 11) in structure A as the comparative example. Fig. Figure 16B is a distribution chart showing the charge carrier concentration in the device when t = t tail ( Fig. 11) in structure D as the embodiment. Fig. 17A is a distribution chart showing an electric field strength in the device when t = t ON ( Fig. 11) in structure A as the comparative example. Fig. Figure 17B is a distribution chart showing the electric field strength in the device when t = t ON ( Fig. 11) in structure D as the embodiment. Fig. 18A is a distribution chart showing the electric field strength in the device when t = t peak ( Fig. 11) in structure A as the comparative example. Fig. Figure 18B is a distribution chart showing the electric field strength in the device when t = t peak ( Fig. 11) in structure D as the embodiment. Fig. 19A is a distribution chart showing the electric field strength in the device when t = ttail ( Fig. 11) in structure A as the comparative example. Fig. Figure 19B is a distribution chart showing the electric field strength in the device when t = t tail ( Fig. 11) in structure D as the embodiment. Fig. Figure 20 is a graphical representation showing an example of the relationships between a proportion λ of a p-collector layer in structure D and various electrical properties, which give a saturation current density J. C (sat), a one-state voltage V CE (sat), a maximum shutdown interruption current density J C (break) and a maximum interruption energy E SC are, when a short circuit occurs. Fig. Figure 21 is a graphical representation showing the relationship between a dosage in the collector and the maximum interruption current density J. C(break) in structure A (broken line) as the comparative example and structure D (solid line) as the embodiment shows. Fig. Figure 22 is a graphical representation showing areas of a reverse bias-safe operation (RBSOAs) in structure A (dashed line) as the comparative example and structure D (solid line) as the embodiment. Fig. Figure 23 is a partial cross-sectional view showing a section of an array of planar IGBTs as another comparative example, extending along line II-II ( Fig. 1) (IGBT 900Z) is included. Fig. Figure 24 is a graphical representation that shows balanced properties between the ON-state voltage V CE (sat) and a shutdown loss E OFFin structure D (solid line) as the embodiment, structure A (dashed line) as the comparative example and planar IGBT (dash-dot line) as the other comparative example. Fig. Figure 25 is a partial cross-sectional view that schematically shows a structure E in a modification, when viewed similarly to Fig. 2 (IGBT 900E, Structure E). Fig. Figure 26 is a partial cross-sectional view that schematically shows a structure F in one modification (IGBT 900F, structure F). Fig. Figure 27 is a partial cross-sectional view schematically showing a structure G of an IGBT as a power semiconductor device in a second embodiment of the present invention (IGBT 900G, structure G). Fig. Figure 28 is a partial cross-sectional view showing area XXVIII in Fig. 27 shows in more detail. Fig. Figure 29 is a partial cross-sectional view that schematically shows an arrangement of a pseudo-trough of field restraint rings in Fig. 28 shows. Fig. 30A is a graphical representation that shows the simulation results of each shutdown waveform of the collector-emitter voltage V. CE and a collector current density J C in the comparative example (dashed line) with structure A and in the embodiment (solid line) with structure G. Fig. Figure 30B is a graphical representation showing simulation results of maximum temperatures in the devices in the comparative example (dashed line) with structure A and in the embodiment (solid line) with structure G. Fig. Figure 31A is a distribution chart showing simulation results of temperatures in the devices in the comparative example with structure A and in the embodiment with structure G. Fig. Figure 31B is a distribution chart showing simulation results of impact ionization rates in the devices in the comparative example with structure A and in the embodiment with structure G. Fig. 32A is a graphical representation of the relationships between a position X and an electric field strength Eedge on the upper surface of the substrate, both in a dynamic state (solid line) and a static state (dattered line) of the comparative example with structure A. Fig. 32B is a graphical representation showing the relationships between a position X and the electric field strength Eedge on the upper surface of the substrate, both in a dynamic state (solid line) and a static state (dattered line) of the embodiment with structure G. Fig. 33 is a graphical representation showing the relationships between a position X edge along a line FF' and an electric field strength E in the static state of the comparative example (dashed line) with structure A ( Fig. 4) and the embodiment (solid line) with structure G ( Fig. 27) shows. Fig. 34 is a graphical representation showing the relationships between an interrupt voltage class V class and a necessary width W edge of an edge termination area in the comparative example with structure A and in the embodiment with structure G. Fig. Figure 35 is a partial cross-sectional view that schematically depicts a structure H of a modification of Fig. 28 shows (IGBT 900H, structure H). Fig. 36A is a partial cross-sectional view that schematically depicts a structure I of a modification of Fig. Figure 28 shows (IGBT 900I, Structure I). Fig. 36B is a partial cross-sectional view that schematically depicts a structure I of a modification of Fig. Figure 28 shows (IGBT 900J, structure J). Fig. Figure 37 is a partial cross-sectional view schematically showing an arrangement of a diode as a power semiconductor device in a third embodiment of the present invention (diode 800A). Fig. Figure 38 is a partial cross-sectional view showing an arrangement of a diode in a comparative example (800Z diode). Fig. 39 is a graphical representation showing the waveforms of a voltage V AK and a current density J A during a recovery operation and a maximum temperature T in the device, both in the embodiment (solid line) and in the comparative example (dashed line). Fig. 40A is a graphical representation that shows a relationship between a position X along a line GG' ( Fig. 37 and Fig. 38) and the current density J A at a time t d ( Fig. 39) shows both in the embodiment (solid line) and in the comparative example (dashed line). Fig. 40B is a graphical representation that shows a relationship between position X along line GG' ( Fig. 37 and Fig. 38) and a temperature T of an upper surface S1 of the device, both in the embodiment (solid line) and in the comparative example (dashed line). Fig. 41 is a distribution chart showing the ratios between latitudes L ABR , W p0 in Fig. 37 and a temperature in the device at time t d ( Fig. 39) shows. Fig. 42A is a distribution chart showing the ratios between latitudes L ABR , W p0 in Fig. 37 and a current density in the device at time t d ( Fig. 39) shows. Fig. 42B is an enlarged view of each of the areas of the broken line in Fig. 42A. Fig. 43 is a graphical representation showing the relationships between a proportion γ and an area S abr of a load resistance range to an area S active cell of an active area and a maximum interruption current density J A (break) or a maximum temperature T max within the device during a recreational operation. Fig. Figure 44 is a top view to describe the area S active cell of the active area and area S arb of the load resistance range. Fig. Figure 45A is a partial cross-sectional view schematically showing an arrangement of a diode as a power semiconductor device in a fourth embodiment of the present invention (diode 800B). Fig. 45B is a partial cross-sectional view showing an arrangement of a modification of Fig. 45A is shown (diode 800C). Fig. 45C is a partial cross-sectional view showing an arrangement of a modification of Fig. 45A is shown (diode 800D). Fig. 45D is a partial cross-sectional view showing an arrangement of a modification of Fig. 45A is shown (diode 800E). Fig. 46A is a graphical representation that shows simulation results of waveforms of a voltage V AK and a current density J A during a recreational operation, both in the embodiment (solid line) and in the comparative example (dattered line). Fig. Figure 46B is a graphical representation showing simulation results of a maximum temperature T in the device during recovery operation in both the embodiment (solid line) and the comparative example (dashed line). Fig. 47A is a graphical representation that shows a relationship between a position X in a line HH' ( Fig. 38) of the comparative example and an electric field strength E surface shows when t = t1 ( Fig. 46A and Fig. 46B). Fig. 47B is a graphical representation that shows a relationship between position X in line HH' ( Fig. 38) of the comparative example and the electric field strength E surface shows when t = t2 ( Fig. 46A and Fig. 46B). Fig. 47C is a graphical representation that shows a relationship between position X in line HH' ( Fig. 38) of the comparative example and the electric field strength E surface shows when t = t3 ( Fig. 46A and Fig. 46B). Fig. 47D is a graphical representation that shows a relationship between position X in line HH' ( Fig. 38) of the comparative example and the electric field strength E surface shows when t = t4 ( Fig. 46A and Fig. 46B). Fig. 48A is a graphical representation that shows a relationship between a position X in a line HH' ( Fig. 45) the embodiment and the electric field strength E surface shows when t = t1 ( Fig. 46A and Fig. 46B). Fig. 48B is a graphical representation that shows a relationship between position X in line HH' ( Fig. 45) the embodiment and the electric field strength E surface shows when t = t2 ( Fig. 46A and Fig. 46B). Fig. 48C is a graphical representation that shows a relationship between position X in line HH' ( Fig. 45) the embodiment and the electric field strength E surface shows when t = t3 ( Fig. 46A and Fig. 46B). Fig. 48D is a graphical representation that shows a relationship between position X in line HH' ( Fig. 45) the embodiment and the electric field strength E surface shows when t = t4 ( Fig. 46A and Fig. 46B). Fig. 48E is a graphical representation that shows a relationship between position X in line HH' ( Fig. 45) the embodiment and the electric field strength E surface shows when t = t5 ( Fig. 46A and Fig. 46B). Fig. 48F is a graphical representation that shows a relationship between position X in line HH' ( Fig. 45) the embodiment and the electric field strength E surface shows when t = t6 ( Fig. 46A and Fig. 46B). Fig. 49A is a graphical representation that shows a relationship between position X in line HH' ( Fig. 38) of the comparative example and a current density j surface shows when t = t, ( Fig. 46A and Fig. 46B) is Fig. 49B is a graphical representation that shows a relationship between position X in line HH' ( Fig. 38) of the comparative example and the current density j surface shows when t = t2 ( Fig. 46A and Fig. 46B). Fig. 49C is a graphical representation that shows a relationship between position X in line HH' ( Fig. 38) of the comparative example and the current density j surface shows when t = t3 ( Fig. 46A and Fig. 46B). Fig. 49D is a graphical representation that shows a relationship between position X in line HH' ( Fig. 38) of the comparative example and the current density j surface shows when t = t4 ( Fig. 46A and Fig. 46B). Fig. 50A is a graphical representation that shows a relationship between position X in line HH' ( Fig. 45) the embodiment and the current density j surface shows when t = t1 ( Fig. 46A and Fig. 46B). Fig. 50B is a graphical representation that shows a relationship between position X in line HH' ( Fig. 45) the embodiment and the current density j surface shows when t = t2 ( Fig. 46A and Fig. 46B). Fig. 50C is a graphical representation that shows a relationship between position X in line HH' ( Fig. 45) the embodiment and the current density j surface shows when t = t3 ( Fig. 46A and Fig. 46B). Fig. 50D is a graphical representation that shows a relationship between position X in line HH' ( Fig. 45) the embodiment and the current density j surface shows when t = t4 ( Fig. 46A and Fig. 46B). Fig. 50E is a graphical representation that shows a relationship between position X in line HH' ( Fig. 45) the embodiment and the current density j surface shows when t = t5 ( Fig. 46A and Fig. 46B). Fig. 50F is a graphical representation that shows a relationship between position X in line HH' ( Fig. 45) the embodiment and the current density j surface shows when t = t6 ( Fig. 46A and Fig. 46B). Fig. 51A is a graphical representation that shows a relationship between position X in line HH' ( Fig. 38) of the comparative example and a temperature T surface an upper surface S1 of the device shows when t = t1 ( Fig. 46A and Fig. 46B). Fig. 51B is a graphical representation that shows a relationship between position X in line HH' ( Fig. 38) of the comparative example and the temperature T surface the upper surface S1 of the device shows when t = t2 ( Fig. 46A and Fig. 46B). Fig. 51C is a graphical representation that shows a relationship between position X in line HH' ( Fig. 38) of the comparative example and the temperature T surface the upper surface S1 of the device shows when t = t3 ( Fig. 46A and Fig. 46B). Fig. 51D is a graphical representation that shows a relationship between position X in line HH' ( Fig. 38) of the comparative example and the temperature Tsurface the upper surface S1 of the device shows when t = t4 ( Fig. 46A and Fig. 46B). Fig. 52A is a graphical representation that shows a relationship between position X in line HH' ( Fig. 45) the embodiment and the temperature T surface an upper surface S1 of the device shows when t = t1 ( Fig. 46A and Fig. 46B). Fig. 52B is a graphical representation that shows a relationship between position X in line HH' ( Fig. 45) the embodiment and the temperature T surface the upper surface S1 of the device shows when t = t2 ( Fig. 46A and Fig. 46B). Fig. 52C is a graphical representation that shows a relationship between position X in line HH' ( Fig. 45) the embodiment and the temperature T surface the upper surface S1 of the device shows when t = t3 ( Fig. 46A and Fig. 46B). Fig. 52D is a graphical representation that shows a relationship between position X in line HH' ( Fig. 45) the embodiment and the temperature T surface the upper surface S1 of the device shows when t = t4 ( Fig. 46A and Fig. 46B). Fig. 52E is a graphical representation that shows a relationship between position X in line HH' ( Fig. 45) the embodiment and the temperature T surface the upper surface S1 of the device shows when t = t5 ( Fig. 46A and Fig. 46B). Fig. 52F is a graphical representation that shows a relationship between position X in line HH' ( Fig. 45) the embodiment and the temperature T surface the upper surface S1 of the device shows when t = t6 ( Fig. 46A and Fig. 46B). Fig. Figure 53 is a graphical representation for describing recreation-safe operating areas in the comparative example (marked by triangles) and the embodiment (marked by circles). Description of the embodiments

[0014] Embodiments of the present invention are described below with reference to the drawings. The same or corresponding parts have the same reference numerals in the drawings and their description is not repeated. First embodiment (via the IGBT 900B)

[0015] With reference to Fig. Figure 1 of an IGBT 900B (power semiconductor device) comprises an active region AR1, a transition region AR2 surrounding a periphery of the active region AR1, and an edge termination region AR3 surrounding a periphery of the transition region AR2. The active region AR1 is a part that performs fundamental functions of the power semiconductor device and, in this embodiment, a part that performs fundamental functions of the IGBT. The edge termination region AR3 is a part that improves breakdown voltage characteristics, stability, and reliability in a static state of the power semiconductor device and maintains breakdown strength in a dynamic state. The transition region AR2 is a part that connects the active region AR1 and the edge termination region AR3 and is a particularly important part for maintaining breakdown strength in a dynamic state.

[0016] The active area AR1 of the IGBT 900B has emitter electrodes 13a having an emitter potential, a gate contact point 29 having a gate potential, and a gate wiring part 28 extending from the gate contact point 29.

[0017] With reference to Fig. 2 describes a structure (referred to as structure B) of the IGBT 900B. Fig. Figure 2 shows a cross-sectional structure, recorded along a line II-II in Fig. 1. The IGBT 900B comprises a substrate SB (semiconductor substrate), an emitter electrode 13a (first electrode), a gate junction electrode 13b, electrodes 13c, 13d, a collector electrode 4 (second electrode), a gate electrode 22, a gate wiring layer 22w, capacitor electrodes 23, 32, a trench insulation layer 10, interlayer insulation layers 12a, 12b, and passivation layers 14, 15. In this embodiment, the substrate SB consists of silicon (Si). The substrate SB has an upper surface S1 (first surface) and a lower surface S2 (second surface opposite the first surface). The upper surface S1 and the lower surface S2 are each located above the active region AR1, the transition region AR2, and the edge termination region AR3, respectively. The substrate SB has a - -Drift layer 1 (drift region), an n-buffer layer 2, a p-collector layer 3 (collector region), an n + -Emitter layer 5, a p+ -layer 6, a base layer 8, an n-layer 24 and a p-protective ring 9.

[0018] The n - -Drift layer 1 is located above the active area AR1, the transition area AR2, and the edge termination area AR3. The n - -Drift layer 1 exhibits an n-type (first conductivity type) and has a defect concentration of, for example, approximately 1 × 10 12 up to 1 × 10 15 cm -3 A potential-free zone (FZ) produced on the wafer by an FZ process, or an epitaxial wafer produced by an epitaxial process, can be used for the n - -Drift layer 1 is prepared. In this case, part of the substrate SB can be removed from the n - -Drift layer 1 is formed by ion implantation and a tempering technique.

[0019] The n-layer 24 is located between the n --Drift layer 1 and the p-base layer 8 are provided. The n-layer 24 is of the n-type and has a maximum impurity concentration at a concentration higher than the impurity concentration in the n - -Drift layer 1 and at a concentration lower than the p-base layer 8 and exhibits a maximum impurity concentration of, for example, approximately 1 × 10 15 up to 1 × 10 17 cm -3 A depth position which the n-layer 24 reaches from the upper surface S1 of the substrate SB is deeper than the p-base layer 8 and has a depth of, for example, approximately 0.5 to 1.0 µm deeper than the p-base layer 8.

[0020] In this embodiment, the n-buffer layer 2 has a part that is located between the n - -drift layer 1 and the p-collector layer 3 are arranged in the active region AR1, and have a part that is located between the n -The drift layer 1 and the collector electrode 4 are arranged in the transition region AR2 and the edge termination region AR3. The n-buffer layer 2 is of the n type and has a higher impurity concentration than the impurity concentration in the n - -Drift layer 1 and exhibits a maximum defect concentration of, for example, approximately 1 × 10 15 up to 1 × 10 17 cm -3 For example, a depth position which the n-buffer layer 2 reaches from the lower surface S2 of the substrate SB is approximately 1.5 to 50 µm.

[0021] The n - The drift layer 1, the n-layer 24, and the buffer layer 2, as described above, together form a region exhibiting the n-type properties (first region). Additionally, one or both of the n-layer 24 and the n-buffer layer 2 can be omitted.

[0022] The p-base layer 8 (second region) is provided on the region (first region) that contains the n - -drift layer 1 and the n-layer 24, and in this embodiment is provided directly above the n-layer 24. A depth position which the p-base layer 8 reaches from the upper surface S1 of the substrate SB is deeper than the n + -Emitter layer 5 and less deep than the n layer 24. The p base layer 8 exhibits a p-type (second conductivity type, distinct from the first conductivity type) and has a maximum impurity concentration of, for example, approximately 1 × 10 16 up to 1 × 10 18 cm -3 on.

[0023] The n + Emitter layer 5 (third region) is provided on the p-base layer 8 and arranged on the upper surface S1. The n + Emitter layer 5, for example, has a depth of approximately 0.2 to 1.0 µm. The n +Emitter layer 5 is of the n type and has a maximum defect concentration of, for example, approximately 1 × 10 18 up to 1 × 10 21 cm -3 on.

[0024] The p + Layer 6 is provided on the base layer 8 and is located on the upper surface S1. The p + Layer 6 exhibits a surface defect concentration of, for example, approximately 1 × 10 18 up to 1 × 10 21 cm -3 on. A depth position which the p + -Layer 6, which is reached from the upper surface S1 of the substrate SB, is preferably equal to or deeper than the n + -Emitter layer 5.

[0025] The p-collector layer 3 is only present in the active region AR1 and forms part of the lower surface S2. The p-collector layer 3 is of the p-type and has a surface defect concentration of, for example, approximately 1 × 10⁻⁶. 16 up to 1 × 10 20 cm-3 The p-collector layer 3 has a depth of, for example, approximately 0.3 to 1.0 µm from the lower surface S2 of the substrate SB.

[0026] The p-protective ring 9 is provided on the upper surface S1 and is of the p-type. The p-protective ring 9 has a p-trough area 9a and a p-edge area 9b. The p-trough area 9a is defined by the p + Layer 6, located on the upper surface S1 in the active region AR1, is connected to the emitter electrode 13a. The p-well region 9a is at least partially contained within the transition region AR2 and has an end portion on the upper surface S1 between the transition region AR2 and the edge termination region AR3. The p-well region 9a further increases the interruptibility of the IGBT 900B.

[0027] The p-edge region 9b is contained within the edge termination region AR3 and is located far from the transition region AR2. Additionally, it shows Fig. 2 schematically only one p-edge region 9b, but a plurality of p-edge regions 9b are designed such that they are arranged at a distance from each other according to a stress to be maintained.

[0028] A gate trench TG and a capacitor trench TC are provided on the upper surface S1 of the substrate SB in the active region AR1. One side wall of the gate trench TG lies on each side of the n - -Drift layer 1 and the n-layer 24 (first area), the p-base layer 8 and the n + -Emitter layer 5 opposite. In this embodiment, one side wall of the capacitor trench TC lies opposite each of the n --Drift layer 1, opposite the n layer 24 and the p base layer 8. The capacitor trench TC, located on the outermost side of the active region AR1, reaches the inside of the p-well region 9a of the p-guard ring 9. The trench insulation layer 10 covers the gate trench TG and the capacitor trench TC of the substrate SB.

[0029] The gate electrode 22 has a part that fills the gate trench TG with the trench insulation layer 10 in between and the p-base layer 8 between the n +The emitter layer 5 and the n-layer 24 (first region) are opposite each other, with the trench insulation layer 10 between the p-base layer 8 and the gate electrode 22. The capacitor electrode 23 has a portion that fills the capacitor trench TC with the trench insulation layer 10 between it. Providing the capacitor electrode 23 reduces the saturation current density in the IGBT 900B and prevents gate voltage oscillation when a load is short-circuited on the IGBT 900B. Additionally, the capacitor trench TC and the capacitor electrode 23 can be omitted.

[0030] The interlayer insulation layer 12a is provided on the upper surface S1 of the substrate SB. The emitter electrode 13a, the gate connection electrode 13b, and the electrodes 13c and 13d are provided on the interlayer insulation layer 12a. The emitter electrode 13a is provided in the active region AR1 and contacts the upper surface S1 of the substrate SB. In particular, the emitter electrode 13a contacts both the n + -Emitter layer 5 as well as the p +Layer 6 is connected via a contact hole provided in the interlayer insulation layer 12a. The gate connection electrode 13b contacts the gate wiring layer 22w via a contact hole. Thus, the gate connection electrode 13b is short-circuited with the gate electrode 22 and therefore exhibits a gate potential. The electrode 13c contacts the p-well region 9a via a contact hole. The electrode 13c can be short-circuited with the emitter electrode 13a. The electrode 13d is a floating electrode and contacts the p-edge region 9b via a contact hole in the IGBT 900B.

[0031] The interlayer insulation layer 12b is provided on the upper surface S1 of the substrate SB. The interlayer insulation layer 12b insulates the substrate SB and the gate wiring layer 22w from each other. The interlayer insulation layer 12b may include a portion that is positioned between a portion of the interlayer insulation layer 12a and the substrate SB.

[0032] The collector electrode 4 is located on the lower surface S2 of the substrate SB. The collector electrode 4 contacts the p-collector layer 3 in the active region AR1. The collector electrode 4 can contact the n-buffer layer 2 (more generally the first region described above) in the transition region AR2 and the edge termination region AR3, as shown in Fig. 2 shown.

[0033] A channel stopper structure CS is preferably provided in the edge termination region AR3. In this embodiment, an n-region 34, a p-region 38 and an n+ -Area 35 on the upper surface S1 of substrate SB is formed in the aforementioned order. Furthermore, a channel stopper trench TS penetrates these areas and the n - -Drift layer 1 is reached, provided on the upper surface S1. A channel stopper electrode 32 is provided in the channel stopper trench TS with the trench insulation layer 10 in between. An electrode 13, which is potential-free, can be provided on the channel stopper electrode 32. Another structure can be used instead of the channel stopper structure CS described above, and a structure consisting of the n + -Area 35 is formed, can be used, for example, simply.

[0034] With reference to Fig. 3, if a proportion of an area of ​​the p-collector layer 3 to the lower surface S2 of the substrate SB is specified, λ is preferably greater than or equal to 55% and less than or equal to 70%. In other words, preferably 55 ≤ 100 × (X p × Y p ) / (X n × Y a ) ≤ 70 is satisfied. Here, X represents n and Y n The chip size of the IGBT 900B. If λ < 55%, hole injection from the p-collector layer 3 into the active region AR1 of the IGBT is insufficient, and thus an ON-state voltage (V) increases. CE (sat)). If λ > 70%, the electric field strength of a weak point (arrow WS in Fig. 2) Due to a local temperature increase during an IGBT shutdown process, as described below, the interruptibility is not reduced because charge carrier injection from the p-collector layer 3 occurs in an ON state of the IGBT, resulting in charge carriers in the region indicated by arrow WS, thus reducing the interruptibility. Consequently, a value of λ represents a suitable range for balancing the IGBT's performance. Additionally, the ratio of the sum of the active area AR1 and the transition area AR2 to the lower surface S2 preferably exceeds 70% and is, for example, approximately 75%. (About the IGBT 900A)

[0035] With reference to Fig. In a comparative example, the IGBT 900A differs from the IGBT 900B in that the p-collector layer 3 is located in a different area in addition to the active area AR1. Specifically, the p-collector layer 3 covers the entire lower surface S2 of the substrate SB. Apart from this, the arrangement is almost identical to that of the IGBT 900B described above.

[0036] In the IGBT 900A, it is likely that repeated shutdown processes cause a local temperature increase at the boundary between the active region AR1 and the transition region AR2 on the upper surface S1 of the substrate SB, namely arrow WS ( Fig. 2) cause. This phenomenon can limit the interruptibility of the IGBT 900A. (On operational effects of the IGBT 900B)

[0037] Unlike the IGBT 900A, the one in Fig. In the IGBT 900B shown in Figure 2, the p-collector layer 3 is not located in the edge termination region AR3 and the transition region AR2. This prevents a temperature increase in the arrow WS during the interrupted operation of the IGBT 900B. The active region AR1 has the same arrangement as that in the IGBT 900A and is therefore not adversely affected in such a way as to increase the ON-state voltage. Accordingly, the IGBT 900B exhibits both a low ON-state voltage and a high interruptibility capability. (About the IGBT 900C)

[0038] With reference to Fig. 5 is a contact (see Fig. 4) The connection of electrode 13c to the p-well region 9a in an IGBT 900C is not provided. The p-well region 9a has an electrical path that connects the emitter electrode 13a with an end portion (arrow WS in the diagram) of the p-well region 9a to the p-type region on the upper surface S1. This electrical path crosses the transition region AR2 between the active region AR1 and the edge termination region AR3 and has a resistive region with a width L EEBR exhibits. The entire resistance area is covered with the intermediate insulation layer 12b. The width L EEBR The following detailed description explains how this is designed to prevent a local temperature rise at one end of the resistance area by distributing the temperature rise between both ends during the IGBT's open-circuit operation. A local temperature rise occurs in the portion of arrow WS in the IGBT 900A ( Fig. 4) while the resistance range in the IGBT 900C is designed to distribute a temperature rise to both ends of the resistance range. Such an effect is called a load resistance, and the resistance range is also referred to as a load resistance range.

[0039] The arrangement is almost identical to that of the IGBT 900B described above, except for the arrangement described above.

[0040] During operation of the IGBT 900C, a local temperature increase occurs not only at one point at one end (right end of width L). EEBR in the diagram) of the load resistance range, but also at a point at another end (left end of the width L). EEBR in the diagram), where the position of one end corresponds to the position of the boundary between the transition region AR2 and the edge termination region AR3 (arrow WS in Fig. 5) corresponds. This causes the temperature rise to be distributed, thus reducing the local temperature rise in the arrow WS. Here, the active region AR1 has the same configuration as that in the IGBT 900A, so the ON-state voltage is not adversely affected. Accordingly, the IGBT 900C exhibits both the low ON-state voltage and the high interruptibility. (About the IGBT 900D)

[0041] With reference to Fig. 6. An IGBT 900D exhibits the characteristics of each of the IGBTs 900B and 900C described above. In particular, the p-collector layer 3, similar to the IGBT 900B, is only provided in the active region AR1. Furthermore, the load resistance region, which has a width L EEBRThe IGBT 900D features a design similar to the IGBT 900C. Apart from this, the arrangement is almost identical to that of the IGBT 900B or IGBT 900C described above. The IGBT 900D can exhibit both a low ON-state voltage and a high interrupt capability by operating in the same manner as either the IGBT 900B or 900C described above. (Verification of the effects of the IGBT 900C)

[0042] Fig. Figure 7 is a diagram of a circuit used for simulating the shutdown operation of a 4500V class IGBT. Fig. Figure 8 shows shutdown waveforms resulting from using the circuit in Fig. 7. Ratios between a time t and a collector-emitter voltage V will be obtained. CE . Fig. Figure 9 shows a temperature distribution in the X-coordinate along a line DD' ( Fig. 4 and Fig. 5), immediately before a collector current density J Cabruptly drops (at the point that is in Fig. 8 is indicated by an arrow), both in the IGBT 900A (dashed line) as the comparative example and in the IGBT 900C (solid line) as the embodiment in which L EEBR = 200 µm. Fig. 10 shows a ratio between a maximum temperature T max within the device and L EEBR .

[0043] As can be seen from the simulation results, the maximum temperature T max within the device, the voltage can be reduced by distributing it across the load resistance area, and if L EEBR In particular, if it is specified that it is greater than or equal to 100 µm, then T maxThe load resistance range must be set to be less than or equal to 800K. As described above, it is clear that providing a load resistance range can prevent operational failure due to heat generation; that is, providing a load resistance range can increase the interruptibility of the IGBT. (Verification of the effects of the IGBT 900B and the IGBT 900D)

[0044] Fig. Figure 11 shows an example of each shutdown waveform in the IGBT 900A (dappled line) as the comparative example and in the IGBT 900D (solid line) as the embodiment. Fig. 12A shows a current potential and hole concentration in an ON state of the comparative example (t ON in Fig. 11) from the view of Fig. 4. Fig. Figure 12B shows the current potential and hole concentration at a maximum value of a collector-emitter voltage V. CE during the shutdown of the comparative example (tpeak the broken line in Fig. 11) from the view of Fig. 4. Fig. Figure 13A shows the current potential and hole concentration in an ON state of the embodiment (t ON in Fig. 11) from the view of Fig. 6. Fig. Figure 13B shows the current potential and hole concentration at a maximum value of the collector-emitter voltage V. CE during the shutdown of the embodiment (t peak the continuous line in Fig. 11) from the view of Fig. 4. Fig. 14A and Fig. Figures 14B each show a charge carrier concentration within the device when t = t ON ( Fig. 11) in the comparative example and embodiment. Fig. 15A and Fig. Figures 15B show the charge carrier concentration within the device when t = t peak ( Fig. 11) in the comparative example and embodiment. Fig. 16A and Fig. Figure 16B shows the charge carrier concentration within the device when t = t tail ( Fig. 11) in the comparative example and embodiment. Fig. 17A and Fig. Figures 17B each show an electric field strength inside the device when t = t ON ( Fig. 11) in the comparative example and embodiment. Fig. 18A and Fig. Figures 18B show the electric field strength inside the device when t = t peak ( Fig. 11) in the comparative example and embodiment. Fig. 19A and Fig. Figure 19B shows the electric field strength inside the device when t = t tail ( Fig. 11) in the comparative example and embodiment.

[0045] As from Fig. 12A, Fig. 12B, Fig. 13A, Fig. 13B, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B, Fig. 16A, and Fig. As can be seen in Figure 16B, the charge carrier concentration of the IGBT 900D (structure D) in this embodiment is almost the same as that in the active region AR1 of the IGBT 900A in the comparative example, but the charge carrier concentration in the edge termination region AR3 of the IGBT 900D is lower than that of the IGBT 900A. The reason for this is likely that hole injection from the p-collector layer 3 does not occur in the transition region AR2 and in the edge termination region AR3. It is also conceivable that this operation is similar to that in the IGBT 900B (structure B) which has the same collector structure as the IGBT 900D.

[0046] Further accelerated, as in Fig. 17A, Fig. 17B, Fig. 18A, Fig. 18B, Fig. 19A and Fig. As shown in Figure 19B, the aforementioned operation results in a decrease in the electric field and a depletion in the transition region AR2 and the edge termination region AR3 during shutdown operation. In particular, with reference to Fig. 19A and Fig. 19B the decrease of the electric field at the boundary between the transition region AR2 and the edge termination region AR3 on the upper surface S1 contributes to an improvement in interruptibility.

[0047] With reference to Fig. 20. A ratio λ of the area of ​​the p-collector layer 3 to the lower surface S2 of the substrate SB must be suitable to maintain an appropriate balance between high breaking capability and low on-state voltage. In the diagram, λ = 100% corresponds to the collector structure of the IGBT 900A in the comparative example. As can be seen from the results shown, λ is preferably greater than or equal to 55% and less than or equal to 70%. Setting a value of λ between 55% and 70% can result in both a high maximum turn-off breakover current density J. C (break) as well as no adverse effect of an increasing ON-state voltage V CE (sat) achieve.

[0048] The result that λ = 75% in the graph corresponds to the structure in which the p-collector layer 3 is located in the active region AR1 and the transition region AR2, but not in the edge termination region AR3. Increasing λ to 75% results in a noticeable decrease in the maximum shutdown interruption current density J. C (break) to see. This indicates that not providing the p-collector layer 3 in the transition region AR2 is important to J C (break) to increase.

[0049] Fig. Figure 21 shows an example of the relationship between the dosage of ion implantation required to form the p-collector layer 3 and the maximum shutdown interruption current density J. C (break) in the IGBT 900A (broken line) as the comparative example and the IGBT 900D (solid line) as the embodiment. Fig. Figure 22 shows the relationship between a power supply voltage V CCand a saturation current density J C (sat) or a maximum power density P max as RBSOAs in the comparative example (dashed line) and the embodiment (solid line). An area defined by each line in Fig. Surrounding the 22 is an area called a recovery safe operating area (SOA). The interruptibility during IGBT turn-off is influenced by the efficiency of hole injection from the p-collector layer 3. Dosage in the p-collector layer 3 is a parameter for controlling the balanced characteristics between the ON-state voltage V. CE (sat) and a shutdown loss E OFF in the IGBT. Even if the dosage in the p-collector layer 3 is adjusted, the balanced properties between V CE (sat) and E OFF To control, the embodiment (continuous line) can achieve a higher J C(break) achieve as in the comparative example (dashed line), as from Fig. 21 can be seen, and is the excellent IGBT, which shows a low dependence of the dosage in the p-collector layer 3 on J. C (break) further shows Fig. 22 the excellent effects of the embodiment, which extends the RBSOA and increases the power density for interruption during shutdown.

[0050] Table 1 below provides a summary of the relationships between the structural properties of the IGBTs 900A to 900D (structures A to D) and the maximum turn-off interruption current density J. C (break) with reference to a weighted current density J C (rated). [Table 1] Struktur Struktur derhinteren OberflächedesÜbergangsbereichs Lastwiderstand J C (break) at V CC =3600V A (vergleichendesBeispiel) (IGBT900A) p-Kollektor Nein 1,0 J C (rated) B (IGBT 900B) n-Puffer Nein 4,0 J C (rated) C (IGBT 900C) p-Kollektor Ja 3,0 J C (rated) D (IGBT 900D) n-Puffer Ja ≥ 7,0 J C (rated)

[0051] As shown above, structures B to D (IGBTs 900B to 900D) exhibit the higher J C(break), namely the higher interruptibility capability than that in structure A (IGBT 900A). Structure D (IGBT 900D) exhibits a particularly remarkably high capability.

[0052] Fig. Figure 23 shows an arrangement of an IGBT 900Z as another comparative example. The IGBT 900Z differs from the IGBTs 900A to 900D described above and has a planar gate electrode 11. Fig. Figure 24 shows the balanced properties between the ON-state voltage V CE (sat) and the shutdown loss E OFF in the IGBT 900D (solid line) as the embodiment and the IGBT 900A (dashed line) and the IGBT 900Z (dash-dotted line) as the comparative examples. The results clearly show that the IGBT 900D exhibits the high turn-off interrupt capability, as demonstrated with reference to Fig. 21 and Table 1 described, and also the excellent balanced properties between the ON-state voltage V CE (sat) and the shutdown loss E OFF exhibits. (About the IGBT 900E and the IGBT 900F)

[0053] With reference to Fig. 25 is in an IGBT 900E as a modification of the IGBT 900D ( Fig. 6) The n-buffer layer 2 is provided only in the active region AR1 and not in the transition region AR2 and the edge termination region AR3. The pattern of the n-buffer layer 2 can be the same as the pattern of the p-collector layer 3. Additionally, such a structure can be combined with the IGBT 900B instead of the IGBT 900D.

[0054] With reference to Fig. 26 indicates in an IGBT 900F as a modification of the IGBT 900B ( Fig. 2) The active region AR1 comprises a metal-semiconductor semiconductor (MIS), structural parts (a left part and a right part in the diagram) in which a structural MIS cell is arranged, and a structural part without MIS (central part in the diagram) in which no structural MIS cell is arranged. In the diagram, the central part is part AR1g, in which the gate wiring part 28 and the gate contact point 29 ( Fig. 1) are provided in the active region AR1. The p-collector layer 3 is not provided in the region AR1g, and as a consequence, the buffer layer 2 contacts the collector electrode 4 on the lower surface S2. The MIS structure is typically a metal oxide semiconductor (MOS) structure. Such a structure also exhibits the same effects as those of the IGBT 900D. Second embodiment

[0055] With reference to Fig. 27 describes a structure (referred to as structure G) of an IGBT 900G in this embodiment.

[0056] A substrate SB in structure G has an n - -Drift layer 1, an n-buffer layer 2, a p-collector layer 3, an n + -Emitter layer 5, a p + -layer 6, a p-base layer 8, an n-layer 24, a p-trough region 9a, a p - -Extension area 9j and a plurality of p - -Field restriction rings 9g. The p-trough area 9a is covered with an intermediate insulation layer 12b in a transition area AR2.

[0057] The p - -Extension region 9j extends outwards (to the right side in the diagram) from the p-trough region 9a on an upper surface S1 and is shallower than the p-trough region 9a. The p --Extension area 9j exhibits a p-type and has a maximum defect concentration and a surface defect concentration that are lower than those of the p-tub.

[0058] Furthermore, with reference to Fig. 28 the p - -Field restriction rings 9g of the p-type. The p - -Field restriction rings 9g are on the upper surface S1 outside the p - -Extension area 9j is provided in an edge termination area AR3. The n - -Drift layer 1 is on the inside of each of the p - -Field restriction rings 9g arranged on the upper surface S1, and each of the p - -Field restriction rings 9g together with the n - -Drift layer 1 on the inside corresponding unit structures US1 to US6 (collectively referred to as USs). A width W cellpitch The unit structure of the US is a fixed value. The p --Field restriction ring 9g, which is located closer to the outside (right side in the diagram), has a smaller proportion of a width W p- to the width W cellpitch The unit structure US is located on the upper surface S1. The unit structure US, which is located closer to the outer surface, has a lower average dosage. Here, the average dosage in the unit structure US is a numerical value, where the number of ions required to form the p - The field restriction ring 9g of the special unit structure US is implanted, divided by an area of ​​the unit structure on the upper surface S1. In other words, the average dosage in the unit structure US is a dosage from a macroscopic point of view, which ignores the internal structure of the unit structure US.

[0059] In the Fig. In the structure shown in 28, each of the unit structures USs on the upper surface S1 of the substrate SB has a fixed width W. cellpitch up. The p - -Field restriction ring 9g, which is located closer to the outside (right side in the diagram), has the smaller W p- on the upper surface S1. To obtain the unit structures USs, an ion implantation mask having a plurality of openings at a fixed distance can be used in an ion implantation step of forming the field-constraint rings 9g, where, for example, the opening located closer to the outside has a smaller width. The field-constraint ring 9g with the smaller width ultimately exhibits a smaller depth when exposed to ion implantation after activation annealing, i.e., after diffusion. Fig. 28 looks like the p --Field restriction rings 9g individually, but approximately 1 / 3 to 1 / 2 of the majority of p - -Field restriction rings 9g, which were originally formed as a defect area, are due to activation annealing with the p - -Extension area 9j connected.

[0060] The width W p The value is preferably reduced by a fixed amount for each unit structure US in the direction of the outside. In this case, an average dosage in the unit structure US changes linearly for each unit structure US in the direction of the outside, provided that the width W cellpitch is fixed. From a macroscopic perspective, which ignores the internal structure of the unit structure US, a pseudo-p is supposed to be. - -Tub 9p shall be provided such that the concentration of impurities decreases with a fixed concentration gradient in one direction of the arrow in the diagram, as shown in Fig. 29 shown. In this arrangement on the upper surface S1, the p - -Extension area 9j ( Fig. 27) the almost constant concentration of defects, while the pseudo-p - -Tub 9p, which is outside the p - -Extension area 9j is arranged, which has a linearly decreasing impurity concentration towards the outside.

[0061] Except for the arrangement described above, the arrangement is almost the same as the arrangement of the IGBT 900D in the first embodiment described above, so that the same or corresponding components have the same reference numerals and their description is not repeated.

[0062] In this embodiment, the unit structures US are made from the p -Field-limiting rings 9g are formed, which are provided in the edge termination region AR3, and the unit structure US, which is located closer to the outside, has the lower average dosage. This arrangement can sufficiently suppress the electric field strength in the transition region AR2, even if the edge termination region AR3 is smaller than the edge termination region AR3, in which the average dosage is not controlled as described above. Thus, a temperature rise at the boundary between the active region AR1 and the transition region AR2 can be prevented without significantly reducing the area of ​​the active region AR1. In other words, both a low ON-state voltage and a high interruptibility can be maintained. In particular, in a case where each of the unit structures USs has a fixed width W cellpitchexhibits both low ON-state voltage and high interruptibility with higher reliability

[0063] The verification results of the operational effects described above are described below.

[0064] Fig. 30A shows the simulation results of each shutdown waveform of the collector-emitter voltage V. CE and the collector current density J C in the IGBT 900A ( Fig. 4) as the comparative example (dashed line) and in the IGBT 900G ( Fig. 27) as the embodiment (solid line). Fig. Figure 30B is a graphical representation showing simulation results of maximum temperatures within the devices in the comparative example (dashed line) and the embodiment (solid line). “×” in Fig. 30A and Fig. 30B represents the failure of the device. The simulation results of the internal state of the device at the point indicated by an arrow in Fig. Items marked 30A are described in more detail in Fig. 31A and Fig. 31B shown. Fig. Figure 31A shows temperatures within the devices in the comparative example and embodiment. Fig. Figure 31B shows impact ionization rates within the devices in the comparative example and the embodiment. Fig. 31A and Fig. In Figure 31B, the portion of the dashed line marked by an arrow corresponds to the transition region AR2. As can be seen from the simulation results, the local temperature rise in the transition region AR2 is lower in this embodiment than in the comparative example. Therefore, this embodiment likely exhibits a lower temperature rise within the device during the IGBT shutdown operation and a higher interruptibility capability.

[0065] Fig. 32A shows the relationship between a position X and an electric field strength Eedge on the upper surface of the substrate in both a dynamic state (solid line) and a static state (dattered line) of the IGBT 900A ( Fig. 4) as the comparative example. Fig. 32B shows the relationship between position X and electric field strength E edgeon the upper surface of the substrate in both a dynamic state (solid line) and a static state (dattered line) of the IGBT 900G ( Fig. 27) than the embodiment. Here, the condition for the static state is that a collector-emitter voltage V CES = 3600 V is a gate voltage V G The voltage is 0 V and the temperature is T = 423 K. For the dynamic state, the state indicated by the arrow is used. Fig. 30A is displayed. As can be seen from the results, the electric field strength is Eedge The boundary between the transition region AR2 and the edge termination region AR3 is lower than that in the IGBT 900A, not only in the static state but also in the dynamic state. In this way, the electric field strength in the IGBT 900G is kept lower than that in the IGBT 900A, thus preventing impact ionization. Fig. 31B), which effectively prevents the local temperature increase ( Fig. 31A).

[0066] As described above, this embodiment can increase the turn-off interrupt capability. Furthermore, the active area AR1 can have the same arrangement as that in the IGBT 900A ( Fig. 4) in the comparative example, so that the other properties are not particularly adversely affected. Thus, this embodiment can also exhibit similar properties to those of the IGBT 900D described above ( Fig. 6) received.

[0067] Furthermore, this embodiment can reduce the width of the edge termination area AR3. According to simulation estimates, the width can be reduced by approximately 40 to 50%. This is described below.

[0068] Fig. 33 shows the ratios between a position X edgealong a line FF' and an electric field strength E in the IGBT 900A ( Fig. 4) as the comparative example (dashed line) and in the IGBT 900G ( Fig. 27) as the embodiment (solid line) under the conditions that a collector-emitter voltage V CES = 4500 V and a temperature T = 298 K. As can be seen from the results, if the comparative example and the embodiment have the same collector-emitter voltage V, it holds. CES The embodiment retains the electric field strength E lower (see the downward arrow in the diagram) than the comparative example, while the measure for position X edge necessary, keeps low (see the left arrow in the diagram).

[0069] Fig. 34 is a graphical representation showing the relationships between an interrupt voltage class V class and a necessary width W edgeof the edge termination area AR3 in the comparative example (dashed line) and in the embodiment (solid line). The necessary width W edge The edge termination area AR3 can be further reduced by 40 to 50% in this embodiment than in the comparative example, regardless of the interruption voltage class V. class In other words, the device arrangement enables Fig. 27 In this embodiment, chip size reduction effects of reducing X n and Y n , which is the chip size of the in Fig. The semiconductor device shown in Figure 3 can be used without changing the size of the active region AR1 occupied in the semiconductor device. In particular, this embodiment can increase the number of semiconductor devices (the theoretical number of chips) per wafer on which the semiconductor devices are formed and can reduce the cost of the chip.

[0070] The following section describes a modification. With reference to Fig. 35 an IGBT 900H has a potential-free electrode 13e on each of the p - -Field-limiting rings 9g with the intermediate insulation layers 12a, 12b in between. Each of the potential-free electrodes 13e is within the p - -field restriction ring 9g arranged directly below the potential-free electrode 13e in a lateral direction (lateral direction in Fig. 35) with the intermediate insulation layers 12a, 12b arranged between them. With reference to Fig. 36A in an IGBT 900I a gate connection electrode 13b extends (see Fig. 27) to the p - -Extension area 9j with the intermediate insulation layers 12a, 12b, which the p - -Cover extension area 9j, between the gate connection electrode 13b and the p --Extension area 9j. It should be noted that the gate connection electrode 13b is designed to be on the inside of the p - -extension area 9j is arranged, and the potential-free electrodes 13e are designed such that, as described above, they are located within the p - -Field restriction rings 9g are arranged in the lateral direction (sideways direction in the diagram). With reference to Fig. 36B shows an IGBT 900J with the structure of the IGBT 900I ( Fig. 36A), from which the potential-free electrodes 13e are omitted. These structures can achieve the higher failure voltage and higher interruptibility, while a distribution of the electric field strength in the edge termination region AR3, which is provided by the IGBT 900G in Fig. 32B and Fig. 33 is marked, does not vary over time and is stabilized in a range of operating temperatures that guarantee the performance of the IGBT even when electrical stress is applied. Third embodiment

[0071] This embodiment provides descriptions of a diode which has the same arrangement as the load resistance range ( Fig. 5: the part with width L EEBR in the p-well area 9a in the IGBT 900C) which is described in the first embodiment. In addition, part of the descriptions of the same arrangement as in the IGBT 900C is not repeated.

[0072] With reference to Fig. 37 A diode 800A (power semiconductor device) in this embodiment has an active region AR1, a transition region AR2 provided around a periphery of the active region AR1, and an edge termination region AR3 provided around a periphery of the transition region AR2, similar to the one in Fig. Figure 11 shows the IGBT. The active region AR1 is a part that has the basic functions of the diode in this embodiment.

[0073] The 800A diode comprises a substrate SB (semiconductor substrate), an anode electrode 13 (first electrode), a cathode electrode 4D (second electrode), and an interlayer insulation layer 12. The substrate SB has an n - -Drift layer 1 (drift region), an n-buffer layer 2, an anode layer 8D, a p-protection ring 9, a p-layer 26, an n + -Layer 27 and one n +-area 35. The anode electrode 13 is located in the active region AR1 and contacts the anode layer 8D on an upper surface S1 of the substrate SB. The anode layer 8D is on the n - A drift layer 1 is provided. The cathode electrode 4D contacts a semiconductor layer consisting of the p-layer 26 and the n-layer. + -Layer 27 is formed on a lower surface S2 of the substrate. The n + Layer 27 is only present in the active region AR1. The n-buffer layer 2 is located between the semiconductor layer and the n - -Drift layer 1 is provided. The intermediate insulation layer 12 has openings in the active area AR1.

[0074] The anode layer 8D has a depth of, for example, approximately 0.5 to 10 µm. The anode layer 8D is of a p-type structure and has a maximum impurity concentration of, for example, approximately 1 × 10⁻⁶. 16 up to 1 × 10 20 cm -3The p-protection ring 9 has a depth of, for example, approximately 5 to 10 µm. The p-protection ring 9 has a maximum impurity concentration of, for example, approximately 1 × 10 16 up to 1 × 10 20 cm -3 up. The n + -Area 35 has a depth of, for example, approximately 0.2 to 1 µm. The n + Area 35 exhibits an n-type and has a maximum impurity concentration of, for example, approximately 1 × 10 18 up to 1 × 10 21 cm -3 The p-layer 26 has a depth of, for example, approximately 0.3 to 5 µm. The p-layer 26 has a surface defect concentration of, for example, approximately 1 × 10 16 up to 1 × 10 20 cm -3 up. The n + Layer 27 has a depth of, for example, approximately 0.3 to 5 µm. The n + Layer 27 exhibits a surface defect concentration of, for example, approximately 1 × 10 18 up to 1 × 10 20 cm-3 on.

[0075] A p-shaped well region 9a in the diode 800A forms an electrical path that connects the anode electrode 13 with an end portion (right end in the diagram) of the p-shaped well region 9a to the p-type region on the upper surface S1. This electrical path crosses the transition region AR2 between the active region AR1 and the edge termination region AR3 and has a resistive region with a width L ABR The entire resistance area is covered with the intermediate insulation layer 12. The p-trough area 9a has a width W. p0 on. The outer circumferential end of the n + -Layer 27 and the boundary between the transition area AR2 and the edge termination area AR3 are separated by a distance that has a width W GR in between.

[0076] The widths L ABR , W p0 , and W GRare important parameters in the design of the 800A diode. The width L ABR is designed to achieve a load-resistance effect by distributing a temperature rise across both ends of a resistive region during a diode recovery process, thereby preventing a local temperature rise at one end. Specifically, a temperature rise due to a local current concentration at a point in the diode is prevented. Fig. The arrow WS shown in 37 is distributed to prevent a local temperature increase. In this respect, the width L ABR especially greater than or equal to 100 µm.

[0077] The load resistance range described above is achieved in an 800Z diode ( Fig. 38) not provided for in a comparative example. Fig. Figure 38 schematically shows a p-edge region 9b, but there are multiple p-edge regions 9b, similar to Fig. 37. In the 800Z diode, a local temperature rise is likely to occur at the boundary between the active region AR1 and the transition region AR2, namely arrow WS, on the upper surface S1 of the substrate SB during a recovery process. This phenomenon limits the interruptibility of the 800Z diode.

[0078] In contrast, this embodiment prevents a local temperature increase due to a current concentration at the boundary between the transition region AR2 and the edge termination region AR3 by distributing the current in the load resistance region corresponding to the position of the boundary between the transition region AR2 and the edge termination region AR3 during the recovery operation of the diode, as described below with reference to Fig. As described in section 40, the active region AR1 can have the same arrangement as in the conventional diode, so that no adverse effect such as an increase in the ON-state voltage is noticeable. As described above, the 800A diode, like the IGBT 900C, exhibits both the low ON-state voltage and the high breaking capability.

[0079] The verification results of the operational effects described above are described below.

[0080] Fig. 39 shows waveforms of a voltage V AK and a current density J A during a recovery operation and a maximum temperature T within the device both in the diode 800A as the embodiment (solid line) and in the diode 800Z as the comparative example (dappled line). Fig. 40A shows a ratio between a position X along a line GG' ( Fig. 37 and Fig. 38) and the current density J A at a time t d ( Fig. 39) both in the embodiment (solid line) and the comparative example (dashed line), and Fig. Figure 40B shows a relationship between a position X and a temperature T. In the comparative example (dashed line), where the load resistance range is not included, a concentration of the current J occurs. A at the end part of the transition region AR2, which is located around the boundary between the transition region AR2 and the edge termination region AR3, a local increase in temperature T occurs. As a consequence, the diode 800Z, as shown in Fig. Figure 39 shows that it is unable to complete the interrupted operation, resulting in a failure. In contrast, the current density J in the 800A diode is... AThe current is distributed throughout the transition region AR2 without being highly concentrated, and there is no point that heats up to 800 K or more, a temperature at which diode failure is likely to occur. The load resistor region distributes the current, allowing the 800A diode to operate in open-circuit mode without failure. Thus, the diode's breaking capability is improved in this embodiment.

[0081] Fig. 41, Fig. 42A and Fig. 42B shows ratios between the latitudes L ABR , W p0 ( Fig. 37) the diode 800A and a temperature or current density within the device at time t d ( Fig. 39). As can be seen from the results, L ABR < W p0 to be determined in order to prevent a concentration of current density and a local temperature increase in order to improve the interruptibility of the diode.

[0082] Fig. Figure 43 shows the ratios between a proportion γ and an area S abr of the load resistance area to an area S active cell (namely the area of ​​the anode electrode 13) of the active region AR1 ( Fig. 37) and a maximum interruption current density J A (break) or a maximum temperature T max within the device during recreational operation. In the example from Fig. 37 is the area S abr essentially the same as the area of ​​the AR2 transition zone, as in Fig. 44 shown. J A (break) is an experimental result in the actual device and T max is a simulation result. If γ is determined by the simulation such that T max If it is specified that the value is less than or equal to 800 K (within a safety range SZ in the diagram), the actual device with the high J can be used. A(break) will be obtained. In particular, it is clear that the high J A (break) can be obtained if γ is greater than or equal to 2% and less than or equal to 40%.

[0083] With reference to Fig. 37 is the width W GR preferably specified to be larger than the width W p0 To summarize the topic of parameters, the following conditions must be met to increase the interruptibility of the 800A diode. LABR <Wp0 2%≤y≤40% WGR>Wp0 Fourth embodiment

[0084] This embodiment provides descriptions of a diode which has the same arrangement as the unit structure US in the IGBT 900G ( Fig. 28), which is described in the second embodiment. In addition, part of the descriptions of the same arrangement as in the IGBT 900G or the diode 800A described above ( Fig. 37) not repeated.

[0085] With reference to Fig. In embodiment 45A, a diode 800B has an interlayer insulation layer 12a and an interlayer insulation layer 12b on an upper surface S1 of a substrate SB in a transition region AR2 and an edge termination region AR3. The substrate SB has an anode layer 8D (impurity layer) provided on the upper surface S1 and having a p-type. The substrate SB has a p - -Extension area 9j and a plurality of p - -Field restriction rings 9g on the upper surface S1 in the edge termination area AR3. Similar to the third embodiment, a - -Drift layer 1 on the inside of each of the p - -Field restriction rings 9g arranged on the upper surface S1, and each of the p - -Field restriction rings 9g together with the n - -Drift layer 1 on the inside the unit structure US ( Fig. 28). Fig. 45B to 45D each indicate diodes 800C to 800E, which are modifications. The diode 800C ( Fig. 45B) exhibits similarity to the IGBT 900H ( Fig. 35) potential-free electrodes 13e on. In the diode 800D ( Fig. 45C) an anode electrode 13 with the intermediate insulation layers 12a, 12b between them extends to the p - -Extension area 9j, similar to the gate connection electrode 13b in the IGBT 900I ( Fig. 36A). The diode 800E ( Fig. 45D) exhibits the structure of the diode 800D ( Fig. 45C), from which the potential-free electrodes 13e are omitted.

[0086] Fig. 46A shows waveforms of a voltage V AK and a current density J A during a recovery operation in both the diode 800B as the embodiment (solid line) and the diode 800Z as the comparative example (dattered line), and Fig. Figure 46B shows the maximum temperatures T within the devices during recovery operation. In the comparative example, when t = 5.5 µs, an abrupt drop in V occurs. AK and an abrupt temperature rise to T > 800 K occurs. In other words, the diode fails mid-recovery operation. In contrast, in this embodiment, the interruption is completed without failure.

[0087] Fig. Figures 47A to 47D each show a ratio between a position X in a line HH' ( Fig. 38) of the comparative example and an electric surface field strength E surface , if t = t1 to t4 ( Fig. 46A and Fig. 46B). Fig. Figures 48A to 48F each show a ratio between a position X in a line HH' ( Fig. 45A) of the embodiment and the electric surface field strength E surface , if t = t1 to t6 ( Fig. 46A and Fig. 46B). Fig. Figures 49A to 49D each show a ratio between position X in line HH' of the comparative example and a current density j. surface , if t = t1 to t4. Fig. 50A to 50F each show a ratio between position X in line HH' of the embodiment and the current density j surface, if t = t1 to t6. Fig. Figures 51A to 51D each show a relationship between the position X in the line HH' of the comparative example and a temperature T. surface the upper surface S1 of the device, when t = t1 to t4. Fig. Figures 52A to 52F each show a relationship between the position X in line HH' of the embodiment and the temperature T. surface the upper surface S1 of the device, when t = t1 to t6.

[0088] As can be seen from the results, the electric field strength in the transition region AR2 and in the edge termination region AR3, particularly in the transition region AR2, is lower during recovery operation in this embodiment than in the comparative example, and the temperature rise in the transition region AR2 is suppressed. Thus, the 800B diode exhibits a high interruptibility similar to the IGBT 900G. As a result, the effect of extending the SOA can be achieved.

[0089] Fig. Figure 53 is a graphical representation for describing recovery SOAs in the comparative example (indicated by triangles) and the embodiment (indicated by circles). Here, (dj / dt) represents max a maximum value of a time derivative of a current density that is permissible during the interruption, and P maxrepresents a maximum power density. The value of dj / dt is an edge of a current density waveform in a region that is, for example, in Fig. 46A is shown, and the larger value allows the diode to perform recovery at a higher speed (that is, the interrupt capability during the diode's recovery operation is higher). The results clearly show that the recovery SOA is improved, since this embodiment, which has a value of dj / dt approximately three times larger than that in the comparative example, allows for recovery at a higher speed and enables a 50-fold increase in power density interruption compared to the comparative example.

[0090] The power semiconductor device in each embodiment is particularly suitable for the high breakdown voltage class of approximately 3300 to 6500 V, but the breakdown voltage of the power semiconductor device is not particularly limited and can, for example, be greater than or approximately equal to 600 V. Furthermore, the material for the semiconductor substrate is not limited to silicon and can be a wide-bandgap material, such as silicon carbide (SiC) and gallium nitride (GaN). The first and second conductivity types of the semiconductor substrate can each be n-type and p-type, respectively, and vice versa.

[0091] Furthermore, according to the present invention, each embodiment within the scope of the invention can be suitably varied or omitted. Although the invention has been shown and described in detail, the foregoing description is merely an illustration in all aspects, and the present invention is not intended to be limited to it. It is therefore understood that numerous modifications and variations can be developed without departing from the scope of the invention. Reference symbol list

[0092] 1 n - - Drift layer (drift region); 2 n-buffer layer (buffer layer); 3 p-collector layer (collector region); 4 Collector electrode (second electrode); 4D Cathode electrode (second electrode); 5 n + -Emitter layer; 6 p + -layer; 8 p-base layer; 8D anode layer (defect layer); 9 p-protective ring; 9a p-trough area; 9b p-edge area; 9g p --Field restriction ring; 9j p - -Extension area; 10 Trench insulation layer; 11 Gate electrode; 12, 12a, 12b Intermediate insulation layer; 13 Anode electrode (first electrode); 13a Emitter electrode (first electrode); 13b Gate junction electrode; 13c, 13d Electrode; 13e Float electrode; 14, 15 Passivation layer; 22 Gate electrode; 22w Gate wiring layer; 23 Capacitor electrode; 24 n layer; 26 p layer; 27 n + -layer; 28 Gate wiring section; 29 Gate contact point; 32 Channel stopper electrode; 34 n area; 35 n + -area; 38p area; 800A, 800B diode; 900A to 900I IGBT; AR1 active region; AR2 transition region; AR3 edge termination region; CS channel stopper structure; S1 upper surface (first surface); S2 lower surface (second surface); SB substrate (semiconductor substrate); TC capacitor trench; TG gate trench; TS channel stopper trench; US, US1 to US6 unit structure.

Claims

[1] Power semiconductor device (800B to 800E, 900G to 900J) comprising an active region (AR1), a transition region (AR2) provided around a periphery of the active region, and an edge termination region (AR3) provided around a periphery of the transition region, wherein the power semiconductor device comprises: a semiconductor substrate (SB) having a first surface (S1) and a second surface (S2) opposite the first surface, wherein the first surface and the second surface are each arranged over the active region, the transition region and the edge termination region, wherein the semiconductor substrate has: a drift area (1) provided above the active area, the transition area and the edge termination area and having a first conductivity type, a trough area (9a) provided on the first surface, is at least partially contained in the transition area, has an end part on the first surface between the transition area and the edge termination area and has a second conductivity type that differs from the first conductivity type, an extension area (9j) that extends outwards from the trough area on the first surface, is flatter than the trough area and has the second conductivity type, and a plurality of field-limiting rings (9g) provided on the first surface outside the expansion area in the edge termination area and having the second conductivity type, wherein the drift area is arranged on the inside of each of the field-limiting rings on the first surface, each of the field-limiting rings together with the drift area arranged on the inside forming at least one unit structure (U1 to U6), wherein the field-limiting ring located closer to the outside has a smaller proportion of a width to a width of the unit structure on the first surface, wherein the unit structure closer to the outside has a lower average dosage; a first electrode (13a) which is provided in the active region and contacts the first surface of the semiconductor substrate; and a second electrode (4) which touches the second surface of the semiconductor substrate, wherein each of the unit structures on the first surface of the semiconductor substrate has a fixed width (W cellpitch ) and the field restriction ring (9g) located closer to the outside has a shallower depth. [2] Power semiconductor device according to claim 1, wherein the semiconductor substrate has a collector area (3) which is provided only in the active area, forms part of the second surface and has the second conductivity type, wherein the second surface in the edge termination area has only the first conductivity type. [3] Power semiconductor device according to claim 2, wherein the collector area has an area comprising more or equal to 55% and less than or equal to 70% of the second surface of the semiconductor substrate. [4] Power semiconductor device according to claim 1, wherein the first surface of the semiconductor substrate has an electrical pathway formed on it, wherein the electrical pathway connects the first electrode to the end part of the well area with an area of ​​the second conductivity type, the electric railway has a load resistance area formed from the basin area and having a width L, and The width L is set such that it causes a local temperature increase at both ends of the load resistance range during intermittent operation of the power semiconductor device. [5] Power semiconductor device according to claim 4, wherein the width L is greater than or equal to 100 µm. [6] Power semiconductor device according to claim 4, wherein the first surface of the semiconductor substrate in the active region is an area S act exhibits The load resistance region on the first surface of the semiconductor substrate in the transition region is an area S abr exhibits, and the area S abr greater than or equal to 2% and less than or equal to 40% of the area S act is. [7] Power semiconductor device (800C, 900H) according to claim 1, further comprising a potential-free electrode (13e) provided on each of the field limitation rings. [8] Power semiconductor device (900J) according to claim 1, further comprising: an intermediate insulation layer (12a, 12b) covering the extension area; a gate electrode (22); and a gate connection electrode (13b) which is provided on the extension area with the intermediate layer insulation layer in between and is short-circuited with the gate electrode. [9] Power semiconductor device (900I) according to claim 1, further comprising: a potential-free electrode (13e) provided on each of the field limitation rings; an intermediate insulation layer (12a, 12b) covering the extension area; a gate electrode (22); and a gate connection electrode (13b) which is provided on the extension area with the intermediate layer insulation layer in between and is short-circuited with the gate electrode. [10] Power semiconductor device (800E) according to claim 1, wherein the semiconductor substrate has an impurity layer (8D) provided on the first surface and having the second conductivity type, wherein the power semiconductor device further comprises: an intermediate insulation layer (12a, 12b) covering the extension area, a first electrode (13) having a region that contacts the defect layer in the active region and a region that is arranged on the extension region, with the intermediate insulation layer between the extension region and the first electrode, and a second electrode (4) which is provided on the second surface of the semiconductor substrate. [11] Power semiconductor device (800D) according to claim 1, wherein the semiconductor substrate has an impurity layer (8D) provided on the first surface and having the second conductivity type, wherein the power semiconductor device further comprises: a potential-free electrode (13e) provided on each of the field limitation rings, an intermediate insulation layer (12a, 12b) covering the extension area, a first electrode (13) having a region that contacts the defect layer in the active region and a region that is arranged on the extension region, with the intermediate insulation layer between the extension region and the first electrode, and a second electrode (4) which is provided on the second surface of the semiconductor substrate.

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