Method for manufacturing an optoelectronic semiconductor component and optoelectronic semiconductor component

Abstract

A method for manufacturing an optoelectronic semiconductor device, comprising the following steps: A) Providing a structured semiconductor layer sequence (21, 22, 23) comprising: - a one-piece formed first semiconductor layer (21) with a base surface (21c), a principal extent plane, at least one depression (211), in particular a plurality of depressions (211), and a first top surface (21a) facing away from the base surface (21c) in the region of the depressions (211); - an active layer (23); and - a second semiconductor layer (22) on a side of the active layer (23) facing away from the first semiconductor layer (21), wherein: - the active layer (23) and the second semiconductor layer (22) are jointly structured and together with the first semiconductor layer (21) form at least one emission region (3).B) Simultaneous application of a first contact layer (41) on the first cover surface (21a) and a second contact layer (42) on the second cover surface (3a) of the at least one emission region (3) facing away from the first semiconductor layer (21) such that: - the first contact layer (41) and the second contact layer (42) are electrically separated from each other; - the first contact layer (41) and the second contact layer (42) are parallel to each other and to the main extension plane within the manufacturing tolerances; and - no passivation layer is used during the manufacturing process, whereby the first cover surface (21a) is exposed before the application of the first contact layer (41) and is thereby completely covered by the first contact layer (41).

Description

A method for producing an optoelectronic semiconductor component and an optoelectronic semiconductor component are specified.The document WO 2013 / 092304 A1 describes a display device and a method for producing a display device.The publication US 2013 / 0187192 A1 describes an optoelectronic component and a method for producing the same.The publications DE 102012112530 A1 and DE 1020121063664 A1 describe methods for producing optoelectronic semiconductor chips and optoelectronic semiconductor chips.One object to be achieved is to specify a simplified method for producing an optoelectronic semiconductor component. A further object to be achieved is to specify an optoelectronic semiconductor component which can be produced in a simplified manner.A method for producing an optoelectronic semiconductor component is specified. The optoelectronic semiconductor component can be, for example, a radiation-emitting semiconductor component, such as, for example, a light-emitting diode. For example, the optoelectronic semiconductor component can be provided at least as part or component of a display device and / or at least as part or component of a light source. Furthermore, the optoelectronic semiconductor component can be a radiation-detecting semiconductor component, such as a photodiode, for example. In particular, electromagnetic radiation can be emitted and / or detected with the optoelectronic semiconductor component in a spatially resolved manner.According to at least one embodiment of the method, a semiconductor layer sequence is provided. The semiconductor layer sequence comprises a first semiconductor layer, an active layer and a second semiconductor layer. The semiconductor layer sequence is structured. Structures of the semiconductor layer sequence can be elevations, depressions, recesses and / or recesses in this case and in the following. In particular, a structuring can have an extent which is at least 0.5 μm in at least one dimension. A structuring can extend at least partially through the first semiconductor layer, the active layer and / or the second semiconductor layer. For example, regions of the semiconductor layer sequence are removed and form at least one depression, cutout and / or cutout which adjoins an elevation in the semiconductor layer sequence.The first semiconductor layer, the second semiconductor layer, and the active layer are formed of a semiconductor material. The semiconductor material may be based on a nitride compound semiconductor material, for example. The first semiconductor layer can be formed to be n-conducting, while the second semiconductor layer can be formed to be p-conducting. The first semiconductor layer, the active layer and the second semiconductor layer can be produced, for example, by epitaxial growth on a growth substrate.The first semiconductor layer is integrally formed and has a bottom surface. Here and in the following, a layer is formed in one piece if it is formed from one piece and / or is formed continuously. Preferably, at least one surface of the first semiconductor layer is formed in a plan view in a multiply contiguous manner, preferably in a singly contiguous manner. A "top view" here and in the following is a top view of the optoelectronic semiconductor component from the bottom surface of the first semiconductor layer or from a side facing away from the bottom surface.The bottom surface is preferably formed as simply contiguous. Furthermore, the first semiconductor layer has a main extension plane in which it extends in lateral directions. Perpendicular to the main extension plane, in the vertical direction, the first semiconductor layer has a thickness. The thickness of the semiconductor layer is small against the maximum extension of the first semiconductor layer in a lateral direction.The first semiconductor layer further comprises at least one depression. In particular, the semiconductor layer may have a plurality of depressions. When a "plurality" of depressions is mentioned below, the associated disclosure can also relate to embodiments with only a single depression. For example, the at least one depression is a trench and / or a recess in the first semiconductor layer. The at least one depression can form the structuring of the semiconductor layer sequence. The first semiconductor layer has a smaller thickness in the region of the depressions than in the regions outside the depressions. Here and in the following, the "thickness" of a layer denotes its extension along the vertical direction. Each depression has a depth, the depth corresponding to the reduction in the thickness of the first semiconductor layer in the region of the depressions. Furthermore, each depression has a width which is given by the shortest distance between two regions of the first semiconductor layer having a higher thickness. The depressions do not completely penetrate the semiconductor layer, as a result of which it can be formed in one piece. The first semiconductor layer further has a first cover surface facing away from the bottom surface in the region of the depressions. For example, the first cover surface has a higher doping and / or a higher conductivity than regions of the first semiconductor layer which have a smaller distance from the base surface in the vertical direction than the first cover surface.The active layer is attached to a side of the first semiconductor layer facing away from the bottom surface. The second semiconductor layer is arranged on a side of the active layer facing away from the first semiconductor layer.The active layer and the second semiconductor layer are patterned together. The structuring can be effected, for example, using an etching process with an etching mask produced by means of phototechnology.The active layer and the second semiconductor layer together with the first semiconductor layer form at least one emission region. In this case, it is possible for the semiconductor layer sequence to have an emission region formed in one piece. In this case, the semiconductor layer sequence has a single emission surface facing away from the first semiconductor layer, which is formed in a multiply coherent manner. However, it is also possible for the semiconductor layer sequence to have a plurality of emission regions which are laterally separated from one another by the depressions. The width of the depressions then corresponds, for example, to the smallest lateral distance between two emission regions.According to at least one embodiment of the method, a first contact layer and a second contact layer are applied. The two contact layers are applied simultaneously. Application is preferably carried out using the same method. In particular, the same method can be the same method step. The first contact layer is applied to the first cover surface and has a first contact surface facing away from the first cover surface. The second contact layer is applied to a second cover surface of the at least one emission region facing away from the first semiconductor layer and has a second contact surface facing away from the second cover surface.In the case of an emission region formed in one piece, the second cover surface can be the contiguous emission surface of the emission region. The second contact layer can then be formed integrally and the second contact surface can be formed multiply continuously. In the case of a plurality of spatially spaced emission regions, the second cover surface can be a multiplicity of non-contiguous surfaces. The second contact layer can then be formed in multiple pieces, wherein each region of the second contact layer formed in one piece is assigned an emission region one-to-one.The simultaneous application of the first contact layer and the second contact layer takes place in such a way that the first contact layer and the second contact layer are electrically separated from one another. For example, the electrical separation can be effected by a spatial spacing of the first contact layer and the second contact layer. For example, the second contact layer and the first contact layer are arranged vertically spaced apart from one another, wherein this vertical spacing can be caused by the finite depth of the depressions. The first and the second contact layer then run in two different planes which are vertically spaced apart from one another and which each run along the main extension plane. For example, the vertical distance between the first contact surface and one of the second contact surfaces is at most 2 μm, preferably at most 1 μm. Preferably, the thickness of the first contact layer and the second contact layer is smaller than the depth of the depression. The vertical distance between the first contact surface and the active layer is preferably at least 0.5 μm, particularly preferably at least 0.2 μm.The first contact layer and the second contact layer extend parallel to one another and to the main extension plane within the scope of the manufacturing tolerances. Preferably, all side surfaces of the at least one emission region running transversely to the main extension plane are substantially free of the first and the second contact layer. A surface running "transversely" to the main extension plane is in this case and in the following in particular a surface running non-parallel. Preferably, a "transversely" extending surface encloses an angle of at least 70° with the main extension plane.The simultaneous application of the first contact layer and the second contact layer can be effected with a directed deposition method. For example, the directional deposition method is a physical vapor deposition (PVD).The first and the second contact layer are formed, for example, with an electrically conductive material, such as a metal or a transparent conductive oxide. The first and the second contact layer can contain silver, aluminum, rhodium, platinum, gold, zinc oxide, indium tin oxide and / or titanium, for example, or consist of these materials.It is also possible for the first and second contact layers to be unstructured. "Unstructured" can mean in this context that a desired structuring, for example in relation to the emission regions, is effected merely by self-structuring, in particular by using a directed deposition method. In particular, it is possible that a self-structuring does not require a mask, such as an etching mask, a photomask and / or a growth mask.According to at least one embodiment of the method for producing an optoelectronic semiconductor component, the latter has the following steps: A) providing a structured semiconductor layer sequence, comprisinga first semiconductor layer formed in one piece and having a base surface, a main plane of extent, at least one depression, in particular a multiplicity of depressions, and a first top surface, facing away from the base surface, in the region of the depressions,an active layer; anda second semiconductor layer on a side of the active layer facing away from the first semiconductor layer, whereinthe active layer and the second semiconductor layer are structured jointly and form at least one emission region together with the first semiconductor layer,B) simultaneously applying a first contact layer to the first cover surface and a second contact layer to a second cover surface of the at least one emission region facing away from the first semiconductor layer in such a way thatthe first contact layer and the second contact layer are electrically separated from one another,the first contact layer and the second contact layer extend parallel to one another and to the main extension plane within the scope of the manufacturing tolerances, andall side surfaces of the at least one emission region and / or of the active layer running transversely to the main plane of extension are free of the first contact layer and of the second contact layer.The process steps are preferably carried out in the sequence indicated.According to at least one embodiment of the method, the active layer and the second semiconductor layer are collectively structured into a plurality of laterally spaced apart regions. Each region of the active layer and the second semiconductor layer forms an emission region together with the first semiconductor layer. The regions of the active layer or of the second semiconductor layer can be in particular regions formed in one piece. Each emission region is then assigned one-piece region of the active layer and one-piece region of the second semiconductor layer. In other words, the active layer and the second semiconductor layer can each be formed in multiple pieces and comprise regions formed in one piece, which are preferably formed in a simple coherent manner in a plan view.In the present method, the concept is in particular followed of providing an optoelectronic semiconductor component having a high number of emission regions by simultaneously applying the first contact layer and the second contact layer using a directed deposition method. In particular, the lateral extents of the emission regions and / or the width of the depressions separating the emission regions can be formed as small as possible by this method. Due to the use of a directed deposition method in conjunction with the utilization of the spatial and thus electrical separation of the first and the second contact layer by the depressions, a separate photo technique is sometimes not necessary for the application of the first and the second contact layer. This eliminates the need for adjustment complexity required in a phototechnology and, in addition, eliminates the need for masks for the phototechnology. Furthermore, the formation of depressions with a small width and / or of laterally small emission regions is possible, since the respective expansions are not restricted by adjustment tolerances of the phototechnology. For example, depressions having a width of at most 2 μm and / or emission regions having a lateral extent of at most 10 μm, preferably at most 5 μm and particularly preferably at most 2 μm can thus be provided. Furthermore, it is possible to specify with such a method an optoelectronic semiconductor component having an emission region formed in one piece with depressions, the width of which is at most 2 μm.According to at least one embodiment of the method, a passivation layer is applied to all side surfaces of the emission regions before step B) of the method. The passivation layer completely covers the side surfaces of the emission regions. In this case and in the following, the term "emission regions" is also to be understood as meaning an individual emission region formed in one piece. For example, the passivation layer is formed with an electrically insulating material such as SiO 2, SiN, Al 2 O 3, or another metal oxide and / or metal nitride. A passivation layer is described in the publication WO 2014 / 033041 A1, the disclosure content of which is hereby expressly incorporated by reference.The passivation layer can be applied, for example, as follows. First, the passivation layer is applied to all the exposed outer surfaces facing away from the base surface. Subsequently, the passivation layer is partially removed using a directed etching method, for example a dry etching method with a plasma, which may contain chlorine, fluorine and / or argon. In this case, regions in which the first and the second contact layer are applied later are exposed. In other words, the first cover surface and the second cover surface are exposed at least in places. The partial removal is effected in such a way that only regions of the passivation layer running transversely to the main direction of extent remain on the exposed outer surfaces. For example, after partial removal, the side surfaces of the emission regions are mainly covered by the passivation layer.According to at least one embodiment of the method, the passivation layer is removed after step B). For example, the passivation layer may be removed by etching. The etching can be carried out, for example, using a buffered oxide etching (BOE), H 3 PO 4 or HF. In this case, the concept is in particular followed of removing material of the first and second contact layer which was deposited on the passivation layer during the application of the first and second contact layer, together with the passivation layer, and thus cancelling a short circuit between the first and second contact layers. The traces of material may have been deposited on the side surfaces by, for example, deposition that is not ideally directed in the vertical direction.In particular, the tracks of the material are material islands whose three-dimensional extent is so small that the material islands are at least partially not interconnected. In particular, no electrically conductive path is formed between the first contact layer and the second contact layer. The tracks can be droplets, grains and / or particles of the material which have, for example, an average extent in each spatial dimension of at most 1 / 5, preferably at most 1 / 10, of the thickness of the second contact layer and / or of the first contact layer.According to at least one embodiment of the method, the as yet unfinished optoelectronic semiconductor component is immersed in an etching bath for a predeterminable period of time after method step B). As a result, traces of the material of the first contact layer and of the second contact layer are removed from the side surfaces of the emission regions or edge surfaces of the passivation layer facing away from the emission regions. Due to the removal of these traces, a short circuit between the first contact layer and the second contact layer may be prevented and / or removed. For example, the immersion in the etching bath takes place for a time span of at most 1 / 5, preferably at most 1 / 10 and particularly preferably at most 1 / 20, of a total etching time. The total etching time is the time which would be necessary for the complete removal of the first and second contact layer. In particular, the total etching time can be the time that would be required when using the same etching chemistry for the removal of a layer having the same material and / or the same thickness as the first and the second contact layer, respectively.According to at least one embodiment of the method, the following method steps are carried out after method step B): C) whole-area application of a first insulation layer on exposed outer surfaces facing away from the first semiconductor layer, D) partial removal of the first insulation layer in the region of the second contact surfaces of the emission regions, E) application of a metallization at the regions of the second contact surfaces at which the first insulation layer has been removed.The exposed outer surfaces can be, for example, the first contact surface of the first contact layer, the second contact surface of the second contact layer, the side surfaces of the emission regions and / or outer surfaces of the passivation layer facing away from the emission regions.The first insulation layer is formed with an electrically insulating material such as SiO 2, SiN, or Al 2 O 3 for example. The whole-area application can be effected in the present case by a conformally covering deposition method. For example, the application is carried out by means of a vapor deposition method or sputtering. "Whole-area application" here and in the following denotes an application in such a way that the exposed outer surfaces are completely covered by the first insulation layer. After the whole-area application of the first insulation layer, the first semiconductor layer and the emission regions can be completely covered by the first insulation layer, which is formed in particular in one piece.The partial removal of the first insulation layer can be effected, for example, using a photo technique. In this case, the second contact layer may be exposed in the regions in which the first insulation layer has been partially removed.After partial removal, metallization is deposited in the exposed areas. For the application of the metallization, the same photo technique as for the partial removal of the first insulation layer can be used. The metallization is preferably in direct electrical contact with the second contact layer and serves for the electrical contacting of the second contact layer. The second contact layer is preferably completely covered by the metallization and / or the first insulation layer and is no longer freely accessible from the outside and can be electrically contacted only via the metallization. In other words, the metallization encapsulates the openings of the first insulation layer produced during partial removal and can seal the second contact layer from the outside. The metallization can project vertically beyond the first insulation layer. In other words, the metallization can be formed thicker than the first insulation layer.The metallization has in particular a high thickness, of at least 0.2 μm, for example. In particular, the metallization can have a thickness which corresponds to at least 5 times the thickness of the first and second contact layers.According to at least one embodiment of the method, method steps following step E) are carried out:F) applying a second insulation layer, which together with the first insulation layer forms a dielectric, in such a way that the dielectric fills the depressions completely and protrudes vertically beyond the metallization,G) removing the dielectric in such a way that metal surfaces of the metallization facing away from the first semiconductor layer end flush with end surfaces of the dielectric facing away from the first semiconductor layer.The second insulation layer is preferably formed here from the same material as the first insulation layer.The dielectric can completely cover the first contact layer on its side facing away from the first semiconductor layer. The dielectric may further completely cover the second contact layer at locations free of metallization. The dielectric preferably serves for the additional electrical insulation of the first contact layer, the second contact layer and / or the metallization from one another and to the outside. In particular, a short circuit between the first contact layer and the second contact layer can be made more difficult by the dielectric.The removal of the dielectric is carried out, for example, using a chemical-mechanical polishing process. For example, regions of the metallization are also removed during the removal. After removal, the metal surfaces of the metallization end flush with the end surfaces of the dielectric. The metal surfaces thus preferably form a planar surface together with the end surfaces. In other words, the metal surfaces protrude and / or do not protrude below the end surfaces.An optoelectronic semiconductor component is furthermore specified. The optoelectronic semiconductor component can preferably be produced using a method described here. All features disclosed for the method are thus also disclosed for the optoelectronic semiconductor component and vice versa.According to at least one embodiment of the optoelectronic semiconductor component, the latter comprises the structured semiconductor layer sequence. The semiconductor layer sequence comprises the first semiconductor layer having the bottom surface, the main extension plane, the at least one depression, in particular the plurality of depressions, and the first top surface, facing away from the bottom surface, in the region of the depressions. The semiconductor layer sequence furthermore has the active layer and the second semiconductor layer on a side of the active layer facing away from the first semiconductor layer.The active layer and the second semiconductor layer are patterned together. Preferably, the active layer and the second semiconductor layer are collectively structured into a plurality of laterally spaced apart regions. Each region of the second semiconductor layer and the active layer forms one of the emission regions together with the first semiconductor layer.According to at least one embodiment of the optoelectronic semiconductor component, the latter comprises the first contact layer which is applied to the first cover surface of the first semiconductor layer and the second contact layer which is applied to the second cover surface of the emission regions facing away from the bottom surface.The first contact layer and the second contact layer are electrically separated from each other. In other words, the first contact layer and the second contact layer are not electrically conductively connected to one another. For example, the thickness of the first contact layer and of the second contact layer is less than the depth of the respectively associated depression. The depth of a depression is, for example, the structured depth of the depression.The first contact layer and the second contact layer run parallel to one another and to the main extension plane within the scope of the manufacturing tolerances. Furthermore, the first contact layer and the second contact layer have the same thickness. The first contact layer and the second contact layer are formed from the same material. The same thickness and the formation from the same material show the simultaneous production of the first contact layer and the second contact layer on the finished component.According to at least one embodiment of the optoelectronic semiconductor component, the latter comprises a structured semiconductor layer sequence having a first semiconductor layer formed in one piece and having a base surface, a main extension plane, at least one depression, in particular a multiplicity of depressions, and a first cover surface, facing away from the base surface, in the region of the depressions. Furthermore, the optoelectronic semiconductor component comprises an active layer and a second semiconductor layer on a side of the active layer facing away from the first semiconductor layer. The active layer and the second semiconductor layer are collectively structured into regions, in particular into a plurality of regions laterally spaced apart from one another, and each region forms an emission region together with the first semiconductor layer. A first contact layer is applied to the first cover surface of the first semiconductor layer. On the second cover surface of the emission regions facing away from the bottom surface, a second contact layer is applied. The first contact layer and the second contact layer are not electrically conductively connected to one another, extend parallel to one another and to the main extension plane within the scope of the production tolerances, have the same thickness and are formed from the same material. Furthermore, all side surfaces of the at least one emission region and / or of the active layer running transversely to the main extension plane are free of the first contact layer and of the second contact layer.According to at least one embodiment of the optoelectronic semiconductor component, all side surfaces of the emission regions running transversely to the main extension plane are completely covered with the passivation layer. The passivation layer is an electrically insulating layer. For example, the passivation layer may directly border the side regions of the emission regions. For example, the passivation layer may directly adjoin the active layer, the first semiconductor layer and / or the second semiconductor layer.According to at least one embodiment of the optoelectronic semiconductor component, the side surfaces of the emission regions or, if the passivation layer is applied to the side surfaces, outer surfaces of the passivation layer facing away from the emission regions have traces of the material of the first contact layer and of the second contact layer. These traces of material may have been applied to the side surfaces of the emission regions or the outer surfaces of the passivation layer during the directed deposition of the first contact layer and the second contact layer. The production process can thus be directly detected on the traces of the material.According to at least one embodiment of the optoelectronic semiconductor component, the first contact layer is formed in one piece and surrounds the emission regions in each case in a frame-like manner. "frame-like" means here and below not that the emission regions have to be surrounded on four side faces arranged rectangular to one another. Rather, the emission regions can also be triangular, polygonal, oval or round in a plan view, for example, and are correspondingly surrounded by the first contact layer. In other words, in a plan view, the first contact layer is formed multiply continuously. In a plan view, the first contact layer would then appear as a grating or as a network, wherein the emission regions are surrounded by individual meshes of the grating or of the network. This coherent formation of the first contact layer enables, in particular, simple electrical contacting of the first semiconductor layer by means of a single first contact layer. For example, the first contact layer can be extended outwards for electrical contacting at the edge of the optoelectronic semiconductor component or can be exposed at least in places at the edge of the optoelectronic semiconductor component.According to at least one embodiment of the optoelectronic semiconductor component, the second contact layer is formed in multiple pieces, wherein a region of the second contact layer formed in one piece is assigned one-to-one to each emission region. Preferably, each region of the second contact layer formed in one piece is formed in a simple coherent manner in a plan view.According to at least one embodiment of the optoelectronic semiconductor component, the second contact layer is formed integrally and the first contact layer is formed in multiple pieces, wherein a region of the first contact layer formed integrally is assigned one-to-one to each depression. The second contact layer encloses the first contact layer in a frame-like manner.According to at least one embodiment of the optoelectronic semiconductor component, the first contact layer and the second contact layer appear as a continuous metal layer in a plan view. In other words, there is always a plane which runs parallel to the main extension plane through a metal layer.According to at least one embodiment of the optoelectronic semiconductor component, the metallization with the metal surfaces facing away from the emission regions is applied on the second contact layer. The metallization is formed in multiple pieces and each emission region is assigned a region of the metallization formed in one piece in one piece. In this case, each one-piece region of the metallization can have a smaller lateral extent than the emission region assigned unambiguously to it. In other words, the metallization is formed smaller than the emission regions in plan view.According to at least one embodiment of the optoelectronic semiconductor component, the dielectric is arranged between the emission regions. The metal surfaces of the metallization terminate flush with the end surfaces of the dielectric facing away from the first semiconductor layer.The first contact layer is completely covered by the dielectric on its side facing away from the first semiconductor layer. The dielectric thus electrically isolates the first contact layer. Furthermore, the dielectric completely covers the second contact layer at locations not covered by the metallization. The second contact layer is thus also electrically insulated by the dielectric.According to at least one embodiment of the optoelectronic semiconductor component, the first cover surface of the first semiconductor layer is covered in places by the dielectric and / or by the passivation layer. For example, during the production method, the passivation layer was first applied to the side surfaces of the emission regions and then removed again. The first cover surface may then have been exposed in the regions in which the passivation layer was previously arranged. The dielectric is then applied at these locations and adjoins the first cover surface.The regions of the second contact layer project laterally in places beyond the respectively assigned emission region. In other words, the second contact layer may laterally have a greater extent than the emission regions. Removal of the previously present passivation layer can likewise be detected at this lateral protrusion. Thus, when applying the first and the second contact layer, the upper outer surface of the passivation layer facing away from the first cover surface is also covered with the material of the second contact layer. When removing the passivation layer, this additional material laterally protrudes beyond the emission regions.According to at least one embodiment of the optoelectronic semiconductor component, the first cover surface of the first semiconductor layer is completely covered by the first contact layer. For example, during the production method, no passivation layer has been used, whereby the first cover surface is exposed before the application of the first contact layer. As a result, the first cover surface can be completely covered with the first contact layer.In the following, the method described here and the optoelectronic semiconductor component described here are explained in more detail on the basis of exemplary embodiments and the associated figures.FIGS. 1A to 1J show an exemplary embodiment of a method described here on the basis of schematic sectional representations.FIGS. 2, 3 show exemplary embodiments of an optoelectronic semiconductor component described here on the basis of schematic sectional representations.FIGS. 4A and 4B show an exemplary embodiment of a method described here on the basis of schematic sectional representations.FIG. 4C shows an exemplary embodiment of an optoelectronic semiconductor component described here on the basis of a schematic sectional illustration.FIGS. 5 and 6 show exemplary embodiments of an optoelectronic semiconductor component described here on the basis of schematic plan views.Identical, similar or identically acting elements are provided with the same reference numerals in the figures. The figures and the proportions of the elements shown in the figures with respect to one another are not to be considered as true to scale. Rather, for improved clarity and / or for improved understanding, individual elements may be represented with an exaggerated size.On the basis of the schematic sectional illustration of FIG. 1A, a first method step of a method described here for producing an optoelectronic semiconductor component is explained in more detail. A semiconductor layer sequence 21, 22, 23 is provided on a growth substrate 1. For example, the material of the semiconductor layer sequence 21, 22, 23 is based on a nitride compound semiconductor material. The semiconductor layer sequence 21, 22, 23 has a first semiconductor layer 21 with a bottom surface 21 cfacing the growth substrate 1. On the side of the first semiconductor layer 21 facing away from the bottom surface, an active layer 23 and a second semiconductor layer 22 are applied.A patterned mask layer 71 is applied to an upper surface 22 aof the second semiconductor layer 22 facing away from the bottom surface 21 c. The patterning of the mask layer 71 may be performed using a photo technique. For example, for this purpose, the mask layer 71 can first be applied over the whole area of the second semiconductor layer 22 and then wet-chemically etched with BOE and / or dry-chemically with a fluorine or argon plasma using a patterned photoresist.For example, the mask layer 71 may be formed with SiN. Alternatively or additionally, the mask layer 71 may be formed with a transparent conductive oxide such as indium tin oxide. In this case, it is possible that the mask layer 71 is not peeled off in the subsequent processing steps and remains on the semiconductor device. The mask layer 71 may then be used as a protection contact.With reference to the schematic sectional illustration of FIG. 1B, a further method step of a method described here is explained in more detail. In this method step, the semiconductor layer sequence 21, 22, 23 is structured. Here, the second semiconductor layer 22 and the active layer 23 are completely removed in the regions not covered by the mask layer 71. Furthermore, the first semiconductor layer 21 is partially removed in these regions. The complete or partial removal is preferably carried out using a dry chemical etching process. Here, for example, a chlorine plasma and / or an argon plasma can be used.After the partial removal, a structured semiconductor layer sequence 21, 22, 23 is present. The structured semiconductor layer sequence 21, 22, 23 has the integrally formed first semiconductor layer 21 which has depressions 211 in the regions which are not covered by the mask layer 71. The first semiconductor layer 21 has a first cover surface 21 afacing away from the bottom surface 21 cin the region of the depressions 211.Furthermore, the structured semiconductor layer sequence 21, 22, 23 comprises the active layer 23 and the second semiconductor layer 22, which are collectively structured into a plurality of regions 221, 231 laterally spaced apart from one another. Each of the regions 221, 231 forms together with the first semiconductor layer 21 an emission region 3. Further, the emission regions 3 are connected to each other only by the first semiconductor layer 21. Each emission region 3 has side surfaces 3 bextending transversely with respect to the main plane of extent of the first semiconductor layer 21. In addition, the emission regions 3 have a second cover surface 3 awhich is embodied in a non-contiguous manner. Prior to removing the mask layer 71, a thin electrically conductive layer formed with a conductive oxide, for example, may optionally be deposited. Such a conductive layer serves to reduce the use stress of the component.In at least one embodiment, the structuring or the partial removal takes place in such a way that mutually facing side surfaces 3 bof adjacent emission regions 3 are spaced apart from one another by at most 5 μm, preferably at most 2 μm. In other words, the depressions 211 have a width of at most 5 μm, preferably at most 2 μm.According to the schematic sectional illustration of FIG. 1C, a further method step of a method described here is explained in more detail. In this method step, a passivation layer 72 is applied to the side surfaces 3 bof the emission regions 3 running transversely to the main extension plane. The passivation layer 72 preferably completely covers the side surfaces 3 bof the emission regions 3 and directly adjoins the regions of the active layer 231 and of the second semiconductor layer 221. The passivation layer 72 can thus serve for encapsulating the active layer 23 and thus for avoiding short circuits. The passivation layer 72 is formed for this purpose with an insulating material, such as SiO 2, SiN, Al 2 O 3 for example. Further, the passivation layer 72 may be adjacent to the first top surface 21 aof the first semiconductor layer 21.According to the schematic sectional illustration of FIG. 1D, a further method step of a method described here is explained in more detail. In the method step shown, the mask layer 71 is removed. However, unlike shown, it is also possible for the mask layer 71 to remain on the regions 221 of the second semiconductor layer 22. In this case, the mask layer 71 may be formed with, for example, a transparent conductive oxide and / or an electrically conductive material. The removal of the mask layer 71 can be effected, for example, with H 3 PO 4 and / or a fluorine plasma. Preferably, the removal of the mask layer 71 is carried out with an etching chemistry that has a high selectivity with respect to the passivation layer 72. In other words, the passivation layer 72 is preferably not removed by the etch chemistry. According to the schematic sectional illustration of FIG. 1E, a further method step of a method described here for producing an optoelectronic semiconductor component is explained in more detail. In the method step shown, the first contact layer 41 and the second contact layer 42 are applied in a simultaneous method step. The first contact layer 41 and the second contact layer 42 are applied, for example, using a directed deposition method, such as, for example, vapor deposition. As a result, only surfaces which run parallel to the main extension direction of the first semiconductor layer 21 are covered with the first contact layer 41 and the second contact layer 42.The first contact layer 41 is arranged on the first cover surface 21 aof the first semiconductor layer 21 after the application. The first contact layer 41 is formed integrally and severally continuously in plan view. The first contact layer 41 encloses the emission regions 3 in a frame-like manner.Furthermore, the second contact layer 42 is arranged after the application on the second cover surface 3 aof the emission regions 3 and preferably completely covers them. The second contact layer 42 is embodied in multiple pieces in the present case, wherein regions 421 of the second contact layer 42 embodied in one piece are each assigned one-to-one to an emission region 3. Unlike the illustration in FIGS. 1A to 1J, alternatively, the first contact layer 41 can also be formed in multiple pieces and the second contact layer 42 can be formed in one piece. In this case, regions of the first contact layer 41 formed in one piece are then each assigned one-to-one to a depression 211.The thickness of the first contact layer 41 and the second contact layer 42 is selected to be smaller than the depth of the recesses 211. The thickness of the two contact layers 41, 42 can be adjusted, for example, by the duration of the vapor deposition. This enables the electrical separation of the first contact layer 41 and the second contact layer 42 by a spatial separation.It is possible that outer surfaces 72 eof the passivation layer 72 are covered with traces of the material 44 of the two contact layers 41, 42 during the application of the first contact layer 41 and the second contact layer 42. However, these traces of material 44 have a significantly lower average thickness than the first contact layer 41 and the second contact layer 42.According to the schematic sectional illustration of FIG. 1F, a further method step of a method described here is explained in more detail. In the method step shown here, the traces of material 44 are removed, for example, by means of a short immersion in a chemical and / or by means of a longer immersion in a strongly diluted chemical. Alternatively, it is also possible that the directed deposition method for the two contact layers 41, 42 does not leave traces of the material 44 behind and thus immersion in an etching bath is not necessary.According to the schematic sectional illustration of FIG. 1G, a further method step of a method described here is explained in more detail. In the method step shown here, an insulation layer 73 is applied over the whole area to exposed outer surfaces facing away from the first semiconductor layer 21. The exposed outer surfaces can in the present case be a first contact surface 41 aof the first contact layer 41 facing away from the first semiconductor layer 21 and second contact surfaces 42 aof the second contact layer 42 facing away from the first semiconductor layer 21. Furthermore, outer surfaces 72 eof the passivation layer 72 facing away from the emission regions 3 can also be covered by the insulation layer 73. Preferably, all exposed outer surfaces are completely covered by the insulation layer 73. The insulation layer 73 can be a dielectric layer which can be formed, for example, with SiO 2, SiN or Al 2 O 3.According to the schematic sectional illustration of FIG. 1H, a further method step of a method described here for producing an optoelectronic semiconductor component is explained in more detail. In the method step shown, the first insulation layer 73 is partially removed in the region of the emission regions 3. Preferably, the second contact surfaces 42 aare exposed at least in places. The exposed regions 81 in which the second contact surface 42 ais exposed preferably have a smaller lateral extent than the emission regions 3.According to the schematic sectional illustration of FIG. 1I, a further method step of a method described here is explained in more detail. At the exposed regions 81, a metallization 43 is applied to the second contact areas 42 a. Metallization 43 preferably fills exposed regions 81 completely. Metallization 43 is embodied in multiple pieces, areas 431 of metallization 43 embodied in one piece being assigned one-to-one to an emission area 3.According to the schematic sectional illustration of FIG. 1J, a further method step of a method described here is explained in more detail. In the method step shown, a second insulation layer 74 is applied, which together with the first insulation layer 73 forms a dielectric 73, 74. Dielectric 73, 74 preferably fills depressions 211 completely. The second insulation layer 74 is preferably applied in such a way that the dielectric 73, 74 completely fills the depressions 211 and the end surfaces 74 aof the dielectric 74 facing away from the bottom surface 21 cterminate flush with the metal surface 43 aof the metallization 43. For this purpose, for example, the second insulation layer 74 is first applied in such a way that it protrudes beyond the metallization 43 in the vertical direction at least in places and covers the metal surface 43 aat least in places. Chemical mechanical polishing (CMP) may partially remove the dielectric 73, 74 to form a flush termination between the end surface 74 aand the metal surface 43 a.The composite of the structured semiconductor layer sequence 21, 22, 23, the passivation layer 72, the first contact layer 41, the second contact layer 42, the dielectric 73, 74 and the metallization 43 then forms a compact optoelectronic semiconductor component.According to the schematic sectional illustration of FIG. 2, an optoelectronic semiconductor component described here is explained in more detail. In comparison with the last method step of FIG. 1J, the growth substrate 1 is detached and an active matrix element 6 is attached to the side of the optoelectronic semiconductor component facing away from the bottom surface 21 c. This active matrix element 6 serves for the electrical contacting of the regions of the second semiconductor layer 221 of the emission regions 3 using the metallizations 43. For example, each emission region 3 is assigned a control unit 61, which can comprise at least one transistor, for example, in the active matrix element 6.Furthermore, the first semiconductor layer 21 is partially removed at its bottom surface 21 c,so that the first contact layer 41 is partially freely accessible at these lateral openings 212. The first contact layer 41 can be electrically contacted at the lateral openings 212.According to the schematic sectional illustration of FIG. 3, a further exemplary embodiment of an optoelectronic semiconductor component described here is explained in more detail. The optoelectronic semiconductor component shown differs from that of FIG. 2 in that no passivation layer 72 is present in the regions of the depressions. This was removed, for example, during the production process. The second contact layer 42 laterally protrudes beyond the emission regions 3. From this lateral protrusion, it can be seen that during the production process a passivation layer 72 has been used, wherein the passivation layer 72 has been removed.According to the schematic sectional illustration of FIG. 4A, an alternative method for producing an optoelectronic semiconductor component described here is explained in more detail. In the method step shown, the first contact layer 41 and the second contact layer 42 have already been applied. In contrast to the method of FIGS. 1A to 1J, no passivation layer 72 is provided. This eliminates the method step of applying the passivation layer 72, as a result of which the width of the depressions 211 can be reduced, since this is not limited by the finite extent of the passivation layer 72.Due to the lack of passivation layer 72, first contact layer 41 directly adjoins side surfaces 3 bof emission regions 3. In the exemplary embodiment shown, the first contact layer 41 completely covers the first cover surface 21 a. The second contact layer 42 has a lateral extent which corresponds to the lateral extent of the emission regions 3. In other words, the second contact layer 42 does not laterally project beyond the emission regions 3 in the present exemplary embodiment.According to the schematic sectional illustration of FIG. 4B, a further method step is explained in more detail. In the method step shown here, the first insulation layer 73 is applied. This directly adjoins the side surfaces 3 bof the emission regions 3 and completely covers the first contact surface 41 a.According to the schematic sectional illustration of FIG. 4C, an optoelectronic semiconductor component described here is explained in more detail. The optoelectronic semiconductor component produced with the method of FIGS. 4A and 4B is shown before the separation of the growth substrate 1. the dielectric 73, 74 and the metallization 43 have been applied as in the method of FIGS. 1A to 1K. The dielectric 73, 74 directly adjoins the side surfaces 3 bof the emission regions 3. The first cover surface 21 aof the first semiconductor layer 21 is completely covered by the first contact layer 41.According to the schematic plan view of FIG. 5, an optoelectronic semiconductor component described here is explained in more detail. Four emission regions 3 are shown, which are laterally spaced apart from one another. The emission regions 3 are separated by the recesses 211 covered with the first contact layer 41. The first contact layer 41 encloses the emission regions 3 in a frame-like manner. A passivation layer 72 is applied to the side surfaces 3 bof the emission regions 3. The emission regions 3 are covered by the second contact layer 42 which is divided into integrally formed regions 421. The second contact layer is covered by the metallization 43 comprising the metal surfaces 43 a.According to the schematic plan view of FIG. 6, an optoelectronic semiconductor component described here is explained in more detail. The optoelectronic semiconductor component of FIG. 6 has a single emission region 3 formed in one piece. The emission region 3 is structured. The structuring is effected by the plurality of depressions 211. The recesses 211 are covered with the first contact layer 41. The first contact layer 41 is formed in multiple pieces and encloses the depressions 211 in a frame-like manner. The side surfaces 3 bof the emission region 3 are each covered by a passivation layer 72. The emission region 3 is covered by the second contact layer 42 and the metallization 43 with the metal surface 43 a.The depressions 211 serve in the present case for simplified electrical contacting of the first semiconductor layer 21 covered by the second semiconductor layer 22. For this purpose, the first contact surface 41 acan be freely accessible and / or electrically contactable at least in places. The depressions 211 can in this case have the function of vias and / or feedthroughs.In the optoelectronic semiconductor component described here or in the method described here, the ideas are in particular followed of providing an easily producible optoelectronic semiconductor component with a small width of the depressions 211 between the emission regions 3 by simultaneously depositing the first contact layer 41 and the second contact layer 42. Deep 211 depressions between the emission regions 3 can in particular bring about an electrical separation of the first contact layer 41 and the second contact layer 42 without additional insulation layers. As a result, the distances between the emission regions 3 can be designed to be particularly small.

Claims

Method for producing an optoelectronic semiconductor component, comprising the following steps: A) providing a structured semiconductor layer sequence (21, 22, 23) comprising - a first semiconductor layer (21) formed in one piece and having a base surface (21c), a main extension plane, at least one depression (211), in particular a plurality of depressions (211), and a first cover surface (21a) facing away from the base surface (21c) in the region of the depressions (211), - an active layer (23) and - a second semiconductor layer (22) on a side of the active layer (23) facing away from the first semiconductor layer (21), wherein - the active layer (23) and the second semiconductor layer (22) are structured jointly and together with the first semiconductor layer (21) form at least one emission region (3), B) Simultaneous application of a first contact layer (41) on the first cover surface (21a) and a second contact layer (42) on the second cover surface (3a) of the at least one emission region (3) facing away from the first semiconductor layer (21) in such a way that - the first contact layer (41) and the second contact layer (42) are electrically separated from one another, - the first contact layer (41) and the second contact layer (42) extend parallel to one another and to the main extension plane within the scope of the production tolerances and - no passivation layer is used during the production method, as a result of which the first cover surface (21a) is exposed before the application of the first contact layer (41) and as a result the first cover surface (21a) is completely covered with the first contact layer (41).Method according to the preceding claim, wherein the first contact layer (41) and the second contact layer (42) are deposited by means of a directed deposition method.Method according to one of the preceding claims, wherein the active layer (23) and the second semiconductor layer (22) are structured into a plurality of regions (221, 231) laterally spaced apart from one another and each region (221, 231) together with the first semiconductor layer (21) forms an emission region (3).Method according to one of the preceding claims, wherein all side surfaces (3b) of the active layer (23) running transversely to the main extension plane are free of the first contact layer (41) and of the second contact layer (42).Method according to one of the preceding claims, wherein all side surfaces (3b) of the at least one emission region (3) running transversely to the main plane of extent are free of the first contact layer (41) and of the second contact layer (42).Method according to one of the preceding claims, wherein the not yet completed optoelectronic semiconductor component is dipped into an acid bath for a predeterminable period of time after step B) in such a way that tracks (44) of the material of the first contact layer (41) and of the second contact layer (42) are removed from the side surfaces (3b) of the emission regions (3).Method according to one of the preceding claims, wherein after step B) the following method steps are carried out: C) whole-area application of a first insulation layer (73) on the exposed outer surfaces facing away from the first semiconductor layer (21), D) partial removal of the first insulation layer (73) in the region of second contact surfaces (42a) of the second contact layer (42) facing away from the emission regions, E) application of a metallization (43) on the regions (81) of the second contact surfaces (42a) on which the first insulation layer (73) has been removed.Method according to the preceding claim, wherein after step E) the following method steps are carried out: F) applying a second insulation layer (74) which together with the first insulation layer (73) forms a dielectric (73, 74) in such a way that the dielectric fills the depressions (211) completely and projects beyond the metallization (43) in the vertical direction; G) removing the dielectric (73, 74) in such a way that metal surfaces (43a) of the metallization (43) facing away from the first semiconductor layer (21) end flush with end surfaces (74a) of the dielectric (73, 74) facing away from the first semiconductor layer (21).Optoelectronic semiconductor component, comprising - a structured semiconductor layer sequence (21, 22, 23) having - a first semiconductor layer (21) formed in one piece and having a base surface (21c), a main extension plane, at least one depression (211), in particular a plurality of depressions (211), and a first cover surface (21a) facing away from the base surface (21c) in the region of the depressions (211), - an active layer (23) and - a second semiconductor layer (22) on a side of the active layer (23) facing away from the first semiconductor layer (21), wherein - the active layer (23) and the second semiconductor layer (22) are structured jointly into regions (221, 231), in particular into a plurality of regions (221, 231) laterally spaced apart from one another, and each region (221, 231) together with the first semiconductor layer (21) forms an emission region (3), - a first contact layer (41), which is applied to the first cover surface (21a), and - a second contact layer (42) which is applied to a second cover surface (3a) of the emission regions (3) which is remote from the base surface (21c), wherein - the first contact layer (41) and the second contact layer (42) are not electrically conductively connected to one another, extend parallel to one another and to the main extension plane within the scope of production tolerances, have the same thickness and are formed from the same material, and - in which the first cover surface (21a) of the first semiconductor layer (21) is completely covered by the first contact layer (41).Optoelectronic semiconductor component according to the preceding claim, in which the side surfaces (3b) of the emission regions (3) or outer surfaces of the passivation layer (72) facing away from the emission regions (3) have tracks (44) of the material of the first contact layer (41) and of the second contact layer (42).Optoelectronic semiconductor component according to one of the preceding claims, in which - the first contact layer (41) is formed in one piece and surrounds the emission regions (3) in each case in the manner of a frame, and - the second contact layer (42) is formed in multiple pieces, wherein each emission region (3) is assigned a region of the second contact layer (421) formed in one piece.Optoelectronic semiconductor component according to one of the preceding claims, in which - the first contact layer (41) is formed in multiple pieces, wherein a region of the first contact layer (41) formed in one piece is assigned to each depression (211), and - the second contact layer (42) is formed in one piece, and encloses the depressions (211) in a frame-like manner, wherein a region of the second contact layer (421) formed in one piece is assigned to each emission region (3).Optoelectronic semiconductor component according to one of the preceding claims, in which the first contact layer (41) and the second contact layer (42) appear as a continuous metal layer in a plan view from a side facing away from the base surface (21c) of the first semiconductor layer (21).Optoelectronic semiconductor component according to one of the preceding claims, in which a metallization (43) with metal surfaces (43a) facing away from the first semiconductor layer (21) is applied on the second contact layer (42), wherein - the metallization (43) is formed in multiple pieces, wherein a region of the metallization (431) formed in one piece is assigned to each emission region (3) in one piece and - each region of the metallization (431) formed in one piece has a smaller lateral extent than the emission region (3) assigned to it in one piece.Optoelectronic semiconductor component according to the preceding claim, in which a dielectric (73, 74) is arranged between the emission regions (3), wherein - the metal surfaces (43a) of the metallization (43) end flush with end surfaces (74a) of the dielectric (73, 74) facing away from the first semiconductor layer (21), - the dielectric (73, 74) completely covers the first contact layer (41) on its side facing away from the first semiconductor layer (21), and - the dielectric (73, 74) completely covers the second contact layer (42) at locations which are not covered by the metallization (43).Optoelectronic semiconductor component according to one of the preceding claims, in which - the first cover surface (21a) of the first semiconductor layer (21) laterally protrudes in places from the dielectric (73, 74), and - the regions of the second contact layer (421) laterally protrude in places from the respectively assigned emission region (3).Optoelectronic semiconductor component, comprising - a structured semiconductor layer sequence (21, 22, 23) having - a first semiconductor layer (21) formed in one piece and having a base surface (21c), a main extension plane, at least one depression (211), in particular a plurality of depressions (211), and a first cover surface (21a) facing away from the base surface (21c) in the region of the depressions (211), - an active layer (23) and - a second semiconductor layer (22) on a side of the active layer (23) facing away from the first semiconductor layer (21), wherein - the active layer (23) and the second semiconductor layer (22) are structured jointly into regions (221, 231), in particular into a plurality of regions (221, 231) laterally spaced apart from one another, and each region (221, 231) together with the first semiconductor layer (21) forms an emission region (3), - a first contact layer (41), which is applied to the first cover surface (21a), and - a second contact layer (42) which is applied to a second cover surface (3a) of the emission regions (3) which is remote from the base surface (21c), wherein - the first contact layer (41) and the second contact layer (42) are not electrically conductively connected to one another, extend parallel to one another and to the main extension plane within the scope of production tolerances, have the same thickness and are formed from the same material, and - all side surfaces (3b) of the active layer (23) which extend transversely to the main extension plane are free of the first contact layer (41) and of the second contact layer (42).Optoelectronic semiconductor component according to the preceding claim, wherein all side surfaces (3b) of the at least one emission region (3) running transversely to the main extension plane are free of the first contact layer (41) and of the second contact layer (42).

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