SEMICONDUCTOR DEVICE

Abstract

Semiconductor device (10) comprising: a plurality of first devices (110) of a first area (102); one or more second devices (120) of a second area (104); and a connecting conductor (130) electrically connecting the first device (110) to the second device (120), the connecting conductor (130) comprising: current paths (132, 134, 136, 138) which are adjacent to one another and have opposite directions in at least a part thereof, and are connected in parallel to each of the plurality of first devices (110), a first current path (132) on one side of the first devices (110) with a direction away from the second device (120) and a second current path (134) connected to the first current path (132) and running parallel to the first current path (132) on the side of the first devices (110), which second current path (134) is bent from the first current path (132) so that it has a direction towards the second device (120), a third current path (136) on one side of the second device (120) with a direction away from the first devices (110), and a fourth current path (138) connected to the third current path (136) and running parallel to the third current path (136) on the side of the second device (120), which fourth current path (138) is bent from the third current path (136) so that it has a direction towards the first devices (110), and wherein: a plurality of connections between the first current path (132) and the plurality of first devices (110) are each made by a plurality of first connecting parts (142); one or more connections between the third current path (136) and the one or more second devices (120) are each made by second connecting parts (144); the connecting conductor (130) has a parallel plate structure formed from the adjacent current paths (132, 134, 136, 138); the first current path (132) and the second current path (134) are each formed as plate-shaped conductor sections arranged parallel to one another; and the third current path (136) and the fourth current path (138) are each formed as plate-shaped conductor sections arranged parallel to one another.

Description

BACKGROUND OF THE INVENTION 1. TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device. 2. STATE OF THE ART

[0002] Conventionally, a power semiconductor module, which is a semiconductor device operating at high power, includes, for example, a wiring electrode that causes current to flow in one direction and another wiring electrode that causes current to flow in a direction opposite to the one direction, and these electrodes are brought into close contact with each other in parallel so that the inductances and induced magnetic fields generated by these wiring electrodes cancel each other, as recited in Patent Documents 1 and 2, for example.

[0003] Patent Document 3 discloses a semiconductor module comprising a base substrate with semiconductor elements, an emitter terminal unit capable of electrically connecting an emitter of the semiconductor circuit to an external circuit unit, and a collector terminal unit capable of electrically connecting a collector of the semiconductor circuit to the external circuit unit. The emitter terminal unit and the collector terminal unit each have resilient elements arranged parallel to the substrate. Patent Document 1: JP H09-172 139 A Patent document 2: JP 2002- 353 407 A Patent document 3: WO 2009 / 074 454 A2

[0004] However, there are cases where, due to the circuitry contained in the power semiconductor module, there are no current paths that can be arranged to cancel the inductances and induced magnetic fields. For example, in a case where there is only one current path that simply supplies current from one device to another, the inductances and induced magnetic fields will affect the internal or external devices because there is no current path that causes an approximately equivalent current to flow in the opposite direction. SHORT DESCRIPTION

[0005] According to one aspect of the present invention, there is provided a semiconductor device according to claim 1. Further aspects of the invention are the subject of the dependent claims, the drawings and the description of

[0006] It is conceivable that the connecting conductor comprises current paths which have opposite directions in at least part of it. (Point 1)

[0007] According to one aspect, a semiconductor device may include one or more first devices of a first region.

[0008] The semiconductor device may comprise one or more second devices of a second region.

[0009] The semiconductor device may include a connecting conductor electrically connecting the first device to the second device.

[0010] The connecting conductor may contain current paths which are adjacent to one another and have opposite directions in at least a part thereof. (Point 2)

[0011] The connecting conductor can cause current to flow from the first device to the second device.

[0012] The connecting conductor may cause current to flow in at least a portion thereof in a direction from the second device to the first device. (Point 3)

[0013] The connecting conductor can cause current to flow from the second device to the first device.

[0014] The connecting conductor may cause current to flow in at least a portion thereof in a direction from the first device to the second device. (Point 4)

[0015] The connecting conductor may have a parallel plate structure formed by the adjacent current paths. (Point 5)

[0016] The semiconductor device may include a plurality of first devices in the first region.

[0017] The connecting conductor may be connected to each of the plurality of first devices in parallel. (Point 6)

[0018] The semiconductor device may include a plurality of second devices in the second region.

[0019] The connecting conductor may be connected to each of the plurality of second devices in parallel. (Point 7)

[0020] The connecting conductor may include a main line portion comprising the first current path, the second current path, the third current path, and the fourth current path.

[0021] The connecting conductor may include a plurality of first connecting parts each connecting the first current path to the plurality of first devices.

[0022] The connecting conductor may include a plurality of second connecting parts each connecting the third current path to the plurality of second devices. (Point 8)

[0023] The semiconductor device may include a plurality of first devices in the first region.

[0024] The semiconductor device may include a plurality of second devices in the second region.

[0025] The plurality of first devices and the plurality of second devices may be arranged in a direction from the first region to the second region. (Point 9)

[0026] The connecting conductor may further include a terminal portion connected to the outside and transmitting current to and from the outside. (Point 10)

[0027] The semiconductor device may further comprise a substrate.

[0028] In the semiconductor device, the first region and the second region may be provided in the substrate. (Point 11)

[0029] The substrate may be an isolated substrate. (Point 12)

[0030] The first devices and the second device may be insulated gate bipolar transistors or power MOSFETs.

[0031] The brief description section does not necessarily describe all required features of the embodiments of the present invention. The present invention may also be a subcombination of the features described above. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates an exemplary configuration of a semiconductor device 10 according to the present embodiment. Fig. 2 is an exemplary plan view of a semiconductor device 10 according to the present embodiment. Fig. 3 illustrates an exemplary circuit mounted on the semiconductor device 10 according to the present embodiment. Fig. 4 illustrates an example of a substrate 100 according to the present embodiment. Fig. 5 illustrates an example of a semiconductor device 10 according to the present embodiment. Fig. 6 illustrates a first exemplary operation of a 3-stage circuit formed from the semiconductor device 10 according to the present embodiment. Fig. 7 shows a second exemplary operation of the Fig. 6 shows the 3-stage circuit. Fig. 8 represents a third exemplary operation of the Fig. 6 shows the 3-stage circuit. Fig. 9 represents a fourth exemplary operation of the Fig. 6 shows the 3-stage circuit. Fig. 10 represents a fifth exemplary operation of the Fig. 6 shows the 3-stage circuit. Fig. 11 represents a sixth exemplary operation of the Fig. 6 shows the 3-stage circuit. DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

[0032] Some embodiments of the present invention are described below.

[0033] Fig. 1 illustrates an exemplary configuration of a semiconductor device 10 according to the present embodiment. The semiconductor device 10 allows current to flow in such a way that, when this current is transferred between a plurality of devices mounted on this semiconductor device 10, the effect of inductances and induced magnetic fields is reduced. In this way, the effects of this current outside or inside these devices are reduced. In other words, the surge voltage generated by the change in this current due to the switching of the devices is reduced. The semiconductor device 10 includes a first device 110, a second device 120, and a connecting conductor 130. The semiconductor device 10 further includes a substrate 100.

[0034] Devices, a circuit board connected to these devices, and the like are mounted on the substrate 100. The substrate 100 is preferably a single-sided mounting substrate on which devices are mounted on only one side. The substrate 100 is preferably an insulated substrate such as a DCB (copper direct bonding) substrate or an AMB (active metal brazing) substrate. Here, an example will be described in which the substrate 100 according to the present embodiment includes a first region 102 and a second region 104 adjacent to the first region 102. In Fig. 1, the first region 102 and the second region 104 are shown as regions lined up in a surface of the substrate 100 in the X-axis direction.

[0035] One or more first devices 110 are mounted on the first region 102. A plurality of first devices 110 may be mounted on the first region 102. Furthermore, for example, the first devices 110 may be arranged along a direction from the first region 102 to the second region 104.

[0036] One or more second devices 120 are mounted on the second region 104. A plurality of second devices 120 may be mounted on the second region 104. Furthermore, for example, the second devices 120 may be arranged along a direction from the first region 102 to the second region 104. Fig. 1 illustrates an example in which three of the first devices 110 and three of the second devices 120 are arranged in the X-axis direction.

[0037] As an example, the first devices 110 and the second devices 120 are power semiconductor elements used to control a power device or the like, and power control devices such as diodes, transistors, thyristors, or triacs. The first devices and the second devices are, for example, reverse blocking insulated gate bipolar transistors (RG-IGBTs). Furthermore, the first devices 110 and the second devices 120 may be circuits to which a plurality of these power control devices are connected.

[0038] The connecting conductor 130 electrically connects the first devices 110 and the second devices 120. The connecting conductor 130 causes current to flow from the first devices 110 to the second devices 120 or from the second devices 120 to the first devices 110 according to a voltage difference between the first devices 110 and the second devices 120.

[0039] The connecting conductor 130 includes a plurality of current paths, and at least a portion of the connecting conductor 130 includes current paths that have opposite directions and are adjacent to one another. The connecting conductor 130 is preferably formed from a metal with high electrical conductivity, such as copper or aluminum, and is preferably formed in one piece. The connecting conductor 130 includes a first current path 132, a second current path 134, a third current path 136, a fourth current path 138, a first connecting portion 142, a second connecting portion 144, and a terminal portion 146.

[0040] The first current path 132 is on the side of the first device 110 and extends in a direction opposite to the side of the second device 120. In other words, the first current path 132 is on the side of the first region 102 and extends in a direction opposite to the second region 104, e.g., the -X-axis direction. The first current path 132 is connected to the second current path 134.

[0041] The second current path 134 is on the side of the first region 102 and is bent from the first current path 132 so that it extends in a direction toward the second device 120. In other words, the second current path 134 is bent from the first current path 132 so that it is adjacent to the first current path 132 and extends from the first region 102 to the second region 104, e.g., in the +X-axis direction.

[0042] The third current path 136 is on the side of the second device 120 and extends in a direction away from the first device 110. In other words, the third current path 136 is on the side of the second region 104 and extends in a direction away from the first region 102, e.g., in the +X-axis direction. The third current path 136 is connected to the fourth current path 138.

[0043] The fourth current path 138 is on the second region 104 side and is bent from the third current path 136 so that it extends in a direction toward the first device 110. In other words, the fourth current path 138 is bent from the third current path 136 so that it is adjacent to the third current path 136 and extends from the second region 104 to the first region 102, e.g., in the -X axis direction, and is connected to the second current path 134. In other words, when viewed from the second current path 134 side, the fourth current path 138 continues from the second current path 134 so that it extends in a direction away from the first region 102. Furthermore, the third current path 136 is bent from the fourth current path 138 so that it is adjacent to the fourth current path 138 and approaches the first region 102.

[0044] In other words, the first current path 132 is not directly electrically connected to the third current path 136, but is instead connected to the third current path 136 via the second current path 143 and the fourth current path 138. In this way, the connecting conductor 130 has a main conduction part formed by a plurality of current paths connected in the order of the first current path 132, the second current path 134, the fourth current path 138, and the third current path 136. In the semiconductor device 10, current is caused to flow between the first device 110 and the second device 120 using this main conduction part. A connection is established between the main conduction part and the first device 110 by the first connection part 142, and a connection is established between the main conduction part and the second device 120 by the second connection part 144.

[0045] The first connection part 142 establishes a connection between the first current path 132 and the first device 110. In a case where a plurality of first devices 110 are mounted on the substrate 100, a plurality of first connection parts 142 are provided in the connection conductor 130. A plurality of connections between the first current path 132 and the plurality of first devices are respectively established through the plurality of first connection parts 142. As an example, the first connection part 142 is connected to a circuit board or the like formed of copper or the like on the surface of the substrate 100, and is electrically connected to the first device 110 via this circuit board.In a case where a plurality of first devices 110 are provided on the first region 102, the connecting conductor 130 is electrically connected to each of the plurality of first devices 110 through the first connecting parts 142 and branches or combines the current flowing therethrough.

[0046] The second connection part 144 is connected between the third current path 136 and the second device 120. In a case where a plurality of second devices 120 are mounted on the substrate 100, a plurality of second connection parts 144 are provided in the connection conductor 130. A plurality of connections between the third current path and the plurality of second devices 120 are respectively established through the plurality of second connection parts 144. As an example, the second connection part 144 is connected to a circuit board or the like formed on a surface of the substrate 100 made of copper or the like, and is connected to the second device 120 via this circuit board.In a case where a plurality of second devices 120 are provided on the second region 104, the connecting conductor 130 is electrically connected to each of the plurality of second devices 120 through the second connecting parts 144 and branches or combines the current flowing therethrough.

[0047] The terminal part 146 is connected to the outside and transmits current to and from the outside. In a case where the terminal part 146 causes current (voltage) to be transmitted between the outside of the semiconductor device 10 and the first device 110 and / or the second device 120, the terminal part 146 functions as an input terminal and / or output terminal.

[0048] The above-described connecting conductor 130 causes current to flow from the first device 110 to the second device 120 or from the second device 120 to the first device 110 via the bent current path. For example, when the voltage of the first device 110 is greater than the voltage of the second device 120, the connecting conductor 130 causes current to flow from the first device 110 to the second device 120. In this case, the connecting conductor 130 causes current to flow in at least a portion of the connecting conductor 130 in a direction from the second device 120 to the first device 110. In the present embodiment, the connecting conductor 130 causes current to flow in the first current path 132 in a direction (-X direction) from the second device 120 to the first device 110.

[0049] Furthermore, if the voltage of the second device 120 is greater than the voltage of the first device 110, the connecting conductor 130 causes current to flow from the second device 120 to the first device 110. In this case, the connecting conductor 130 causes current to flow in at least a portion thereof in a direction from the first device 110 to the second device 120. In the present embodiment, the connecting conductor 130 causes current to flow in the third current path 136 in a direction (+X direction) from the first device 110 to the second device 120. The connecting conductor 130 forms a parallel plate structure in which adjacent current paths are parallel to each other and reduces the inductances and the induced magnetic fields generated in these current paths. The operation in which the connecting conductor 130 reduces the inductances and the induced magnetic fields is carried out using Fig. 2 described.

[0050] Fig. 2 is an exemplary plan view of a semiconductor device 10 according to the present embodiment. Fig. 2 shows an example in which the connecting conductor 130 of the Fig. 1 causes current to flow from the first device 110 to the second device 120. More specifically, Fig. 2 is used to describe an example in which the plurality of first devices 110 has a greater potential than the plurality of second devices 120 and power is provided to the second devices 120.

[0051] The plurality of first connecting parts 142 transmit the current supplied from each of the plurality of first devices 110 to the first current path 132 to combine these currents. The first current path 132 combines the current supplied from each of the plurality of first devices 110 arranged along the X-axis direction while flowing in a direction away from the second devices 120 (-X-axis direction). The first current path 132 is connected to the second current path 134, and the second current path 134 diverts current from the first current path 132 and flows in a direction (+X-axis direction) toward the second devices 120.

[0052] Here, the first current path 132 and the second current path 134 are adjacent to each other and form a parallel plate structure in at least a portion thereof. In other words, the currents in the parallel plates flow in opposite directions, and therefore, the inductances and induced magnetic fields generated due to the currents flowing through the first current path 132 and the second current path 134 are in opposite directions and cancel each other out. Accordingly, by having the first current path 132 and the second current path 134 adjacent, it is possible to reduce the inductances and induced magnetic fields generated due to the currents flowing through the first current path 132 and the second current path 134, respectively.

[0053] The second current path 134 is connected to the fourth current path 138, and the fourth current path 138 causes current to flow from the second current path 134 on the second region 104 side in a direction away from the first devices 110 (+X-axis direction). The fourth current path 138 is connected to the third current path 136, and the third current path 136 causes the current from the fourth current path 138 to be bent and flow in a direction (-X-axis direction) toward the first devices 110.

[0054] Here, the third current path 136 and the fourth current path 138 are adjacent to each other and form a parallel plate structure in at least a portion thereof. In other words, the currents in the parallel plates flow in opposite directions, and therefore, the inductances and induced magnetic fields generated due to the currents flowing through the third current path 136 and the fourth current path 138 are in opposite directions and cancel each other out. Accordingly, by having the third current path 136 and the fourth current path 138 adjacent to each other, it is possible to reduce the inductances and induced magnetic fields generated due to the currents flowing through the third current path 136 and the fourth current path 138.

[0055] The plurality of second connecting parts 144 each branch the current flowing through the third current path 136 and supply these divided currents to the second devices 120, respectively. In other words, the third current path 136 causes the currents supplied from the plurality of first devices 110 lined up in the X-axis direction to flow in a direction (+X-axis direction) to the first devices 110 on the second region 104 side, while branching these currents to the plurality of second devices 120 lined up in the X-axis direction.

[0056] Accordingly, the connecting conductor 130 according to the present embodiment can cause current to flow from the plurality of first devices 110 to the plurality of second devices 120 while reducing the effect of the inductances and the induced magnetic fields. In this way, by arranging current paths that redirect the current flowing through them to realize currents in the opposite direction in the connecting conductor 130 adjacent to each other, the generation of the inductances and the induced magnetic fields is reduced. Consequently, the connecting conductor 130 can reduce the generation of the inductances and the induced magnetic fields without requiring another connecting conductor, another current path, or the like.Consequently, the connecting conductor 130 can reduce the effects of inductances and induced magnetic fields on the external or internal devices even when a current path is provided that carries current from one device to another device.

[0057] In this way, the connecting conductor 130 according to the present embodiment reduces the impact on external or internal devices and can thus be wired without considering the relationship with other current paths. Consequently, with the connecting conductor 130, it is possible to increase the degree of freedom for wiring design for high-performance transmission and reception, a control circuit, or the like. Furthermore, since the connecting conductor 130 reduces the impact on internal devices, it is possible to mount a device or the like (e.g., the first device 110 or the second device 120) near this connecting conductor 130. Consequently, it is possible to reduce the installation area of the semiconductor device 10.

[0058] Fig. 3 illustrates an exemplary circuit mounted on the semiconductor device 10 according to the present embodiment. Fig. 3 illustrates an example of a semiconductor device that switches the power supply between a predetermined plurality of types. The semiconductor device includes a first device 110 and a second device 120 connected in reverse parallel between a terminal M and a terminal U. Furthermore, the semiconductor device includes a third device 210 and a fourth device 220 connected in series between a terminal P and a terminal N. Furthermore, the semiconductor device includes a fifth device 212 and a sixth device 222 connected in series between the terminal P and the terminal N.

[0059] The collector terminal of the first device 110 is connected to the terminal M and the emitter terminal of the first device 110 is connected to the terminal U. In other words, the first device 110 functions as a switching device which switches whether current flows from the terminal M to the terminal U in accordance with a control signal supplied to the base terminal. Furthermore, the connection terminal of the second device 120 is connected to the terminal U and the emitter terminal of the second device 120 is connected to the terminal M. In other words, the second device 120 functions as a switching device which switches whether current flows from the terminal U to the terminal M in accordance with a control signal supplied to the base terminal.

[0060] The collector terminal of the third device 210 is connected to the terminal P and the emitter terminal of the third device 210 is connected to the terminal U. In other words, the third device 210 functions as a switching device which switches whether current flows from the terminal P to the terminal U in accordance with a control signal supplied to the base terminal. The collector terminal of the fourth device 220 is connected to the terminal U and the emitter terminal of the fourth device 220 is connected to the terminal N. In other words, the fourth device 220 functions as a switching device which switches whether current flows from the terminal U to the terminal N in accordance with a control signal supplied to the base terminal.

[0061] The fifth device 212 is a diode in which the anode terminal, which is one of its terminals, is connected to the terminal U and in which the cathode terminal, which is another of its terminals, is connected to the terminal P and causes current to flow in one direction from the terminal U to the terminal P. In other words, the fifth device 212 is connected in opposite parallel to the third device 210 between the terminal P and the terminal U. The sixth device 222 is a diode in which the anode terminal, which is one of its terminals, is connected to the terminal N and in which the cathode terminal, which is another of its terminals, is connected to the terminal U and causes current to flow in one direction from the terminal N to the terminal U.In other words, the sixth device 222 is connected in opposite parallel to the fourth device 220 between the terminal U and the terminal N.

[0062] Fig. 4 and Fig. 5 are used to describe an example in which the semiconductor device described above is used as the one shown in Fig. 1 and Fig. 2 described semiconductor device 10 is formed. Fig. 4 illustrates an example of a substrate 100 according to the present embodiment. The connecting conductor 130 is connected to the substrate 100, thereby forming the semiconductor device 10. In other words, the Fig. 4 in a state before the attachment of the connecting conductor 130. Furthermore, the substrate 100 shown in Fig. 4 in a state in which the devices, the circuit board and the like have already been formed.

[0063] A circuit board corresponding to the terminal P, the terminal N, the terminal M, and the terminal U is formed, for example, on the substrate 100. The plurality of terminals, denoted by the same reference numerals, are each electrically connected by wire bonding or the like.

[0064] The first device 110 is provided on the first region 102 and is connected to the port M and the port U. The second device 120 is provided on the second region 104 and is connected to the port M and the port U. The third device 210 and the fifth device 212 are provided on the first region 102 and are connected to the port P and the port U. The fourth device 220 and the sixth device 222 are provided on the second region 104 and are connected to the port U and the port N. Fig. 4 illustrates an example in which three of each device are mounted on the substrate 100.

[0065] The terminals M, the terminals N, the terminals P, and the terminals U may be connected to a circuit board or the like provided on the substrate 100. Similarly, each of the electrodes of the first devices 110, the second devices 120, the third devices 210, and the fourth devices 220 may be connected to the circuit board or the like provided on the substrate 100.

[0066] Fig. 5 illustrates an exemplary semiconductor device 10 according to the present embodiment. Fig. Fig. 5 illustrates a state in which the connecting conductor 130 according to the present embodiment is mounted on the Fig. 4 shown substrate 100. Furthermore, in Fig. 5 furthermore a connecting conductor 230, a connecting conductor 240 and a connecting conductor 250 are attached.

[0067] The first connection part 142 of the connection conductor 130 is connected to the terminal U of the first region 102, and the second connection part 144 is connected to the terminal U of the second region 104. Further, the connection part 146 acting as the terminals U of the semiconductor device 10 is connected, for example, to an external load. Thus, the emitter terminal of the first device 110 is connected to the collector terminal of the second device 120 via the connection conductor 130. Furthermore, the emitter terminal of the first device 110 and the collector terminal of the second device 120 are connected to the external load via the connection part 146.

[0068] The connecting conductor 230 includes a third connecting part 232 and a fourth connecting part 234. The third connecting part 232 is connected to the terminal M of the first region 102, and the fourth connecting part 234 is connected to the terminal M of the second region 104. The connecting conductor 230 further includes a terminal part that functions, for example, as the terminals M of the semiconductor device 10, and this terminal part is connected to an external power source. Thus, the collector terminal of the first device 110 is connected to the emitter terminal of the second device 120 via the connecting conductor 230. Furthermore, the collector terminal of the first device 110 and the emitter terminal of the second device 120 are connected to the external power source.

[0069] The connecting conductor 240 has a fifth connecting part 242. The fifth connecting part 242 is connected to the terminal P of the first region 102. Furthermore, the connecting conductor 240 has a terminal part that functions, for example, as the terminals P of the semiconductor device 10, and this terminal part is connected to the external power source. Thus, the collector terminals of a plurality of third devices 210 and the cathode terminals of the fifth devices 212 are connected to the external power source via the connecting conductor 240.

[0070] The connecting conductor 250 has a sixth connecting part 252. The sixth connecting part 252 is connected to the terminal N of the second region 104. Furthermore, the connecting conductor 250 has a terminal part that functions, for example, as the terminals N of the semiconductor device 10, and this terminal part is connected to the external power source or a reference potential. Consequently, the emitter terminals of a plurality of fourth devices 220 and the anode terminals of the sixth devices 222 are connected to the external power source with reference potential via the connecting conductor 250.

[0071] When electricity, as in the Fig. 1 and Fig. 2, flows from the first devices 110 to the second devices 120, the semiconductor device 10 connected in the manner described above can cause current to flow from the plurality of first devices 110 to the plurality of second devices 120 while reducing the generation of the inductances and the induced magnetic fields using the connecting conductor 130.

[0072] In the semiconductor device 10, there are cases where current is input from the outside via the connecting conductor 240 (i.e., from the P terminal) and current is output to the outside via the connecting conductor 230 (i.e., from the M terminal). In this case, the connecting conductor 230 has a parallel plate structure with the connecting conductor 240 in the first region 102, and thus the currents flowing through the connecting conductor 230 and the connecting conductor 240, respectively, have current paths in opposite directions. Consequently, in the semiconductor device 10, it is possible to reduce the generation of inductances and induced magnetic fields.

[0073] Furthermore, in the semiconductor device 10, there are cases where current is input from the outside via the connecting conductor 230 (i.e., from the M terminal) and output to the outside via the connecting conductor 250 (i.e., the N terminal). In this case, the connecting conductor 230 has a parallel plate structure with the connecting conductor 250 in the second region 104, and thus the currents flowing through the connecting conductor 230 and the connecting conductor 250, respectively, have current paths in opposite directions. Consequently, in the semiconductor device 10, it is possible to reduce the generation of inductances and induced magnetic fields.

[0074] In the manner described above, in a case where there are two different current paths that are independent of each other and through which current flows in opposite directions in the semiconductor device 10, the two current paths are formed adjacent to each other in such a manner as to form a parallel plate structure. Furthermore, in a case where there is only one independent current path and no corresponding current path in which current flows in the opposite direction in the semiconductor device 10, this one current path includes a plurality of connected current paths, and these current paths, which have opposite directions, are provided so as to be adjacent to each other in at least a part thereof.As a result, the semiconductor device 10 can reduce the inductances and induced magnetic fields of the entire power semiconductor module, which are generated according to the current flowing due to power control. In other words, it is possible to reduce the surge voltage generated in the semiconductor module.

[0075] By combining one or more of the Fig. Furthermore, with the semiconductor devices 10 shown in FIG. 5, it is possible to form a power control circuit in which the inductances and induced magnetic fields are reduced. Specifically, by combining two or more semiconductor devices 10, it is possible to form a more complicated power control circuit. For example, by combining two semiconductor devices, it is possible to form a power control circuit that outputs multiple signal levels.

[0076] Fig. 6 illustrates a first exemplary operation of a 3-stage circuit formed from the semiconductor device 10 according to the present embodiment. Fig. 6 shows an example of the Fig. 5 as a two-phase power control circuit 10. In Fig. 6, the components included in the first-phase semiconductor device 10 are represented by a lowercase letter "a" (e.g., the first device 110a, the second device 120a, and the like) and the components included in the second-phase semiconductor device 10 are represented by a lowercase letter "b" (e.g., the first device 110b, the second device 120b, and the like).

[0077] The terminal Ma and the terminal Mb, the terminal Na and the terminal Nb, and the terminal Pa and the terminal Pb are each electrically connected to one another. A power source E1 is connected between the terminal Ma and the terminal Pa. In other words, the power source E1 is connected between the terminal Mb and the terminal Pb. Furthermore, a power source E2 is connected between the terminal Ma and the terminal Na. In other words, the power source E2 is connected between the terminal Mb and the terminal Nb. The power source E1 and the power source E2 can be essentially the same power source. Furthermore, a load L is connected between the terminal Ua and the terminal Ub. Fig. The power control circuit shown in Figure 6 outputs a plurality of signal levels to the load L.

[0078] Fig. 6 illustrates an example in which the first device 110a and the second device 120b are turned ON, and all other switching devices are turned OFF. In this case, the power sources E1 and E2 do not form a closed circuit with the load L, and therefore, the voltage level supplied to the load L by the power control circuit is 0 [V].

[0079] Fig. 7 shows a second exemplary operation of the Fig. 6 shows the 3-stage circuit. Fig. 7 illustrates an example in which the second device 120b and the third device 210a are turned ON, and all other switching devices are turned OFF. In this case, the power source E1 forms a closed circuit with the load L, and therefore the power control circuit can supply a predetermined constant voltage level to the load L. Here, the predetermined constant voltage is +V [V].

[0080] Fig. 8 represents a third exemplary operation of the Fig. 6 shows the 3-stage circuit. Fig. 8 illustrates an example in which the third device 210a and the fourth device 220b are turned ON and all other switching devices are turned OFF. In this case, the power sources E1 and E2 form a closed circuit with the load, and therefore the power control circuit can supply a predetermined constant voltage level to the load L. For example, if the power sources E1 and E2 supply substantially the same voltage, the predetermined constant voltage level is +2V [V]. As described above, the Fig. 6 can supply three positive signal levels of 0 [V], +V [V] and +2V [V] to the load L.

[0081] Fig. 9 represents a fourth exemplary operation of the Fig. 6 shows the 3-stage circuit. Fig. 9 illustrates an example in which the first device 110b and the second device 120a are turned ON, and all other switching devices are turned OFF. In this case, the power sources E1 and E2 do not form a closed circuit with the load L, and therefore, the voltage level supplied to the load L by the power control circuit is 0 [V].

[0082] Fig. 10 represents a fifth exemplary operation of the Fig. 6 shows the 3-stage circuit. Fig. Figure 10 illustrates an example in which the third device 210b and the fourth device 220a are turned ON and all other switching devices are turned OFF. In this case, the power sources E1 and E2 form a closed circuit with the load L, and therefore the power control circuit can supply a predetermined constant voltage to the load L. Fig. 10 is the connection between the power sources E1 and E2 and the load L opposite the Fig. 8 shown connection between the power sources E1 and E2 and the load L in the opposite direction and therefore the predetermined constant voltage level is - 2V [V].

[0083] Fig. 11 represents an exemplary sixth operation of the Fig. 6 shows the 3-stage circuit. Fig. 11 illustrates an example in which the first device 110b and the fourth device 220a are turned ON, and all other switching devices are turned OFF. In this case, the power source E2 forms a closed circuit with the load L, and therefore the power control circuit can supply a predetermined constant voltage to the load L. Fig. 11 is the connection between the power source E2 and the load L opposite the Fig. 7, the connection between the power source E1 and the load L is in the opposite direction and therefore the predetermined constant voltage level is -V [V]. As described above, the voltage in Fig. 6 can supply three negative signal levels of 0 [V], -V [V] and -2V [V] to the load L.

[0084] As described above, the semiconductor device 10 according to the present embodiment can form a power control circuit that outputs a plurality of signal levels. Furthermore, when a short circuit occurs between the terminals of the semiconductor device 10 or the like, and an overcurrent flows between the first device 110 and the second device 120 in the same semiconductor device 10, it is possible to reduce the inductances and the induced magnetic fields, and prevent damage or the like to the elements. Furthermore, when an overcurrent flows between the terminal P and the terminal M in the same semiconductor device 10, it is possible to reduce the inductances and the induced magnetic fields, and prevent damage or the like to the elements.In the same way, when an overcurrent flows between the terminal N and the terminal M in the same semiconductor device 10, it is possible to reduce the inductances and the induced magnetic fields and prevent damage or the like to the elements.

[0085] The operations, methods, steps, and stages of each process performed by an apparatus, system, program, and method illustrated in the claims, embodiments, or diagrams may be performed in any order, as long as the order is not indicated by "before," "previous," or the like, and as long as the output from a preceding process is not used in a subsequent process. Although the process flow is described in the claims, embodiments, or diagrams using terms such as "first" or "next," this does not necessarily mean that the process must be performed in that order. List of reference symbols 10 semiconductor device 100 substrate 102 first area 104 second area 110 first facility 120 second facility 130 connecting conductors 132 first current path 134 second current path 136 third current path 138 fourth current path 142 first connecting part 144 second connecting part 146 connecting part 210 third facility 212 fifth facility 220 fourth facility 222 sixth facility 230 connecting conductors 232 third connecting part 234 fourth connecting part 240 connecting conductors 242 fifth connecting part 250 connecting conductors 252 sixth connecting part

Claims

[1] Semiconductor device (10) comprising: a plurality of first devices (110) of a first area (102); one or more second devices (120) of a second area (104); and a connecting conductor (130) electrically connecting the first device (110) to the second device (120), the connecting conductor (130) comprising: current paths (132, 134, 136, 138) which are adjacent to one another and have opposite directions in at least a part thereof, and are connected in parallel to each of the plurality of first devices (110), a first current path (132) on one side of the first devices (110) with a direction away from the second device (120) and a second current path (134) connected to the first current path (132) and running parallel to the first current path (132) on the side of the first devices (110), which second current path (134) is bent from the first current path (132) so that it has a direction towards the second device (120), a third current path (136) on one side of the second device (120) with a direction away from the first devices (110), and a fourth current path (138) connected to the third current path (136) and running parallel to the third current path (136) on the side of the second device (120), which fourth current path (138) is bent from the third current path (136) so that it has a direction towards the first devices (110), and wherein: a plurality of connections between the first current path (132) and the plurality of first devices (110) are each made by a plurality of first connecting parts (142); one or more connections between the third current path (136) and the one or more second devices (120) are each made by second connecting parts (144); the connecting conductor (130) has a parallel plate structure formed from the adjacent current paths (132, 134, 136, 138); the first current path (132) and the second current path (134) are each formed as plate-shaped conductor sections arranged parallel to one another; and the third current path (136) and the fourth current path (138) are each formed as plate-shaped conductor sections arranged parallel to one another. [2] The semiconductor device according to claim 1, wherein the connecting conductor (130) causes current to flow from the first devices (110) to the second device (120) and causes current in at least a part thereof to flow in a direction from the second device (120) to the first devices (110). [3] The semiconductor device according to claim 1, wherein the connecting conductor (130) causes current to flow from the second device (120) to the first devices (110) and causes current in at least a part thereof to flow in a direction from the first devices (110) to the second device (120). [4] A semiconductor device according to any one of claims 1 to 3, comprising: a plurality of second devices (120) in the second area (104), wherein the connecting conductor (130) is connected in parallel to each of the plurality of second devices (120). [5] A semiconductor device according to claim 1, wherein the connecting conductor (130) comprises: a main line part having the first current path (132), the second current path (134), the third current path (136) and the fourth current path (138); a plurality of first connecting parts (142) each connecting the first current path (132) to the plurality of first devices (110); and a plurality of second connecting parts (144) each connecting the third current path (136) to the plurality of second devices (120). [6] A semiconductor device according to any one of claims 1 to 5, comprising: a plurality of first devices (110) in the first area (102); and a plurality of second devices (120) in the second area (104), wherein the plurality of first devices (110) and the plurality of second devices (120) are arranged in a direction from the first region (102) to the second region (104). [7] The semiconductor device according to any one of claims 1 to 6, wherein the connecting conductor (130) further includes a terminal part (146) connected to the outside and transmitting current to and from the outside. [8] A semiconductor device according to any one of claims 1 to 7, further comprising: a substrate (100), wherein the first region (102) and the second region (104) are provided in the substrate (100). [9] A semiconductor device according to claim 8, wherein the substrate (100) is an insulated substrate. [10] A semiconductor device according to any one of claims 1 to 9, wherein the first devices (110) and the second device (120) are insulated gate bipolar transistors or power MOSFETs.

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