SIGNAL TRANSMISSION CIRCUIT AND POWER CONVERTER DEVICE

Abstract

Signal transmission circuit (6) comprising: - a first circuit (100) configured to output first and second transmission signals (VS, VR) based on an external input signal (XIN); - first and second transformers (10, 20) configured to receive the first and second transmission signals (VS, VR) on a primary side and to generate first and second transformer output signals (RX1, RX2) on a secondary side; and - a second circuit (200) configured to generate an external output signal (XOUT) based on the first and second transformer output signals (RX1, RX2), wherein the external input signal (XIN) has first and second logic levels, changes from the second logic level to the first logic level at a first transition time and changes from the first logic level to the second logic level at a second transition time, wherein the first circuit (100) receives the first and second transmission signals (VS,VR) outputs such that the first transmission signal (VS) changes between the first and second logic levels in a first period when the external input signal (XIN) is at the first logic level, and such that it is fixed at the second logic level when the external input signal (XIN) is at the second logic level, and is set to the first logic level for a predetermined period at the first transition time of the external input signal (XIN), and such that the second transmission signal (VR) changes between the first and second logic levels in a second period when the external input signal (XIN) is at the second logic level, and such that it is fixed at the second logic level when the external input signal (XIN) is at the first logic level, and is set to the first logic level for a predetermined period at the second transition time of the external input signal (XIN).and the second circuit (200) comprises: - first and second control protection devices (23S, 23R) configured to invalidate the first and second transformer output signals (RX1, RX2) for first and second mask periods based on the first or second logic level of the external output signal; - a first signal shaping circuit (24S, 25S) configured to receive the first transformer output signal (RX1) via the first control protection device (23S) and, by inverting, amplifying, and shaping the waveform of the first transformer output signal (RX1), to generate a first logic set signal (VS2) indicating an active level for a first logic set period that exceeds a period for which the first transformer output signal (RX1) indicates an active level; - a second signal shaping circuit (24R, 25R) configuredto receive the second transformer output signal (RX2) via the second control protection device (23R) and to generate a second logic set signal (VR2) by inverting, amplifying, and shaping the waveform of the second transformer output signal (RX2), which indicates an active level for a second logic set period that exceeds a period for which the second transformer output signal (RX2) indicates an active level; a logic set signal control circuit (26) configured to receive the first and second logic set signals (VS2, VR2) and to invalidate the indication of an active level by the first and second logic set signals (VS2, VR2) when both the first and second logic set signals (VS2, VR2) indicate an active level; the logic set signal control circuit (26) further configured to receive the first and second logic set signals (VS2, VR2) without any changes,if at least one of the first and second logic set signals (VS2, VR2) indicates an inactive level, and an output signal generation circuit (27) configured to receive the first and second logic set signals (VS2, VR2) via the logic set signal control circuit (26) and to generate the external output signal (XOUT) which is set to one logic level of the first and second logic levels when the first logic set signal (VS2) indicates an active level, and which is set to the other logic level when the second logic set signal (VR2) indicates an active level.

Description

Technical field

[0001] The present invention relates to a signal transmission circuit that transmits a signal via a transformer and to an energy conversion device that includes the signal transmission circuit. State of the art

[0002] For example, in an inverter that drives a three-phase AC motor, a conventional signal transmission circuit used in a driver circuit device for a power semiconductor switching element in the inverter has the following arrangement.

[0003] The conventional signal transmission circuit transmits first and second input signals at different signal speeds while maintaining electrical isolation. It further comprises a pulse generation unit, first and second transmission units, a buffer circuit, and an oscillation determination circuit. The first and second transmission units transmit first and second pulse signals, generated by the pulse generation unit according to the logic states of the first and second input signals, to the buffer circuit and the oscillation determination circuit, respectively, while maintaining electrical isolation.

[0004] The buffer circuit receives a first recovery output signal by restoring the first input signal based on the rising edges of the first and second pulse signals. The oscillation determination circuit receives a second recovery output signal by restoring the second input signal based on the oscillation states of the first and second pulse signals. A signal transmission circuit with such an arrangement is disclosed, for example, in patent document 1. State of the art Patent literature

[0005] Document 1: Japanese patent application publication JP 2014-7502 A Summary of the invention's objective

[0006] In the above arrangement of a conventional signal transmission circuit, if the ON pulse width (active level) of the first input signal is shorter than the control times of the first and second pulse signals generated by the pulse generation unit, a time period can occur during which both the first and second pulse signals are in the ON state. When this time period occurs, both input signals are sent to the buffer circuit in the ON state.

[0007] In this state, the output signals from the buffer circuit, specifically the first and second recovery output signals, enter an unstable state in which their contents change depending on whether one of the input signals (first and second pulse signals) is executed earlier by the buffer circuit. This leads to a malfunction. Alternatively, a delay occurs until one of the first and second pulse signals reaches the OFF state (inactive level).

[0008] As described above, the problem with the conventional signal transmission circuit is that it is unable to output external output signals (first and second recovery output signals) that accurately reflect external input signals (first and second input signals).

[0009] The present invention was conceived to solve the above problem and has the objective of providing a signal transmission circuit that outputs external output signals which accurately reflect external input signals, and of providing an energy conversion device which includes the signal transmission circuit. Means of solving the problem

[0010] A signal transmission circuit according to claim 1 of the present invention comprises the following: a first circuit configured to output first and second transmission signals based on an external input signal; first and second transformers configured to receive the first and second transmission signals on a primary side and to receive first and second transformer output signals on a secondary side; and a second circuit configured to generate an external output signal based on the first and second transformer output signals, wherein the external input signal has first and second logic levels, changes from the second logic level to the first logic level at a first transition time, and changes from the first logic level to the second logic level at a second transition time, wherein the first circuit outputs the first and second transfer signals such that the first transfer signal changes between the first and second logic levels in a first period when the external input signal is at the first logic level, that it is furthermore fixed at the second logic level when the external input signal is at the second logic level, and is set to the first logic level for a predetermined period at the first transition time of the external input signal.and wherein the first circuit outputs the first and second transmission signals such that the second transmission signal changes between the first and second logic levels in a second period when the external input signal is at the second logic level, that it is furthermore fixed at the second logic level when the external input signal is at the first logic level, and is set to the first logic level for a predetermined period at the second transition time of the external input signal.

[0011] Furthermore, the second circuit exhibits the following: First and second control protection devices configured to invalidate the first and second transformer output signals for first and second mask periods based on the first or second logic level of the external output signal; a first signal shaping circuit configured to receive the first transformer output signal via the first control protection device and to generate a first logic set signal indicating an active level for a first logic set period that exceeds a period for which the first transformer output signal indicates an active level; a second signal shaping circuit configured to receive the second transformer output signal via the second control protection device and to generate a second logic set signal indicating an active level for a second logic set period that exceeds a period for which the second transformer output signal indicates an active level; a logic set signal control circuit configured to receive the first and second logic set signals and to invalidate the indication of an active level by the first and second logic set signals if both the first and second logic set signals indicate an active level; and An output signal generation circuit configured to receive the first and second logic set signals via the logic set signal control circuit and to generate the external output signal, which is set to one logic level of the first and second logic levels when the first logic set signal indicates an active level, and which is set to the other logic level when the second logic set signal indicates an active level. Effects of the invention

[0012] In the signal transmission circuit according to the present invention, the first circuit outputs the first and second transmission signals, which change between the first and second logic levels in the first and second periods at the time when an external input signal is present at the first and second logic levels, in addition to the first and second transition times of the external input signal. This enables the second circuit to reliably detect changes of the external input signal from the second and first logic levels to the first and second logic levels as the first and second transformer output signals.

[0013] Furthermore, the first and second control protection devices invalidate the first and second transformer output signals in the first and second mask periods based on the first or second logic level of an external output signal. This improves the reliability of an external output signal generated by the output signal generation circuit by setting a period in the first mask period during which it is not necessary to detect whether the external input signal has changed to the first logic level, and also by setting a period in the second mask period during which it is not necessary to detect whether the external output signal has changed to the second logic level.

[0014] Furthermore, the first and second signal-shaping circuits generate the first and second logic set signals, which indicate an active level for the first and second logic set periods that exceed the periods for which the first and second transformer output signals indicate an active level. This allows the output signal generation circuit to produce an external output signal that reliably reflects the command contents of the first and second logic set signals.

[0015] Furthermore, the logic set signal control circuit invalidates the first and second logic set signals if both indicate an active level. This reliably prevents a situation where both the first and second logic set signals are set to an active level when the output signal generation circuit produces an external output signal, thus improving the reliability of the external output signal.

[0016] Therefore, the signal transmission circuit according to the present invention outputs an external output signal that precisely reflects an external input signal. This enables highly reliable signal transmission.

[0017] Further objectives, features, aspects and advantages of the present invention will become even clearer from the following detailed description and the accompanying drawings. Brief description of the drawings

[0018] The figures show:

[0019] Fig. 1 a block diagram showing the arrangement of a signal transmission circuit according to a first embodiment of the present invention;

[0020] Fig. 2 a block diagram showing the overall arrangement of an energy converter device comprising the signal transmission circuit according to the first embodiment;

[0021] Fig. 3 a waveform diagram showing waveforms in operation during signal transmission processing by the signal transmission circuit according to the first embodiment;

[0022] Fig. 4 a block diagram showing the internal structure of a pulse converter circuit as a component of a first circuit of the signal transmission circuit according to the first embodiment;

[0023] Fig. 5 a waveform diagram showing waveforms during operation in a pulse conversion process using the in Fig. The pulse converter circuit shown in section 4 is shown;

[0024] Fig. 6 a circuit diagram showing the internal structure of a Fig. The detection circuit shown in Figure 4 is for a rising edge;

[0025] Fig. 7 a waveform, which shows waveforms in operation during detection processing using the detection circuit for a rising edge, which are detailed in Fig. 6 is shown;

[0026] Fig. 8 a circuit diagram showing the internal structure of a Fig. The detection circuit for a falling edge is shown in Figure 4;

[0027] Fig. Figure 9 is a waveform diagram showing waveforms during operation in detection processing using the falling edge detection circuit, detailed in Fig. 8 is shown;

[0028] Fig. 10 a circuit diagram showing the internal structure of a Fig. 1 shows the control protection element shown;

[0029] Fig. 11 a circuit diagram showing the internal structure of a Fig. The control circuit shown in 1 is shown;

[0030] Fig. 12 a waveform diagram showing waveforms in operation, relating to details of the control carried out by the control circuit located in Fig. 11 is shown in detail;

[0031] Fig. 13 a circuit diagram showing the internal structure of a Fig. The buffer circuit shown in section 4 is shown;

[0032] Fig. 14 a block diagram showing an arrangement according to a first aspect in an energy converter device according to a second embodiment of the present invention;

[0033] Fig. 15 a block diagram showing an arrangement according to a second aspect in the energy converter device according to the second embodiment of the present invention;

[0034] Fig. 16 a block diagram showing an arrangement according to a third aspect in the energy converter device according to the second embodiment of the present invention;

[0035] Fig. 17 a block diagram showing an arrangement according to a first aspect in an energy converter device according to a third embodiment of the present invention;

[0036] Fig. 18 a block diagram showing an arrangement according to a second aspect in the energy converter device according to the third embodiment of the present invention;

[0037] Fig. 19 a block diagram showing an arrangement according to a third aspect in the energy converter device according to the third embodiment of the present invention. Description of the embodiments Embodiment 1 Overall arrangement of the signal transmission circuit 6

[0038] Fig. Figure 1 shows a block diagram illustrating the overall arrangement of a signal transmission circuit. 6 This represents a first embodiment of the present invention. The signal transmission circuit 6 According to the first embodiment, the following is referred to Fig. 1 described. In each embodiment described below, the same reference numerals denote the same components, and redundant descriptions are omitted where necessary.

[0039] As in Fig. The signal transmission circuit shown in 1 is... 6 through a first circuit 100, a transformer 10 (first transformer), a transformer 20 (second transformer) and a second circuit 200 educated.

[0040] The transformer 10 has a coil 110 as a primary coil and a coil 210 as a secondary coil. The transformer 20 has a coil 120 as a primary coil and a coil 220 as a secondary coil.

[0041] The first circuit 100 is electrically connected to the coil 110 of the transformer 10 and the coil 120 of the transformer 20 connected. The second circuit 200 is electrically connected to the coil 210 of the transformer 10 and the coil 220 of the transformer 20 tied together.

[0042] The first circuit 100transmits an input signal XIN (external input signal) that is externally connected via an input port 101 is received via the transformer 10 and the transformer 20 to the second circuit 200 .

[0043] The first circuit 100 It also provides an output signal XOUT (external output signal) from an output terminal. 201 the second circuit 200 outwards, based on the induced voltage signals RX1 and RX2 from the transformers 10 and 20 based.

[0044] Accordingly, the signal transmission circuit 6 The signal transmission processing takes place during the reception of the input signal XIN and the output of the output signal XOUT, which reflects the signal content of the input signal XIN. That is, the output signal XOUT is a signal that corresponds to the input signal XIN.

[0045] The connection between the transformer 10 and the first and second circuit 100 and 200 is described below. The first end of the coil 110 is connected to the first output terminal (for a transmission signal VS) of the first circuit 100 connected. The first circuit 100 sets the second end of the coil 110 to a reference potential VSS1. The first end of the coil 210 is connected to the first input terminal (for the induced voltage signal RX1) of the second circuit 200 connected. The second circuit 200 sets the second end of the coil 210 to a reference potential VSS2.

[0046] The connection between the transformer 20 and the first and second circuit 100 and 200 is described. The first end of the coil 120is connected to the second output terminal (for a transmission signal VR) of the first circuit 100 connected. The second end of the coil 120 is on the reference potential VSS1 of the first circuit 100 set. The first end of the coil 220 is connected to the second input terminal (for the induced voltage signal RX2) of the second circuit 200 connected. The second circuit 200 sets the second end of the coil 220 to the reference potential VSS2.

[0047] The first circuit 100 features a pulse converter circuit 102 as a key component. The pulse converter circuit 102 It provides the transmission signal VS (first transmission signal) and the transmission signal VR (second transmission signal), which is based on the input connection. 101 The received input signal XIN is sent to the first end of the coil. 110 and the first end of the coil120 out, each of which is connected to the first and second output terminals.

[0048] Although described in more detail later, the pulse converter circuit uses 102 a first clock signal, obtained as an AND result between the input signal XIN and an oscillation signal from an oscillator, to be used as the transmission signal VS, a first pulse signal to the first end of the coil 110 to output a result obtained as an OR operation between the signal obtained by detecting a rising edge of the input signal XIN and the first clock signal.

[0049] Furthermore, the pulse converter circuit uses 102 a second clock signal, obtained as an AND result between the signal obtained by inverting the input signal XIN and an oscillation signal from the oscillator, to transmit a second pulse signal VR to the first end of the coil120 to output a result obtained as an OR operation between the signal obtained by detecting a falling edge of the input signal XIN and the second clock signal.

[0050] Accordingly, the transformer receives 10 On the primary side, the transmission signal VS (first transmission signal) is connected to the first output terminal of the first circuit. 100 and receives the induced voltage signal RX1 (first transformer output signal) on the secondary side at the first input terminal of the second circuit. 200 .

[0051] The transformer receives in the same way 20 On the primary side, the transmission signal VR (second transmission signal) is connected to the second output terminal of the first circuit. 100 and receives the induced voltage signal RX2 (second transformer output signal) on the secondary side at the second input terminal of the second circuit.200 .

[0052] The second circuit 200 is equipped with control protection elements 23S and 23R , buffer circuits 24S and 24R , Schmitt circuits 25S and 25R , a control circuit 26 and an intermediate storage circuit 27 formed. The first and second input terminals of the second circuit 200 are each connected to the first end of the coil 210 of the transformer 10 and the first end of the coil 220 of the transformer 20 tied together.

[0053] The control protection element 23S It has an input range IN, an output range OUT, and a control input range SW. The input range IN receives the induced voltage signal RX1 from the first input terminal of the second circuit. 200The control input area SW receives the output signal XOUT from the buffer circuit. 27 as a VSM control signal.

[0054] The control protection element 23S The induced voltage signal RX1 is output from the output range OUT without any change in a period other than a first mask period, for which the control signal VSM indicates "H". However, it should be noted that the control protection element 23S The induced voltage signal RX1 is forcibly invalidated in the first mask period and the output range OUT is set to "L".

[0055] Similarly, the control protection element 23R The circuit has an input range IN, an output range OUT, and a control input range SW. The input range IN receives the induced voltage signal RX2 from the second input terminal of the second circuit. 200The control input area SW receives an inverted output signal XOUT from the buffer circuit. 27 as a VRM control signal.

[0056] The control protection element 23R The induced voltage signal RX2 is output from the output range OUT without any change in one period except for a second mask period, for which the control signal VRM indicates "H". However, it should be noted that the control protection element 23R The induced voltage signal RX2 is forcibly invalidated in the second mask period and the output range OUT is set to "L".

[0057] In this way, the control protection elements are invalidated. 23S and 23R the induced voltage signals RX1 and RX2 (first and second transformer output signals) in the first and second mask periods.

[0058] The buffer circuit 24SA signal VS1 is received by inverting and amplifying the induced voltage signal RX1, which is transmitted via the control protection element. 23S is obtained. The Schmitt circuit 25S A signal VS2 is obtained by shaping the waveform of signal VS1. Due to the fact that signal VS2 is an inverted version of signal VS1, the above waveform shaping process is equivalent to generating signal VS2 (first logic set signal), which indicates "H" (active level) for one period (first logic set period) that exceeds the period for which signal VS1 indicates "L" (active level).

[0059] The buffer circuit 24R A signal VR1 is received by inverting and amplifying the induced voltage signal RX2, which is transmitted via the control protection element. 23R is obtained. The Schmitt circuit 25RA signal VR2 is obtained by shaping the waveform of signal VR1. Due to the fact that an inverted version of signal VR1 is obtained as signal VR2, the above waveform shaping process is equivalent to generating signal VR2 (second logic set signal), which indicates "H" (active level) for one period (second logic set period) that exceeds the period for which signal VR1 indicates "L" (active level).

[0060] Accordingly, the buffer circuit functions 24S and the Schmitt circuit 25S as a first signal shaping circuit. The first signal shaping circuit receives the induced voltage signal RX1 (first transformer output signal) via the control protection element. 23S (First control protection device). If the induced voltage signal RX1 is not passed through the control protection element 23SWhen invalidated, the circuit generates the signal VS2 (first logic set signal), which indicates "H" (active level) for the first logic set period that exceeds a period for which the induced voltage signal RX1 indicates "H" (active level).

[0061] The buffer circuit functions in the same way. 24R and the Schmitt circuit 25R as a second signal shaping circuit. The second signal shaping circuit receives the induced voltage signal RX2 (second transformer output signal) via the control protection element. 23R (Second control protection device). If the induced voltage signal RX2 is not passed through the control protection element 23R If the logic is invalidated, the circuit generates the signal VR2 (second logic set signal), which indicates "H" (active level) for the second logic set period that exceeds a period for which the induced voltage signal RX2 indicates "H" (active level).

[0062] The control circuit 26 It receives the signals VS2 and VR2 (first and second logic set signals). If both signals VS2 and VR2 indicate "H" (active level), the control circuit is invalidated. 26 "H" of the signals VS2 and VR2 and outputs "L" signals VS3 and VR3.

[0063] If, on the other hand, at least one of the signals VS2 and VR2 is set to "L", the control circuit outputs 26 the signals VS2 and VR2 as the signals VS3 and VR3 without any change to a set input range S and a reset input range R of the buffer circuit 27 away.

[0064] The intermediate storage circuit 27 As an output signal generation circuit, it receives the signals VS3 and VR3 via the control circuit. 26 (Logic set signal control circuit). In this case, if the control circuit 26If no invalidation processing has been performed with respect to the signals VS2 and VR2, the signals VS3 and VR3 become the signals VS2 and VR2 (first and second logic set signals).

[0065] Accordingly, the buffer circuit receives 27 The signals VS3 and VR3. When the signal VS3 (= VS2) indicates "H" (active level), the buffer circuit is activated. 27 set to "H" (one of the logic levels "H" and "L"). When the signal VR3 (= VR2) indicates "H" (active level), the buffer circuit is activated. 27 set to "L" (the other logic levels being "H" and "L"). The buffer circuit 27 It generates the output signal XOUT (external output signal) and outputs it from an output range Q. Furthermore, the buffer circuit provides 27the inverted output signal XOUT as an inverted signal of the output signal XOUT together with the output signal XOUT from an inverting output range QB. Energy converter device 60 including signal transmission circuitry 6

[0066] Fig. Figure 2 shows a block diagram illustrating the overall arrangement of the energy converter device. 60 including the signal transmission circuit 6 as described in the first embodiment. As in Fig. As shown in 2, the signal transmission circuit 6 according to the first embodiment, used to provide a control signal S4 for performing driver control of a power semiconductor switching element 2 (Power semiconductor switching element), such as an IGBT, in the energy conversion device 60 , to transfer.

[0067] That is, the energy conversion device 60, which are used to control an engine 1 The device, intended for use in a hybrid vehicle, an electric vehicle, or the like, has the following components: the power semiconductor switching element 2 , a driver unit 3 as a driver circuit that controls the power semiconductor switching element 2 controls, a control system 4 , which provides a control signal S4 for the driver unit 3 generated to power the driver unit 3 to cause the power semiconductor switching element 2 to control, and the signal transmission circuit 6 according to the first embodiment, which receives the control signal S4 from the controller 4 when the input signal XIN is received and it is sent as the output signal XOUT to the driver unit 3 transfers.

[0068] The signal transmission circuit 6 is between the control 4 and the driver unit 3arranged. This enables the signal transmission circuit 6 , the control signal S4 from the controller 4 to receive the input signal XIN, to generate the output signal XOUT according to the control signal S4, and to send it to the driver unit 3 to output while the control 4 is isolated from devices that are to be controlled by high voltages, such as the driver unit. 3 , the power semiconductor switching element 2 and the engine 1 . Signal transmission processing using the signal transmission circuit 6

[0069] Fig. Figure 3 shows a waveform diagram illustrating waveforms during operation in signal transmission processing using the signal transmission circuit. 6 according to the first embodiment of the present invention.

[0070] Fig. Figure 3 shows the waveforms during operation of the input signal XIN, which is fed into the signal transmission circuit. 6 is entered, an oscillation signal CLK in the first circuit 100 , of the transmission signal VS, which is the first pulse signal from the first circuit 100 to the first end of the coil 110 is transmitted, and the transmission signal VR, which is the second pulse signal that comes from the first circuit 100 to the first end of the coil 120 is transmitted. These signals are those that are transmitted to the first circuit. 100 , including the pulse converter circuit 102 are assigned.

[0071] Furthermore, it shows Fig. 3 the waveforms during operation of the induced voltage signal RX1, which is at the first end of the coil 210 generated and by the second circuit 200 is received, of the induced voltage signal RX2, which is at the first end of the coil 220generated and by the second circuit 200 is received, the signal VS1, which is an output signal from the buffer circuit 24S is, of the signal VR1, which is an output signal from the buffer circuit 24R is, of the signal VS2, which is an output signal from the Schmitt circuit 25S is, and of the signal VR2, which is an output signal from the Schmitt circuit 25R is.

[0072] Furthermore, it shows Fig. 3 the waveforms during operation of the signal VS3, which is an input signal for the set input range S of the buffer circuit 27 is, of the signal VR3, which is an input signal for the reset input range R of the buffer circuit 27 is the output signal XOUT (= control signal VSM) from the signal transmission circuit 6 , which is an output signal from a (non-inverting) output range Q of the buffer circuit 27is, and of the inverted output signal XOUT (= control signal VRM), which is an output signal from the inverting output range QB of the buffer circuit 27 is.

[0073] The detailed arrangement and operation of each unit in the signal transmission circuit 6 will be described in more detail below. Arrangement of each unit in the signal transmission circuit 6

[0074] Fig. Figure 4 shows a block diagram illustrating the internal structure of the pulse converter circuit. 102 as a component of the first circuit 100 the signal transmission circuit 6 represents. Fig. Figure 5 shows a waveform diagram illustrating waveforms during operation of the pulse conversion process of the pulse converter circuit. 102 This represents... It should be noted that the arrangement of the pulse converter circuit... 102 , which in Fig. Figure 4 is merely an example and is not to be understood as exhaustive or restrictive.

[0075] As in Fig. As shown in section 4, the pulse converter circuit 102 The following: a detection circuit 31 for a rising edge, a detection circuit 32 for a falling edge, an oscillator 38 , two AND gates 34 and 35 , two OR gates 36 and 37 and an inverter 39 The input signal XIN, which goes into the pulse converter circuit 102 When entered, the detection circuit 31 for a rising edge, the detection circuit 32 for a sloping flank, the one input of the AND gate 34 and the input area of ​​the inverter 39 supplied.

[0076] The oscillation signal CLK from the oscillator 38 will be connected to the other input of the AND gate34 and the one input of the AND gate 35 supplied. An output signal from the inverter 39 will be connected to the other input of the AND gate 35 supplied. An output signal VA from the detection circuit. 31 For a rising edge, one input of the OR gate is used. 36 supplied. An output signal VC from the AND gate. 34 The other input of the OR gate is then sent. 36 supplied. An output signal VB from the detection circuit. 32 For a falling edge, one input of the OR gate is used. 37 supplied. An output signal VD from the AND gate. 35 The other input of the OR gate is then sent. 37 supplied.

[0077] As in Fig. As shown in section 5, the pulse converter circuit 102 , when the logic value of the input signal XIN changes from "L" to "H" (first transition time), the detection circuit 31For a rising edge, the signal VA is output, which has an "H" pulse with a correspondingly predetermined period width. When the logic value of the input signal XIN changes from "H" to "L" (second transition time), the detection circuit outputs 32 For a falling edge, the signal VB is also generated, which has an "H" pulse with a correspondingly predetermined period width.

[0078] The oscillator 38 It outputs the oscillation signal CLK with a predetermined period. The AND gate 34 It outputs the signal VC, which is the AND result between the input signal XIN and the oscillation signal CLK. The AND gate 35 It outputs the signal VD, which is the AND result between the input signal XIN and an inverted version of the oscillation signal CLK. The signals VA and VC are fed to the OR gate. 36 supplied, and an output signal from the OR gate 36becomes the transmission signal VS, which is generated by the pulse converter circuit 102 The signals VB and VD are output. 37 supplied. An output signal from the OR gate. 37 becomes the transmission signal VR, which is generated by the pulse converter circuit 102 is issued.

[0079] Accordingly, the input signal XIN (external input signal) is a signal with "H" and "L" (first and second logic levels) that changes from "L" to "H" at the first transition time, and from "H" to "L" at the second transition time.

[0080] Furthermore, the transmission signal VS (first transmission signal) is a signal that changes between "H" and "L" in one period (first period) of the oscillation signal CLK when the input signal XIN is set to "H". It is also fixed at "L" when the input signal XIN is set to "L", and is set to "H" for a predetermined period at the first transition time of the input signal XIN.

[0081] Similarly, the transmission signal VR (second transmission signal) is a signal that changes between "H" and "L" in one period (second period (= first period)) of the oscillation signal CLK when the input signal XIN is set to "L". Furthermore, it is fixed at "L" when the input signal XIN is set to "H", and at "H" for a predetermined period during the second transition time of the input signal XIN.

[0082] Fig. Figure 6 shows a circuit diagram illustrating the internal structure of the device. Fig. 4 detection circuits shown 31 for a rising flank. Fig. Figure 7 shows a waveform diagram illustrating waveforms during operation in a detection processing circuit. 31 for a rising edge. It should be noted that the arrangement of the detection circuit 31 for a rising flank that is in Fig. Figure 6 is merely an example and is not exhaustive.

[0083] As in Fig. The detection circuit shown in Figure 6 is... 31 for a rising edge through a delay circuit 311 , an inverter 312 and an AND gate 313 formed. A signal DIN1, which is fed into the detection circuit. 31 When input for a rising edge, the input area of ​​the delay circuit is used. 311 and the one input of the AND gate 313supplied. The signal DIN1, which goes into the delay circuit 311 The input is delayed by a predetermined period (in Fig. 7 (labeled "τ") and to the other input of the AND gate 313 via the inverter 312 supplied. An output signal from the AND gate. 313 An output signal DOUT1 is generated by the detection circuit 31 for a rising flank.

[0084] As in Fig. As shown in Figure 7, the detection circuit 31 For a rising edge, the signal DOUT1 is output with an "H" pulse width for the predetermined period τ when the input signal DIN1 changes from "L" to "H".

[0085] Accordingly, the in Fig. 4 detection circuits shown 31For a rising edge, output the signal VA with the "H" pulse width according to the predetermined period τ at the first transition time when the input signal XIN changes from "L" to "H".

[0086] Fig. Figure 8 shows a circuit diagram illustrating the internal arrangement of the components. Fig. 4 detection circuits shown 32 indicates a sloping flank. Fig. Figure 9 shows a waveform diagram illustrating waveforms during operation in the detection processing by the detection circuit. 32 for a sloping flank. It should be noted that the in Fig. 8 shown arrangement of the detection circuit 32 This is merely one example of a sloping flank and is not exhaustive.

[0087] As in Fig. Figure 8 shows the detection circuit. 32 for a falling edge using a delay circuit 321 , an inverter 322and an AND gate 323 formed. One of the detection circuits 32 The signal supplied to DIN2 for a falling edge is connected to the input area of ​​the delay circuit. 321 and the input area of ​​the inverter 322 supplied. An output signal from the inverter 322 This will be one input of the AND gate. 323 supplied.

[0088] The signal DIN2, which goes into the delay circuit 321 The input is delayed by the predetermined period τ and sent to the other input of the AND gate. 323 supplied. An output signal from the AND gate. 323 An output signal DOUT2 is generated by the detection circuit 32 for a sloping flank.

[0089] As in Fig. As shown in 9, the detection circuit 32For a falling edge, the signal DOUT2 is output with an "H" pulse width for the predetermined period τ when the input signal DIN2 changes from "H" to "L".

[0090] Therefore, the in Fig. 4 detection circuits shown 32 For a falling edge, output the signal VB with an "H" amplitude corresponding to the predetermined period τ at the second transition time described above when the input signal XIN changes from "H" to "L".

[0091] Fig. Figure 10 shows a circuit diagram illustrating the internal structure of a control protection element. 23 ( 23S , 23R ). It should be noted that the control protection element 23 a circuit arrangement that provides each of the control protection elements 23S and 23R common to all. Furthermore, the arrangement of the control protection element is 23 , which in Fig. Figure 10 is merely an example and is not exhaustive.

[0092] As in Fig. As shown in 10, the control protection element 23 The following: two NMOS transistors 231 and 232 and a PMOS transistor 233 An input area IN of the control protection element 23 is known to be connected to the drain (terminal) of the NMOS transistor 231 , the drain of the NMOS transistor 232 and the drain of the PMOS transistor 233 connected. An output area OUT of the control protection element. 23 is connected to the IN input area. A control input area SW of the control protection element. 23 is connected to the gate (terminal) of the NMOS transistor 231 tied together.

[0093] The source (terminal) of the NMOS transistor 231 is set to a reference potential VSS. The gate and source of the NMOS transistor. 232are also set to the reference potential VSS. On the other hand, the gate and source of the PMOS transistor are 233 Set to a power supply potential VDD. It should be noted that the control protection element 23 an overvoltage protection element whose gate potential is fixed, and a part (in this case the NMOS transistor) 231 ) of the surge protection element while it controls its operation.

[0094] If in the control protection element 23 A control signal (VSM, VRM) received from the control input area SW indicates "H", the NMOS transistor 231 The control signal is switched on to set the output range to "L" and to invalidate any signal received from the input range IN. When the control signal indicates "L", the NMOS transistor is switched on. 231switched off to allow a signal received from the input range IN to be output from the output range OUT without any modification.

[0095] Accordingly, the control protection element can 23S Invalidate the induced voltage signal RX1 for one period, as the first mask period, for which the control signal VSM (= output signal XOUT), received from the control input area SW, indicates "H" (first logic level).

[0096] Similarly, the control protection element can 23R The induced voltage signal RX2 is invalidated for one period, the second mask period, for which the control signal VRM (inverted output signal XOUT), received from the control input area SW, indicates "H". This means that the output signal XOUT indicates "L" (second logic level).

[0097] It should be noted that the control protection elements 23S and 23Rthe induced voltage signals RX1 and RX2 without any modification to the input ranges of the buffer circuits 24S and 24R output in the following stage if the control signals VSM and VRM are set to "L".

[0098] Fig. Figure 11 shows a circuit diagram illustrating the internal structure of the control circuit. 26 represents. Fig. Figure 12 shows a waveform diagram illustrating waveforms during operation with respect to details of the control circuitry. 26 The control system is implemented. It should be noted that the arrangement of the components in Fig. 11 control circuit shown 26 This is merely one example and is not exhaustive.

[0099] As in Fig. As shown in 11, the control circuit 26 The following: two AND gates 261 and 262 and a NAND gate 263 An input signal I1 is fed to one input of the AND gate. 261and the one input of the NAND gate 263 An input signal I2 is fed into one input of the AND gate. 262 and the other input of the NAND gate 263 fed in. The other input of the AND gate 261 and the other input of the AND gate 262 receive an output signal from the NAND gate 263 .

[0100] As in Fig. Shown in 12, the control circuit prevents 26 The control circuit detects the occurrence of a state in which input signals I1 and I2 are simultaneously set to "H" and outputs signals O1 and O2 respectively, corresponding to the input signals I1 and I2. That is, the control circuit... 26 outputs the input signals I1 and I2 as the output signals O1 and O2 without any modification if at least one of the input signals I1 and I2 is set to "L", and sets the output signals O1 and O2 to "L" if both input signals I1 and I2 are set to "H".

[0101] In this way, the control circuit is invalidated. 26 When receiving the signals VS2 and VR2 (first and second logic set signals) as input signals I1 and I2, the display shows "H" for the signals VS2 and VR2 when both signals VS2 and VR2 are at "H" (active level) and outputs the "L" signals VS3 and VR3.

[0102] It should be noted that if at least one of the signals VS2 and VR2 is set to "L", the signals VS2 and VR2 will be output as the signals VS3 and VR3 without any change.

[0103] Fig. Figure 13 shows a circuit diagram illustrating the internal structure of a buffer circuit. 24 ( 24S and 24R ). It should be noted that the buffer circuit 24 a circuit arrangement that includes both the buffer circuit 24S as well as the buffer circuit 24R what they have in common. Furthermore, the arrangement of the buffer circuit 24 , which in Fig. Figure 13 is merely an example and is not exhaustive.

[0104] As in Fig. As shown in 13, the buffer circuit 24 The following: an NMOS transistor 241 , a resistance 242 and a capacitor 243 An input signal IN is applied to the gate of the NMOS transistor. 241 supplied. The drain of the NMOS transistor 241 is with the second end of the resistance 242 , and the source is connected to the reference potential VSS. The first end of the resistor 242 is set to the power supply potential VDD.

[0105] One electrode of the capacitor 243 is with the second end of the resistance 242 and the drain of the NMOS transistor 241 connected. The other electrode of the capacitor 243 is set to the reference potential VSS. A signal from one electrode of the capacitor 243The received signal is an output signal OUT.

[0106] The buffer circuit 24 The above arrangement is an amplifier that outputs the output signal OUT by inverting the input signal IN. Setting constants for the resistor 242 and the capacitor 243 will determine the time it takes for the output signal OUT to return to the power supply potential VDD. Operation of the signal transmission circuit 6

[0107] The overall operation of the signal transmission circuit 6 will next be discussed with reference to Fig. 3 described. As described above, the signal transmission circuit has 6 The following applies: the transformer 10 with the coil 110 and the coil 210 , the transformer 20 with the coil 120 and the coil 220 , the first circuit 100 , which is connected to the coil 110and the coil 120 is connected, and the second circuit 200 , which is connected to the coil 210 and the coil 220 is connected. The signal transmission circuit 6 transmits the input signal XIN, which is from the first circuit 100 is supplied when the induced voltage signals RX1 and RX2 are sent to the second circuit 200 via the transformer 10 and the transformer 20 and outputs the XOUT signal from the second circuit 200 out of.

[0108] Time t1 is the first transition time at which the pulse converter circuit 102 the first circuit 100 The input signal XIN changes from "L" to "H". The pulse converter circuit 102 transmits the "H" pulse transmission signal VS to the first end of the coil 110The output is triggered when the input signal XIN changes from "L" to "H". It should be noted that during the period from time t1 to time t2, when the input signal XIN is "H", the transmission signal VS is output. This VS is generated by ORing the signal obtained by detecting a rising edge of the input signal XIN and the oscillation signal CLK from the control circuit. 26 will be received.

[0109] If the transmission signal VS changes from "L" to "H" at time t1 as the starting point, a current change occurs in the coil. 110 on, and the induced voltage signal RX1, caused by the change in current, is applied to the first end of the coil. 210 Output. It is assumed that the induced voltage signal RX1 is sent to the control protection element. 23S is supplied and the control signal VSM (= output signal XOUT), which is supplied to the control input area SW of the control protection element. 23SThe voltage supplied is set to "L". In this case, the induced voltage signal RX1 is sent to the buffer circuit. 24S output in the subsequent stage without any change in state.

[0110] The induced voltage signal RX1, which is transmitted via the control protection element 23S into the buffer circuit 24S The input signal is output as VS1, an amplified inverted signal. The output signal VS1 from the buffer circuit 24S is connected to the Schmitt circuit 25S entered, and the waveform-like signal VS2 changes from "L" to "H".

[0111] The output signal VS2 from the Schmitt circuit 25S is connected to an input terminal I1 of the control circuit 26 entered. Since at this time the input signal VR2 is connected to an input terminal I2 of the control circuit 26 When "L" is selected, the output signal VS3 is taken from the output terminal O1 of the control circuit26 output in the same state as the input signal VS2. When the output signal VS3 is from the control circuit 26 (the input signal to the set input area S of the buffer circuit 27 When the input signal changes from "L" to "H", an output signal from the (non-inverting) output range Q of the buffer circuit also changes. 27 from "L" to "H" and is used as the output signal XOUT from the signal transmission circuit 6 issued.

[0112] In this case, the output signal is taken from the output range Q of the buffer circuit. 27 as the control signal VSM for the control protection element 23S fed to the control input area SW. When the control signal VSM changes from "L" to "H", the input terminal IN of the control protection element is... 23Sconnected to the reference potential VSS2. As a result, the induced voltage signal RX1 is set to the same potential as the reference potential VSS2 and is invalidated.

[0113] Since the state of the inverted output signal XOUT, as an output signal from the inverting output range QB of the buffer circuit 27 , on "H", it should be noted that in a period up to time t1 the input terminal IN of the control protection element 23R is connected to the reference potential VSS2 until the control signal VRM, which is connected to the control input area SW of the control protection element, is received. 23R is supplied, that is, an output signal from the inverting output range QB of the buffer circuit. 27 The voltage changes from "L" to "H". As a result, the induced voltage signal RX2 is set to the same potential as the reference potential VSS2 and is invalidated.

[0114] Time t2 is the second transition time, at which the signal enters the pulse converter circuit. 102 the first circuit 100 The input signal XIN changes from "H" to "L". When the input signal XIN changes from "H" to "L", the pulse converter circuit outputs 102 the "H" pulse transmission signal VR to the first end of the coil 120 It should be noted that in a period after time t2, for which the input signal XIN is at "L", the pulse converter circuit 102 outputs the transmission signal VR, which is generated by ORing the signal obtained by detecting a falling edge of the input signal XIN and the oscillation signal CLK from the oscillator. 38 will be received.

[0115] When the transmission signal VR changes from "L" to "H", a change in current occurs in the coil. 120on, and the induced voltage signal RX2, which is induced by the current change, is sent to the first end of the coil 220 Output. It is assumed that the induced voltage signal RX2 is fed into the control protection element. 23R is entered, and the VRM control signal, which is sent to the SW control input area of ​​the control protection element. 23R The voltage supplied is set to "L". In this case, the induced voltage signal RX2 is sent to the buffer circuit. 24R output in the subsequent stage without any change in state.

[0116] The induced voltage signal RX2, which is transmitted via the control protection element 23R into the buffer circuit 24R The input signal is output as VR1, an amplified inverted signal. The output signal VR1 from the buffer circuit 24R is connected to the Schmitt circuit 25RInput, and the waveform-like signal VR2 changes from "L" to "H". The output signal VR2 from the Schmitt circuit 25R is connected to input terminal I2 of the control circuit 26 entered. Since the input signal VS2 corresponds to the input terminal I1 of the control circuit 26 At this time, when the signal is on "L", the output signal VR3 is taken from the output terminal O2 of the control circuit. 26 output in the same state as the input signal VR2.

[0117] If the output signal VR3 differs from the control circuit 26 (the input signal to the reset input range R of the buffer circuit 27 When the value changes from "L" to "H", an output signal from the output range Q of the buffer circuit also changes. 27 from "H" to "L" and is considered the output signal XOUT from the signal transmission circuit 6 issued.

[0118] It is assumed that the inverted output signal XOUT, which is an output signal from the inverting output range QB of the buffer circuit, 27 is when the VRM control signal enters the SW control input area of ​​the control protection element. 23R When power is supplied, the VRM control signal changes from "L" to "H". In this case, the input terminal IN of the control protection element is... 23R connected to the reference potential VSS2, and the induced voltage signal RX2 is set to the same potential as the reference potential VSS2 and is invalidated.

[0119] In this way, the first circuit 100 in the signal transmission circuit 6 According to the first embodiment, a plurality of pulse signals (transmission signals VS and VR) are sent to the first end of the coil. 110 and the first end of the coil 120corresponding to a change in the logic value of the input signal XIN and the oscillation signal CLK from the oscillator. This allows the signal transmission circuit to 6 , even if the second circuit 200 If the signal is disrupted by noise, it can be quickly readjusted so that signals are transmitted with high reliability.

[0120] That means the first circuit 100 This enables the second circuit 200 , as the induced voltage signals RX1 and RX2 (first and second transformer output signals) reliably detect a change in the input signal XIN from "L" to "H" or from "H" to "L" when the transmission signals VS and VR are output, which change between "H" and "L" in periods of the oscillation signal CLK (first and second periods) in periods for which the input signal XIN is set to "H" and "L", in addition to the first and second transition times of the input signal XIN.

[0121] More precisely, even if the second circuit 200 If an "H" rising edge of the induced voltage signal RX1 is not detected at time t1 because the signal RX1 rises again at a rise edge time of the first pulse signal VS immediately after time t1 (for example, a rise edge time t1a based on the signal CLK), the second circuit 200 The output signal XOUT, which is almost normal, is displayed even if its pulse width is slightly shortened. Since in this case the output signal XOUT (control signal VSM) is held at "L" until time t1a, the control protection element is invalidated. 23S The induced voltage signal RX1 does not occur immediately after time t1a.

[0122] Furthermore, the induced voltage signals RX1 and RX2 are each connected to the buffer circuits. 24S and 24Rin the subsequent stages, while each is connected to the reference potential VSS, in order to use the control protection elements in first and second mask periods, which are unnecessary detection periods. 23S and 23R the second circuit 200 to be invalidated.

[0123] The induced voltage signal RX1 from the coil 210 and the induced voltage signal RX2 from the coil 220 are amplified and produced in a waveform using the buffer circuits 24S and 24R and the Schmitt circuits 25S and 25R designed to increase the "H" (active level) pulse widths of the VS2 and VR2 signals. These are input signals to the set input range S and the reset input range R of the buffer circuit. 27, compared to the "H" (active level) pulse widths of the induced voltage signals RX1 and RX2, so that signals are transmitted with high reliability.

[0124] That is, the first signal shaping circuit, which uses the buffer circuit 24S and the Schmitt circuit 25S is formed, and the second signal shaping circuit, which is formed by means of the buffer circuit 24R and the Schmitt circuit 25R The signals VS2 and VR2 (first and second logic set signals) are generated, indicating "H" (active level) in the first and second logic set periods, which exceed the periods for which the induced voltage signals RX1 and RX2 (first and second transformer output signals) indicate "H" (active level).

[0125] This enables the intermediate storage circuit 27, to function as an output signal generation circuit to generate the output signal XOUT, which reliably reflects the command contents of the signal VS2 (= VS3) and the signal VR2 (= VR3).

[0126] Furthermore, if using the control circuit 26 This prevents the set input area S and the reset input area R of the buffer circuit from 27 By simultaneously setting them to the ON state ("H" level), malfunctions and signal delays that would otherwise be caused by the simultaneous ON state can be prevented.

[0127] That means the control circuit 26 , which is a logic set-signal control circuit, invalidates the signals VS2 and VR2 when both signals VS2 and VR2 indicate "H" (active level), thus reliably avoiding a situation in which both signals VS2 and VR2 are set to "H" when the buffer circuit 27The output signal XOUT is generated. This makes it possible to improve the reliability of the output signal XOUT.

[0128] Furthermore, the control protection elements invalidate 23S and 23R (First and second control protection devices) the induced voltage signals RX1 and RX2 (first and second transformer output signals) in the first and second mask periods. This allows the reliability of the buffer circuit to be checked. 27 to improve the generated output signal XOUT by setting a period in the first mask period in which there is no need to detect whether the input signal XIN has changed to "H" (first logic level) and further by setting a period in the second mask period in which it is not necessary to detect whether the input signal XIN has changed in the control protection elements 23S and 23R has changed to "L" (second logic level).

[0129] More precisely, it is located in the control protection element. 23S A period in which the output signal XOUT has already indicated "H" (first logic level) is set as the first mask period, thus improving the reliability of "H" of the output signal XOUT, which is provided by the buffer circuit. 27 is generated.

[0130] Similarly, the control protection element 23R A period in which the output signal XOUT has already indicated "L" (second logic level) is set as the second mask period, thus improving the reliability of "L" of the output signal XOUT, which is processed by the buffer circuit. 27 is generated.

[0131] Accordingly, the signal transmission circuit 6According to the first embodiment, the output signal XOUT accurately reflects the input signal XIN and can therefore transmit signals with high reliability.

[0132] Furthermore, as in Fig. As shown in 2, the energy converter device 60 the signal transmission circuit 6 according to the first embodiment, in order to better suppress noise during signal transmission when the control 4 the control signal S4 to the driver unit 3 This transmits the signal in a way that improves reliability and avoids malfunctions and signal delays. This enables long-term use of the energy converter device. 60 . Design 2

[0133] Fig. Figure 14 shows a block diagram representing an arrangement in which a first aspect of an energy converter device according to a second embodiment of the present invention is used in motor control. Fig. Figure 14 shows the arrangement of an energy converter device 61 with the signal transmission circuit 6 according to the first embodiment described above.

[0134] As in Fig. As shown in 14, the energy converter device 61 , which are used to control an engine 1 intended for use in a hybrid vehicle, electric vehicle or the like, the following applies: a power module unit 81 , which are achieved by integrating one or more power semiconductor switching elements 2 ( Fig. Figure 14 shows a power semiconductor switching element 2 ) and a driver unit 3 obtained through resin sealing, a control 4, which provides a control signal S4 for the driver unit 3 generated to power the driver unit 3 to cause the power semiconductor switching element 2 to control, and a signal transmission circuit 6 , which receives the control signal S4 from the controller 4 to the driver unit 3 transfers.

[0135] The signal transmission circuit 6 is between the control 4 and the driver unit 3 trained. The signal transmission circuit 6 isolates the control 4 of devices that are to be controlled by high voltages, such as the driver unit 3 , the power semiconductor switching element 2 and the engine 1 Furthermore, it receives the control signal S4 from the controller. 4 It outputs the signal as an input signal XIN and outputs it as an output signal XOUT.

[0136] The energy converter device61 According to the second embodiment, the following is featured: the signal transmission circuit 6 , which improves the precision of signal transmission and promotes the prevention of malfunctions and signal delays, and the power module single unit 81 , which are caused by the power semiconductor switching element 2 and the driver unit 3 This can improve the precision of signal transmission through the energy converter device. 61 This improves performance and helps prevent malfunctions and signal delays. In turn, this enables the long-term use of the energy converter device. 61 .

[0137] Fig. Figure 15 shows a block diagram representing an arrangement in which a second aspect of the energy converter device according to the second embodiment of the present invention is applied to the motor control. As shown in Fig. As shown in 15, it is also possible to use an energy converter device. 62 to use a power module single unit 82 features, which are achieved by integrating the signal transmission circuit 6 together with the power semiconductor switching element 2 and the driver unit 3 obtained by resin sealing. This makes it possible to achieve the same effects as those of the first aspect of the invention.

[0138] Fig. Figure 16 shows a block diagram representing an arrangement in which a third aspect of the energy converter device according to the second embodiment of the present invention is applied to the motor control. As in Fig. As shown in 16, a power module single unit can be 83 , which are achieved by integrating the control system 4 together with the power semiconductor switching element 2 , the driver unit 3 and the signal transmission circuit6 obtained by resin sealing, even an energy converter device 63 be, which can achieve the same effects as those of the first aspect of the invention. embodiment 3

[0139] Fig. Figure 17 shows a block diagram representing an arrangement according to a first aspect, in which an energy converter device according to a third embodiment of the present invention is used in the motor control. An energy converter device is described below as an example. 71 explains which signal transmission circuit 6 according to the first embodiment described above.

[0140] As in Fig. As shown in 17, the energy converter device 71 , which are used to control an engine 1 intended for use in a hybrid vehicle, an electric vehicle or the like, the following applies: a power module unit84 , which are achieved by integrating one or more power semiconductor switching elements 2 , a driver unit 3 and an anomaly detector 5 obtained through resin sealing, a control 4 , which provides a control signal S4 for the driver unit 3 generated to power the driver unit 3 to cause the power semiconductor switching element 2 to control a signal transmission circuit 6A (first signal transmission circuit), which transmits the control signal S4 from the controller 4 to the driver unit 3 transmits, and a signal transmission circuit 6B (second signal transmission circuit), which is connected to the anomaly detector 5 detected anomaly detection signal S5 to the controller 4 transfers.

[0141] The anomaly detector 5is an existing component element that represents a short-circuit state or a heated state of the power semiconductor switching element 2 or a drop in the power supply voltage of the driver unit 3 detected and then outputs the anomaly detection signal S5, which indicates a corresponding anomaly state, in order to provide protection against the short-circuit state or the heated state of the power semiconductor switching element. 2 or a drop in the power supply voltage of the driver unit 3 to enable.

[0142] The signal transmission circuit 6A and the signal transmission circuit 6B Each exhibits an arrangement with a function that is essentially the same as that of the signal transmission circuit. 6 according to the first embodiment.

[0143] The signal transmission circuit 6A is between the control 4and the driver unit 3 provided. The signal transmission circuit 6A isolates the control 4 of devices that are to be controlled by high voltages, such as the driver unit 3 , the power semiconductor switching element 2 , the engine 1 and the anomaly detector 5 Furthermore, it receives the control signal S4 from the controller. 4 as an input signal XIN1 and outputs the signal as an output signal XOUT1.

[0144] The signal transmission circuit 6B is between the control 4 and the anomaly detector 5 provided. The signal transmission circuit 6B isolates the control 4 of devices that are to be controlled by high voltages, such as the driver unit 3 , the power semiconductor switching element 2 , the engine 1 and the anomaly detector 5The signal transmission circuit 6B XIN2 receives the anomaly detection signal S5 as an input signal, which is from the anomaly detector. 5 is output, which detects an anomalous operation such as a voltage drop in the supply voltage, an overcurrent or an increased temperature in the power module unit 84 has occurred, which was caused by the driver unit 3 , the power semiconductor switching element 2 and the like, and outputs the detection signal as an output signal XOUT2.

[0145] The energy converter device 71 According to the third embodiment, the following features are present: the signal transmission circuits 6A and 6B (first and second signal transmission circuits) that improve the precision of signal transmission and promote the prevention of malfunctions and signal delays, and the power module single unit 84, which are achieved by integrating the power semiconductor switching element 2 , the driver unit 3 and the anomaly detector 5 This can improve the precision of signal transmission through the energy converter device. 71 This improves performance and helps prevent malfunctions and signal delays. In turn, this enables long-term use of the energy converter device. 71 with an anomaly detection function using the anomaly detector 5 .

[0146] Fig. Figure 18 shows a block diagram illustrating an arrangement in which a second aspect of the energy converter device according to the third embodiment of the present invention is used in motor control. As shown in Fig. As shown in 18, it is also possible to use an energy converter device. 72 to use a power module single unit 85features, which are achieved by integrating the signal transmission circuit 6A and the signal transmission circuit 6B together with the power semiconductor switching element 2 , the driver unit 3 and the anomaly detector 5 is obtained through resin sealing. This makes it possible to achieve the same effects as those of the first aspect of the invention.

[0147] Fig. Figure 19 shows a block diagram representing an arrangement in which a third aspect of the energy converter device according to the third embodiment of the present invention is used in motor control. As shown in Fig. As shown in 19, a power module single unit can 86 , which are achieved by integrating the control system 4 together with the power semiconductor switching element 2 , the driver unit 3 , the anomaly detector 5 , the signal transmission circuit 6Aand the signal transmission circuit is preserved by resin sealing, even an energy conversion device 73 be, which can achieve the same effects as those of the first aspect of the invention.

[0148] It should be noted that the respective embodiments of the present invention can be freely combined within the scope of the invention, and each embodiment can be modified as needed or features can be omitted.

[0149] Although the present invention has been described in detail above, the above description is in all aspects only exemplary and the invention is not limited thereto. It should be clear that numerous modifications, not specifically illustrated, are conceivable without deviating from the scope of the present invention. Reference symbol list 1 engine 2 Power semiconductor switching element 3 driver unit 4 Control 5 Anomaly Detector 6 Signal transmission circuit 6A, 6B Signal transmission circuit 10, 20 transformer 23S, 23R Control Protection Element 24S, 24R buffer circuit 25S, 25R Schmitt circuit 26 Control circuit 27 Intermediate storage circuit 60–63 Energy converter device 71–73 Energy converter device 81–86 Power module 100 first circuit 102 Pulse converter circuit 200 second circuit

Claims

[1] Signal transmission circuit comprising the following: – a first circuit ( 100 ), which is configured to output first and second transmission signals (VS, VR) based on an external input signal (XIN); – first and second transformers ( 10 , 20 ), which are configured to receive the first and second transmission signals on a primary side and to generate first and second transformer output signals (RX1, RX2) on a secondary side; and – a second circuit ( 200 ), which is configured to generate an external output signal (XOUT) based on the first and second transformer output signals, wherein the external input signal has first and second logic levels, changes from the second logic level to the first logic level at a first transition time and changes from the first logic level to the second logic level at a second transition time, wherein the first circuit outputs the first and second transmission signals such that the first transmission signal changes between the first and second logic levels in a first period when the external input signal is at the first logic level, and such that it is fixed at the second logic level when the external input signal is at the second logic level, and is set to the first logic level for a predetermined period during the first transition time of the external input signal, and such that the second transmission signal changes between the first and second logic levels in a second period when the external input signal is at the second logic level, and such that it is fixed at the second logic level when the external input signal is at the first logic level, and is set to the first logic level for a predetermined period at the second transition time of the external input signal, and the second circuit features: – first and second control protection devices ( 23S , 23R ), which are configured to invalidate the first and second transformer output signals for first and second mask periods based on the first or second logic level of the external output signal, – a first signal shaping circuit ( 24S , 25S ), which is configured to receive the first transformer output signal via the first control protection device and to generate a first logic set signal (VS2) indicating an active level for a first logic set period that exceeds a period for which the first transformer output signal indicates an active level, – a second signal shaping circuit ( 24R , 25R), which is configured to receive the second transformer output signal via the second control protection device and to generate a second logic set signal (VR2) indicating an active level for a second logic set period that exceeds a period for which the second transformer output signal indicates an active level, – a logic set signal control circuit ( 26 ), which is configured to receive the first and second logic set signals and to invalidate the indication of an active level by the first and second logic set signals if both the first and second logic set signals indicate an active level, and – an output signal generation circuit ( 27), which is configured to receive the first and second logic set signals via the logic set signal control circuit and to generate the external output signal, which is set to one logic level of the first and second logic levels when the first logic set signal indicates an active level, and which is set to the other logic level when the second logic set signal indicates an active level. [2] Signal transmission circuit according to claim 1, wherein the first control protection device specifies as the first mask period a period for which the external output signal indicates the first logic level, and where the second control protection device specifies a period as the second mask period for which the external output signal indicates the second logic level. [3] Energy conversion device comprising the following: – a power semiconductor switching element ( 2 ); – a driver circuit (3 ), which is configured to drive the power semiconductor switching element; – a control system ( 4 ), which is configured to generate a control signal (S4) to cause the driver circuit to drive the power semiconductor switching element; and – a signal transmission circuit ( 6 ) according to claim 1 or 2, wherein the signal transmission circuit is formed between the controller and the driver circuit, the controller is isolated from the driver circuit, receives the control signal from the controller as the external input signal and outputs the external output signal to the driver circuit. [4] Energy converter device according to claim 3, wherein the driver circuit and the power semiconductor switching element are integrally integrated in a single power module unit ( 81 – 83 are trained. [5] Energy converter device according to claim 4, wherein the signal transmission circuit is further integrally integrated into the power module ( 82 , 83 ) is trained. [6] Energy converter device according to claim 5, wherein the control is further integrally integrated into the power module ( 83 ) is trained. [7] Energy conversion device comprising the following: – a power semiconductor switching element ( 2 ); a driver circuit ( 3 ), which is configured to drive the power semiconductor switching element; – a control system ( 4 ), which is configured to generate a control signal (S4) to cause the driver circuit to drive the power semiconductor switching element; and – an anomaly detector ( 5), which is configured to detect an anomalous condition caused in the power semiconductor switching element or driver circuit and outputs an anomaly detection signal (S5); and – first and second signal transmission circuits ( 6A , 6B ), wherein the first and the second signal transmission circuit each comprise a signal transmission circuit according to claim 1 or 2, wherein the first signal transmission circuit is formed between the controller and the driver circuit, the controller is isolated from the driver circuit, receives the control signal from the controller as the external input signal (XIN1) and outputs the external output signal (XOUT1) to the driver circuit and wherein the second signal transmission circuit is formed between the controller and the anomaly detector, the controller is isolated from the anomaly detector, receives the anomaly detection signal from the anomaly detector as the external input signal (XIN2) and outputs the external output signal (XOUT2) to the controller. [8] Energy converter device according to claim 7, wherein the driver circuit, the power semiconductor switching element and the anomaly detector are integrally integrated in a single power module unit ( 84 – 86 are trained. [9] Energy converter device according to claim 8, wherein the first and the second signal transmission circuit are integrally integrated into the power module ( 85 , 86 are trained. [10] Energy converter device according to claim 9, wherein the control is integral in the power module ( 86 ) is trained.