Design structure for reducing the pre-charge voltage for arrays of static random access memories.

Abstract

Memory cell arrangement consisting of Static-Random-Access-Memory (SRAM) cells, which includes: one or more groups of SRAM cells (106), wherein each of the one or more groups of SRAM cells (106) contains two or more SRAM cells (106) which are connected by at least one common local bit line (108) to an input of a local read amplifier (104), and wherein outputs of the local read amplifiers (104) are connected to a shared global bit line (102), wherein the shared global bit line (102) is connected to a pre-charge circuit configured to pre-charge the shared global bit line (102) prior to reading data with a programmable pre-charge voltage, wherein the pre-charge circuit includes a limiter circuit comprising: a pre-charge regulator circuit (202) connected to the shared global bit line (102) for pre-charging the shared global bit line (102) with the programmable pre-charge voltage; and an evaluation and translation circuit (204) which is connected to the pre-charge control circuit (202) and the shared global bit line (102) for compensating leakage current of the shared global bit line (102) without changing a voltage value of the bit line, wherein the pre-charge control circuit (202) comprises: a first p-FET (P1) whose source terminal is connected to a supply voltage (110) and whose drain terminal is connected to a first terminal of a pre-charge switch (206), the second terminal of which is connected to the shared global bit line (102); and a first n-FET (N1) whose source terminal is connected to the first terminal of the pre-charge switch (206), wherein a drain terminal of the first n-FET (N1) is connected to a gate terminal of the first p-FET (P1) and to a first terminal of a first programmable resistor (208) whose second terminal is connected to the supply voltage (110), where one gate terminal of the first n-FET (N1) is connected to a signal reference voltage (Vref), the evaluation and translation circuit (204) includes: a second n-FET (N2), whose source terminal is connected to the shared global bit line (102) and whose drain terminal is connected to a first terminal of a second programmable resistor (210), whose second terminal is connected to the supply voltage (110), where one gate terminal of the second n-FET (N2) is connected to the signal Vref, and wherein an output terminal (212) of a global bit line (102) is connected to the drain terminal of the second n-FET (N2).

Description

BACKGROUND

[0001] The invention relates generally to a read precharge value of SRAM cells and, more particularly, to memory cell arrays of groups of SRAM cells. The invention further relates to a corresponding structure.

[0002] SRAM cells are often arranged in a domino logic structure, in which two or more SRAM cells (static random access memory cells) are connected in parallel with local bit lines. An amplifier between local bit lines and a shared global bit line are used to decouple the local bit lines from the global bit line. Typically, both the local and global bit lines can be precharged to a high voltage before a read operation and can be discharged to ground, or pulled down, during a read operation. This can enable a higher read rate than directly sensing the state of the global bit line. A specific cell can be selected for reading by activating the cell's word line.If the discharged local bit line is the one connected to the global bit line, discharging the local bit line can activate a logic element that discharges the local bit line.

[0003] By using this mechanism to detect the state of an SRAM cell, it may not be necessary to precharge a local bitline and / or a global bitline to the full magnitude of Vdd (also known as the supply voltage). In other words, full-scale precharging is not required.

[0004] Other documents have addressed this area. For example, US Patent No. 8,947,970 B2 discloses "a memory device comprising a plurality of bit cells of a static random access memory (SRAM) and a word line driver coupled to provide a word line signal to the bit cells. The word line driver receives a global word line signal that remains active while the word line signal is enabled and is subsequently disabled."

[0005] US patent application 2010 / 0296354-A1 discloses a static random access memory including "a memory cell connected to a pair of bit lines and supplied with the supply voltage from a first power supply, a precharge circuit connected to the pair of bit lines, ... and a voltage reduction circuit connected between the precharge circuit and the first power supply."

[0006] However, one problem concerning the global bit line remains. The global bit lines represent an intrinsic capacitance. Since a majority of the aforementioned amplifiers can be connected to the global bit line, the global bit line requires a lot of power during a read operation of the SRAM cells. Since the SRAM cell can be precharged in an initial phase of a read operation and discharged in an evaluation phase, depending on the contents of the SRAM cells, approximately 50% of the global bit lines are charged and / or discharged in each memory cycle. Energy equal to the product of the operating frequency, the effective capacitance of the global bit lines, the supply voltage (Vdd), and the precharge voltage may be required. This can contribute significantly to the power consumption of an SRAM array.Because SRAM cells are often used as Level 1 or Level 2 cache memory in processors, the power consumption of these RAM arrays can contribute significantly to the power consumption of the processor.

[0007] The following documents also address similar tasks: Document US 2011 / 0 280 088 A1 describes that a reduced bitline precharge level increases the SRAM beta ratio and thus improves the stabilization range. The precharge level is also supplied to a sensor amplifier, a write driver, and source voltages for control signals. Document US 2003 / 0 156 47 8 A1 describes a non-volatile dynamic semiconductor memory device with a sensor device that uses a differential sensor amplifier circuit. A memory cell is connected to a bitline using a wordline, and a reference memory cell is connected to an anti-bitline using a reference wordline. The potential difference between the bitline and the anti-bitline is amplified by the sensor amplifier.Furthermore, document US 2014 / 0 126 273 A1 describes a domino SRAM memory with one or more SRAM memory cells connected to a local bitline. The SRAM may include a precharge device provided between a supply voltage and the local bitline. Furthermore, a global bitline (GBL) discharge logic may be provided between a local bitline and a GBL. However, the approaches described therein do not solve the problem outlined above.

[0008] Therefore, there is a need to reduce the amount of energy required to precharge the global bit lines in the first phase of a read operation. SUMMARY

[0009] This need is addressed by a memory cell arrangement of groups of static random access memory (SRAM) cells according to the independent claims. Further embodiments are described by the dependent claims.

[0010] The proposed memory cell arrangement of groups of SRAM cells can offer numerous advantages and technical effects: The proposed memory cell arrangement of groups of SRAM cells is not dependent on a specific SRAM cell structure. For example, six-transistor 1-bit SRAM cells can be used, as can eight-transistor 1-bit SRAM cells. Field-effect transistors (FETs) can typically be used. These can be p-type FETs or n-type FETs, or a combination of both. The inventive concept can also be applied to bipolar SRAM cells. The precharge value of the shared global bit line does not have to depend on a switching threshold of a CMOS inverter and therefore does not have to be fixed, but can be programmable depending on environmental parameters, for example, the supply voltage, the chip temperature, or the operating frequency. Thus, the precharge value can remain constant even if the supply voltage changes.Thus, the precharge value of the shared global bitline can depend solely on a reference voltage Vref, allowing a lower precharge value even if the supply voltage increases. This can result in even greater power savings.

[0011] Furthermore, no historical effects need to be considered, since the shared global bitline acts as the keeper section of the evaluation and translation circuits, maintaining the precharge value. Furthermore, the precharge value can be controlled independently for each shared global bitline. The global bitlines can be reference-based global bitlines.

[0012] As a result of decoupling the precharge circuit and the SRAM cells, there are no dependencies on the characteristics of the SRAM cell.

[0013] It should also be noted that the precharge value of the global bitline can be lower than the supply voltage minus a threshold, for example, of a CMOS inverter, and in particular, can be less than half of Vdd. An obvious effect is that more power can be saved during operation than with known technologies.

[0014] Additional embodiments of the memory cell arrangement of groups of SRAM cells are described below.

[0015] According to a preferred embodiment of the memory cell arrangement of groups of SRAM cells, the programmable precharge voltage is less than half the value of a supply voltage Vdd. This has the advantage of a greater energy saving effect if the precharge value of the shared bitline can be reduced to half of Vdd in technological terms. The lower the precharge value of the global bitline can be during stable operation, the more energy can be saved. One skilled in the art will recognize that every additional milliwatt of saved energy serves to make SRAM cells more effective in SRAM chips or as part of processors.

[0016] According to a further preferred embodiment of the memory cell arrangement of groups with SRAM cells, the precharge regulator circuit can comprise a first p-FET, which is connected by its source terminal to the supply voltage Vdd and by its drain terminal to a first connection point of a precharge switch. This precharge switch can be connected at its second connection point to the shared global bit line. A first n-FET can be connected at its source terminal to the first connection point of the precharge switch, wherein a drain terminal of the first n-FET can be connected to a gate terminal of the first p-FET and to a first connection point of a first programmable resistor, which is connected at its second connection point to the supply voltage Vdd. A gate terminal of the first n-FET can be connected to a voltage signal Vref.

[0017] Note that the first resistor can be interpreted as an equivalent circuit for a transistor or FET with a preset voltage connected to its gate terminal. It can thus be considered a programmable resistor.

[0018] It should also be noted that the voltage Vref can define the value with which the shared global bit line can be precharged before a second part of a read cycle of an SRAM cell activated, for example, by the associated word line.

[0019] According to another preferred embodiment of the memory cell arrangement of groups of SRAM cells, the evaluation and translation circuit may comprise a second n-FET, which may be connected by its source terminal to the shared global bit line and by its drain terminal to a first terminal of a second programmable resistor, which may be connected by its second terminal to the supply voltage Vdd. A gate terminal of the second n-FET may be connected to the signal Vref, and an output terminal of the global bit line may be connected to the drain terminal of the second n-FET.

[0020] Similar to the first resistor, the second resistor can be considered an equivalent circuit for a transistor or FET with a preset voltage connected to its gate terminal. It can thus be considered a programmable resistor.

[0021] According to an additional embodiment of the memory cell arrangement of groups of SRAM cells, the signal Vref can be configured to control a precharge value of the shared global bit line. Thus, the precharge value can be controlled independently of the supply voltage. The precharge value of the shared global bit line can be controlled independently, allowing the lowest possible precharge value to be used, thereby ensuring stable operation of the SRAM cell read operation.

[0022] According to an advantageous embodiment of the memory cell arrangement of groups with SRAM cells, the precharge regulator circuit can comprise a second p-FET, the drain terminal of which is connected to the shared global bit line and the source terminal to the supply voltage. A gate terminal of the second p-FET can be connected to a drain terminal of a third p-FET transistor, the source terminal of which can be connected to the supply voltage Vdd. A drain terminal of a fourth p-FET can also be connected to the gate terminal of the second p-FET, the source terminal of which can be connected to the supply voltage Vdd. A third p-FET can also be connected by its drain terminal to the gate terminal of the second p-FET and by its source terminal to a drain terminal of a fourth n-FET, the source terminal of which can be connected to the shared global bit line.

[0023] A gate terminal of the fourth n-FET and a gate terminal of the third p-FET may be commonly connected to a precharge line GPCHG of a global bit line. A gate terminal of the third n-FET may be connected to a Vref line, and the gate terminal of the fourth p-FET may be connected to a Vbias-p line.

[0024] The precharge regulator circuit is active during a high voltage phase of GPCHG and inactive during a low voltage phase of GPCHG. When the precharge regulator circuit is active, the sixth p-FET is controlled such that the more the voltage value of the global bitline deviates from the precharge value set using the reference voltage Vref, the more current the sixth p-FET supplies to the global bitline. When the programmed precharge value is reached, the current driving capability of the sixth p-FET is greatly reduced. In this state, the sixth p-FET will only compensate for the leakage current of the shared global bitline to keep the precharge value constant. When the precharge regulator circuit is inactive, the sixth p-FET is turned off.

[0025] According to a feasible embodiment of the memory cell arrangement of groups of SRAM cells, a drain terminal of a fifth n-FET may be connected to the shared global bitline, with its source terminal connected to ground. A gate terminal of the fifth n-FET may be connected to a voltage signal Vbias-n, which maintains the precharge regulator circuit and the evaluation and translation circuit in stable operating conditions. This circuit can ensure a stable charge value of the shared global bitline even when there are no or only weak leakage currents.

[0026] According to an additional embodiment of the memory cell arrangement of groups with SRAM cells, the evaluation and translation circuit may comprise a sixth n-FET having its source terminal connected to the shared global bitline and its drain terminal connected to the output of the global bitline. A fifth p-FET may have its drain terminal connected to the output terminal of the global bitline and its source terminal connected to the supply voltage Vdd. A sixth p-FET may have its source terminal connected to the supply voltage Vdd and its drain terminal connected to a source terminal of a seventh p-FET having its drain terminal connected to the output terminal of the global bitline.

[0027] Furthermore, a gate terminal of the seventh p-FET may be connected to a drain terminal of an eighth p-FET, which has its source terminal connected to the supply voltage Vdd. The gate terminal of the seventh p-FET may also be connected to a drain terminal of a seventh n-FET, which has its source terminal connected to ground.

[0028] In this embodiment, the signal Vref may be connected to a gate terminal of the sixth n-FET, the signal Vbias-p may be connected to a gate terminal of the sixth p-FET, and an inverted signal of the global bit line precharge signal GPCHGN may be connected to a gate terminal of the fifth p-FET.

[0029] This embodiment can be considered a first implementation of the evaluation and translation circuit. The sixth n-FET can decouple the shared global bit line, which has a high capacitance, and the output line of the global bit line, which has a low capacitance compared to the shared global bit line.

[0030] The seventh p-FET, the eighth p-FET, and the seventh n-FET can be considered as a feedback circuit that interrupts the path from Vdd through the sixth and seventh p-FETs to an output (terminal) of a global bitline to prevent cross-current from Vdd to the pull-down unit when a sense amplifier attempts to discharge the shared global bitline, thus saving power and speeding up the evaluation phase.

[0031] The sixth n-FET, whose source terminal is connected to the shared global bitline and whose drain terminal is connected to the global bitline output terminal, can achieve decoupling between the shared global bitline and the global bitline output terminal. This allows a much lower precharge value to be allowed at the shared global bitline than is evident at the global bitline output terminal. The evaluation and translation circuit can enable the translation of the precharge value.

[0032] According to another embodiment of the memory cell arrangement of groups of SRAM cells, the evaluation and translation circuit may comprise an eighth n-FET whose source terminal is connected to the shared global bit line and whose drain terminal is connected to a source terminal of a ninth n-FET, whose source terminal may be connected to the supply voltage Vdd. The source terminal of a tenth p-FET may be connected to the supply voltage Vdd, and its drain terminal may be connected to the drain terminal of the ninth p-FET. The source terminal of an eleventh p-FET may be connected to the supply voltage Vdd, and its gate terminal may be connected to the drain terminal of the ninth n-FET.

[0033] A drain terminal of the eleventh p-FET may be connected to the output terminal of the global bit line, a drain terminal of a tenth n-FET and a drain terminal of an eleventh n-FET may be connected to the output terminal of the global bit line, and a source terminal of the tenth n-FET and a source terminal of the eleventh n-FET may be connected to ground Vss.

[0034] The signal Vref may be connected to a gate terminal of the ninth n-FET, the signal Vbias-p may be connected to a gate terminal of the ninth p-FET, an inverted signal of the global bitline precharge signal GPCHGN may be connected to a gate terminal of the tenth p-FET, and the global bitline precharge signal GPCHG may be connected to a gate terminal of the tenth n-FET, wherein the signal Vbias-n may be connected to a gate terminal of the eleventh n-FET.

[0035] This embodiment may represent a second alternative implementation of the evaluation and translation circuit. It may be faster than the first embodiment of the evaluation and translation circuit (discussed above). The first embodiment may conserve more power and be less complex.

[0036] According to a further embodiment of the memory cell arrangement of groups of SRAM cells, the evaluation and translation circuit may comprise a twelfth n-FET, the source terminal of which may be connected to the shared global bit line and the drain terminal of which may be connected to a source terminal of a thirteenth n-FET; wherein the drain terminal of this thirteenth n-FET may be connected to a twelfth p-FET, the source terminal of which may be connected to the supply voltage Vdd.

[0037] The source terminal of a thirteenth p-FET may be connected to the supply voltage Vdd, and its drain terminal to the drain terminal of the twelfth p-FET. The source terminal of a fourteenth p-FET may be connected to the supply voltage Vdd, and its gate terminal to the drain terminal of the thirteenth n-FET. The drain terminal of a fourteenth n-FET may be connected to a drain terminal of the fourteenth p-FET, and its source terminal to a drain terminal of a fifteenth n-FET whose source terminal is connected to ground.

[0038] An inverter whose input is connected to the drain terminal of the fourteenth FET and whose output is connected to the output terminal of the global bitline may also be part of this embodiment. Furthermore, the source terminal of a fifteenth p-FET may be connected to the supply voltage Vdd, and its drain terminal may be connected to the drain terminal of the fourteenth p-FET, whose gate terminal is connected to the output terminal of the global bitline. A gate terminal of the fourteenth n-FET may also be connected to the output terminal of the global bitline.

[0039] The signal Vref may be connected to a gate terminal of the thirteenth n-FET, the signal Vbias-p may be connected to a gate terminal of the twelfth p-FET, an inverted signal of the global bitline precharge signal GPCHGN may be connected to a gate terminal of the thirteenth p-FET, the global bitline precharge signal GPCHG may be connected to a gate terminal of the sixteenth n-FET, and the signal Vbias-n may be connected to a gate terminal of the fifteenth n-FET.

[0040] This embodiment may represent a third alternative for the evaluation and translation circuit. It may represent a good compromise between the first and second implementations, as its operating speed lies between the first and second implementations of the evaluation and translation circuit, as explained above. On the other hand, it can save more power than the second implementation of the evaluation and translation circuit. Therefore, a developer may have a choice between different options of the same basic principle: reducing the precharge value of the shared global bitline as much as possible in a given environment.

[0041] According to a further optional embodiment of the memory cell array of groups of SRAM cells, at least one element of the group comprising the reference voltage Vref, the signal Vbias-n, or the signal Vbias-p can be controlled by a process voltage-temperature circuit that reflects the actual operating parameters. This can have the advantage that the actual operating parameters can be used to operate the memory cell array of SRAM cells at an operating point with defined low power consumption.

[0042] According to a feasible embodiment of the structure, the structure may include a netlist that can describe the memory cell arrangement of groups of SRAM cells. This netlist may be required for automated production systems for the memory cell arrangement of SRAM cells.

[0043] And according to another feasible embodiment of the body structure, the body structure may include at least one set of test data, identification data, verification data, or design specifications. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The drawings included in this disclosure are incorporated in and constitute a part of the specification. They illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure. The drawings are merely illustrative of typical embodiments and do not limit the disclosure. Fig. 1 illustrates an example of SRAM cells connected to a shared global bitline, according to embodiments of the present disclosure. Fig. 2 illustrates a basic embodiment of the inventive memory cell arrangement of groups with SRAM cells according to embodiments of the present disclosure. Fig. 3 illustrates an embodiment of the inventive precharge regulator according to embodiments of the present disclosure Fig. Figure 4 illustrates a first implementation of the evaluation and translation circuit of the general layout of the evaluation and translation circuit of Fig. 2 according to embodiments of the present disclosure. Fig. Figure 5 illustrates a second implementation of the evaluation and translation circuit of the general layout of the evaluation and translation circuit of Fig. 2 according to embodiments of the present disclosure. Fig. Figure 6 illustrates a third implementation of the evaluation and translation circuit of the general layout of the evaluation and translation circuit of Fig. 2 according to embodiments of the present disclosure. Fig. 7 illustrates a flowchart of an implementation process used in semiconductor design, manufacturing, and / or testing, according to embodiments of the present disclosure.

[0045] While the embodiments described herein are susceptible to numerous modifications and alternative forms, the drawings have shown the details thereof by way of example and will be described in detail. It should be understood, however, that the specific embodiments described should not be used in a limiting sense. On the contrary, the invention is intended to cover all modifications, substitutions, and alternatives that fall within the spirit and scope of the invention. DETAILED DESCRIPTION

[0046] In the context of this description, the following conventions, terms and / or expressions may be used: The term 'group of multiple SRAM cells' may refer to a plurality of static random access memory (SRAM) cells connected to a common output line, also known as a local bit line. The local bit line may be shared by a plurality of SRAM cells and may be connected to an input of a local bit line amplifier.

[0047] The term 'local sense amplifier' may refer to the above-mentioned local bit line amplifier, which may be positioned between a common local bit line and a global bit line.

[0048] The term 'local bit line' may refer to the common output line for a plurality of SRAM cells that connects the plurality of SRAM cells to a local sense amplifier.

[0049] The term 'global bitline' or 'shared global bitline' can refer to a line connected to a plurality of sense amplifiers or local sense amplifiers. A characteristic of the global bitline can be its relatively large parasitic capacitance due to its size and the relatively large number of local sense amplifiers connected to it.

[0050] The term 'precharge circuit' may refer to a circuit comprising a plurality of electronic components for precharging a bit line of any type prior to a read cycle of an SRAM that is directly or indirectly connected to the global bit line. In a first phase of a read cycle, the global bit line may be precharged and, if necessary, discharged during a second phase of a read cycle depending on the logical value of the bit read from the SRAM cell. Further details will be described with reference to Fig. 1 explained.

[0051] The term 'precharge regulator circuit' may refer to a circuit comprising a plurality of electronic components arranged and interconnected to ensure precharging of the global bit line before or during a first phase of a read operation may occur.

[0052] The term 'evaluation and translation circuitry' may refer to a plurality of electronic components arranged and interconnected to ensure recognition of the bit stored in a selected SRAM cell, even when the precharge is below a full scale precharge value. An additional task of the evaluation and translation circuitry may also be to translate the relatively low precharge value on the global bitline into stable and recognizable values ​​and signals for downstream electronic components.

[0053] The term 'programmable precharge voltage' can refer to a voltage that can be set to a specific predefined and / or self-adjustable value. For example, the global bitline can be precharged before reading with the programmable precharge voltage. The term 'netlist' can refer to the connectivity of an electronic implementation. A single netlist can be a list of all component terminals that should be electrically connected for the circuit to function. Netlists typically convey connectivity information and provide nothing more than instances, nets, and possibly some attributes.

[0054] A detailed description of the figures follows. All instructions in the figures are schematic. First, a representation of groups of SRAM cells connected to a local bit line and a global bit line is shown. Various alternative embodiments of the inventive memory cell arrangement of groups of SRAM cells are described below.

[0055] Fig. 1 shows an example of SRAM cells connected to a shared global bitline. All SRAM cells 106 may be connected in groups to a common local bitline LBL 108. The local bitlines 108 may each be connected to a corresponding local sense amplifier 104. The output of the local sense amplifier 104 may be connected to a shared global bitline 102. It will be clear to one skilled in the art that the parasitic capacitance 116 of a reference-referenced global bitline 102 should not be underestimated, especially when a large number of local sense amplifiers 104 are connected to the shared global bitline.

[0056] An additional p-FET P0 may act as a precharge circuit together with a guard / leakage current compensation circuit 118. The additional p-FET P0 may be connected to a supply voltage Vdd 110. When an inverted precharge signal GPCHGN of the global bit line is connected to the gate terminal of P0, the voltage of the global bit line may exhibit, particularly during a transition from "1" to "0" 112a, a transition 114 when performing a "0" read operation and a transition 117 when performing a "1" read operation. It should be understood that simultaneous switching of a plurality of such instances as in Fig. 1 may generate enormous transient current peaks and may require a comparatively high average AC power.

[0057] Fig. 2 shows an embodiment of the inventive memory cell arrangement of groups with SRAM cells according to various embodiments of the present disclosure. As already described in the context of Fig. As explained in Figure 1, local sense amplifiers 104 provide their output signals to a shared global bit line 102, which has a parasitic or intrinsic capacitance 116. The outputs of local sense amplifiers 104 are connected to local bit lines 108, which in turn are connected to the 1-bit SRAM cells (not shown). Also shown are a precharge regulator circuit 202 and an evaluation and translation circuit 204.

[0058] The precharge regulator circuit 202 includes a first p-FET P1, whose source terminal is connected to the supply voltage Vdd and whose drain terminal is connected to a first terminal of a switch 206—shown as an equivalent circuit—that receives a precharge signal GPCHG 214, 214a of a global bit line. A second terminal of the switch 206 is connected to the shared global bit line 102. On the other hand, a source terminal of a first n-FET N1 is connected to the first terminal of the switch 206. A drain terminal of the first n-FET is connected to a gate terminal of the first p-FET P1 and to a first terminal of a resistor 208. The second terminal of the resistor 208 is connected to the supply line 110. Details of the resistor 208 are explained in the following figures.

[0059] In addition to the precharge regulator circuit 202, an evaluation and translation circuit 204 is shown. The evaluation and translation circuit 204 includes a second n-FET N2, whose source terminal is connected to the shared global bitline 102 and whose drain terminal is connected to a second resistor 210, which may represent an equivalent circuit for details explained in the subsequent figures. The second resistor 210 may also be connected to the supply voltage Vdd 110. A global bitline output signal GBLout 212 is available at the drain terminal of the second n-FET N2. The gate terminal of the first n-FET N1 and the gate terminal of the second n-FET N2 are commonly connected to a voltage Vref, which is responsible for setting the precharge value of the shared global bitline 102.

[0060] One skilled in the art will recognize that the second n-FET N2 is connected between the shared global bitline 102 and the global bitline output signal GBLout 212. One of the tasks of the evaluation and translation circuitry is to translate or transform the relatively low voltage of the shared global bitline 102 to normal values ​​of "0" or "1" so that it can be interpreted as a logic "0" or logic "1" by subsequent circuitry. It should be understood that the precharge value on the shared global bitline, as shown in Fig. 2, with these circuits 202 and 204, the precharge value can be much lower than is achievable with existing technologies. The precharge value can be stabilized by the evaluation and translation circuit 204, which can essentially be viewed as a copy of the precharge regulator circuit 202. The evaluation and translation circuit 204 also compensates for bitline leakage current without changing the bitline value. Furthermore, the evaluation and translation circuit 204 provides logic values ​​(Vdd / Vss) to downstream logic elements (see above). An optional discharge unit, to be explained later, can be used to further stabilize the bitline value.

[0061] Fig. 3 shows an embodiment of an inventive precharge regulator circuit 202 according to various embodiments of the present disclosure. The precharge regulator circuit 202 may be connected to the evaluation and translation circuit 204. The drain terminal of a p-FET P2 is connected to the shared global bitline 102 and its source terminal to the supply voltage Vdd 110. The shared global bitline 102 may have a parasitic or intrinsic capacitance 116. A gate terminal of the p-FET P2 is connected to a drain terminal of a p-FET P3. The source terminal of the p-FET P3 may be connected to the supply voltage Vdd 110. Fig. 3 also shows a p-FET P4, which has a drain terminal also connected to the gate terminal of the p-FET P2, and a source terminal connected to the supply voltage Vdd 110. The connection 304 can be interpreted as a control line GPCHG for precharging the global bitline. The drain terminal of an n-FET N3 is also connected to the gate terminal of the p-FET P2, and its source terminal to a drain terminal of an n-FET N4. The source terminal of the n-FET N4 is connected to the shared global bitline 102. Furthermore, a gate terminal of the n-FET N4 and a gate terminal of the p-FET P3 are commonly connected to a precharge line GPCHG of the global bitline, a gate terminal of the n-FET N3 is connected to the reference voltage Vref line, and the gate terminal of the p-FET P4 is connected to a Vbias-p line. The p-FET P4 can be considered as the equivalent of the first resistor 208 of Fig. 2 should be considered.

[0062] Additionally, to stabilize the value of the global bit line, the drain terminal of an n-FET N5 may be connected to the shared global bit line 102 and its source terminal to ground Vss 302. The gate terminal of the n-FET N5 may receive a bias voltage Vbias-n to control the stabilization effect on the shared global bit line and to maintain stable operating conditions of the precharge regulator circuit and the evaluation and translation circuit.

[0063] Fig. 4 shows a first embodiment of the evaluation and translation circuit 204 as part of the limiter circuit. The evaluation and translation circuit 204 may be connected to the precharge regulator circuit 202. The source terminal of an n-FET N6 is connected to the shared global bitline 102, and its drain terminal is connected to the global bitline output terminal 212. Accordingly, the shared global bitline 102 and the signal at the global bitline output terminal 212 may be decoupled from each other. The global bitline 102 and the global bitline output terminal 212 may exhibit different voltage values ​​for a logic "0" or a logic "1." The global bitline 102 may have a parasitic capacitance 116.

[0064] As in Fig. As can be seen in Figure 4, the drain terminal of the p-FET P5 is connected to the output terminal 212 of the global bit line, and its source terminal is connected to the supply voltage Vdd 110. The source terminal of the p-FET P6 is connected to the supply voltage Vdd 110, and its drain terminal is connected to a source terminal of a p-FET P7, whose drain terminal is connected to the output terminal 212 of the global bit line. A gate terminal of the p-FET P7 is connected to a drain terminal of a p-FET P8, whose source terminal is connected to the supply voltage Vdd 110. The gate terminal of the p-FET P7 is also connected to a drain terminal of an n-FET N7, whose source terminal is connected to ground 302.In addition, the reference voltage Vref signal is connected to a gate terminal of the n-FET N6, the Vbias-p signal is connected to a gate terminal of the p-FET P6, and an inverted signal GPCHGN of the global bit line precharge signal is connected to a gate terminal of the p-FET P5.

[0065] In this configuration, p-FETs P7 and P8 and n-FET N7 form a feedback loop 402 as part of the guard portion of evaluation and translation circuitry 204. This interrupts the path from Vdd through p-FET P6 and p-FET P7 to the global bitline output 212 to prevent cross-current from Vdd to the pull-down unit when a sense amplifier attempts to discharge the shared global bitline, thereby saving power and speeding up the evaluation phase.

[0066] The p-FET P6 can in turn be considered as a counterpart of the second resistor 210 of Fig. 2. The combination of the precharge regulator 202 of Fig. 3 and the evaluation and translation circuit 204 of Fig. 4 enables a fast and energy-saving implementation of the inventive concept.

[0067] It can also be noted that the reference voltage Vref can be controlled with a so-called PVT (Process Voltage Temperature) circuit, which can reflect the current state of the SRAM cell array. For example, if the supply voltage Vdd 110 is higher than expected, the precharge value of the shared global bitline 102 does not need to increase as well. It can remain at the low value defined by the reference voltage Vref. In conventional technologies, the precharge value can increase with an increasing supply voltage. A similar concept can be applied to the signal values ​​Vbias-p and Vbias-p.

[0068] Fig. 5 shows a second embodiment of the evaluation and translation circuit 204. The evaluation and translation circuit 204 can be connected to a precharge regulator circuit 202. Fig. 5, the evaluation and translation circuit 204 comprises an n-FET N8 whose source terminal is connected to the global bit line 102 and whose drain terminal is connected to a source terminal of an n-FET N9, whose drain terminal is connected to a p-FET P9, whose source terminal is connected to the supply voltage Vdd 110. A p-FET P10 is connected at its source terminal to the supply voltage Vdd 110 and at its drain terminal to the drain terminal of a p-FET P9. The source terminal of a p-FET P11 is connected to the supply voltage Vdd 110 and its gate terminal to the drain terminal of the n-FET N9. The connection between the gate terminal of the p-FET P11 and the drain terminal of the n-FET N9 forms an "Eval" line 502.

[0069] A drain terminal of p-FET P11 is connected to the output terminal 212 of the global bit line. A drain terminal of an n-FET N10 and a drain terminal of an n-FET N11 are connected to the output terminal 212 of the global bit line. A source terminal of the n-FET N10 and a source terminal of the n-FET N11 are connected to ground Vss 302.

[0070] The reference voltage Vref signal is connected to a gate terminal of the n-FET N9. The bias voltage Vbias-p signal is connected to a gate terminal of the p-FET P9. An inverted signal GPCHGN of the global bit line precharge signal is connected to a gate terminal of the tenth p-FET transistor, and the global bit line precharge signal GPCHG is connected to a gate terminal of the n-FET N10. The bias voltage Vbias-n signal is connected to a gate terminal of the n-FET N11.

[0071] This embodiment of the evaluation and translation circuit 204 may be faster than the first embodiment of the evaluation / translation circuit 204, but it may save less power than the first embodiment. Furthermore, the shared global bit line 102 is decoupled from the global bit line output terminal 212. The p-FET P9 may again be configured as the equivalent of the second resistor 210 of Fig. 2 should be considered.

[0072] Fig. 6 shows a third implementation of the evaluation and translation circuit 204 of the general layout of the evaluation and translation circuit 204 according to Fig. 2. The evaluation and translation circuit 204 may be connected to a precharge regulator circuit 202. The evaluation and translation circuit 204 here includes an n-FET N12, whose source terminal is connected to the global bit line 102 and whose drain terminal is connected to a source terminal of an n-FET N13. The drain terminal of the n-FET N13 may be connected to a drain terminal of a p-FET P12, whose source terminal is connected to the supply voltage Vdd 110.

[0073] The source terminal of a p-FET P13 is connected to the supply voltage Vdd 110, and its drain terminal is connected to the drain terminal of the p-FET P12. A p-FET P14 is connected via its source terminal to the supply voltage Vdd and via its drain terminal to the drain terminal of the n-FET N13, forming an "Eval" line 602. The drain terminal of an n-FET N14 is connected to a drain terminal of the p-FET P14, and its source terminal is connected to a drain terminal of an n-FET N15, whose source terminal is connected to ground Vss 302.

[0074] The drain terminal of an n-FET N16 is connected to the drain terminal of the p-FET P14, and its source terminal is connected to ground Vss 302. The input of an inverter 702 is connected to the drain terminal of the p-FET P14, and its output is connected to the output terminal 212 of the global bit line. A p-FET P15 is connected via its source terminal to the supply voltage Vdd 110 and via its drain terminal to the drain terminal of the p-FET P14. The p-FET P15 can be connected via its gate terminal to the output terminal 212 of the global bit line. A gate terminal of the n-FET N14 is also connected to the output terminal 212 of the global bit line.

[0075] The reference voltage Vref signal is connected to a gate terminal of n-FET N13, an inverted signal of the Vbias-p signal is connected to a gate terminal of p-FET P12, an inverted signal GPCHGN of the global bit line precharge signal is connected to a gate terminal of p-FET P13, and the global bit line precharge signal GPCHG is connected to a gate terminal of n-FET N16. Finally, the Vbias-n signal is connected to a gate terminal of n-FET N15.

[0076] It should be noted that the speed of this evaluation and translation circuit 204 is between that of the first embodiment of the evaluation and translation circuit 204 according to Fig. 4 and the second embodiment of the evaluation and translation circuit 204 according to Fig. 5. However, the improvements in energy saving can be achieved compared to the second embodiment of the evaluation and translation circuit according to Fig. 5 larger.

[0077] Fig. 7 shows an illustration of an exemplary implementation flow 700 used, for example, in the development, simulation, testing, layout, and manufacturing of semiconductor IC logic. The implementation flow 700 includes processes, engines, and / or mechanisms for processing build structures or devices to generate logical or otherwise functionally equivalent representations of the build structures and / or devices described above and in the Fig. 1 to 6. The build structures processed and / or generated by the implementation flow 700 may be encoded on machine-readable transmission or storage media to contain data and / or instructions that generate a logically, structurally, mechanically, or otherwise functionally equivalent representation of hardware components, circuits, units, or systems when executed or otherwise processed in a data processing system. Machines include any machine used in an IC development process, such as, but not limited to, developing, manufacturing, or simulating a circuit, component, unit, or system. Machines may include, for example: lithography machines, machines and / or equipment for generating masks (e.g.,Electron beam writing devices), computers or equipment for simulating build-up structures, any equipment used in the manufacturing or testing process, or any machine for programming functionally equivalent representations of the build-up structures into any medium (e.g., a machine for programming a programmable gate array).

[0078] The implementation flow 700 may vary depending on the type of representation being designed. For example, an implementation flow for forming an application-specific integrated circuit (ASIC) may differ from an implementation flow 700 for executing a standard component or from an implementation flow 700 for instantiating the implementation in a programmable array, e.g., a programmable gate array (PGA) or a field-programmable gate array (FPGA) offered by Altera® Inc. or Xilinx®.

[0079] Fig. 7 illustrates several such build structures, including an input build structure 720 that is preferably processed by an execution process. Build structure 720 may be a build structure with logical simulation that is generated and processed by an execution process to produce a logically equivalent functional representation of a hardware device. Build structure 720 may also or alternatively include data and / or program instructions that, when processed by an execution process, produce a functional representation of the physical structure of a hardware device. Whether representing functional and / or structural design features, build structure 720 may be generated using electronic computer-aided design (ECAD), for example, implemented by a core developer / designer.When encoding on a machine-readable data transmission, gate array, or storage medium, the build structure may be accessed or processed by one or more hardware and / or software modules in the execution process 710 to simulate an electronic component, circuit, electronic or logic module, device, unit, or system such as those described in the . Fig. 1 through 6. Therefore, the build structure 720 may include files or other data structures, including human- and / or machine-readable source code, compiled structures, and computer-executable code structures that functionally simulate or otherwise represent circuits or other levels of hardware logic design when processed by an execution or simulation data processing system. These data structures may include Hardware Description Language (HDL) execution entities or other data structures that conform to and / or are compatible with low-level HDL design languages, such as Verilog and VHDL, such as C or C++, and / or higher-level design languages.

[0080] The development process 710 preferably uses and includes hardware and software modules for synthesizing, translating, or otherwise processing an execution / simulation of functional replacements of the components, circuits, units, or logical structures included in the Fig. 1 through 6, for generating a netlist 780, which may include build structures such as build structure 720. For example, netlist 780 may comprise compiled or otherwise processed data structures representing a list of lines, discrete components, logic gates, control circuits, I / O devices, models, etc., that describe the interconnection with other elements and circuits in an integrated circuit implementation. Netlist 780 may be synthesized using an iterative process in which netlist 780 is resynthesized one or more times depending on implementation specifications and parameters for the device. As with other build structure types described herein, netlist 780 may be recorded on a machine-readable data storage medium or programmed into a programmable gate array.The medium may be a non-volatile storage medium such as a magnetic or optical disk drive, a programmable gate array, compact flash, or other flash memory. Additionally, or alternatively, the medium may be system or cache memory, buffer space, or electrically or optically conductive devices and materials on which data packets can be transmitted or temporarily stored via the Internet or other suitable networking means.

[0081] The development process 710 may include hardware and software modules for processing a variety of input data structure types, including the netlist 780. These data structure types may be located, for example, in library elements 730 and contain a group of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.). The data structure types may further include design specifications 750, tag data 750, test data 760, design rules 770, and test files 785, which may contain input test patterns, output test results, and other test information.The development process 710 may further include, for example, common mechanical design processes such as stress analysis, thermal analysis, simulation of mechanical events, process simulation for operations such as casting, molding, and compression molding, etc. One skilled in the art of mechanical design will recognize the scope of possible mechanical design tools and applications used in the development process 710 without departing from the scope or inventive spirit of the invention. The development process 710 may also include modules for executing common circuit design processes such as timing analysis, testing, execution rule checking, placement and routing operations, etc.

[0082] The development process 710 uses and includes logical and physical execution tools such as HDL compilers and simulation model building tools to process the build structure 720 along with some or all of the presented supporting data structures along with additional mechanical executions or (if applicable) data to generate a second build structure 790. The build structure 790 is located on a storage medium or a programmable gate array in a data format used for data exchange of mechanical entities and structures (e.g., information stored in IGES, DXF, Parasolid XT, JT, DRG, or another suitable format for storing or reproducing such mechanical build structures).Similar to the build structure 720, the build structure 790 preferably comprises one or more files, data structures, or other computer-encoded data or instructions residing on transmission or data storage media that embody a logically or otherwise functionally equivalent form of one or more of the methods described in the . Fig. 1 to 6 when processed by an ECAD system. In one embodiment, the build structure 790 may comprise a compiled executable HDL simulation model that implements the Fig. The units shown in 1 to 6 are functionally simulated.

[0083] The build structure 790 may also use a data format used for exchanging integrated circuit layout data and / or a symbolic data format (e.g., information stored in GDSII (GDS2), GL1, OASIS, mapping files, or any other suitable format for storing such design data structures). The build structure 790 may include information such as symbolic data, mapping files, test data files, design content files, manufacturing data, layout parameters, performance, metal levels, cavities, shapes, data for routing through the production line, and any other data required by a manufacturer or other designers / developers to manufacture a unit or structure described above and in the Fig.1 to 6. The build structure 790 may then proceed to a stage 795 in which the build structure 790 may, for example: be presented for manufacturing, released for production, released for mask manufacturing, sent to another execution site, returned to the customer, etc.

[0084] The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the spirit and scope of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, practical application, or technical improvement over existing technology, or to enable others skilled in the art to understand the disclosed embodiments.

[0085] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context expressly indicates otherwise. It is further understood that the terms "comprise" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0086] The corresponding structures, materials, effects, and replacements for all means or steps plus functional elements in the following claims are intended to include any structure, material, or effect for performing the function in combination with other specifically claimed elements. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limiting of the invention in the form disclosed. Many modifications and variations will be apparent to one skilled in the art without departing from the scope and spirit of the invention.The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, and to enable others skilled in the art to understand the present invention, since various embodiments with various modifications are suitable for the particular use contemplated.

Claims

[1] Memory cell arrangement of static random access memory (SRAM) cells, which has: one or more groups of SRAM cells (106), wherein each of the one or more groups of SRAM cells (106) includes two or more SRAM cells (106) connected to an input of a local sense amplifier (104) by at least one common local bit line (108), and wherein outputs of the local sense amplifiers (104) are connected to a shared global bit line (102), wherein the shared global bit line (102) is connected to a precharge circuit configured to precharge the shared global bit line (102) with a programmable precharge voltage prior to reading data, wherein the precharge circuit includes a limiter circuit comprising: a precharge regulator circuit (202) connected to the shared global bit line (102) for precharging the shared global bit line (102) with the programmable precharge voltage; and an evaluation and translation circuit (204) connected to the precharge regulator circuit (202) and the shared global bit line (102) for compensating for leakage current of the shared global bit line (102) without changing a voltage value of the bit line, the precharge regulator circuit (202) comprising: a first p-FET (P1) whose source terminal is connected to a supply voltage (110) and whose drain terminal is connected to a first terminal of a precharge switch (206), the second terminal of which is connected to the shared global bit line (102); and a first n-FET (N1) whose source terminal is connected to the first terminal of the precharge switch (206), wherein a drain terminal of the first n-FET (N1) is connected to a gate terminal of the first p-FET (P1) and to a first terminal of a first programmable resistor (208) whose second terminal is connected to the supply voltage (110), wherein a gate terminal of the first n-FET (N1) is connected to a signal reference voltage (Vref), wherein the evaluation and translation circuit (204) comprises: a second n-FET (N2) whose source terminal is connected to the shared global bit line (102) and whose drain terminal is connected to a first terminal of a second programmable resistor (210), whose second terminal is connected to the supply voltage (110), wherein a gate terminal of the second n-FET (N2) is connected to the signal Vref, and wherein an output terminal (212) of a global bit line (102) is connected to the drain terminal of the second n-FET (N2). [2] Memory cell arrangement according to claim 1, wherein the programmable precharge voltage is less than half the value of a supply voltage (110). [3] The memory cell array of claim 1, wherein the signal Vref is for controlling a precharge value of the shared global bit line (102). [4] Memory cell arrangement of static random access memory (SRAM) cells, which has: one or more groups of SRAM cells (106), wherein each of the one or more groups of SRAM cells (106) includes two or more SRAM cells (106) connected to an input of a local sense amplifier (104) by at least one common local bit line (108), and wherein outputs of the local sense amplifiers (104) are connected to a shared global bit line (102), wherein the shared global bit line (102) is connected to a precharge circuit configured to precharge the shared global bit line (102) with a programmable precharge voltage prior to reading data, wherein the precharge circuit includes a limiter circuit comprising: a precharge regulator circuit (202) connected to the shared global bit line (102) for precharging the shared global bit line (102) with the programmable precharge voltage; and an evaluation and translation circuit (204) connected to the precharge regulator circuit (202) and the shared global bit line (102) for compensating for leakage current of the shared global bit line (102) without changing a voltage value of the bit line, the precharge regulator circuit (202) comprising: a second p-FET (P2) having a drain terminal connected to the shared global bit line (102) and a source terminal connected to a supply voltage (110), a gate terminal of the second p-FET (P2) being connected to a drain terminal of a third p-FET (P3), a source terminal of the third p-FET (P3) being connected to the supply voltage (110); a fourth p-FET (P4) whose drain terminal is connected to the gate terminal of the second p-FET (P2) and whose source terminal is connected to the supply voltage (110); and a third n-FET (N3) whose drain terminal is connected to the gate terminal of the second p-FET (P2) and whose source terminal is connected to a drain terminal of a fourth n-FET (N4) whose source terminal is connected to the shared global bit line (102), wherein a gate terminal of the fourth n-FET (N4) and a gate terminal of the third p-FET (P3) are commonly connected to a precharge line (GPCHG) of a global bit line, wherein a gate terminal of the third n-FET (N3) is connected to a signal Vref and wherein a gate terminal of the fourth p-FET (P4) is connected to a p-bias signal (Vbias-p). [5] The memory cell array of claim 4, wherein a drain terminal of a fifth n-FET (N5) is connected to the shared global bit line (102), a source terminal of the fifth n-FET (N5) is connected to ground (302), and a gate terminal of the fifth n-FET (N5) is connected to an n-bias signal (Vbias-n) for maintaining the precharge regulator circuit (202) and the evaluation and translation circuit (204) in stable operating conditions. [6] Memory cell arrangement of static random access memory (SRAM) cells, which has: one or more groups of SRAM cells (106), wherein each of the one or more groups of SRAM cells (106) includes two or more SRAM cells (106) connected to an input of a local sense amplifier (104) by at least one common local bit line (108), and wherein outputs of the local sense amplifiers (104) are connected to a shared global bit line (102), wherein the shared global bit line (102) is connected to a precharge circuit configured to precharge the shared global bit line (102) with a programmable precharge voltage prior to reading data, wherein the precharge circuit includes a limiter circuit comprising: a precharge regulator circuit (202) connected to the shared global bit line (102) for precharging the shared global bit line (102) with the programmable precharge voltage; and an evaluation and translation circuit (204) connected to the precharge regulator circuit (202) and the shared global bit line (102) for compensating for leakage current of the shared global bit line (102) without changing a voltage value of the bit line, the evaluation and translation circuit (204) comprising: a sixth n-FET (N6) having a source terminal connected to the shared global bit line (102) and a drain terminal connected to an output terminal of a global bit line (212); a fifth p-FET (P5) whose drain terminal is connected to the output terminal of the global bit line (212) and whose source terminal is connected to a supply voltage (110); and a sixth p-FET (P6) whose source terminal is connected to the supply voltage (110) and whose drain terminal is connected to a source terminal of a seventh p-FET (P7) whose drain terminal is connected to the output terminal of the global bit line (212), wherein a gate terminal of the seventh p-FET (P7) is connected to a drain terminal of an eighth p-FET (P8) whose source terminal is connected to the supply voltage (110), wherein the gate terminal of the seventh p-FET (P7) is also connected to a drain terminal of a seventh n-FET (N7) whose source terminal is connected to ground (302), wherein a signal Vref is connected to a gate terminal of the sixth n-FET (N6), wherein a signal Vbias-p is connected to a gate terminal of the sixth p-FET (P6), and wherein an inverted signal of the precharge signal of the global bit line is connected to a gate terminal of the fifth p-FET (P5). [7] Memory cell arrangement of static random access memory (SRAM) cells, which has: one or more groups of SRAM cells (106), wherein each of the one or more groups of SRAM cells (106) includes two or more SRAM cells (106) connected to an input of a local sense amplifier (104) by at least one common local bit line (108), and wherein outputs of the local sense amplifiers (104) are connected to a shared global bit line (102), wherein the shared global bit line (102) is connected to a precharge circuit configured to precharge the shared global bit line (102) with a programmable precharge voltage prior to reading data, wherein the precharge circuit includes a limiter circuit comprising: a precharge regulator circuit (202) connected to the shared global bit line (102) for precharging the shared global bit line (102) with the programmable precharge voltage; and an evaluation and translation circuit (204) connected to the precharge regulator circuit (202) and the shared global bit line (102) for compensating for leakage current of the shared global bit line (102) without changing a voltage value of the bit line, the evaluation and translation circuit (204) comprising: an eighth n-FET (N8) having a source connected to the shared global bit line (102) and a drain connected to a source of a ninth n-FET (N9) having a drain connected to a drain of a ninth p-FET (P9) having a source connected to a supply voltage (110); a tenth p-FET (P10) whose source terminal is connected to the supply voltage (110) and whose drain terminal is connected to the drain terminal of the ninth p-FET (P9); and an eleventh p-FET (P11), whose source terminal is connected to the supply voltage (110) and whose gate terminal is connected to the drain terminal of the ninth n-FET (N9), wherein a drain terminal of the eleventh p-FET (P11) is connected to an output terminal of a global bit line (212), wherein a drain terminal of a tenth n-FET (N10) and a drain terminal of a tenth n-FET (N10) and a drain terminal of an eleventh n-FET are connected to the output terminal of the global bit line (212), wherein a source terminal of the tenth n-FET (N10) and a source terminal of the eleventh n-FET (N11) are connected to ground (302), wherein a signal Vref is connected to a gate terminal of the ninth n-FET (N9), wherein a signal Vbias-p is connected to a gate terminal of the ninth p-FET (P9), wherein an inverted signal of the precharge signal of a global bit line is connected to a gate terminal of the tenth p-FET (P10), wherein the precharge signal of the global bit line is connected to a gate terminal of the tenth n-FET (N10), and wherein a signal Vbias-n is connected to a gate terminal of the eleventh n-FET (N11). [8] Memory cell arrangement of static random access memory (SRAM) cells, which has: one or more groups of SRAM cells (106), wherein each of the one or more groups of SRAM cells (106) includes two or more SRAM cells (106) connected to an input of a local sense amplifier (104) by at least one common local bit line (108), and wherein outputs of the local sense amplifiers (104) are connected to a shared global bit line (102), wherein the shared global bit line (102) is connected to a precharge circuit configured to precharge the shared global bit line (102) with a programmable precharge voltage prior to reading data, wherein the precharge circuit includes a limiter circuit comprising: a precharge regulator circuit connected to the shared global bit line (102) for precharging the shared global bit line (102) with the programmable precharge voltage; and an evaluation and translation circuit (204) connected to the precharge regulator circuit (202) and the shared global bit line (102) for compensating for leakage current of the shared global bit line (102) without changing a voltage value of the bit line, the evaluation and translation circuit (204) comprising: a twelfth n-FET (N12) having a source connected to the shared global bit line (102) and a drain connected to a source of a thirteenth n-FET (N13) having a drain connected to a drain of a twelfth p-FET (P12) having a source connected to a supply voltage (110); a thirteenth p-FET (P13) having its source terminal connected to the supply voltage (110) and its drain terminal connected to the drain terminal of the twelfth p-FET (P12); a fourteenth p-FET (P14) having its source terminal connected to the supply voltage (110) and its gate terminal connected to the drain terminal of the thirteenth n-FET (N13); a fourteenth n-FET (N14) whose drain terminal is connected to a drain terminal of the fourteenth p-FET (P14) and whose source terminal is connected to a drain terminal of a fifteenth n-FET (N15), whose source terminal is connected to ground (302); a sixteenth n-FET (N16) having its drain terminal connected to the drain terminal of the fourteenth p-FET (P14) and its source terminal connected to ground (302); an inverter whose input is connected to the drain terminal of the fourteenth p-FET (P14) and whose output is connected to an output terminal of a global bit line (212); and a fifteenth p-FET (P15) whose source terminal is connected to the supply voltage (110) and whose drain terminal is connected to the drain terminal of the fourteenth p-FET (P14), wherein the gate terminal of the fifteenth p-FET (P15) is connected to the output terminal of the global bit line (212), wherein a gate terminal of the fourteenth n-FET (N14) is connected to the output terminal of the global bit line (212), wherein a signal Vref is connected to a gate terminal of the thirteenth n-FET (N13), wherein a signal V-bias-p is connected to a gate terminal of the twelfth p-FET (P12), wherein an inverted signal of a precharge signal of a global bit line is connected to a gate terminal of the thirteenth p-FET (P13), wherein the precharge signal of the global bit line is connected to a gate terminal of the sixteenth n-FET (N16), and wherein a signal Vbias-n is connected to a gate terminal of the fifteenth n-FET (N15). [9] The memory cell array of claim 7, wherein at least one of the groups comprising the signal Vref, the signal Vbias-n, or the signal Vbias-p is controlled by a process voltage-temperature circuit.

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