Method, system, and computer program product for bypassing a memory access for a load instruction using an instruction address mapping

Abstract

A computer-executed method to bypass memory access for a load instruction, wherein the method comprises: Determining a predicted instruction address (IA) that corresponds, at least in part, to a load IA belonging to the load instruction, by accessing an initial data structure that is indexed with IAs belonging to load instructions; Utilizing at least one part of the predicted IA to: i) access a second data structure to determine a first physical register that stores a value associated with the load instruction, or ii) access a third data structure instead of accessing the second data structure to obtain the value associated with the load instruction; and Executing a predicted load operation as part of the load instruction, at least in part, by setting a second physical register to the value belonging to the load instruction.

Description

TECHNICAL AREA

[0001] The invention relates to a method for bypassing memory access for a load instruction using an instruction address assignment, as well as a corresponding system and computer program product. BACKGROUND

[0002] Executing computer program instructions can involve storing data in physical registers. During program execution, data stored in a physical register may need to be moved to memory, and data stored in memory may need to be loaded into a physical register. In microarchitectural designs (e.g., a central processing unit (CPU)), instruction execution units are located closer to physical registers than to memory. Thus, loading data from memory (even a cache) into a physical register typically takes more time than copying the data from another physical register.

[0003] The dissertation "Exploiting Aggressive Memory Dependence Speculation To Simplify The Store-Load Datapath" by T. Sha, University of Pennsylvania, 2011, describes a mechanism for bypassing the forwarding of a load instruction to a store instruction. A predictor forecasts a dependency on a specific store for a given load and assigns the store's sequence number to the load. The store enters a memory queue at the time of register renaming. At the subsequent commit time, the store is instead allocated to a memory buffer, where it remains at least until its value is written to the cache. If a load depends on a store, the load is classified as forwarding if its corresponding store is in the memory buffer, and as immediate if the corresponding store is still in the memory queue.The plan is that for forwarding loads, a new physical register should be used as the target register. Conversely, for immediate loads, the target register of the load is set to the source register of the corresponding store.

[0004] The scientific paper "Storage-Free Memory Dependency Prediction" by A. Perais and A. Seznec, published on November 13, 2016, in IEEE Computer Architecture Letters, Vol. 16, No. 2, pp. 149-152, addresses the problem that when predicting a memory dependency (MDP), not all instances of a given static load necessarily depend on all instances of a given static memory. Therefore, for a given load, MDP should predict the exact memory instruction on which the load depends, and not just whether or not it depends on inflight memory; that is, ideally, the prediction should be non-binary.The authors first argue that, given the advanced state of modern branch predictors, the fact that a given dynamic load depends on inflight memory can be captured using the branch predictor's binary predictive capabilities, thus providing a rough MDP without memory overhead. Second, the authors demonstrate, through the use of hysteresis counters, that the precise source memory can indeed be identified. The presented form of MDP delivers state-of-the-art performance levels and requires less than 70 additional bits of memory compared to a baseline without MDP.

[0005] The scientific publication "Memory Renaming: Fast, Early and Accurate Processing of Memory Communication" by G.S. Tyson and T.M. Austin, published in the International Journal of Parallel Programming, Vol. 27, No. 5, 1999, introduces a modification of a processor pipeline known as memory renaming. Memory renaming employs register access techniques for loading and storing instructions to accelerate memory traffic processing. The approach works by accurately predicting memory communication early in the pipeline and then redirecting that communication to fast physical registers. SUMMARY

[0006] The invention addresses the following problems: providing a method for bypassing memory access for a load instruction while achieving higher instruction execution performance. These problems are each solved by the features of the independent claims. Embodiments of the invention are the subject of the dependent claims.

[0007] In one or more exemplary embodiments of the disclosure, a method for bypassing a memory access for a load instruction is disclosed. The method involves determining a predicted instruction address (IA) corresponding to a load IA belonging to the load instruction, at least in part, by accessing a first data structure that is indexed only with IAs belonging to load instructions, and using at least a portion of the predicted IA to i) access a second data structure to determine a first physical register that stores a value belonging to the load instruction, or ii) access a third data structure instead of accessing the second data structure to obtain the value belonging to the load instruction.The procedure further involves executing a predicted load operation, at least in part, by setting a second physical register to the value that corresponds to the load instruction.

[0008] In one or more further exemplary embodiments of the disclosure, a system for bypassing memory access for a load instruction is disclosed. The system includes at least one memory that stores computer-executable instructions and at least one processor configured to access the at least one memory and execute the computer-executable instructions to perform a set of operations.The operations include determining a predicted instruction address corresponding to a load instruction (IA) belonging to the load instruction, at least in part, by accessing a first data structure indexed only with IAs belonging to load instructions, and using at least part of the predicted IA to i) access a second data structure to determine a first physical register storing a value belonging to the load instruction, or ii) access a third data structure instead of the second data structure to obtain the value belonging to the load instruction. The operations also include executing a predicted load operation, at least in part, by setting a second physical register to the value belonging to the load instruction.

[0009] In one or more further exemplary embodiments of the disclosure, a computer program product for bypassing a memory access for a load instruction is disclosed, comprising a non-volatile storage medium which can be read by a processing circuit, wherein the storage medium stores instructions which can be executed by the processing circuit to cause a process to be carried out.The method involves determining a predicted instruction address (IA) corresponding to a load IA belonging to the load instruction, at least partially, by accessing a first data structure indexed only with IAs belonging to load instructions, and using at least part of the predicted IA to i) access a second data structure to determine a first physical register storing a value belonging to the load instruction, or ii) access a third data structure instead of the second data structure to obtain the value belonging to the load instruction. The method further involves executing a predicted load operation, at least partially, by setting a second physical register to the value belonging to the load instruction. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a block diagram that schematically depicts the execution of a predicted load operation in order to avoid a memory access for a load instruction according to one or more exemplary embodiments of the disclosure. Fig. Figure 2 is a process flow diagram illustrating a method for performing a predicted load operation to avoid memory access for a load instruction according to one or more exemplary embodiments of the disclosure. Fig. Figure 3 is a process flow diagram illustrating a method for determining whether a predicted load operation should be performed to avoid a memory access for a load instruction according to one or more exemplary embodiments of the disclosure. Fig. Figure 4 is a schematic representation of an illustrative data processing unit configured to perform one or more exemplary embodiments of the disclosure. DETAILED DESCRIPTION

[0010] Exemplary embodiments of the disclosure include, among others, systems, methods, computer-readable data carriers, techniques, and methodical procedures for performing a predicted load operation that bypasses a memory access for a load instruction. In certain exemplary embodiments, a first physical register that predictively stores a value to be loaded by the load instruction is labeled, and the value stored in the first physical register is copied to a second physical register for use by a consumer operation. A predicted memory instruction corresponding to the load instruction can be labeled, and an assignment table can be accessed to obtain data belonging to the predicted memory instruction. The data can include a label of the first physical register as well as a label (e.g.,a statement containing an instruction identifier of a producer operation that created / modified the value stored in the first physical register. As a result of executing the predicted load operation, the desired data is obtained from the producer operation, and the cache memory access that would otherwise be necessary to execute the load instruction and copy the data from a memory location into a physical register is avoided.

[0011] Fig. Figure 1 is a block diagram that schematically depicts the execution of a predicted load operation in order to avoid a memory access for a load instruction according to one or more exemplary embodiments of the disclosure. Fig. Figure 2 is a process flow diagram of an illustrative method 200 for performing a predicted load operation to avoid a memory access for a load instruction according to one or more exemplary embodiments of the disclosure. Fig. Figure 3 is a process flow diagram of an illustrative method 300 for determining whether a predicted load operation should be executed to avoid a memory access for a load instruction according to one or more exemplary embodiments of the disclosure. Fig. 2 and Fig. 3 are below in conjunction with Fig. 1 described.

[0012] Each operation of procedure 200 and / or procedure 300 can be performed by one or more components (e.g., engines) located in Fig. Figure 1 is shown. This component(s) can be implemented in any combination of hardware, software, and / or firmware. In certain exemplary embodiments, one or more of these components can be implemented at least partially as software and / or firmware, which contains one or more program modules or is a group of one or more program modules containing computer-executable instructions that, when executed by a processing circuit, cause one or more operations to be performed. A system or unit described herein as being configured to perform exemplary embodiments of the disclosure can include one or more processing circuits, each of which can contain one or more processing units or nodes.Instructions executable by a computer may include computer-executable program code which, when executed by a processing unit, can cause input data contained in or referenced by the computer-executable program code to be accessed and processed to produce output data.

[0013] Firstly, referring to Fig. Figure 1 shows a group of engines, including a prediction engine 102, a register monitoring engine 104, a read / write engine 106, and an instruction execution engine 108. These engines can be implemented in any combination of hardware, software, and / or firmware. In certain exemplary embodiments, these engines can be run across one or more units, which are connected via the Fig. The 4 illustrated configurations are available.

[0014] Now, referring to the Fig. 1 and Fig. Block 202, in conjunction with each other, allows computer-executable instructions of the instruction execution engine 108 to be executed to cause a producer operation to be performed, which creates / modifies a value belonging to a specific architecture-defined register from the set of architecture-defined registers 128 defined in the microarchitecture. For ease of explanation, the reference number 128 herein may be used to denote the aforementioned specific architecture-defined register. In certain exemplary embodiments, a set of architecture-defined registers may be specified as part of a microarchitecture design. The set of architecture-defined registers may be associated with a set of physical registers in the microarchitecture.In certain exemplary embodiments, the number of physical registers can be greater than or equal to the number of architecture-defined registers. Thus, architecture-defined register 128 can be assigned to different physical registers for different instructions and / or to multiple physical registers simultaneously. More precisely, a value belonging to architecture-defined register 128 can be stored in different physical registers for different instructions and / or in multiple physical registers simultaneously.

[0015] As a non-exhaustive example, the producer operation can sum the values ​​in two registers and store the resulting sum in one of the registers. For example, if R1 represents architecture-defined register 128, the producer operation can be R1 = R1 + R2, where R2 is another architecture-defined register. As described earlier, architecture-defined register 128 (e.g., R1) can first be mapped to physical register 20 (pR20). Similarly, architecture-defined register R2 can be mapped to physical register 22 (pR22). As a result of the producer operation, the values ​​stored in pR20 and pR22 can be summed, and the resulting sum can be stored in physical register 21 (pR21). Physical register pR21 can then be mapped to architecture-defined register 128 (R1), thus mapping the sum to architecture-defined register 128 (R1).

[0016] In certain exemplary embodiments, computer-executable instructions of the Register Monitoring Engine 104 can be executed to maintain / modify a mapping between architecture-defined registers and physical registers. In an in-order machine, the number of architecture-defined registers can be equal to the number of physical registers. This is because instructions are executed in the order in which they are issued in an in-order machine, and thus there is no need to manage more physical registers than architecture-defined registers. However, in an out-of-order machine, a more recent / younger instruction can be executed before an older instruction, and thus there is a need to manage a larger number of physical registers than architecture-defined registers.

[0017] In these exemplary embodiments, where the number of physical registers exceeds the number of architecture-defined registers, a mapping between architecture-defined registers and physical registers can be maintained. This mapping between architecture-defined registers and physical registers can be reflected in data stored in a register mapping table 138, which is maintained / updated by the register monitoring engine 104. The register mapping table 138 can be indexed with an architecture-defined register and, for each indexed architecture-defined register, store an identifier of a physical register that stores a value belonging to that architecture-defined register. For in-order decoding / allocation to send instructions to an out-of-order engine, only the oldest reference to the architecture-defined register is required.When deleting the contents of the instruction pipeline, requiring the pipeline to revert to a previous state, the architecture-defined register alone may not be sufficient. In such cases, it may also be necessary to know which instruction corresponds to the point at which the deletion occurred. This could be achieved using a micro-op instruction ID.

[0018] Referring specifically to block 202 of procedure 200, the producer operation being executed can result in a value being created and stored in a physical register 130, which is mapped to the architecture-defined register 128. Alternatively, the producer operation can modify an existing value stored in physical register 130. An identifier for the physical register 130 that stores the value created / modified by the producer operation can be stored in the register mapping table 138, along with the corresponding architecture-defined register 128. That is, entries can be written to the register mapping table 138 depending on the producer operation.

[0019] Generally speaking, Register Mapping Table 138 can only map / link a single physical register to an architecture-defined register at a time. However, to accommodate the potential need to clear the contents of the instruction pipeline, Register Mapping Table 138 can store mappings / links between an architecture-defined register and multiple physical registers. For example, suppose that a set of instructions (e.g., instructions 1 through 100) has been allocated. A subset of these instructions may have been issued. Of the issued instructions, an older instruction may still be executing, while the execution of a newer instruction may have completed. For example, the older instruction might be a complex square root calculation or something similar, while the newer instruction might be a relatively simple load instruction.It should be noted that although a newer instruction can complete execution before an older instruction, the newer instruction can only complete and be marked with a checkpoint once the older instruction has completed execution, in order to maintain the appearance that the instructions are executed in order.

[0020] In an example scenario, a predicted branch might have been made at instruction 15. If it is later discovered that the branch was incorrectly predicted (e.g., the branch was made when it shouldn't have been, or vice versa), all instructions in the pipeline after the branch instruction (e.g., instructions 16 through 100) will be incorrect. This would trigger a delete event, causing all instructions in the pipeline after the branch instruction to be deleted and the pipeline to be reset, starting with the correct destination address of the branch instruction.

[0021] In certain exemplary embodiments, the branching instruction described above can occur between two instructions that affect the same architecture-defined register. For example, an instruction before the branching instruction can assign the value belonging to architecture-defined register R7 to architecture-defined register R1, and the instruction after the branching instruction can assign the value belonging to architecture-defined register R2 to R1. It should be understood that the values ​​belonging to these architecture-defined registers can be stored in different physical registers. If the branching is incorrectly predicted, as described above, the value belonging to architecture-defined register R1 must be reset to the value belonging to architecture-defined register R7 (and not to the value belonging to architecture-defined register R2).To properly reset the value of the architecture-defined register R1, the register mapping table 138 must maintain a history of mappings between physical registers and architecture-defined registers. Specifically, in the example presented above, the register mapping table 138 can store a mapping between the architecture-defined register R1 and a physical register corresponding to the architecture-defined register R7, as well as a mapping between the architecture-defined register R1 and a physical register corresponding to the architecture-defined register R2, so that a previous value belonging to the architecture-defined register R1 can be restored if a clear event occurs.Furthermore, a specific instruction identifier can be stored with each mapping to indicate which value should be reset based on where in the instruction pipeline the deletion occurred. It should be understood that the preceding example is merely illustrative and not exhaustive. For instance, register mapping table 138 can store any number of mappings between a given architecture-defined register and physical registers.

[0022] Block 204 can host an event that necessitates transferring register values ​​stored in physical registers to memory. An example of such an event is the execution of a function that requires copying register values ​​stored in physical registers to memory. For instance, if a microarchitecture specifies 16 architecture-defined registers, but an algorithm requires 17 values, not all values ​​can be allocated to the 16 architecture-defined registers simultaneously. Consequently, at least one register value can be transferred to memory to free one or more architecture-defined registers during algorithm execution.In other exemplary embodiments, the number of registers required by a function may not be known before the function is executed, or there may be a risk that executing the function will corrupt register values, in which case register values ​​can be passed to memory.

[0023] Block 206 allows a computer to execute instructions of the instruction execution engine 108 to perform a memory instruction to store a value belonging to architecture-defined register 128 in a memory location. This memory location could be, for example, a cache location such as an L1 cache or an L2 cache. Referring to the same example presented earlier, executing the memory instruction can result in the value stored in pR21 (the physical register 130 mapped to architecture-defined register 128) being stored in a memory location.

[0024] In certain exemplary embodiments, an entry corresponding to the executed memory instruction can be created in a prediction forwarding allocation table 122 (hereinafter referred to in short as allocation table 122). More precisely, computer-executable instructions of the read / write engine 106 can be executed to perform a write operation 126 to create the entry in the allocation table 122. In certain exemplary embodiments, the allocation table 122 can be implemented as a regfile with multiple read and write ports. The regfile can be configured to hold any suitable number of entries (e.g., 32, 64, etc.). A specific number of bits can be allocated to each entry. For example, the entry corresponding to the memory instruction executed at block 206 can be allocated a specific number of bits (e.g.,10 bits) are included, which are intended for storing a virtual instruction address (IA) tag. Mapping table 122 can be indexed with at least some memory IAs.

[0025] The virtual IA tag can be part of the total IA 124 belonging to the memory instruction. The number of bits used to store the virtual IA tag can reflect a trade-off between aliasing, which can result from using a small number of bits for the tag, and the higher number of entries that can be stored in the IA 122 as a result of the smaller number of bits used for the tag. The number of bits used for the tag can also be determined, at least in part, by the amount of memory available for the IA 122, performance requirements, frequency requirements, and / or cost requirements. Furthermore, the entry corresponding to the memory instruction can use a specific number of bits (e.g., 8 bits) to store an instruction identifier (e.g., a micro-op ID) of the memory instruction; a specific number of bits (e.g.,8 bits) for storing an instruction identifier of a producer operation corresponding to the memory instruction; and a specific number of bits (e.g., 8 bits) for storing an identifier of the physical register that has stored (and may be predictively storing) a value created / modified by the producer operation, wherein such a value is copied to a memory location by execution of the memory instruction. It should be understood that the specific execution of mapping table 122, including the number of bits allocated to each entry and to each data field within each entry, is merely illustrative and not exhaustive.

[0026] At block 208, register values ​​can be transferred from memory to the physical registers. For example, register values ​​copied to memory at block 204 can be written back to the physical registers after a return from a function call. In certain exemplary embodiments, however, a load instruction that loads a value from memory to a physical location can be bypassed by performing a predictive load operation.

[0027] Specifically, computer-executable instructions of the prediction engine 102 can be executed at block 210 to predict that the memory instruction executed at block 206 will correlate with a load instruction to be executed, and to use the memory instruction's input logic (IA) to identify a physical register that stores the value belonging to the architecture-defined register 128. More precisely, the prediction engine 102 can identify a memory IA 118 from the prediction array 114 that belongs to the memory instruction which, according to prediction, correlates with the load instruction (or a correlated load IA in the case of handling a constant load operation, which will be described in more detail later in this disclosure). In certain exemplary embodiments, the memory instruction could include multiple micro-op memory operations.In such exemplary embodiments, the load prediction obtained from the prediction array 114 specifies not only the memory IA 118 but also a uop position of the memory instruction. In these exemplary embodiments, where the memory instruction is a single micro-op, the default value of 0 can be used. The prediction engine 102 can then use the correlated IA (either the memory IA 118 or a load IA in the case of constant load operations) to access the mapping table 122 and designate a physical register that stores the value belonging to the correlated instruction (e.g., the value belonging to the architecture-defined register 128).

[0028] Referring again to the previously presented example, the destination of the designated physical register pR21 can be the one associated with the architecture-defined register 128, in which a value has been stored as a result of executing a producer operation corresponding to the predicted storage instruction. This process will be described later in this disclosure with reference to the illustrative procedure of Fig. 3 described in more detail. It should be understood that although the assignment table 122 is shown to be located outside the prediction engine 102 in certain exemplary embodiments, the assignment table 122 may, however, be contained within the prediction engine 102.

[0029] At block 212, computer-executable instructions of the instruction execution engine 108 can be executed to perform the predicted load operation by setting the value in the physical register labeled at block 210 to another physical register that is currently mapped to the architecture-defined register 128. Referring again to the example presented earlier, the value stored in pR21 can be copied to physical register 30 (pR30), where pR30 is currently mapped to the architecture-defined register 128. In certain exemplary embodiments, various requirements may need to be met before the predicted load operation is performed. For example, a confidence value associated with the correlation between the predicted store instruction and the load instruction may need to meet a threshold to proceed with the predicted load operation.Furthermore, various dependency requirements between instructions may need to be met. These requirements are described later in this disclosure with reference to illustrative procedure 300. Fig. 3 described in more detail.

[0030] In certain exemplary embodiments, a checkload operation can be performed to verify that the predicted load operation resulted in the correct value being stored in the physical register currently allocated to architecture-defined register 128, thus ensuring that a consumer operation is processing the correct value. Specifically, computer-executable instructions of instruction execution engine 108 can be executed at block 214 to initiate the checkload operation by retrieving the value associated with architecture-defined register 128 from memory. As mentioned earlier, the value may have been stored in a memory location as a result of the execution of a memory instruction.Referring again to the example presented earlier, the value in pR21, which was stored by the memory instruction at a specific memory location [x], can be retrieved from that memory location [x].

[0031] At block 216, the retrieved value can be compared with the value stored in the physical register identified at block 210. If the values ​​differ, this may indicate that the predicted load operation resulted in the incorrect value being stored in the physical register currently mapped to architecture-defined register 128. Therefore, at block 218, the load instruction and all instructions in the instruction pipeline that are younger than the load instruction can be removed from the pipeline. The pipeline contents can be cleared in this way, particularly in an out-of-order machine, where instructions younger than the load instruction may have already been executed and potentially relied on the incorrect value stored in the physical register associated with the predicted storage instruction.After the pipeline contents have been cleared, the load instruction at block 220 can be executed by not performing the predicted load operation, but instead by retrieving the value belonging to the architecture-defined register 128 from memory. To ensure that the predicted load operation is not performed again, the algorithm can prevent the execution of a predicted load operation immediately after the pipeline contents have been cleared.

[0032] As with reference to the illustrative procedure 300 of Fig. As described in more detail in Section 3, in certain exemplary embodiments the results of the checkload operation can be used to update a confidence value that relates to the correlation between the predicted store instruction and the load instruction. For example, if the value retrieved from memory is equal to the value stored in the physical register that corresponds to the predicted store instruction (a positive finding at block 216), the confidence value can be increased. Conversely, the confidence value can be decreased if the values ​​are different (a negative finding). Furthermore, in certain exemplary embodiments, according to another means of confirming the accuracy of the data, only the predicted load operation can be performed, and the checkload operation can be omitted.

[0033] More precisely, instead of performing a checkload operation, mapping table 122 can be updated to reflect how values ​​stored in memory may change. Specifically, a mechanism can be provided to ensure that a predicted load operation is not performed if the contents in memory corresponding to a value in a physical register are modified by a processor core that stored the value in memory, or by another processor core. Such a mechanism might include providing the possibility for a processor core to be granted exclusive rights to store data in a particular memory location or range of memory locations.

[0034] For example, suppose that a multithreaded program is running on two processor cores—core A and core B. Further suppose that core A has exclusive rights to write to memory location x, but core B needs the ability to write to the same memory location. Assume, moreover, that a memory instruction and a load instruction are executed on core A (referred to below as memory instruction A and load instruction A), and that a memory instruction and a load instruction are executed on core B (referred to below as memory instruction B and load instruction B). Core A can execute memory instruction A to store an initial value at memory location x. Core B can then execute memory instruction B, resulting in a second, different value being stored at memory location x.If, instead of the load instruction A, a predicted load operation were performed, the first value from a physical register would be retrieved, not the correct desired value (i.e., the second value stored at memory location x).

[0035] If a processor core (e.g., core A) no longer has exclusive rights to write to a specific memory location or range of memory locations, the entry in allocation table 122 corresponding to the memory instruction executed by that processor core (e.g., memory instruction A) can be updated to indicate that the entry has been invalidated. More precisely, a bit can be set or inverted to indicate that the value stored in the physical register identified by the entry in allocation table 122 is no longer valid. Referring to the example presented above, a predicted load operation would therefore not be performed on load instruction A, because if the correlated memory instruction input (e.g., the input for memory instruction A) were used to access an entry in allocation table 122, the entry would be invalidated.

[0036] The illustrative procedure 200 of Fig. Step 2 assumes that a predicted charging operation will be carried out. However, as mentioned previously, various parameters may need to be evaluated to determine whether the predicted charging operation can be performed. Fig. Figure 3 is a process flow diagram of an illustrative method 300 for determining whether a predicted load operation should be performed to avoid a memory access for a load instruction according to one or more exemplary embodiments of the disclosure.

[0037] Referring to the Fig. 1 and Fig. 3 in conjunction with each other, a data pair formation between a load instruction and a store instruction can be observed at block 302 using operand addresses 110 belonging to the load instruction and the store instruction. While an instruction address is a memory address that indicates a location in memory where a program instruction is stored, an operand address is a memory address that indicates a location in memory where data processed by a program instruction is stored. In certain exemplary embodiments, program instructions and data used by the program instructions can be stored in the same cache memory (e.g., a shared cache memory) or in different cache memories (e.g., an instruction cache memory and a data cache memory).

[0038] More precisely, block 302 provides access to a data pairing table 112. Data pairing table 112 can be indexed with at least part of the operand address of data belonging to a program instruction (e.g., a store instruction, a load instruction, etc.). When a store instruction is executed, data can be written to data pairing table 112. Specifically, an entry can be created in data pairing table 112 that stores at least part of an operand address belonging to the store instruction, along with an operand address tag (e.g., another part of the operand address belonging to the store instruction) and a store input for the store instruction.

[0039] Assuming 64-bit operand addresses, for example, where bit 0 is the most significant bit and bit 63 is the least significant bit, bits 54 to 63 can be used as the index. Theoretically, bits 0 to 53 could then be stored as the operand address tag. However, since data pairing table 112 is not a functional array but a performance array, a smaller number of bits (e.g., bits 32 to 53) can be used for the operand address tag to strike a balance between the acceptable amount of aliasing and the desired number of entries that data pairing table 112 can hold. This means that if a larger number of bits are used for the operand address tag, less aliasing occurs, but the data pairing table 112 also accepts a smaller number of entries, taking into account a total maximum range / bit budget for the table.Aliasing can occur when two entries in data pairing table 112 have the same operand address index and operand address tag, but correspond to different memory instructions. In this case, the incorrect memory instruction might be paired with a load instruction. Predicted load operations that result in the incorrect value being loaded into a physical register due to aliasing can be countered by performing a check load operation or any of the other exemplary mechanisms described previously.

[0040] Still referring to block 302, data pairing table 112 can be read using a portion of an operand address belonging to a load instruction. Specifically, the portion of the operand address belonging to the load instruction can be used to locate an entry in data pairing table 112 that has a matching operand address index. An operand address tag belonging to the load instruction can then be compared with the operand address tag stored in the matching entry. If the operand address tags match, a possible data pairing 112 between the load instruction and the store instruction can be identified.

[0041] In certain exemplary embodiments, data can be written to the data pairing table 112 for each memory instruction. That is, an entry can be created in the data pairing table 112 for each memory instruction, wherein the entry is indexed with at least a part of the operand address where the data from the memory instruction is stored in memory, and wherein the entry contains the input information (IA) of the memory instruction. However, in certain exemplary embodiments, data can be written to the data pairing table 112 in a power-off learning mode, according to which data cannot be written for every memory instruction.

[0042] In a case, for example, where repeated code (e.g., a loop) is included within a section of code containing predicted branches, a memory instruction may be encountered repeatedly within the loop. Therefore, it may not be necessary to create an entry for the memory instruction in the data pairing table 112 each time it is encountered, because an entry has likely already been created and the memory instruction in the prediction array 114 has probably already been paired with a load instruction. Thus, creating additional entries in the data pairing table 112 is unlikely to provide any additional learning benefit. However, in certain exemplary embodiments, where a loop is present in a section of code containing predicted branches, limited content may still be captured for training purposes.For example, in data pairing table 112, an entry can be created for 1 out of 10 memory instructions. The preceding discussion regarding power-off learning applies equally to constant load operations.

[0043] At block 304, the data pairing between the store instruction and the load instruction can be stored as an entry in a prediction array 114. The data pairing can be stored together with a confidence value that reflects a degree of confidence associated with the pairing. More precisely, the confidence value can indicate a degree of confidence that the execution of the load instruction will result in the retrieval of an identical value from a memory location that was stored at the memory location as a result of the execution of the store instruction that is paired with the load instruction.

[0044] In certain exemplary embodiments, an existing branch prediction structure, such as a branch target buffer (BTB) table, can be used to store data that would otherwise be stored in prediction array 114. The BTB table can, for example, be indexed with the input information (IA) of a branch statement and store a target IA along with the branch IA. The target IA is the IA of a target statement to be executed when the branch is made. In certain exemplary embodiments, each pair of branch IA and target IA can be stored as a single entry in the BTB table. In other exemplary embodiments, the BTB table can contain multi-associative entries, allowing multiple branches to be monitored within a given code block (e.g., a 64-byte code block).

[0045] In these exemplary embodiments, where multiple branches for a given code block can be monitored, a portion of the input instruction (IA) for each branch instruction that may be present in that code block can be shared across all these branch instructions. In a microarchitecture where IAs are represented using, for example, 64 bits, the shared tag can be a starting portion of the most significant bits (e.g., bits 0 to X). This shared tag can be stored only once in the back-to-back table for each branch instruction in the code block, and it can be stored together with a destination IA for each branch instruction and a tag to distinguish the branch instructions from one another (e.g., the least significant bits ((Y+1) to 63, to denote the offset within the code block, taking into account an index (X+1) to Y).This tag sharing frees up additional memory in the BTB table to store store and load IAs for a fixed total of bits. For example, if the BTB table can monitor up to three branch statements within a given code block, and there happen to be fewer than three branch statements within that code block, tag sharing between branch statements (which determines the number of branches to share tag bits) allows additional entries in the BTB table, not used for branch / destination IA mappings, to be used for load / store IA mappings. Specifically, the load IA can be stored instead of the branch IA, and the store IA instead of the destination IA.In this way, a combined BTB table can be managed that stores both pairs of branching and targeting instructions as well as pairs of loading and storing instructions, thereby eliminating the need to manage the separate prediction array 114.

[0046] An IA 116 can be identified at block 306. The IA 116 can be provided as input to the prediction engine 102. At block 308, computer-executable instructions of the prediction engine 102 can be executed to access the prediction array 114 using the IA 116 in order to determine a predicted memory IA 118 that corresponds to the IA 116. Specifically, the prediction array 114 can be indexed by using at least portions of instruction addresses. Thus, at least a portion of the IA 116 can be used to determine whether the prediction array 114 contains a data pair between the IA 116 and an IA belonging to a memory instruction. If such a data pair exists, the memory instruction can be treated as a predicted memory instruction corresponding to the instruction containing the IA 116.

[0047] In certain exemplary embodiments, the instruction can first be decoded using IA 116 to determine that it is a load instruction before IA 116 is used to access the prediction array 114. Accessing the prediction array 114 only when an instruction has been decoded and determined to be a load instruction may save power. However, this would likely also slow down program execution, since accesses to the prediction array 114 can only occur when an instruction has been decoded and determined to be a load instruction. In other exemplary embodiments, it may not be necessary to first decode the instruction to determine that it is a load instruction, and instead, the prediction array 114 can be accessed for each instruction that is retrieved.In such exemplary embodiments, however, a predicted load operation would only be performed if, upon decoding the instruction whose IA 116 is used to access the prediction array 114, it is finally determined that it is a load instruction.

[0048] In these exemplary embodiments, where the prediction array 114 is accessed before the instruction is decoded, it is possible to access the prediction array 114 at least partially simultaneously with the instruction retrieval (synchronous mode). Alternatively, if the prediction engine 102 is ahead of the instruction retrieval, the prediction array 114 can be accessed at least partially simultaneously with accesses to the BTB table (which usually occur before the instruction retrieval). The instruction retrieval can lag behind the prediction engine 102 if, for example, a cache error occurs in the L1 cache and the L2 cache must be accessed to retrieve the instruction. As another example, the instruction retrieval can lag behind the prediction engine 102 if the instruction retrieval must be performed in sequence, but the prediction array 114 can be accessed out of sequence.

[0049] In certain exemplary embodiments, an instruction identifier (e.g., a micro-op ID) belonging to the predicted memory instruction can be retrieved from prediction array 114 in addition to the predicted memory instruction's input ID. More precisely, an instruction can be divided into multiple micro-op IDs. For example, a memory instruction can actually comprise multiple memory operations, each with its own micro-op ID. The micro-op ID can be used to distinguish memory instructions within a multiple memory instruction, and it can further be used to identify the specific memory instruction within the multiple memory instruction that correlates with a load instruction.

[0050] At block 310, computer-executable instructions of the read / write engine 106 can be executed to access the mapping table 122 using the predicted memory input and / or the instruction identifier belonging to the predicted memory instruction 118, and to perform a read operation 120 to retrieve a corresponding matching entry in the mapping table 122. The matching entry stored in the mapping table 122, which corresponds to the predicted memory instruction, can contain any of the exemplary types of data described previously. Specifically, the matching entry in the mapping table 122 can be a virtual input tag belonging to the predicted memory instruction (e.g., at least part of the predicted memory instruction input 118); an instruction identifier (e.g.,a micro-op ID of the predicted memory instruction; an instruction identifier of a producer operation corresponding to the predicted memory instruction; and an identifier of the physical register that has stored (and is currently storing, as predicted) a value created / modified by the producer operation, such a value being copied to a memory location by the execution of the predicted memory instruction. It should be understood that actual values ​​stored in physical registers are not stored in the prediction array 114, but rather can be stored in a register file.

[0051] At block 312, computer-executable instructions from the prediction engine 102 can be run to determine whether one or more dependency requirements are met. An example dependency requirement is that the predicted load operation occurs after the producer operation has been executed. This can be determined by identifying an instruction identifier belonging to the producer operation in the register / dependency data 134 and comparing the instruction identifier of the producer operation with an instruction identifier belonging to the predicted load operation to ensure that the producer operation has already been executed. Another example dependency requirement is that the predicted store instruction is executed before a check load operation.This can also be determined by comparing an instruction identifier of the predicted memory instruction with an instruction identifier of the check load operation.

[0052] In response to a negative finding at block 312, procedure 300 can resume from block 312, where it again determines whether one or more dependency conditions are met. The determination at block 312 can be repeated until a positive finding is made that all dependency conditions are met. In response to a positive finding at block 312, procedure 300 can switch to block 314, where computer-executable instructions from prediction engine 102 can be executed to determine whether the confidence level reaches a threshold. Depending on the execution, a first value can reach a second value if the first value is greater than or equal to the second value, or if the first value is less than or equal to the second value.The decision at block 312 can be made to ensure that predicted load operations are only performed when the confidence level associated with the pair 112 of load instruction and predicted store instruction reaches a threshold, indicating a suitable level of confidence that a value stored in a physical register as a result of a producer operation belonging to the predicted store instruction is the same value that would be retrieved from memory when the load instruction is executed. This, in turn, indicates a suitable level of confidence that a consumer would process the correct value if a predicted load operation were performed, thus bypassing the execution of the actual load instruction.

[0053] In response to a positive detection at block 314, computer-executable instructions of the instruction execution engine 108 at block 316 can be executed to perform a predicted load operation, at least in part, based on the physical register identified in the matching entry in the mapping table 122. Specifically, another physical register 130, currently mapped to the architecture-defined register 128, can be identified from the register mapping table 138, and the predicted load operation can be performed to copy a value stored in the physical register identified in the matching entry in the mapping table 122 to the physical register 130 currently mapped to the architecture-defined register 128. Furthermore, arbitrary dependencies between registers can be identified from the register / dependency data 134.For example, the value to which the physical register identified in the matching entry in mapping table 122 is set may depend on the values ​​to which other physical registers are set.

[0054] In certain exemplary embodiments, the method 300 can switch from block 316 to block 318. Furthermore, in response to a negative detection at block 314, the method 300 can skip block 316 and switch directly to block 318. At block 318, computer-executable instructions of the instruction execution engine 108 can be executed to perform a checkload operation. As previously mentioned, a checkload operation can involve retrieving a value stored at a memory location specified by the load instruction and comparing the retrieved value with the value of the physical register used to perform the predicted load operation.

[0055] At block 320, the confidence level associated with the pair 112 of load instruction and predicted store instruction can be updated, at least in part, based on whether the check load operation matches the predicted load operation, or more precisely, whether the value retrieved from memory by the check load operation is equal to the value of the physical register used to perform the predicted load operation. If the values ​​do not match, the confidence level can be reduced, making it less likely that future predicted load operations will be performed for load instructions correlated with the predicted store instruction in the prediction array 114.Conversely, if the values ​​match, the confidence level can be increased, making it more likely that future predicted load operations will be performed for load instructions correlated with the predicted store instruction. It should be understood that the predicted load operation at block 316 will not be performed if a negative finding is made at block 314. However, the confidence level at block 320 can still be updated. Specifically, a prediction can still be made, even though a predicted load operation cannot be performed in the case of a negative finding at block 314. After the check load operation at block 318 has been performed, the confidence level at block 320 can then be updated based on whether the prediction was correct. If the prediction is correct, the confidence level can be increased.If the confidence level becomes strong enough, a predicted charging operation can eventually be carried out based on the forecast for the future.

[0056] Performing a predicted load operation according to exemplary embodiments of the disclosure improves instruction execution performance because it involves performing a register-to-register copy operation instead of a memory access. Register operations involve fewer execution cycles than memory accesses. Thus, a consumer operation is able to process a value stored in a physical register as a result of the predicted load operation without having to wait for the actual load instruction to perform a memory access and store the retrieved value in a physical register. Performing a predicted load operation according to exemplary embodiments of the disclosure also allows out-of-order instruction execution.Specifically, in an instruction queue, a more recent instruction that depends on the value belonging to an older load instruction in the queue can be executed while the check of the older load instruction is still waiting to complete, for example, when a predicted load operation is performed to obtain from a physical register the value that the more recent instruction needs for its execution.

[0057] In certain exemplary embodiments, a pattern table can be maintained and accessed to handle situations where a predicted load operation might result in an incorrect value because it is not clear which memory instruction can correlate with a load instruction. For example, suppose the following pseudocode represents conditional code that is executed: if x=1, execute a memory instruction at IA Y to store the value 1 at memory location [x], otherwise execute a memory instruction at IA Z to store the value 2 at memory location [x]. Consequently, different values ​​can be stored at memory location [x] depending on the result of the conditional (i.e., whether x=1 or not, and thus which memory instruction is executed). Further suppose that this conditional code is followed by a load instruction to load the contents of memory location [x] into a physical register.In this example, a predicted load operation might not be performed because the prediction array 114 associates a load IA with a single memory IA, and in this case, it is not clear which memory IA should be correlated with the load IA. This ambiguity is only resolved during program execution when the result of the conditional is known.

[0058] A pattern table, accessible in parallel with prediction array 114, can be used to handle such exemplary cases. The pattern table can store content similar to prediction array 114 (e.g., memory inputs), but it can be indexed differently. Specifically, the pattern table can be indexed using a hash of an input with a pattern representing long-term results of the conditional, while prediction array 114 can be indexed using an input (e.g., a load input). For example, the pattern can indicate the results of the last X number of branching instructions. The pattern can be represented using a global history vector (GHV), where each bit value in the GHV indicates whether a long-term branching instruction was executed.

[0059] While an IA (e.g., a load IA) can be used for indexing against prediction array 114 to attempt to identify the IA of a correlated instruction (e.g., a storage IA, the IA of a correlated load instruction, etc.), in certain exemplary embodiments, the IA can be hashed with a pattern (e.g., the GHV) to obtain a hash value that is used for indexing against the pattern table. If a match for the hash value exists in the pattern table, the corresponding IA stored in that matching entry in the pattern table (e.g., a storage IA, the IA of a correlated load instruction, etc.) can be used instead of the result obtained by accessing prediction array 114 (if any).

[0060] Exemplary embodiments of the disclosure have been described mainly in connection with the identification of store instructions that are correlated with load instructions. However, in certain exemplary embodiments, correlating a store instruction with a load instruction can be difficult. More precisely, in certain exemplary embodiments, a load instruction can be executed repeatedly to load a value from the same memory location (referred to herein as constant load operations). For example, the code currently being executed may contain a loop that necessitates the repeated execution of a constant load operation to load the same data from the same memory location multiple times.In such an exemplary case, the memory instruction that stored this data in this memory location may have been executed much earlier, making it difficult to correlate the memory instruction with the constant load operation.

[0061] In such exemplary embodiments, the data pairing table 112 can be effectively used to enable predicted load operations to be performed in conjunction with constant load operations. More precisely, the data pairing table 112 was previously described as a table that stores the input instructions (IAs) of memory instructions; however, load IAs can also be stored in the data pairing table 112 to enable the execution of predicted load operations in conjunction with constant load operations.If no match is found in data pairing table 112 when at least part of the operand address belonging to a load instruction is indexed according to table 112, a new entry can be created in data pairing table 112. This entry contains as its index at least part of the operand address belonging to the load instruction and stores the input information (IA) of the constant load operation. When the constant load operation is then executed again, a match may be found in data pairing table 112, and a load instruction-load instruction pair can be stored in prediction array 114. An entry in prediction array 114 can be referred to as either a load instruction-load instruction pair or a store instruction-load instruction pair, depending on the case.

[0062] In certain exemplary embodiments, a load instruction may depend on a store instruction that occurred significantly earlier, such that the physical register—whose value was stored in memory by the store instruction—can no longer hold the value required by the load instruction. Even if a predicted store instruction is obtained from the prediction array 114 based on the load instruction's instruction, in such exemplary embodiments either no entry corresponding to this predicted store instruction would be present in the mapping table 122, or the corresponding entry would be invalidated. In either case, a predicted load operation could not be performed using the physical register associated with the predicted store instruction.

[0063] An IA storage data array 136 can be provided to accommodate cases such as the one described above, where a physical register may have been reused or taken out of service between the time a store instruction is executed and the time a load instruction is to be executed, resulting in the invalidation of an entry in the mapping table 122 corresponding to the store instruction. The IA storage data array 136 can store data belonging to store instructions depending on the IAs associated with those storage instructions.

[0064] More precisely, the IA storage data array 136 can be indexed with a storage IA, and instead of storing, for example, an identifier of a physical register assumed to hold a value belonging to a memory instruction (as the allocation table 122 does), the IA storage data array 136 can store the corresponding value itself. Thus, when a memory instruction is executed, a value is written to a cache memory, and additionally, the value can also be stored in the IA storage data array 136 and indexed with the IA of the memory instruction. In this way, the IA storage data array 136 can serve as a backup for the allocation table 122.This means that if an entry corresponding to a memory IA in the mapping table 122 has been invalidated (indicating that the physical register marked in the entry no longer stores the correct value), the IA memory data array 136 can be accessed using the memory IA to attempt to locate an entry within the IA memory data array 136. If a matching entry is found in the IA memory data array 136, the data from the matching entry can be retrieved and used to perform a predicted load operation.

[0065] The IA storage data array 136 can have a larger storage capacity than the allocation table 122 (i.e., be able to hold more entries), but data may be written to the IA storage data array 136 later than to the allocation table 122. This is because a memory instruction must be executed for the data to be written to the IA storage data array 136, whereas data stored in a physical register, which is identified by an entry in the allocation table 122, can be available after the producer operation has been performed, without requiring the execution of a memory instruction.

[0066] Furthermore, in certain exemplary cases, an entry in the allocation table 122 may be invalidated, but the data previously stored in the physical register may not yet have been written to the IA memory data array 136. For example, a processor design may allow multiple memory instructions to be executed in parallel and the corresponding data to be queued for eventual storage in memory. However, writing to the IA memory data array 136 may be bandwidth-limited, resulting in a delay between the execution of memory instructions and the writing of data to the IA memory data array 136. In the case described above, there may therefore be a delay between the time an entry in the allocation table 122 is invalidated and the time an entry is created in the IA memory data array 136.In another exemplary case, an entry in the mapping table 122 may be invalidated and the data may also not be available in the IA storage data array 136 because the entry in the IA storage data array 136 may have been overwritten with data corresponding to a different storage instruction that has the same index as the storage instruction of interest (due to aliasing).

[0067] Whether a predicted load operation is performed in these exemplary cases, where an entry in the mapping table 122 is invalidated and the data of the physical register is not stored in the IA storage data array 136, can depend on the timing with which it is determined that a load operation is a predicted load operation. For example, if it is determined that a load instruction is a predicted load operation before the mapping table 122 and the IA storage data array 136 are accessed, and the entry in the mapping table 122 has been invalidated and there is no entry in the IA storage data array 136, the predicted load operation can still be performed, but it would result in incorrect data being loaded into a register, thus necessitating the deletion of the contents of a pipeline, as described previously.Conversely, if the mapping table 122 and the IA memory data array 136 are accessed before it is determined that a load instruction is a predicted load operation, the predicted load operation cannot be performed if the entry in the mapping table 122 has been invalidated and there is no entry in the IA memory data array 136. In certain exemplary embodiments, the former case is more likely if the prediction array 114 is accessed at least partially in parallel with the instruction retrieval, while the latter case is more likely if the prediction array 114 is accessed at least partially in parallel or dependently with the instruction decoding.

[0068] To reduce the delay between when a physical register is reused (e.g., an entry in the mapping table 122 is invalidated) and when the register value is written to the IA memory data array 136, the register value can be copied to the IA memory data array 136 after the regfile is invalidated in certain exemplary embodiments. Furthermore, the IA memory data array 136 can be read earlier in the instruction pipeline if additional time is required to access it.

[0069] In certain exemplary embodiments, data can be written to the IA storage data array 136 in conjunction with constant load operations. As previously described, if no matching operand address for a load instruction is found in the data pairing table 112 (e.g., no possible storage instruction for pairwise summarization with the load instruction), the IA of the load instruction can be written to the data pairing table 112. Then, when the constant load instruction occurs again, a match is detected in the data pairing table 112, and a load instruction-load instruction pairing is written to the prediction array 114, thus qualifying the load instruction for a prediction. At the point where the load instruction qualifies for a prediction, the data belonging to the load instruction can be written to the IA storage data array 136 and indexed with the IA of the load instruction.If the constant load instruction occurs again, the matching load IA can thus be obtained from the prediction array 114 and used to access the corresponding data in the IA storage data array 136 without having to access the mapping table 122.

[0070] Throughout this entire revelation, the terms "array" and "table" have been used. An array, for example, can be a data structure that is usually limited to one or two read ports, so that typically at most two read operations or one read and one write operation can be performed. A table can contain a larger group of data structures than an array. For example, a table can be a regfile with a larger number of ports than an array, which can be defined in any combination of read and write operations. An array can be more densely populated than a regfile.While certain data structures have been described as either an array or a table, it should be understood that the disclosure is not limited to these types of data structures and that instead any data structure described as an array or a table can be implemented using any suitable type of data structure.

[0071] Furthermore, in certain exemplary embodiments of the disclosure, the term "load instruction" or variants thereof may refer to a single load instruction. In other exemplary embodiments of the disclosure, the term "load instruction" may refer to a load operation that is one of several different micro-ops within a complex instruction that can be used in a Complex Instruction Set Computing (CISC) architecture. For example, an architecture may define an add instruction in which one of the values ​​being added is taken from memory. In such a case, the load instruction may be a micro-op within the add instruction.

[0072] Exemplary embodiments of the disclosure provide various technical features, effects, and / or improvements to the technology. For example, exemplary embodiments of the disclosure provide the technical effect of improved instruction execution performance. Exemplary embodiments of the disclosure also provide the technical effect of improved out-of-sequence instruction execution.These technical effects are achieved, at least in part, through the technical features of identifying an instruction that predictably correlates with a load instruction, obtaining data belonging to a producer operation corresponding to the predicted correlated instruction, and executing a predicted load operation that allows a consumer to use a value stored in a physical register, which is identified in the obtained data, while avoiding a memory access associated with executing the load instruction. The predicted correlated instruction can be a storage instruction or a load instruction (in the case of constant load operations).Further technical features include a prediction array indexed solely using input-only operations (IAs) of load instructions, the ability to predict constant load operations, the combination of the back-to-back table and the prediction array, the ability to perform check load operations, the provision of a pattern table and an IA storage data array to increase the number of opportunities to execute a predicted load operation, and so on. These technical features provide, at least in part, the technical effect of improved instruction execution performance, since copying data from one physical register to another requires fewer execution cycles than accessing a memory location and copying data stored at that memory location into a physical register.These technical features provide, at least in part, the technical effect of improving conventional out-of-sequence instruction execution, since they provide a variety of non-routine and non-conventional mechanisms for performing a predicted load operation. Consequently, the technical features described above and the resulting technical effect constitute an improvement in the functioning of a computer. It should be understood that the foregoing examples of technical features, technical effects, and improvements in the functioning of a computer and computer technology provided by exemplary embodiments of the disclosure are merely illustrative and not exhaustive.

[0073] One or more illustrative embodiments of the disclosure are described herein. Such embodiments serve only to illustrate the scope of this disclosure and are not intended to be limiting in any way. Consequently, variants, modifications, and equivalents of embodiments described herein also fall within the scope of this disclosure.

[0074] Fig. Figure 4 is a schematic representation of an illustrative data processing unit 400 configured to perform one or more exemplary embodiments of the disclosure. The Fig. The depicted unit architecture stack 100 can correspond to an illustrative configuration of the data processing unit 400. Although the unit 400 can be described here in the singular, it should be understood that multiple instances of the unit 400 can be provided and that the functionality described in connection with the unit 400 can be distributed across these multiple instances.

[0075] In an illustrative configuration, the Unit 400 can include one or more processors 402, one or more memory units 404 (referred to herein generically as the memory 404), one or more input / output (“I / O”) interface(s) 406, one or more network interfaces 408, and the data storage 410. The Unit 400 can also include one or more buses 412 that functionally connect various components of the Unit 400.

[0076] The bus(s) 412 may include at least one system bus and / or one memory bus and / or one address bus or one message bus, and it may allow the exchange of information (e.g., data (including computer-executable code), signaling, etc.) between different components of the Unit 400. The bus(s) 412 may, but are not limited to, include a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and so on.The 412 bus(s) can belong to any suitable bus architecture, including, but not limited to, an Industry Standard Architecture (ISA), a Micro Channel Architecture (MCA), an Enhanced ISA (EISA), a Video Electronics Standards Association (VESA) architecture, an Accelerated Graphics Port (AGP) architecture, a Peripheral Component Interconnects (PCI) architecture, a PCI Express architecture, a Personal Computer Memory Card International Association (PCMCIA) architecture, a Universal Serial Bus (USB) architecture, and so on.

[0077] Memory 404 can be used in Fig. Figure 1 depicts physical memory 102 and includes volatile memory (memory that retains its state when powered on) such as random-access memory (RAM) and / or non-volatile memory (memory that retains its state even when powered off) such as read-only memory (ROM), flash memory, ferroelectric RAM (FRAM), and so on. Persistent data storage, as used herein, may include non-volatile memory. In certain exemplary embodiments, volatile memory may provide faster read / write access than non-volatile memory. In certain further exemplary embodiments, certain types of non-volatile memory (e.g., FRAM) may provide faster read / write access than certain types of volatile memory.

[0078] In its various configurations, the 404 memory can incorporate several different types of memory, such as various types of static random-access memory (SRAM), various types of dynamic random-access memory (DRAM), various types of immutable ROM, and / or writable variants of ROM, such as electrically erasable programmable read-only memory (EEPROM), flash memory, and so on. The 404 memory can include main memory as well as various forms of cache memory, such as instruction cache, data cache, address translation buffers (TLBs), and so on. Furthermore, the cache memory, such as a data cache, can be a multi-level cache organized as a hierarchy of one or more cache levels (L1, L2, etc.).

[0079] Data Storage 410 may include removable and / or non-removable storage, including, but not limited to, magnetic storage, optical disk storage, and / or tape storage. Data Storage 410 may provide non-volatile storage of computer-executable instructions and other data. Storage 404 and Data Storage 410, removable and / or non-removable, are examples of computer-readable storage media (CRSM) as used herein.

[0080] The data memory 410 can store computer-executable code, instructions, or the like, which can be loaded into memory 404 and executed by processor(s) 402 to cause processor(s) 402 to perform or initiate various operations. The data memory 410 can also store data that can be copied into memory 404 for use by processor(s) 402 during the execution of computer-executable instructions. Furthermore, output data produced as a result of processor(s) 402 executing computer-executable instructions can first be stored in memory 404 and then copied to data memory 410 for non-volatile storage.

[0081] More specifically, datastore 410 can store one or more operating systems (O / S) 414 (which may include O / S 414 and may include one or more virtual O / S instances); one or more database management systems (DBMS) 416 configured to access memory 404 and / or one or more external datastores (not shown); and one or more program modules, applications, engines, computer-executable code, scripts, or the like, such as a prediction engine 418, a register-monitoring engine 420, a read / write engine 422, and an instruction-executing engine 424. Any of the components depicted as stored in datastore 410 can include any combination of software, firmware, and / or hardware. The software and / or firmware can contain computer-executable instructions (e.g.,include computer-executable program code) that can be loaded into memory 404 for execution by one or more of the processor(s) 402 to perform any of the operations previously described in connection with appropriately named engines.

[0082] Although in Fig. Not shown in Figure 4, data memory 410 can also store various types of data used by components of unit 400 (e.g., data pairs 112, prediction array 114, mapping table 122, IA storage data array 136, etc.). Any data stored in data memory 410 can be loaded into memory 404 for use by processor(s) 402 when executing computer-executable instructions. Furthermore, any data stored in data memory 410 may be stored in external data memory(s) and accessed via DBMS 416, and loaded into memory 404 for use by processor(s) 402 when executing computer-executable instructions.

[0083] The processor(s) 402 can be configured to access the memory 404 and execute computer-executable instructions loaded therein. For example, the processor(s) 404 can be configured to execute computer-executable instructions of the various program modules, applications, engines, or the like of the unit 400 to initiate or simplify the performance of various operations according to one or more embodiments of the disclosure. The processor(s) 402 can include any suitable processing unit capable of accepting data as input, processing the input data according to stored computer-executable instructions, and producing output data.The Processor(s) 402 may include any suitable processing unit, including, but not limited to, a central processing unit, a microprocessor, a Reduced Instruction Set Computer (RISC) microprocessor, a Complex Instruction Set Computer (CISC) microprocessor, a microcontroller, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a digital signal processor (DSP), and so forth. Furthermore, the Processor(s) 402 may incorporate any suitable microarchitecture design including any number of subcomponents such as registers, multiplexers, arithmetic logic units, cache controllers for controlling read / write operations to / from the cache memory, branch prediction functions, or the like.The microarchitecture design of the 402 processor(s) can be capable of supporting any of a large number of instruction sets.

[0084] Referring to further illustrative components depicted as stored in data memory 410, the O / S 414 can be loaded from data memory 410 into memory 404 and provide an interface between other application software running on the unit 400 and hardware resources of the unit 400. More specifically, the O / S 414 can include a set of computer-executable instructions to manage hardware resources of the unit 400 and to provide general services to other application programs. In certain exemplary embodiments, the O / S 414 can include or otherwise control the execution of one or more of the program modules depicted as stored in data memory 410.The O / S 414 can include any operating system known today or that may be developed in the future, including, but not limited to, any server operating system, any mainframe operating system, or any other proprietary or non-proprietary operating system.

[0085] The DBMS 416 can be loaded into memory 404 and supports functionality for accessing, retrieving, storing, and / or manipulating data stored in memory 404, data stored in data store 410, and / or data stored in external data stores. The DBMS 416 can use any of a variety of database models (e.g., relational model, object model, etc.) and support any of a variety of query languages. The DBMS 416 can access data represented in one or more data schemas and stored in any suitable data repository. The external data stores that the Unit 400 can access via the DBMS 416 can include, but are not limited to, databases (e.g., relational, object-oriented, etc.).), file systems, unstructured files, distributed data storage where data is stored on more than one node of a computer network, peer-to-peer network data storage, or the like.

[0086] Referring to further illustrative components of Unit 400, the input / output (I / O) interface(s) 406 can facilitate the reception of input information by Unit 400 from one or more I / O units, as well as the output of information from Unit 400 to the one or more I / O units. The I / O units can include any of a variety of components, such as a display or screen with a touch-sensitive surface or touchscreen; an audio output unit for sound production, such as a loudspeaker; an audio capture unit, such as a microphone; an image and / or video capture unit, such as a camera; a haptic unit; and so on. Any of these components can be integrated into Unit 400 or be separate components.The I / O units can also include, for example, any number of peripheral units such as data storage units, printing units, and so on.

[0087] The I / O interface(s) 406 may also include an interface for an external peripheral device connection, such as a Universal Serial Bus (USB), FireWire, Thunderbolt, Ethernet port, or another connection protocol capable of connecting to one or more networks. The I / O interface(s) 406 may also include a connection to one or more antennas for connecting to one or more networks via a wireless local area network (WLAN) (such as Wi-Fi), Bluetooth, and / or a wireless network radio, such as a radio capable of exchanging data with a wireless transmission network, such as a Long Term Evolution (LTE) network, WiMAX network, 3G network, etc.

[0088] The Unit 400 may also include one or more Network Interfaces 408, through which the Unit 400 can exchange data with any number of other systems, platforms, networks, units, and so on. The Network Interface(s) 408 can enable data exchange with, for example, one or more other units over one or more networks. Such a network or networks may include, but are not limited to, one or more different types of transmission networks, such as cable networks, public networks (e.g., the Internet), private networks (e.g., Frame Relay networks), wireless networks, mobile networks, telephone networks (e.g., a public telephone network), or any other suitable private or public packet-switched or circuit-switched networks.Such a network(s) may have any suitable associated data exchange area and may include, for example, global networks (e.g., the Internet), high-speed networks (MANs, metropolitan area networks), wide area networks (WANs, wide area networks), local area networks (LANs, local area networks), or personal area networks (PANs). Furthermore, such a network may include transmission links and associated network units (e.g., data layer switching units, routers, etc.) to transmit network traffic over any suitable type of medium, including, but not limited to, coaxial cable, twisted wire (e.g., twisted copper wire), fiber optic cable, a hybrid fiber coax (HFC) medium, a microwave medium, a radio frequency transmission medium, a satellite transmission medium, or any combination thereof.

[0089] It should be understood that the program modules that are in Fig. The descriptions of data storage units 410 and 410 are merely illustrative and not exhaustive, and processing described as supported by any particular module may alternatively be distributed across multiple modules, engines, or the like, or performed by a different module, engine, or the like. Furthermore, various program modules, scripts, plugins, application programming interfaces (APIs), or any other suitable computer-executable code, hosted locally on Unit 400 and / or on other data processing units accessible via one or more networks, may be provided to implement functionality provided by the data storage units described in the descriptions of the data storage units 410 and 410. Fig. 4 modules depicted, and / or to support additional or alternative functionality. Furthermore, functionality can be modularized in any suitable way such that processing described as being performed by a particular module can be performed by a group of any number of program modules, or functionality described as being supported by any particular module can be supported, at least in part, by another module. Furthermore, program modules supporting the functionality described herein can be executable across any number of units according to any suitable data processing model, such as a client-server model, a peer-to-peer model, and so on. Furthermore, any of the functionality described as being supported by any of the modules depicted herein can be executable by any group of program modules. Fig. The functionality supported by the 4 modules shown is described and can be implemented, at least partially, in hardware and / or firmware across any number of units.

[0090] It should further be understood that Unit 400 may include alternative and / or additional hardware, software, or firmware components beyond those described or illustrated, without deviating from the scope of the disclosure. In particular, it should be understood that software, firmware, or hardware components depicted as forming part of Unit 400 are for illustrative purposes only and that in various embodiments, some components may be absent or additional components may be provided. While various illustrative modules have been depicted and described as software modules stored in the data memory 410, it should be understood that functionality described as supported by the modules may be enabled by any combination of hardware, software, and / or firmware.It should also be understood that each of the aforementioned modules, in various embodiments, may represent a logical partitioning of supported functionality. This logical partitioning is depicted for the sake of simplicity and may not be representative of the structure of the software, hardware, and / or firmware used to execute the functionality. Consequently, it should be understood that functionality described as being provided by a particular module may, in various embodiments, be provided at least partially by one or more other modules.Furthermore, one or more of the illustrated modules may not be present in certain embodiments, while in other embodiments additional program modules and / or engines not illustrated may be present and may support at least part of the described functionality and / or additional functionality.

[0091] One or more operations of procedure 200 or procedure 300 can be performed by a unit 400, which has the capability described in Fig. The illustrated configuration shown in section 4, or more precisely, one or more program modules, engines, applications, or the like, that can be executed on such a unit. It should be understood, however, that such operations can be performed in conjunction with numerous other unit configurations.

[0092] The illustrative procedure of Fig. 2 or the illustrative procedure of Fig. The operations described and illustrated in Figure 3 can be performed in any suitable order as desired in various exemplary embodiments of the disclosure. Additionally, in certain exemplary embodiments, at least some of the operations can be performed in parallel. Furthermore, in certain exemplary embodiments, fewer, more, or different operations than those described in Figure 3 can be performed. Fig. 2 or Fig. The 3 steps shown will be carried out.

[0093] Although certain embodiments of the disclosure have been described, the person skilled in the art will recognize that numerous other modifications and alternative embodiments are within the scope of the disclosure. For example, any of the functionality or processing options described with reference to a particular system, system component, unit, or unit component can be performed by any other system, unit, or component. While various illustrative embodiments and architectures have been described according to the embodiments of the disclosure, the person skilled in the art will understand that numerous other modifications to the illustrative embodiments and architectures described herein are also within the scope of this disclosure.Furthermore, it should be understood that any operation, element, component, data, or the like described herein as being based on another operation, element, component, data, or the like may additionally be based on one or more further operations, elements, components, data, or the like. Consequently, the phrase "based on" or variations thereof should be interpreted as "based at least in part on".

[0094] The present disclosure may relate to a system, a process, and / or a computer program product. The computer program product may include a computer-readable storage medium (or media) on which computer-readable program instructions are stored to cause a processor to execute aspects of the present disclosure.

[0095] A computer-readable storage medium can be a physical unit capable of retaining and storing instructions for use by a system to execute instructions. For example, a computer-readable storage medium can be an electronic storage unit, a magnetic storage unit, an optical storage unit, an electromagnetic storage unit, a semiconductor storage unit, or any suitable combination thereof, without limitation. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), and erasable programmable read-only memory (EPROM).Flash memory), static random-access memory (SRAM), portable compact storage disk-read-only memory (CD-ROM), DVD (digital versatile disc), USB flash drive, floppy disk, a mechanically coded unit such as punched cards or raised structures in a groove on which instructions are stored, and any suitable combination thereof. A computer-readable storage medium shall not, in its use herein, be understood as volatile signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses guided by a fiber optic cable), or electrical signals transmitted by a wire.

[0096] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to individual data processing units or, via a network such as the internet, a local area network, a wide area network, and / or a wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission lines, wireless transmission, routing computers, firewalls, switching units, gateway computers, and / or edge servers. A network adapter card or network interface in each data processing unit receives computer-readable program instructions from the network and forwards them for storage on a computer-readable storage medium within the respective data processing unit.

[0097] Computer-readable program instructions for executing the steps of the present invention can be assembly instructions, ISA (Instruction Set Architecture) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., as well as conventional procedural programming languages ​​such as C or similar languages. The computer-readable program instructions can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server.In the latter case, the remotely located computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be established with an external computer (for example, via the internet using an internet service provider). In some embodiments, electronic circuits, including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), can execute the computer-readable program instructions by using state information from the computer-readable program instructions to personalize the electronic circuits to perform aspects of the present disclosure.

[0098] Aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams or charts of methods, devices (systems), and computer program products according to embodiments of the invention. It is pointed out that each block of the flowcharts and / or block diagrams or charts, as well as combinations of blocks in the flowcharts and / or block diagrams or charts, can be executed by means of computer-readable program instructions.

[0099] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a specialized computer, or another programmable data processing device to create a machine, such that the instructions executed via the processor of the computer or other programmable data processing device generate a means of implementing the functions / steps specified in the block(s) of the flowcharts and / or block diagrams or charts.These computer-readable program instructions may also be stored on a computer-readable storage medium capable of controlling a computer, programmable data processing device, and / or other units to function in a particular manner, such that the computer-readable storage medium on which instructions are stored has a manufactured product, including instructions that implement aspects of the function / step specified in the block(s) of the flowchart and / or block diagrams or charts.

[0100] The computer-readable program instructions can also be loaded onto a computer, other programmable data processing device, or other unit to cause the execution of a series of process steps on the computer or other programmable device or other unit in order to generate a process executed on a computer, such that the instructions executed on the computer, other programmable device, or other unit implement the functions / steps specified in the block(s) of the flowcharts and / or block diagrams or charts.

Claims

[1] A method performed by a computer to bypass a memory access for a load instruction, the method comprising: determining a predicted instruction address (IA) corresponding to a load IA associated with the load instruction, at least in part by accessing a first data structure indexed with IAs associated with load instructions; Using at least a portion of the predicted IA to: i) access a second data structure to determine a first physical register storing a value associated with the load instruction, or ii) access a third data structure instead of accessing the second data structure to obtain the value associated with the load instruction; and Performing a predicted load operation as part of the load instruction at least in part by setting a second physical register to the value associated with the load instruction. [2] The computer-implemented method of claim 1, wherein the predicted IA is a predicted memory IA associated with a memory instruction, and wherein accessing the second data structure comprises: Accessing an entry in the second data structure indexed with at least a portion of the predicted memory IA; Determining from the entry in the second data structure the first physical register corresponding to the predicted memory IA; and Obtain the value corresponding to the load instruction from the first physical register. [3] A computer-implemented method according to claim 1, further comprising: Determining a confidence value associated with the predicted IA; and Determine that the confidence level reaches a threshold. [4] The computer-implemented method of claim 1, wherein determining the predicted IA corresponding to the load IA associated with the load instruction comprises: Accessing an entry in the first data structure using at least a portion of the loading IA; and Mark the predicted IA from the entry in the first data structure. [5] A computer-implemented method according to claim 4, further comprising: Identifying a data pairing between the predicted IA and the load IA based at least in part on a match between a first operand address associated with the predicted IA and a second operand address associated with the load IA; and Creating the entry in the first data structure based at least in part on the data pairing. [6] The computer-implemented method of claim 4, wherein the first data structure is a branch prediction data structure. [7] The computer-implemented method of claim 1, wherein the predicted IA is a predicted constant load IA, and wherein accessing the third data structure to obtain the value associated with the load instruction comprises: Accessing an entry in the third data structure that is indexed with at least a portion of the predicted constant load IA; and Determine from the entry in the third data structure the value corresponding to the load instruction. [8] The computer-executed method of claim 1, wherein the load instruction is a first load instruction, the load IA is a first load IA, and the predicted IA is a first predicted IA, the method further comprising: Determining a second predicted IA corresponding to a second load IA associated with the second load instruction, wherein the determining comprises: Hashing the second load IA with a pattern to obtain a hash value; Using the hash value to index against a pattern table to identify a matching entry in the pattern table; and Determine the second predicted IA from the matching entry in the pattern table. [9] The computer-implemented method of claim 1, wherein the first data structure is indexed with a first set of load IAs and the third data structure is indexed with a second set of store IAs. [10] A system for bypassing a memory access for a load instruction, the system comprising: at least one memory storing computer-executable instructions; and at least one processor operatively connected to the at least one memory and configured to access the at least one memory to execute the computer-executable instructions to: determine a predicted instruction address (IA) corresponding to a load IA associated with the load instruction, at least in part by accessing a first data structure indexed with IAs associated with load instructions; use at least a portion of the predicted IA to: i) access a second data structure to determine a first physical register storing a value associated with the load instruction, or ii) access a third data structure instead of accessing the second data structure to obtain the value associated with the load instruction; and perform a predicted load operation as part of the load instruction, at least in part by setting a second physical register to the value associated with the load instruction. [11] The system of claim 10, wherein the predicted IA is a predicted memory IA associated with a memory instruction, and wherein the at least one processor is configured to access the second data structure by executing the computer-executable instructions to: access an entry in the second data structure that is indexed with at least a portion of the predicted memory IA; determine from the entry in the second data structure the first physical register corresponding to the predicted memory IA; and to get the value corresponding to the load instruction from the first physical register. [12] The system of claim 10, wherein the at least one processor is further configured to execute the computer-executable instructions to: determine a confidence value corresponding to the predicted IA; and determine that the trust value reaches a threshold. [13] The system of claim 10, wherein the at least one processor is configured to determine the predicted IA corresponding to the load IA associated with the load instruction by executing the computer-executable instructions to: access an entry in the first data structure using at least part of the loading IA; and to identify the predicted IA from the entry in the first data structure. [14] The system of claim 13, wherein the at least one processor is further configured to execute the computer-executable instructions to: to identify a data pairing between the predicted IA and the load IA based at least in part on a match between a first operand address associated with the predicted IA and a second operand address associated with the load IA; and to generate the entry in the first data structure based at least in part on the data pairing. [15] The system of claim 13, wherein the first data structure is a branch prediction data structure. [16] The system of claim 10, wherein the predicted IA is a predicted constant load IA, and wherein the at least one processor is configured to access the third data structure to obtain the value associated with the load instruction by executing the computer-executable instructions to: access an entry in the third data structure that is indexed with at least a portion of the predicted constant load IA; and to determine the value corresponding to the load instruction from the entry in the third data structure. [17] The system of claim 10, wherein the load instruction is a first load instruction, the load IA is a first load IA, and the predicted IA is a first predicted IA, and wherein the at least one processor is further configured to execute the computer-executable instructions to: determine a second predicted IA corresponding to a second load IA associated with the second load instruction, wherein determining comprises: Hashing the second load IA with a pattern to obtain a hash value; Using the hash value to index against a pattern table to identify a matching entry in the pattern table; and Determine the second predicted IA from the matching entry in the pattern table. [18] The system of claim 10, wherein the first data structure is indexed with a first set of load IAs and the third data structure is indexed with a second set of store IAs. [19] A computer program product for bypassing memory access for a load instruction, the computer program product comprising a non-volatile storage medium readable by a processing circuit, the storage medium storing instructions executable by the processing circuit to cause a method to be performed, the method comprising. determining a predicted instruction address (IA) corresponding to a load IA associated with the load instruction, at least in part by accessing a first data structure indexed with IAs associated with load instructions; Using at least a portion of the predicted IA to: i) access a second data structure to determine a first physical register storing a value associated with the load instruction, or ii) access a third data structure instead of accessing the second data structure to obtain the value associated with the load instruction; and Performing a predicted load operation as part of the load instruction at least in part by setting a second physical register to the value associated with the load instruction. [20] The computer program product of claim 19, wherein the predicted IA is a predicted memory IA associated with a memory instruction, and wherein accessing the second data structure comprises: Accessing an entry in the second data structure indexed with at least a portion of the predicted memory IA; Determining from the entry in the second data structure the first physical register corresponding to the predicted memory IA; and Obtain the value corresponding to the load instruction from the first physical register.

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