Semiconductor device

Abstract

Semiconductor device (10) comprising: a semiconductor chip (40) comprising a semiconductor substrate (42) and a surface electrode (44) provided on a surface of the semiconductor substrate (42); and a conductive disk (64), with a disc-shaped section (16); a first convex section (18) projecting from the conducting disk (64); and a second convex section (20) projecting from an end surface (18a) of the first convex section (18), wherein an end surface (20a) of the second convex section (20) is connected to the surface electrode (44), where a width (W2) of the end surface (20a) of the second convex section (20) is narrower than a width (W3) of a base section of the first convex section (18) on one side of the disk-shaped section (16), and a groove (80) extending along a circumference of the end surface (20a) of the second convex section (20) is formed in the end surface (18a) of the first convex section (18).

Description

Technical field

[0001] The technology disclosed herein relates to a semiconductor device. State of the art

[0002] A semiconductor device described in publication JP 2009-146950A comprises a semiconductor chip and a conductive disk. The semiconductor chip is provided with a semiconductor substrate and a surface electrode located on one surface of the semiconductor substrate. The conductive disk has a disc-shaped section and a convex section projecting from the disc-shaped section. An end surface of the convex section is connected to the surface electrode. The conductive disk functions as a terminal to allow current to flow in the semiconductor chip and also as a heat-distributing disk to dissipate heat from the semiconductor chip.

[0003] From German patent application DE 10 2012 211 424 A1, a semiconductor device is known, comprising a semiconductor chip with a semiconductor substrate and a surface electrode provided on a surface of the semiconductor substrate, and a conductive disk comprising a disk-shaped section and a convex section projecting from the disk-shaped section, wherein an end surface of the convex section is connected to the surface electrode. The width of the end surface of the convex section is narrower than the width of a base section of the convex section on one side of the disk-shaped section.

[0004] Publication JP 2013 - 123 016 A also discloses a similar semiconductor device. Here, the convex section protrudes from the bottom of a recess incorporated into the conductive disk.

[0005] Publication JP 2013 - 149 695 A relates to a thermally conductive element, which acts as a heat conduction path generated by a heat-generating body, such as an element, and a semiconductor device provided with the thermally conductive element, and in particular a thermally conductive element, such as a conduction frame and a heat sink, and a semiconductor device provided with the thermally conductive element. A conductive disk can serve as a current conductor, and the surface of a convex section has a narrower width than the base of the convex section. Summary of the invention: Technical problem

[0006] If, in a semiconductor device with a configuration similar to that described in JP 2009-146950A, the convex section protrudes beyond the surface electrode onto a connected surface between the convex section and the surface electrode, it is likely that a high voltage is applied to the surface electrode. Therefore, it is necessary to narrow the width of the convex section.

[0007] Furthermore, when the semiconductor chip is subjected to energy, heat generated within the semiconductor chip is transferred via the convex section to the disk-shaped section. If, at this time, the width of the convex section is narrow, it is less likely that the heat will be transferred from the semiconductor chip to the disk-shaped section, and it may not be adequately distributed from the semiconductor chip. Taking this into account, the disclosure herein proposes a semiconductor device that can distribute heat from a semiconductor chip more effectively. It is the object of the invention to provide such a semiconductor device.

[0008] The object of the invention is achieved by a semiconductor device according to claim 1 or claim 2. An advantageous embodiment is the subject of claim 3. Solution to the technical problem

[0009] A semiconductor device disclosed herein may comprise: a semiconductor chip with a semiconductor substrate and a surface electrode provided on a surface of the semiconductor substrate; and a conductive disk. The conductive disk may comprise a disk-shaped section and a convex section projecting from the disk-shaped section. An end surface of the convex section may be connected to the surface electrode. The width of the end surface of the convex section may be narrower on one side of a disk-shaped section than the width of a base section of the convex section.

[0010] In this semiconductor device, the width of the end surface of the convex section is narrower than the width of the base of the convex section. Because the width of the end surface of the convex section is narrow, it prevents the end surface of the convex section from protruding beyond the surface electrode at its connected surface when the end surface of the convex section is connected to the surface electrode. Therefore, the convex section can be properly connected to the surface electrode, and it prevents a large voltage from being applied to the surface electrode. Furthermore, because the width of the convex section is wider at the base than at the end surface, heat generated in the semiconductor chip is transferred within the convex section, distributing radially from the end surface to the base surface.Even if the width of the end surface is narrow, the heat is effectively transferred to the disk-shaped section. Therefore, in this semiconductor device, heat can be dissipated from the semiconductor chip more efficiently than with known techniques. Brief description of the drawings The Fig. 1 is a top view of a semiconductor device; The Fig. 2 is a cross-sectional view of line II-II in the Fig. 1; The Fig. 3 is a cross-sectional view along a line III-III in the Fig. 1; The Fig. Figure 4 is a cross-sectional view of a semiconductor device of a variant according to the Fig. 2; The Fig. Figure 5 is a cross-sectional view of a semiconductor device of a variant according to the Fig. 2; The Fig. Figure 6 is a cross-sectional view of a semiconductor device of a variant according to the Fig. 2; The Fig. Figure 7 is a cross-sectional view of a semiconductor device of a variant according to the Fig. 2; The Fig. Figure 8 is a cross-sectional view of a semiconductor device of a variant according to the Fig. 3; The Fig. Figure 9 is a perspective exploded view of a semiconductor device of one variant; The Fig. Figure 10 is a perspective view of a management frame; The Fig. Figure 11 is an enlarged top view of a main connection of the conductor frame; The Fig. Figure 12 is a cross-sectional view along a line XI-XI in the Fig. 10, Fig. 11; The Fig. 13 is a cross-sectional view along a line XII-XII in the Fig. 10, Fig. 11; The Fig. 14 is a perspective view of the conduit frame with an attached die; The Fig. Figure 15 is an enlarged top view of the main connection with the attached die according to the Fig. 11; The Fig. Figure 16 is a cross-sectional view of the conductor frame with the attached die according to the Fig. 12; The Fig. Figure 17 is a cross-sectional view of the conductor frame with the attached die according to the Fig. 13; The Fig. Figure 18 is an enlarged top view of a semiconductor chip and the conductor frame after positioning according to the Fig. 11; The Fig. Figure 19 is a cross-sectional view of a semiconductor chip and the conductor frame after positioning according to the Fig. 12; The Fig. Figure 20 is a cross-sectional view of the semiconductor chip and the conductor frame after positioning according to the Fig. 13; The Fig. Figure 21 shows a cross-sectional view of the semiconductor chip and the conductor frame after a backflow according to the Fig. 12; The Fig. Figure 22 shows a cross-sectional view of the semiconductor chip and the conductor frame after a backflow according to the Fig. 13; The Fig. Figure 23 is a cross-sectional view of a semi-finished product after a conductive disk (manual connection) has been connected, according to the Fig. 12; The Fig. Figure 24 is a cross-sectional view of the semi-finished product after an insulating resin layer has been formed, according to the Fig. 12; The Fig. Figure 25 is a top view of the semi-finished product after the insulating resin layer has been formed; The Fig. 26 is a top view of a semiconductor device produced by a manufacturing process of one embodiment; The Fig. Figure 27 is an explanatory diagram of the manufacturing process; The Fig. 28 is an explanatory diagram for the known manufacturing process; The Fig. 29 is a top view of a semiconductor device manufactured by the known manufacturing process; The Fig. 30 is a cross-sectional view showing a plumb layer with a large misalignment; The Fig. Figure 31 is a top view showing the positioning of a convex section of a variant; The Fig. Figure 32 is a cross-sectional view showing the positioning of the convex section of the variant; The Fig. Figure 33 is a cross-sectional view showing the positioning of the convex section of another variant; The Fig. Figure 34 is a cross-sectional view showing the positioning of the convex section of the other variant; The Fig. Figure 35 is a top view showing a positioning of the convex section of one or another variant; The Fig. Figure 36 is a top view showing the positioning of a convex section of a variant; The Fig. Figure 37 is a top view showing the positioning of a convex section of another variant; The Fig. Figure 38 is a top view showing the positioning of a convex section of yet another variant; The Fig. Figure 39 is a top view showing the positioning of a convex section of a variant; The Fig. Figure 40 is a top view showing the positioning of a convex section from another variant; The Fig. Figure 41 is a top view showing the positioning of a convex section of yet another variant; The Fig. Figure 42 is a top view showing the positioning of a convex section of a variant; The Fig. Figure 43 is a top view showing the positioning of a convex section from another variant; The Fig. Figure 44 is a cross-sectional view showing the positioning of a concave section of yet another variant. Description of embodiments

[0011] A semiconductor device 10 according to a in the Fig. The embodiment shown in Figure 1 has two semiconductor chips 40 and 41, conductive disks 60 to 64, signal terminals 26, and an insulating resin 70. Each of the semiconductor chips 40 and 41 contains a switching element (for example, an IGBT (Insulated Gate Bipolar Transistor)). The semiconductor chip 41 is mounted on an upper surface of the conductive disk 62. The semiconductor chip 40 is mounted on an upper surface of the conductive disk 64. A plurality of signal terminals 26 are connected to each of the semiconductor chips 40 and 41. The conductive disk 61 is connected to an upper surface of the semiconductor chip 41. The conductive disk 61 is connected to the conductive disk 63. The conductive disk 60 is connected to an upper surface of the semiconductor chip 40. The conductive disk 60 is connected to the conductive disk 62. The semiconductor chips 40 and 41 are sealed by the insulating resin 70.Portions of the conductive disks 62, 63, and 64 project to the outer surface of the insulating resin 70 and configure terminals 28a, 28b, and 28c, respectively. A portion of each signal terminal 26 also projects to the outer surface of the insulating resin 70. The semiconductor device 10 of this embodiment is characterized by a connection structure between the semiconductor chip 40 and the conductive disk 64, and a connection structure between the semiconductor chip 41 and the conductive disk 62. The connection structure between the semiconductor chip 40 and the conductive disk 64 is essentially the same as the connection structure between the semiconductor chip 41 and the conductive disk 62. Therefore, the connection structure between the semiconductor chip 40 and the conductive disk 64 will be described in detail below.

[0012] As from the Fig. 2 and Fig. As can be seen in Figure 3, the conductive disk 64 has a heat-dissipating disk 16 (disc-shaped section) and a convex section 17 that projects upwards from an upper surface 16a of the heat-dissipating disk 16. The convex section 17 has a first convex section 18 and a second convex section 20. The first convex section 18 projects upwards from the upper surface 16a of the heat-dissipating disk 16. The second convex section 20 projects upwards from an end surface 18a (upper surface) of the first convex section 18. As can be seen from the Fig. As can be seen in Figure 2, the width W2 of the end surface 20a (upper surface) of the second convex section 20 is narrower than the width W3 of the first convex section 18 (that is, the width of a base section of the convex section 17 on one side of the heat-dissipating disk 16). This is because the width of the convex section 17 narrows in a step-like fashion from the base section to the end surface 20a.

[0013] As from the Fig. 2 and Fig. As can be seen in Figure 3, the semiconductor chip 40 has a semiconductor substrate 42, an emitter electrode 44, a collector electrode 48, and signal electrodes 46. The semiconductor substrate 42 contains an IGBT. The emitter electrode 44 is located on a first surface (a lower surface in the Fig. 2 and Fig. 3) of the semiconductor substrate 42. The emitter electrode 44 covers a major part of the first surface of the semiconductor substrate 42. The majority of the signal electrodes 46 are provided on the first surface of the semiconductor substrate 42. Each signal electrode 46 is provided adjacent to the emitter electrode 44. The size of each signal electrode 46 is much smaller than the size of the emitter electrode 44. The collecting electrode 48 is located on a second surface (an upper surface in the Fig. 2 and Fig. 3) of the semiconductor substrate 42. The collecting electrode 48 covers an entire portion of the second surface. The semiconductor chip 40 is arranged such that the emitter electrode 44 is positioned above the end surface 20a of the convex section 17. The emitter electrode 44 is connected to the end surface 20a of the convex section 17 by a solder layer 50.

[0014] As from the Fig. As can be seen in Figure 3, each signal terminal 26 is provided such that its end section is located under the corresponding signal electrodes 46. Each signal terminal 26 is connected to its corresponding signal electrode 46 by a solder layer.

[0015] As from the Fig. 2 and Fig. As can be seen in Figure 3, the conductive disk 60 is positioned above the semiconductor chip 40. The conductive disk 60 is arranged such that a lower surface of it is located above the collecting electrode 48. The lower surface of the conductive disk 60 is connected to the collecting electrode 48 by a solder layer 52.

[0016] The insulating resin 70 covers the conductive disk 64, the solder layers 50, the semiconductor chip 40, the solder layer 52 and the conductive disk 60 except for a lower surface of the conductive disk 64 and an upper surface of the conductive disk 60.

[0017] The conductive disks 60 and 64 function as terminals to allow current to flow in the semiconductor chip 40 and also as heat-dissipating elements, drawing heat away from the semiconductor chip 40. When the potential of a gate terminal, which is one of the signal terminals 26, is raised above a threshold value, the semiconductor chip 40 (i.e., the IGBT) is switched on. If, in this state, a potential higher than that of the conductive disk 64 is applied to the conductive disk 60, a current flows through the semiconductor chip 40. When a current flows through the semiconductor chip 40, the semiconductor chip 40 generates heat. The heat generated in the semiconductor chip 40 is dissipated by the conductive disk 60 and the conductive disk 64. Arrows 90 in the Fig. Figure 2 denotes heat dissipation paths in the conductive disk 64. Since the convex section 17 of the conductive disk 64 has a shape whose width increases from the end surface 20a towards the side of the heat-dissipating disk 16, the heat is transferred as it spreads radially from the semiconductor chip 40 to the heat-dissipating disk 16, as indicated by arrows 90. Therefore, the heat is easily transferred to the heat-dissipating disk 16. Thus, in the semiconductor device 10 of the present embodiment, the heat can be effectively dissipated from the semiconductor chip 40.

[0018] As also from the Fig. As can be seen in Figure 2, since the convex section 17 has a shape whose width narrows from the base section (namely, from the side of the heat-dissipating disk 16) to the end surface 20a, the width W2 of the end surface 20a of the convex section 17 is narrower than a width W1 with the emitter electrode 44. Therefore, the solder layer 50 has a shape whose width narrows from one side of an emitter electrode 44 to one side of an end surface 20a. Because the solder layer 50 has such a shape, it is less likely that a high voltage will be applied to an edge of the emitter electrode 44. As described above, the width W2 of the end surface 20a of the convex section 17 is narrower than the width W1 of the emitter electrode 44, thus suppressing a voltage applied to the edge of the emitter electrode 44.

[0019] As described above, the convex section 17 in the semiconductor device 10 of the present embodiment has a shape whose width narrows from the base section (namely the side of the heat-dissipating disk 16) to the end surface 20a, thus ensuring adequate heat dissipation paths (namely arrows 90) and suppressing the voltage applied to the emitter electrode 44. Therefore, heat can be effectively dissipated from the semiconductor chip 40.

[0020] As from the Fig. As can be seen in Figure 4, the end surface 18a of the first convex section can be provided with a groove 80 extending along a circumference of the end surface 20a of the second convex section 20. The groove 80 can surround the end surface 20a. According to this configuration, excess solder can be absorbed by the groove 80. In one step, connecting the convex section 17 and the emitter electrode 44 via the solder layer 50, a large quantity of solder can be used. In this case, with the provided groove 80, excess solder flows into the groove 80. As a result, the excess solder can be prevented from adhering to an unintended section. As can also be seen in the Fig. As can be seen in Figure 5, the end surface 20a of the second convex section 20 can be provided with a groove 80 extending along the circumference of the end surface 20a. In this configuration, excess solder can also be absorbed by the groove 80.

[0021] As also from the Fig. As can be seen in Figure 6, the convex section 17 can have a chamfered shape whose width narrows from the base section (the side of the heat-dissipating disk 16) to the end surface 20a (that is, a shape whose width continuously narrows from the base section to the end surface 20a). In such a configuration, heat can also be transferred radially, as shown in the Fig. 2 is required.

[0022] As also from the Fig. As can be seen in Figure 7, the upper surface 16a of the heat-dissipating disk 16 can be provided with a groove 80 extending along an outer circumference of the convex section 17. The groove 80 can surround the end surface 20a. According to this configuration, excess solder can be absorbed by the groove 80.

[0023] In the Fig. 3. The signal terminals 26 are connected to the signal electrodes 46 by the solder layers 50. However, as can be seen from the Fig. As can be seen in Figure 8, the signal terminals 26 can be connected to the signal electrodes 46 by connecting wires 58.

[0024] Furthermore, the semiconductor device contains 10 of the Fig. 1. The semiconductor chips 40 and 41 are arranged side by side in a lateral direction (y-direction). However, as can be seen from the Fig. As can be seen in Figure 9, the convex section 17 can be provided in a semiconductor device having a stacked structure. In the Fig. In Figure 9, the conductive disk 60, the semiconductor chip 40, the conductive disk 64, the semiconductor chip 41, and the conductive disk 62 are stacked in their thickest direction. The convex section 17 is positioned on the upper surface of the heat-dissipating disk 16 of the conductive disk 64, and the emitter electrode 44 of the semiconductor chip 40 is connected to the end surface of the convex section 17. Furthermore, the convex section 17 is positioned on the upper surface of the heat-dissipating disk 16 of the conductive disk 62, and the emitter electrode 44 of the semiconductor chip 41 is connected to the end surface of the convex section 17. Even in this configuration, heat can be adequately dissipated from the semiconductor chips 40 and 41 through the convex sections 17. (Manufacturing process)

[0025] Next, a method for manufacturing a semiconductor device is described. A number of manufacturing processes are then described. The following sections describe... Fig. 2 and Fig. The semiconductor device shown in section 10 can be manufactured by some of the manufacturing processes described below. Furthermore, the semiconductor devices of the Fig. 4, Fig. 8 and Fig. 9. They can be manufactured by manufacturing processes in which some of the manufacturing processes described below are used. However, the semiconductor devices of the Fig. 2, Fig. 3, Fig. 4, Fig. 8 and Fig. 9. can be produced by other manufacturing processes.

[0026] The Fig. Figures 10 to 13 show a conductor frame 12 to be used in a manufacturing process of one embodiment. The conductor frame 12 is a component in which a plurality of terminals for connection to a semiconductor chip are interconnected. The conductor frame 12 comprises two chip base plates 14, the main terminals 28a to 28c, and the plurality of signal terminals 26. A semiconductor chip is connected to each of the chip base plates 14. The main terminals 28a and 28c are each connected to their corresponding chip base plates 14. The main terminal 28b is connected to the conductive disk 60 (combination terminal 60). The two chip base plates 14 are essentially identical with respect to their configurations and methods of use, and thus the following description focuses only on one of the chip base plates 14 (the chip base plate 14 on the right in the figure). Fig. 10) proceed.

[0027] The chip base plate 14 has the heat-dissipating disk 16, a convex positioning section 18 (the first convex section), and a projecting connecting section 20 (the second convex section 20). In the Fig. In Figure 11 and the subsequent enlarged top views, the convex positioning section 18 is hatched with oblique lines, and the projecting connecting section 20 is hatched with dots. The heat-dissipating disk 16 is a disk-shaped section that has a greater thickness than other sections of the conductor frame 12. Hereinafter, a direction of thickness after the heat-dissipating disk 16 is referred to as a z-direction, a direction perpendicular to the z-direction is referred to as an x-direction, and a direction perpendicular to both the x-direction and the z-direction is referred to as a y-direction. The convex positioning section 18 is a section that projects upward from the upper surface of the heat-dissipating disk 16. As can be seen from the Fig. As can be seen in Figure 11, in a view along the z-direction, the convex positioning section 18 is essentially square in shape. The projecting connecting section 20 is a section that projects further upwards from an upper surface of the convex positioning section 18. As can be seen from the Fig. As can be seen in Figure 11, the projecting connecting section 20 has a square shape in a view along the z-direction. As can be seen from the Fig. 11 and Fig. As can be seen in Figure 12, the majority of the signal connections 26 are arranged adjacent to one side of the projecting connecting section 20.

[0028] The corresponding signal connections 26 extend a long distance in the x-direction and are arranged with intervals between them in the x-direction. One end of each signal connection 26 is located above the heat-dissipating disk 16. A clearance is provided between the signal connections 26 and the chip base plate 14. As can be seen from the Fig. As can be seen in Figure 10, the signal terminals 26 are connected to each other by a pull rod 22. Furthermore, the signal terminals 26 are connected to the chip base plate 14 by the pull rod 22 and a suspension line 23. As can be seen in the Fig. As can be seen in Figure 11, the convex positioning section 18 is not arranged in a position where it is directed towards the signal terminals 26. Except at the position that is directed towards the signal terminals 26, the convex positioning section 18 is arranged to surround the projecting connecting section 20.

[0029] In the manufacturing process of the present embodiment, a first step is to attach a tool. In the step of attaching a tool, a tool (template) 30 is attached to the conductor frame 12, as shown in the Fig. As can be seen from 14 to 17. The tool 30 has a square ring shape as its cross-sectional form. As can be seen from the Fig. As can be seen in Figure 15, the tool 30 engages with the convex positioning section 18 in such a way that an inner circumferential surface 30a of the tool 30 comes into firm contact with an outer circumferential surface 18b of the convex positioning section 18. In doing so, the tool 30 is precisely positioned with respect to the guide frame 12. As can be seen in the Fig. 14 and Fig. As can be seen from Figure 16, a notch 30b is provided on a part of a lower surface of the tool 30. When the tool 30 is attached to the conductor frame 12, the notch 30b is positioned according to the majority of the signal terminals 26. Because the notch 30b is provided, the tool 30 does not come into contact with the signal terminals 26. As can be seen from the Fig. As can be seen in Figure 15, a clearance is provided between the tool 30 and the projecting connecting section 20. As can be seen from the Fig. 16 and Fig. As can be seen from Figure 17, the height of the tool 30 is higher than the height of the projecting connecting section 20.

[0030] The next step involves arranging a semiconductor chip. In this step, as shown in the... Fig. As can be seen from Figures 18 to 20, the semiconductor chip 40 is positioned within the tool 30. The tool 30 is in engagement with the semiconductor chip 40. First, the semiconductor chip 40 is described. As can be seen from the Fig. 19 and Fig. As can be seen in Figure 20, the semiconductor chip 40 has the semiconductor substrate 42, the emitter electrode 44, the signal electrodes 46, and the collector electrode 48. An IGBT (Insulated Gate Bipolar Transistor) is provided in the semiconductor substrate 42. The emitter electrode 44 and the signal electrodes 46 are located on the first surface of the semiconductor substrate 42 (a lower surface thereof in the Fig. 19 and Fig. 20) provided. Although only one signal electrode 46 from the Fig. As can be seen in Figure 19, the semiconductor chip 40 has several signal electrodes 46, corresponding to the number of signal terminals 26 (for example, 5). The signal electrodes 46 are located adjacent to the emitter electrode 44. The emitter electrode 44 is much larger than each signal electrode 46. The signal electrodes 46 include a gate electrode of the IGBT, a temperature sensing electrode, a current sensing electrode, a voltage sensing electrode, and similar components. A signal with a potential of the emitter electrode 44 as a reference potential is applied to the signal electrodes 46. Therefore, the potential difference between the signal electrodes 46 and the emitter electrode 44 is small. The collector electrode 48 covers a portion of the second surface of the semiconductor substrate 42 (one surface opposite the first surface, which is a top surface with fixed points 19 and 20).

[0031] In the step of arranging a semiconductor chip, the semiconductor chip 40 is inserted into the tool 30 from above, with the emitter electrode 44 oriented downwards. Therefore, the semiconductor chip 40 is positioned within the tool 30. As can be seen from the Fig. As can be seen in Figure 19, the semiconductor chip 40 is inserted such that the emitter electrode 44 is arranged above the projecting connecting section 20, and each signal electrode 46 is arranged above the end section of its corresponding signal terminal 26. At the same time, the solder layers 50 are inserted between the emitter electrode 44 and the projecting connecting section 20 and between each signal electrode 46 and its corresponding signal terminal 26. As can be seen from the Fig. As can be seen in Figure 18, in the view along the z-direction, a contour of the semiconductor chip 40 is slightly smaller than a contour (that is, the outer circumferential surface 18b) of the convex positioning section 18. Thus, the semiconductor chip 40 is slightly smaller than the inner circumferential surface 30a of the tool 30. For this reason, when the semiconductor chip 40 is positioned within the tool 30, the high load applied by the tool 30 is suppressed. Therefore, the failure or chipping of the semiconductor substrate 42 is suppressed. In the step of positioning a semiconductor chip, a circumferential surface of the semiconductor chip 40 is guided through the inner circumferential surface 30a of the tool 30, and thus the semiconductor chip 40 is positioned with respect to the tool 30. Specifically, the semiconductor chip 40 is positioned over the tool 30 with respect to the guide frame 12. Fig. The projecting connecting section 20 and the emitter electrode 44 are shown by dashed lines in Figure 18. As can be seen from the Fig. As can be seen in Figure 18, in the view along the z-direction, the entire upper surface of the projecting connecting section 20 is arranged within a contour of the emitter electrode 44. Using the tool 30, the emitter electrode 44 and the projecting connecting section 20 can be positioned precisely relative to each other, as shown in the Fig. 18 is evident.

[0032] Next, a remelting step is performed. In the remelting step, a stacked body that has been assembled as shown in the Fig. As can be seen from 18 to 20, the stack is passed through a remelting furnace. Therefore, the stack is heated once and then cooled to room temperature. When the stack is heated, the solder layers 50 melt. When the stack is then cooled, the solder layers 50 solidify. As can be seen from the Fig. 21 and Fig. As can be seen in Figure 22, the emitter electrode 44 is connected to the protruding connecting section 20 by the solder layer 50, and the signal electrodes 46 are also connected to their corresponding signal terminals 26 by the solder layers 50. After the remelting step, the tool 30 is removed from the conductor frame 12 and the semiconductor chip 40.

[0033] As from the Fig. As can be seen in Figure 23, the common terminal 60 (i.e., the conductive disk 60) is arranged above the semiconductor chip 40, and the common electrode 48 is connected to the common terminal 60 by the solder layer 52. The common terminal 60 is a wiring connection to the common electrode 48 and also serves as a heat-dissipating element for dissipating heat from the common electrode 48. Furthermore, the main terminal 28b is shown in the Fig. 10 is also connected to the collective connection 60.

[0034] As from the Fig. 24 and Fig. As can be seen in Figure 25, an insulating resin layer 70 is next formed by injection molding, covering the semiconductor chip 40. Sections of the corresponding connections that are linked to the semiconductor chip 40 are also covered by the insulating resin layer 70. Each of the signal connections 26 and each of the main connections 28a to 28c protrudes outwards from the insulating resin layer 70.

[0035] Next, the conductor frame 12 is cut outside the insulating resin layer 70 to remove a section marked with diagonal lines in the Fig. 25 is hatched (the pull rod 22, the suspension line 23, and similar components). For this reason, the signal connections 26 are separated from each other and also from the chip base plate 14. Furthermore, the main connections 28a to 28c are separated from each other. As a result, the Fig. 26 evident semiconductor device completed.

[0036] Next, a known method for fabricating a semiconductor device is described. In the known fabrication method, a conductor frame 112 is used in which a chip base plate 160 and signal connections 126 are integrated, as shown in the Fig. 27 is evident. As can be seen from the Fig. As can be seen in Figure 27, the conductor frame 112 is first mounted on a first tool 191. The conductor frame 112 is positioned relative to the first tool 191 by inserting a pin 191a of the first tool 191 into a bore 112a provided in the conductor frame 112. Next, a second tool 192 is mounted on the conductor frame 112. The second tool 192 is positioned relative to the first tool 191 by inserting the pin 191a of the first tool 191 into a bore 192a of the second tool 192. Next, a semiconductor chip 140 is positioned within a ring section 192b of the second tool 192. The semiconductor chip 140 has a semiconductor substrate 142, an emitter electrode 144, signal electrodes 146 and a collecting electrode 148. Here, the semiconductor chip 140 is arranged with the collecting electrode 148 facing downwards.The collecting electrode 148 is then connected to the chip base plate 160 via a solder layer 150. After the collecting electrode 148 has been connected to the chip base plate 160, the first tool 191 and the second tool 192 are removed.

[0037] Next, each signal electrode 146 of the semiconductor chip 140 is connected to its corresponding signal terminal 126 of the conductor frame 112 by a wire connection.

[0038] Next, an emitter terminal 114 is placed on a third tool 193, as shown in the Fig. As can be seen in Figure 28. The third tool 193 has a recess 193a, and the emitter terminal 114 is arranged in the recess 193a. The emitter terminal 114 is positioned relative to the third tool 193 by the recess 193a. Next, the component is attached to the third tool 193, in which the semiconductor chip 140 and the conductor frame 112 are connected. Here, the emitter electrode 144 of the semiconductor chip 140 is arranged above a protruding connecting section 114a of the emitter terminal 114. Here, the conductor frame 112 is positioned relative to the third tool 193 by inserting a pin 193b of the third tool 193 into the bore 112a of the conductor frame 112. Afterward, the emitter electrode 144 is connected to the protruding connecting section 114a via a solder layer 152. As from the Fig. As can be seen in Figure 29, the semiconductor chip 140 is then sealed in an insulating resin layer 170. After the insulating resin layer 170 has formed, the conductor frame 112 is cut on an outer side of the insulating resin layer 170 to remove a section marked with diagonal lines in the Fig. 29 is hatched (a pull rod, a suspension line, and similar components). The corresponding connections are then disconnected. Following the steps mentioned above, the fabrication of the semiconductor device is completed using the known method.

[0039] In the known method, a misalignment occurs between the emitter electrode 114 and the protruding connection section 114a, resulting from the cumulative misalignment between the first tool 191 and the conductor frame 112, between the first tool 191 and the second tool 192, between the second tool 192 and the semiconductor chip 140, between the third tool 193 and the emitter terminal 114, and between the third tool 193 and the conductor frame 112. Since many misalignment factors are present, the misalignment between the emitter electrode 144 and the protruding connection section 114a is likely to be large.If the misalignment between the emitter electrode 144 and the protruding connection section 114a is large, heat transfer to the emitter terminal 114 on a part of the semiconductor chip 140 becomes difficult, and that part of the semiconductor chip 140 may be exposed to a locally high temperature. Furthermore, if the misalignment between the emitter electrode 144 and the protruding connection section 114a is excessively large, the protruding connection section 114a may extend outwards beyond the emitter electrode 144, as shown in the diagram. Fig. As can be seen in Figure 30. In this case, the solder layer 152 splashes beyond the emitter electrode 144 and becomes overhanging. In this configuration, the insulating resin layer 170 penetrates a gap between the solder layer 152 and the semiconductor substrate 142. In this configuration, an excessively high voltage is applied to the solder layer 152 and the emitter electrode 144 due to the thermal expansion of the insulating resin layer 170 between the solder layer 152 and the semiconductor substrate 142, and thus the reliability of the solder layer 152 and the emitter electrode 144 is drastically reduced.

[0040] In contrast, in the embodiment's method, misalignments between the tool 30 and the guide frame 12, and between the tool 30 and the semiconductor chip 40, cause misalignment between the emitter electrode 44 and the protruding connection section 20. Due to the reduced number of misalignment factors, the misalignment between the emitter electrode 44 and the protruding connection section can be suppressed. Therefore, the heat dissipation performance of the semiconductor device can be stabilized during mass production. This prevents the production of semiconductor devices with poor heat dissipation performance. In particular, in the embodiment's method, the emitter electrode 44 is larger than the protruding connection section 20, as shown in the Fig. 18 is evident, and thus the occurrence of the from the Fig. 30 evident cases can be reliably prevented. Therefore, the reliability of the solder layer 50 and the emitter electrode 44 can be ensured.

[0041] Furthermore, the known method uses the conductor frame 112, in which the aggregate chip base plate 160 and the signal connections 126 are integrated. After the conductor frame 112 (that is, the one with diagonal lines in the Fig. 29 hatched sections) was cut, remaining sections 160a of the suspension line remain at positions exposed outside the insulating resin layer 170, as shown in the Fig. As can be seen in Figure 29. Since the remaining sections 160a of the suspension line are connected to the collector chip base plates 160, the signal terminals 126 (which have a potential essentially equal to that of the emitter) and the remaining sections 160a (which have a potential equal to that of the collector) exhibit a particularly large potential difference between them. Therefore, it is likely that creepage discharge occurs between the signal terminals 126 and the remaining sections 160a. For this reason, in the known method, notches 180 (recesses that ensure a greater creepage distance between the remaining sections 160a and the signal terminals 126) must be provided in a lateral surface of the insulating resin layer 170 between the remaining sections 160a and the signal terminals 126 to prevent creepage discharge.However, with the provided notches 180 there is a problem that an internal stress of the insulating resin layer 170 can become large, and can reduce the service life of the insulating resin layer 170 against cracking and the like.

[0042] In contrast, the embodiment of the method uses a conductor frame 12 in which each emitter chip base plate 14 and its corresponding signal connections 26 are integrated. After the conductor frame 12 (that is, the one with diagonal lines in the Fig. (25 hatched sections) was cut, remaining sections 23a of the suspension line 23 remain at exposed positions outside the insulating resin layer 70, as shown in the Fig. As can be seen in Figure 26. Since the remaining sections 23a are connected to their corresponding emitter chip base plates 14, the signal terminals 26 (which have a potential essentially equal to that of the emitter) and the remaining 23a (which have a potential equal to that of the emitter) exhibit a very small potential difference between them. Therefore, it is less likely that creepage will occur between the remaining sections 23a and the signal terminals 26. For this reason, no notch is required in a lateral surface of the insulating resin layer 70 between the remaining sections 23a and the signal terminals 26. Consequently, the lifetime of the insulating resin layer 70 against cracking is improved. Furthermore, since no notch is required, no offset is necessary between the signal terminals 26 and the signal electrode 46 along the Y-direction.For this reason, the suspension line 23 can be provided on both sides of each set of the majority of the signal terminals 26, and positional accuracy between the signal terminals 26 and the semiconductor chip 40 is improved.

[0043] Furthermore, the manufacturing process of the embodiment, as shown in the Fig. As can be seen in Figure 19, the projecting connecting section 20 extends upwards from the upper surface of the heat-dissipating plate 16, and the clearance is provided between the projecting connecting section 20 and the tool 30, thus ensuring a space between the signal electrodes 46 and the heat-dissipating plate 16. Therefore, wiring (i.e., the signal connections 26) for the signal electrodes 46 can be arranged in this space. Thus, the wiring for the signal electrodes 46 can be appropriately provided.

[0044] In the embodiment described above, the semiconductor chip 40 is positioned within the tool 30 after the tool 30 has been attached to the conductor frame 12. However, the tool 30 can also be attached to the conductor frame 12 after the semiconductor chip 40 has been positioned within the tool 30. It should be noted that in many cases, each of the steps is simply performed in the same order as described in the embodiment.

[0045] Furthermore, in the embodiment mentioned above, the projecting connecting section 20 and the convex positioning section 18 are continuous. However, as can be seen from the Fig. 31 and Fig. As can be seen in Figure 32, the convex positioning section 18 can be arranged in a position that is separated from the projecting connecting section 20.

[0046] Furthermore, in the embodiment mentioned above, the projecting connecting section 20 is higher than the convex positioning section 18.

[0047] However, as can be seen from the Fig. 33 and Fig. As can be seen in Figure 34, the projecting connecting section 20 and the convex positioning section 18 can have the same height.

[0048] Furthermore, in the aforementioned embodiment, the convex positioning section 18 is arranged around the projecting connecting section 20. However, as can be seen from the Fig. 35 and Fig. As can be seen in Figure 36, the convex positioning sections 18 can be discreetly arranged around the projecting connecting section 20. As long as the tool 30 can be positioned, the convex positioning section(s) 18 can be arranged in any way. Furthermore, in the embodiment mentioned above, the tool 30 has a ring shape. However, as can be seen in the Fig. As can be seen from 39 to 40, tool 30 can have a different shape than the ring shape. Fig. Figure 42 shows a configuration in which two semiconductor chips 40 and 41 (with two protruding connecting sections 20 corresponding to the semiconductor chips to be connected) are positioned by the tool 30. Even in these configurations, the conductor frame 12 and the semiconductor chip(s) 40 can be positioned relative to each other by the tool 30, which engages both of the positioning sections of the conductor frame 12 and the semiconductor chip(s) 40. As can also be seen from the Fig. As can be seen in Figure 43, the tool 30 can be a disc-shaped element provided with a square bore in it.

[0049] Furthermore, in the embodiment described above, the entire upper surface of the convex positioning section 18 is connected to the solder layer 50. However, a treatment of a surface that does not exhibit solder wettability (for example, a surface roughness treatment, etc.) can be performed on an outer circumferential section of the upper surface of the convex positioning section 18. In this configuration, a portion (a central section) of the upper surface of the convex positioning section 18 is connected to the solder layer 50. In this case, the portion of the upper surface of the convex positioning section 18 that exhibits solder wettability (i.e., the area connected to the solder) can be smaller than the emitter electrode 44.

[0050] Furthermore, in the embodiment mentioned above, the tool 30 is positioned by the convex positioning section 18. However, as can be seen from the Fig. As can be seen in Figure 44, a concave positioning section 19 can be provided instead of the convex positioning section 18. The tool 30 can be positioned by bringing an outer circumferential surface 30c of the tool 30 into contact with a lateral surface of the concave positioning section 19.

[0051] Some of the technical elements disclosed herein are listed below. It should be noted that the respective technical elements are independent of one another and are useful alone or in combination.

[0052] In one exemplary semiconductor device disclosed herein, the width of the convex section can taper in a step-like manner from the base section to the end surface. In another exemplary semiconductor device disclosed herein, the width of the convex section can taper continuously from the base section to the end surface.

[0053] In an exemplary semiconductor device disclosed herein, a groove extending along a circumference of the end surface may be provided in a surface of the convex section or in a surface of the disk-shaped section adjacent to the convex section.

[0054] If the end surface of the convex section is connected to the surface electrode of the semiconductor chip via solder, any excess solder is absorbed into the groove according to this configuration. As a result, it is prevented that the excess solder adheres to an unintended section.

[0055] In an exemplary semiconductor device disclosed herein, the semiconductor chip may include a signal electrode provided on the surface of the semiconductor substrate. Additionally, the semiconductor device may also include a signal terminal connected to the signal electrode. (Disclosure of the state of the art)

[0056] The manufacturing processes disclosed herein are described below in comparison to the prior art.

[0057] Publication JP 2009-146950A describes a semiconductor device in which a conductor frame has a protruding connection section, and the protruding connection section is connected to a main electrode of a semiconductor chip. The protruding connection section of the conductor frame provides space for signal wiring. The insertion of a positioning pin into the conductor frame prevents misalignment between the semiconductor chip and the conductor frame.

[0058] In a case involving the mounting of a conductor frame with a protruding connection section, as described in Publication JP 2009-146950A, misalignment can occur when the protruding connection section is soldered to a main electrode. If the position of the protruding connection section of the conductor frame is misaligned with respect to the main electrode of a semiconductor chip, heat transfer from the semiconductor chip to the conductor frame becomes difficult. As a result, the heat dissipation performance of the semiconductor device is degraded. In a method described in Publication JP 2009-146950A, the conductor frame must be provided with a hole into which a pin is inserted, thus hindering heat dissipation at the location of the hole.Therefore, the disclosure herein provides a method capable of positioning a conductor frame and a semiconductor chip relative to each other without impeding heat dissipation.

[0059] A method disclosed herein for manufacturing a semiconductor device connects a semiconductor chip to a conductor frame using a tool. The semiconductor chip may include a main electrode provided on a surface of the semiconductor chip. The conductor frame may include a protruding connecting section and a positioning section, and the positioning section may have at least one convex and one concave shape provided around the protruding connecting section.The procedure may include: engaging the tool with the positioning section in a state in which a clearance is provided between the protruding connecting section and the tool; engaging the tool with the semiconductor chip; and connecting the protruding connecting section to the main electrode of the semiconductor chip via a solder in a state in which the tool is engaged with the positioning section and the semiconductor chip.

[0060] In this manufacturing process, the tool engages with the positioning section of the lead frame, thus suppressing misalignment between the lead frame and the tool. Furthermore, the tool also engages with the semiconductor chip, thus also suppressing misalignment between the semiconductor chip and the tool. Therefore, the lead frame and the semiconductor chip are positioned relative to each other via the tool. Consequently, misalignment between the lead frame and the semiconductor chip is suppressed. In the state where the lead frame and the semiconductor chip are positioned relative to each other via the tool, as described above, the main electrode of the semiconductor chip is connected to the protruding connecting section of the lead frame by a solder joint.This method suppresses misalignment of the protruding connection section with respect to the main electrode, thus preventing a deterioration in the heat dissipation performance of the semiconductor device. Furthermore, in this method, the positioning section has a convex or concave shape, ensuring that heat dissipation is not impeded at the positioning section. Therefore, a semiconductor device with high heat dissipation performance can be stably manufactured using this method.

[0061] In an exemplary manufacturing process disclosed herein, the positioning section can have a convex shape. In the engaging tool with the positioning section, a lateral surface of the tool can be brought into contact with a lateral surface of the convex shape.

[0062] In an exemplary manufacturing process disclosed herein, the positioning section can have a concave shape. In the engaging tool with the positioning section, a lateral surface of the tool can be brought into contact with a lateral surface of the concave shape.

[0063] In an exemplary manufacturing process disclosed herein, in the state in which the tool is engaged with the positioning section and the semiconductor chip, in a viewing direction along a direction in which the semiconductor chip and the conductor frame are stacked, an entirety of a region of the protruding connecting section to which the solder is connected can be arranged within a contour of the main electrode.

[0064] This configuration prevents the solder connecting the main electrode and the protruding connecting section from having an overhanging shape.

[0065] In an exemplary manufacturing process disclosed herein, the engaging tool can be carried out with the semiconductor chip after the tool has been engaged with the positioning section.

[0066] In an exemplary manufacturing process disclosed herein, the main electrode can be an emitter electrode. Furthermore, the semiconductor chip can comprise a signal electrode provided on a surface where the emitter electrode is provided, and a collector electrode provided on a rear surface located on a side opposite the emitter electrode. Additionally, the conductor frame can comprise a main body with the protruding connecting section and the positioning section, and a signal terminal extending from the main body.This manufacturing process may also include connecting the signal terminal to the signal electrode; connecting a common terminal to the common electrode; forming an insulating resin layer covering the semiconductor chip after the protruding interconnect section, the signal terminal, and the common terminal have been connected to the semiconductor chip; and cutting off the signal terminal from the main body after the insulating resin layer has been formed.

[0067] After the signal terminal is cut from the main body, both the signal terminal and the main body are exposed to the outside of the insulating resin in this manufacturing process. However, since the signal terminal (i.e., the signal electrode) and the main body (i.e., the emitter electrode) have a small potential difference between them, it is less likely that leakage will occur between the signal terminal and the main body.

[0068] Furthermore, the disclosure herein provides a semiconductor device with high heat dissipation performance. This semiconductor device can comprise a semiconductor chip with a main electrode provided on a surface of the semiconductor chip and a conduction frame. The conduction frame can have a protruding connection section and a positioning section with at least one convex and one concave shape provided around the protruding connection section. The protruding connection section can be connected to the main electrode via a solder joint.

[0069] This semiconductor device can be manufactured using the aforementioned manufacturing processes. Since the positioning section has a convex or concave shape in this semiconductor device, heat dissipation at the positioning section is not impeded, and the semiconductor device provides high heat dissipation performance.

Claims

[1] Semiconductor device (10) comprising: a semiconductor chip (40) having a semiconductor substrate (42) and a surface electrode (44) provided on a surface of the semiconductor substrate (42); and a conductive disc (64), with a disc-shaped section (16); a first convex portion (18) projecting from the conductive disc (64); and a second convex portion (20) projecting from an end surface (18a) of the first convex portion (18), wherein an end surface (20a) of the second convex portion (20) is connected to the surface electrode (44), where a width (W2) of the end surface (20a) of the second convex portion (20) is narrower than a width (W3) of a base portion of the first convex portion (18) on one side of the disc-shaped portion (16), and a groove (80) extending along a circumference of the end surface (20a) of the second convex portion (20) is formed in the end surface (18a) of the first convex portion (18). [2] Semiconductor device (10) comprising: a semiconductor chip (40) having a semiconductor substrate (42) and a surface electrode (44) provided on a surface of the semiconductor substrate (42); and a conductive disc (64), with a flat surface (16a); and a convex portion (17) projecting from the flat surface (16a), wherein an end surface (20a) of the convex portion (17) is connected to the surface electrode (44), wherein a width (W2) of the end surface (20a) of the convex portion (17) is narrower than a width (W3) of a base portion of the convex portion (17) on one side of the disc-shaped portion (16), and a groove (80) extending along a circumference of the end surface (20a) of the convex portion (17) is formed in the flat surface (16a) adjacent to the convex portion (17). [3] The semiconductor device (10) according to claim 2, wherein a width of the convex portion (17) narrows continuously from the base portion to the end surface (20a).

Images