SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Abstract

Semiconductor device comprising: a semiconductor substrate (10) having a first main surface and a second main surface opposite to the first main surface, wherein the semiconductor substrate (10) comprises a first semiconductor region (2) of a second conductivity type, which is provided in a surface layer on one side of the first main surface of the semiconductor substrate (10); a second semiconductor region (1) of a first conductivity type, which is provided on one side of the second main surface of the semiconductor substrate (10), wherein the second semiconductor region (1) is a region of the semiconductor substrate (10) excluding the first semiconductor region (2); an element structure provided on the side of the first main surface of the semiconductor substrate (10) and having a pn junction between the first semiconductor region (2) and the second semiconductor region (1); an intermediate layer insulating film (13) provided on the first main surface of the semiconductor substrate (10) and covering the element structure, wherein the intermediate layer insulating film (13) comprises a first insulating film (11) provided on the first main surface of the semiconductor substrate (10), and a second insulating film (12) provided on top of the first insulating film (11) and consisting of an insulating material having an etching rate that is faster than an etching rate of an insulating material of the first insulating film (11) with respect to hydrofluoric acid or dilute hydrofluoric acid, a contact hole (14) that selectively opens the interlayer insulating film (13) to expose the first main surface of the semiconductor substrate (10), wherein the contact hole (14) comprises a lower section (14b) arranged in the first insulating film (11) and an upper section (14a) arranged in the second insulating film (12) and has a side wall with a step (14c) between the upper section (14a) and the lower section (14b), wherein a width (w1) of the upper section (14a) is greater than a width (w2) of the lower section (14b) in a direction parallel to the first main surface of the semiconductor substrate (10), wherein the upper section (14a) has an aspect ratio in the range of 0.5 to 1.5, wherein the lower section (14b) has an aspect ratio in the range of 0.5 to 1.5; a first metal film (15) which is provided along an inner surface of the contact hole (14), wherein the first metal film (15) exhibits high adhesion to the semiconductor substrate (10) and forms an ohmic contact with the semiconductor substrate (10); a second metal film (16) embedded in the contact hole (14) on top of the first metal film (15); and a first electrode (17) which is provided on the interlayer insulating film (13) and the second metal film (16) and is electrically connected to the first semiconductor area (2) via the second metal film (16) and the first metal film (15).

Description

TECHNICAL AREA

[0001] Embodiments of the invention relate to a semiconductor device and a method for manufacturing a semiconductor device. STATE OF THE ART

[0002] To improve the characteristics of a semiconductor device, a conventional approach is to refine unit cells (functional units of an element). A method for forming a contact plug by embedding a metal with high embedding properties, such as tungsten (W), in a contact hole of a micropattern and using the contact plug to form a contact (electrical contact) between a front electrode and a semiconductor substrate is known as a method for forming a micro unit cell (see, for example, patent document 1 (paragraphs 0015 to 0016). Fig. 1-1)).

[0003] In patent document 1, when connecting wiring layers stacked with an interlayer insulating film, a titanium film (Ti film) and a titanium nitride film (TiN film) are sequentially formed along the inner wall of a contact hole formed in the interlayer insulating film. Subsequently, a tungsten film is embedded onto the titanium nitride film in the contact hole by a reduction reaction using tungsten hexafluoride (WF6) and monosilane (SiH4) or hydrogen (H2).

[0004] A method for manufacturing a conventional semiconductor device is described. Fig. Figure 10 is a flowchart outlining a process for fabricating a conventional semiconductor device. First, a predetermined element structure is formed on one side of the front surface of a semiconductor substrate (semiconductor wafer) (step S101). Next, a high-temperature oxide film (HTO film) is formed on a front surface of the semiconductor substrate as the first layer of an interlayer insulating film (step S102).

[0005] Next, a silicon oxide film (SiO2 film) is formed on the front surface of the semiconductor substrate by means of a boron phosphosilicate glass film (BPSG film) or the like as the second layer of the interlayer insulating film (step S103). Next, a resist mask, in which contact hole formation areas are open, is formed on the interlayer insulating film as an etching mask to be used in a subsequent etching process (step S104).

[0006] Next, the interlayer insulating film is selectively removed by dry etching using the resist mask as a mask, thereby forming the contact holes (step S105). Each contact hole has a sidewall that is substantially orthogonal to the front surface of the semiconductor substrate and has a substantially rectangular cross-sectional shape with a uniform width in one depth direction. In a process in step S105, a natural oxide film forms on a silicon face (Si face) (contact formation site between a barrier metal and the semiconductor substrate) exposed in the contact holes.

[0007] Next, the resist mask is removed (step S106). As a pretreatment for a subsequent sputtering process, the natural oxide film formed during the process in step S105 is removed by a reverse sputtering process or wet setting using an aqueous solution of buffered hydrofluoric acid (BHF) (step S107). During the process in step S107, the cross-sectional shape of the contact holes is maintained in the state it was in after the process in step S105.

[0008] Next, a titanium film and a titanium nitride film are sequentially formed along the inner walls of the contact holes by sputtering to form the barrier metal (step S108). Then, curing (heat treatment) causes titanium atoms in the barrier metal and silicon atoms in the semiconductor substrate to react with each other to form titanium silicide, thereby creating an ohmic contact between the barrier metal and the semiconductor substrate (step S109).

[0009] Next, a tungsten film is formed on the titanium nitride film by a chemical vapor deposition (CVD) process, so that it is embedded in the contact holes (step S110). The tungsten film is then etched back, leaving it only on the titanium nitride film in the contact holes (step S111). Afterward, remaining parts, such as a front electrode, a p +-Collector area, a rear electrode is formed, thereby completing the semiconductor device.

[0010] Another method for forming a contact hole has been proposed, in which an opening (through hole) is formed in an intermediate insulating film in which a silicon oxide film and a PSG film are sequentially stacked, using a resist mask as a mask. After the opening width of the upper PSG film has been made wider than the opening width of the lower silicon oxide film by wet-setting with an aqueous solution of fluorinated hydrogen (BHF) to form the contact hole, the resist mask is then removed (see, for example, patent document 2 (paragraphs 0014 to 0016). Fig. 4 and Fig. 5) and patent document 3 (paragraphs 0014 to 0018, Fig. 1) Patent document 4 shows a semiconductor device comprising a first insulating film-like layer arranged on the semiconductor substrate and comprising a first contact hole; a contact pin arranged in the first contact hole; a first surface electrode extending over the first insulating film-like layer and the contact pin; a conductive layer; a second insulating film-like layer arranged over the conductive layer and comprising a second contact hole wider than the first contact hole; a side metal layer covering a corner section in the second contact hole and configured from the same type of metal as the contact pin; and a second surface electrode extending over the second insulating film-like layer and into the second contact hole, covering the side metal layer and configured from a different type of metal than the contact pin.A bonding plate is arranged in a portion of the second surface electrode on the bottom surface of the second contact hole. Furthermore, patent document 5 describes a manufacturing process for semiconductor devices in which a multilayer insulating film with different etch rates is applied to a substrate. More precisely, a contact hole is first formed by anisotropic etching and then subjected to an isotropic etching step. This creates a stepped sidewall, which improves the step coverage of the metallization. Patent document 6 discloses a trench MOSFET structure made of silicon carbide. The device uses an accumulation channel that is spaced from the trench wall by a p-base region to achieve a low on-resistance. Patent document 1: JP 2005- 302 752 A Patent document 2: JP H05-74 732 A Patent Document 3: JP S63-175 442 A Patent document 4: DE 10 2015 121 482 A1 Patent document 5: JP 2004- 266 082 A Patent document 6: US 2004 / 0 145 011 A1 REVELATION OF THE INVENTION PROBLEM TO BE SOLVED BY THE INVENTION

[0011] With conventional techniques (see Fig. 10) The following problems occur. Fig. Figures 11 to 14 are cross-sectional views of a conventional semiconductor device during manufacturing. Fig. Figures 11 to 14 do not show element structures in a semiconductor substrate 110. Fig. Figure 14 schematically represents a state of a tungsten film 106 as seen by a scanning electron microscope (SEM) after the process in step S110 in Fig. 10 and is filmed before a process in step S111. Fig. 11 to 14 are states during the processes in steps S105, S107, S108, S110 in Fig. 10.

[0012] As described above, in the process in step S105, the width w101 of a contact hole 104 is uniform in the depth direction ( Fig. 11) In the process in step S108, a barrier metal 105 grows partially thicker at the upper ends (edges between side walls of the contact hole 104 and a front surface of the semiconductor substrate 110) 104a of the contact hole 104. Therefore, a width w111 between facing sections of the barrier metal 105 at the upper ends 104a of the contact hole 104 is narrower than a width w112 between facing sections of the barrier metal 105 at a section 104c other than the upper ends 104a of the contact hole 104 ( Fig. 13) In the process in step S110, the tungsten film 106 grows on the barrier metal 105 on an inner wall of the contact hole 104 and mutually facing sections of a surface of the tungsten film 106 on the mutually facing side walls of the contact hole 104 come into contact with each other, thereby filling a gap between mutually facing sections of the tungsten film 106 on the side walls, thus filling the contact hole 104 with the tungsten film 106.

[0013] As described above, when the width w111 between the facing sections of the barrier metal 105 at the upper ends 104a of the contact hole 104 narrows, sections of the tungsten film 106 at the facing upper ends 104a of the contact hole 104 come into contact with each other beyond the sections of the surface of the tungsten film 106 at the facing side walls of the contact hole 104, thereby closing the contact hole 104. When the contact hole 104 is closed in this way, a cavity (void) 120 appears in the tungsten film 106 ( Fig. 14) Fluorine-based gas introduced into a reactor (chamber) during the formation of the tungsten film 106 is trapped in the cavity 120. Furthermore, the cavity 120 is positioned deep enough from the surface of the tungsten film 106 that it does not reappear on the surface of the tungsten film 106 after the etching of the tungsten film 106 in step S111. Therefore, the cavity 120 remains in the tungsten film 106 in a state containing the fluorine-based gas, even after the etching in step S111.

[0014] The fluorine-based gas trapped in cavity 120, which occurs in the tungsten film 106, adversely affects the reliability of the semiconductor device (product). In particular, problems arise such as corrosion of a front electrode (electrode, etc., containing aluminum (Al) as its main component: not shown) on the tungsten film 106 by the fluorine-based gas trapped in cavity 120, an increase in the size of cavity 120 due to expansion of the trapped fluorine-based gas, and the formation of a cavity in the front electrode, etc. Fig. 14 the cavity 120 is a section of the tungsten film 106 with a denser color than that of the tungsten film 106.

[0015] Furthermore, during the sputtering pretreatment in step S107, the natural oxide film, which becomes a resistive component if left in the semiconductor device, is removed. However, of an HTO film 101 and a BPSG film 102, which configure an interlayer insulating film 103, at a section 104b on the BPSG film 102, the sidewall of the contact hole 104 is removed and recessed by the sputtering pretreatment in step S107 ( Fig. 12) Consequently, the width w102 of section 104b of the contact hole 104 on the BPSG film 102 becomes wider than the width w101 when the contact hole 104 is formed. Therefore, the sputtering pre-treatment in step S107 is also a factor that causes the occurrence of the cavity 120 in the tungsten film 106.

[0016] The problems described above become more noticeable when the aspect ratio (= depth d101 of the contact hole 104 / width w101 of the contact hole 104) of the contact hole 104 increases. The contact hole 104 of a sample that is in Fig. Figure 14, which is schematically represented, has, for example, an essentially trapezoidal cross-sectional shape in which a width w101' (≈ 0.6 µm) between the upper ends 104a is defined as slightly wider than a width w103 (≈ 0.5 µm) of a lower side thereof. In this case, the width w101 of the contact hole 104 is the width w101' between the upper ends 104a of the contact hole 104. An embedding property of the tungsten film 106 with respect to the contact hole 104 is determined by the width w101' between the upper ends 104a of the contact hole 104. In other words, the width w101' between the upper ends 104a of the contact hole 104 is defined by the embedding property of the tungsten film 106 with respect to the contact hole 104. Fig. The schematically represented sample 14 represents an occurrence of the cavity 120 in the tungsten film 106 when the aspect ratio (= the depth d101 of the contact hole 104 / the width w101' between the upper ends 104a of the contact hole 104) of the contact hole 104 is approximately 1.6 (≈ 1 µm / 0.6 µm).

[0017] To solve the problems associated with the above conventional techniques, one object of the invention is to provide a semiconductor device and a method for manufacturing a semiconductor device that can facilitate size reductions and improve reliability. MEANS TO SOLVE THE PROBLEM

[0018] The present invention relates to a semiconductor device with the features of claim 1 and a method for manufacturing a semiconductor device with the features of claim 11. Advantageous embodiments are defined in the dependent claims.

[0019] Furthermore, the semiconductor device according to the invention is characterized in that, in the above invention, the cross-sectional shape of the section of the contact hole on the second insulating film is a trapezoidal shape with a width on one side in the direction of the first electrode that is wider than a width on one side in the direction of the first insulating film.

[0020] Furthermore, the semiconductor device according to the invention is characterized in that, in the above invention, the cross-sectional shape of the section of the contact hole on the first insulating film is a trapezoidal shape with a width on one side in the direction of the second insulating film that is wider than a width on one side in the direction of the semiconductor substrate.

[0021] Furthermore, the semiconductor device according to the invention is characterized in that, in the above invention, the width of the section of the contact hole on the first insulating film is in a range of 0.3 µm to 1.0 µm.

[0022] Furthermore, the semiconductor device according to the invention is characterized in that, in the above invention, the first insulating film is a silicon glass film.

[0023] Furthermore, the semiconductor device according to the invention is characterized in that, in the above invention, the first insulating film contains phosphorus or contains phosphorus and boron.

[0024] Furthermore, the semiconductor device according to the invention is characterized in that, in the above invention, the second insulating film is a high-temperature oxide film or a thermal oxide film.

[0025] Furthermore, the semiconductor device according to the invention is characterized in that, in the above invention, the first metal film contains titanium as the main component.

[0026] Furthermore, the semiconductor device according to the invention is characterized in that, in the above invention, the second metal film contains tungsten as the main component.

[0027] Furthermore, the semiconductor device according to the invention is characterized in that the above invention also includes a third semiconductor region and a second electrode. The third semiconductor region is in contact with the second semiconductor region and is provided in a surface layer on the second main surface of the semiconductor substrate. The second electrode is electrically connected to the third semiconductor region. The element structure comprises the first semiconductor region, a fourth semiconductor region, a gate insulating film, and a gate electrode. The fourth semiconductor region of the first conductivity type is selectively provided within the first semiconductor region. The gate insulating film is provided in contact with a section of the first semiconductor region between the second semiconductor region and the fourth semiconductor region.The gate electrode is located on the opposite side of the first semiconductor area to allow the gate insulation film to be inserted between them.

[0028] To solve the above problems and achieve one of the objectives of the invention, a method for manufacturing a semiconductor device according to the invention further comprises the following features. First, a process is carried out to form a first semiconductor region of a second conductivity type in a surface layer of a first main surface of a semiconductor substrate of a first conductivity type, and to form an elemental structure with a pn junction between the first semiconductor region and a second semiconductor region of the first conductivity type on one side of the first main surface of the semiconductor substrate, wherein the second semiconductor region is a section of the semiconductor substrate excluding the first semiconductor region. Next, a second process is carried out to form an intermediate insulating film covering the elemental structure on the first main surface of the semiconductor substrate.Next, a third process is carried out on the interlayer insulation film to form a resist film in which a predetermined section is open.

[0029] Next, a fourth process is carried out to selectively remove the interlayer insulating film and form a contact hole that selectively exposes the first major surface of the semiconductor substrate by performing etching using the resist film as a mask. Next, a fifth process is carried out to remove the resist film. Finally, a sixth process is carried out to remove a natural oxide film covering a portion of the first major surface of the semiconductor substrate exposed in the contact hole by performing wet sets using an aqueous solution containing hydrofluoric acid or a dilute hydrofluoric acid solution.Next, a seventh process is carried out to form a first metal film with high adhesion to the semiconductor substrate, forming an ohmic contact with the semiconductor substrate along an inner wall of the contact hole. Next, an eighth process is carried out to embed a second metal film on top of the first metal film in the contact hole.

[0030] Next, a ninth process is carried out to form a first electrode on the interlayer insulating film and the second metal film, and to electrically connect the first electrode to the first semiconductor region via the second metal film and the first metal film. The second process comprises: a process to form a first insulating film as an interlayer insulating film on the first main surface of the semiconductor substrate, and a process to form a second insulating film as an interlayer insulating film on top of the first insulating film, the second insulating film being formed from an insulating material with an etch rate that is faster than that of the first insulating film with respect to the aqueous solution.In the sixth process, a step is formed on a side wall of the contact hole by wet forming in a step-like shape, whereby a width of a section of the contact hole on the second insulating film is made wider than a width of a section on the first insulating film.

[0031] Furthermore, the method for manufacturing a semiconductor device according to the invention is characterized in that, in the sixth process of the above invention, the section of the contact hole on the first insulating film has an aspect ratio in a range of 0.5 to 1.5 by wet forming.

[0032] Furthermore, the method for manufacturing a semiconductor device according to the invention is characterized in that, in the fourth process of the invention above, the section of the contact hole on the second insulating film has an aspect ratio that is set in a range of 0.5 to 1.5.

[0033] Furthermore, the method for manufacturing a semiconductor device according to the invention is characterized in that, in the fourth process of the above invention, the contact hole is formed by anisotropic etching.

[0034] Furthermore, the method for manufacturing a semiconductor device according to the invention is characterized in that, in the fourth process of the above invention, the contact hole is formed by isotropic etching.

[0035] Furthermore, the method for manufacturing a semiconductor device according to the invention is characterized in that, in the fourth process of the above invention, the width of the section of the contact hole on the first insulating film is set such that it lies in a range of 0.3 µm to 1.0 µm.

[0036] Furthermore, the method for manufacturing a semiconductor device according to the invention is characterized in that, in the seventh process of the above invention, the first metal film is formed by a sputtering process.

[0037] Furthermore, the method for manufacturing a semiconductor device according to the invention is characterized in that, in the seventh process of the above invention, the first metal film is formed by a chemical vapor deposition process.

[0038] Furthermore, the method for manufacturing a semiconductor device according to the invention is characterized in that, in the above invention, the first insulating film is a silicon glass film.

[0039] Furthermore, the method for manufacturing a semiconductor device according to the invention is characterized in that, in the above invention, the first insulating film contains phosphorus or contains phosphorus and boron.

[0040] Furthermore, the method for manufacturing a semiconductor device according to the invention is characterized in that, in the above invention, the second insulating film is a high-temperature oxide film or a thermal oxide film.

[0041] Furthermore, the method for manufacturing a semiconductor device according to the invention is characterized in that, in the above invention, the first metal film contains titanium as the main component.

[0042] Furthermore, the method for manufacturing a semiconductor device according to the invention is characterized in that, in the above invention, the second metal film contains tungsten as the main component.

[0043] According to the present invention, by wet-setting the pre-processing for forming the first metal film, the width of a section of the contact hole in the second insulating film is made wider in a stepped manner than the width of a section in the first insulating film, thereby enabling a reduction in the aspect ratio of the contact hole. Consequently, even when a contact hole of a micro-pattern for unit cell size reductions is formed, the first metal film can be formed with a uniform thickness along the inner wall of the contact hole. Furthermore, the second metal film, which forms the contact plug, can be embedded in the contact hole on the first metal film without creating a void in the second metal film. EFFECT OF INVENTION

[0044] The semiconductor device and the method for manufacturing a semiconductor device according to the present invention achieve an effect insofar as size reductions can be facilitated and reliability can be improved. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a cross-sectional view of a structure of the semiconductor device according to one embodiment. Fig. Figure 2 is a flowchart outlining a method for manufacturing the semiconductor device according to the embodiment. Fig. Figure 3 is a cross-sectional view of the semiconductor device according to the embodiment during manufacturing. Fig. Figure 4 is a cross-sectional view of the semiconductor device according to the embodiment during manufacturing. Fig. Figure 5 is a cross-sectional view of the semiconductor device according to the embodiment during manufacturing. Fig. Figure 6 is a cross-sectional view of the semiconductor device according to the embodiment during manufacturing. Fig. Figure 7 is a cross-sectional view of the semiconductor device according to the embodiment during manufacturing. Fig. Figure 8 is a cross-sectional view of the semiconductor device according to the embodiment during manufacturing. Fig. Figure 9 is a cross-sectional view of another example of a state of the semiconductor device according to the embodiment during manufacturing. Fig. Figure 10 is a flowchart outlining a process for manufacturing a conventional semiconductor device. Fig. Figure 11 shows a cross-sectional view of the conventional semiconductor device during manufacturing. Fig. Figure 12 shows a cross-sectional view of the conventional semiconductor device during manufacturing. Fig. Figure 13 shows a cross-sectional view of the conventional semiconductor device during manufacturing. Fig. Figure 14 shows a cross-sectional view of the conventional semiconductor device during manufacturing. BEST WAY(S) TO IMPLEMENT THE INVENTION

[0045] Embodiments of a semiconductor device and a method for manufacturing a semiconductor device according to the present invention are described in detail with reference to the accompanying drawings. In this description and the accompanying drawings, layers and regions preceded by n or p indicate that the majority charge carriers are electrons or holes. Furthermore, + or - appended to n or p indicates that the impurity concentration is higher or lower, respectively, than in layers and regions without + or -. In the following description of the embodiments and the accompanying drawings, main sections that are identical are given the same reference numerals and are not described again. (Form of execution)

[0046] A structure of a semiconductor device according to one embodiment is described, using an insulated gate bipolar transistor (IGBT) as an example. Fig. Figure 1 is a cross-sectional view of a structure of the semiconductor device according to the embodiment. Fig. Figure 1 shows two unit cells of an active region (the region in which current flows when an element is in an ON state) that controls the current drive, while other unit cells adjacent to these unit cells and an edge termination region surrounding a perimeter of the active region are not shown (similarly in Figure 1). Fig. 3 to 9).

[0047] The edge termination region is a region between the active region and a side surface of a semiconductor substrate 10 and is part of an n'-type drift region (second semiconductor region) 1. It serves to mitigate an electric field on one side of the front surface of a chip and to withstand a breakdown voltage (withstand voltage). The breakdown voltage is a voltage limit at which no misfiring or destruction of a component occurs. For example, an edge termination structure such as a just-turn terminal extension (JTE) structure, a field limiting ring (FLR), a field plate, a RESURF, or the like is located in the edge termination region.

[0048] The semiconductor device according to the embodiment, which is in Fig. Figure 1 shows a trench-gate IGBT that includes a MOS gate (insulated gate formed by metal, an oxide film, and a semiconductor) of a trench-gate structure on one side of the front surface of the semiconductor substrate (semiconductor chip) 10. The MOS gate is defined by a p-type base region (first semiconductor region) 2, an emitter region of n + -type (fourth semiconductor region) 3, a contact region 4 from the p +-type, a trench 5, a gate insulating film 6, and a gate electrode 7. A unit cell is configured by a trench 5 and contacts (electrical contact sections between the semiconductor substrate 10 and an emitter electrode 17) adjacent on both sides of the trench 5. The p-type base region 2 is selectively provided in a surface layer on a front surface of the semiconductor substrate 10. Another section of the semiconductor substrate 10, besides the p-type base region 2, and a collector region of the p-type + -Type (third semiconductor region) 8, which are described below, is the drift region 1 of the n- - Type.

[0049] Emitter area 3 of n + -Type and contact area 4 from p +-Type are selectively formed in a surface region (the surface layer at the front surface of the semiconductor substrate 10) of the p-type base region 2. The emitter region 3 of the n + -Type and contact area 4 from p + The -type elements are in contact with each other. Trench 5 penetrates emitter area 3 from n. + -type and the base area 2 of the p-type and reaches the drift area 1 of the n- - Type. In trench 5, the gate electrode 7 is provided above the gate insulation film 6. The collector area 8 from p + A type of electrode is provided in a surface layer on a rear surface of the semiconductor substrate 10. A collector electrode (second electrode) 9 is provided on the rear surface of the semiconductor substrate 10 and is connected to the collector region 8 from the p + -Type electrically connected.

[0050] On the front surface of the semiconductor substrate 10, a high-temperature oxide film (HTO film) 11 and a BPSG film 12 are sequentially stacked as an interlayer insulating film 13, which covers the gate electrode 7. The interlayer insulating film 13 is provided across the entire front surface of the semiconductor substrate 10. The thickness of the HTO film 11 can, for example, be in the range of approximately 1000 Å to 2000 Å. The thickness of the BPSG film 12 can, for example, be in the range of approximately three to four times the thickness of the HTO film 11. Instead of the HTO film 11, a thermal oxide film can be used as the bottom layer of the interlayer insulating film 13. Instead of the BPSG film 12, a PSG film or a film made of undoped silicate glass (NSG) can be used as the top layer of the interlayer insulation film 13.

[0051] A contact hole 14, which penetrates the interlayer insulating film 13 in the depth direction, is provided in the interlayer insulating film 13. The depth direction is a direction from the front surface to the rear surface of the semiconductor substrate 10. The underside of the contact hole 14 can be accessed via the front surface of the semiconductor substrate 10 in the direction of a collector side (in the direction of the collector region 8 from p). +-type). In other words, a through-hole of the interlayer insulating film 13 and a groove formed on the front surface of the semiconductor substrate 10 and continuous with the through-hole can together form the contact hole 14. The contact hole 14 can be arranged in a striped pattern extending parallel to the front surface of the semiconductor substrate 10 or in a matrix-like pattern as viewed from the front surface of the semiconductor substrate 10.

[0052] Furthermore, the contact hole 14 has a cross-sectional shape in which the width w1 of a section 14a on the BPSG film 12 is wider than the width w2 of a section 14b on the HTO film 11. In other words, a single step 14c is provided on a side wall of the contact hole 14 at an interface between the HTO film 11 and the BPSG film 12, and the width of an upper end face of the contact hole 14 is wider than the width of a lower face of the contact hole 14 in a step-like shape due to the step 14c. An upper end of the contact hole 14 is an edge between a side wall of the contact hole 14 and the front surface of the semiconductor substrate 10.

[0053] The aspect ratio (= the depth d1 of section 14a of contact hole 14 on BPSG film 12 / the width w1 of section 14a of contact hole 14 on BPSG film 12) of section 14a of contact hole 14 on BPSG film 12 can, for example, lie in a range of approximately 0.5 to 1.5. One reason for this is as follows.

[0054] If the aspect ratio of section 14a of contact hole 14 on the BPSG film 12 is less than 0.5 and the contact hole 14 is filled with a tungsten film 16, a void will appear on an upper section of the tungsten film 16. Therefore, the tungsten film 16 in the contact hole 14 can also be removed (etched away) by back-etching to leave the tungsten film 16 only in the contact hole 14.

[0055] If the aspect ratio of section 14a of contact hole 14 on BPSG film 12 exceeds 1.5 and contact hole 14 is filled with tungsten film 16, sections of tungsten film 16 deposited on the front surface of semiconductor substrate 10 contact each other and are connected, thereby closing an upper section of section 14a of contact hole 14 on BPSG film 12 and a void may appear in tungsten film 16.

[0056] The aspect ratio (= the depth d2 of section 14b of contact hole 14 on the HTO film 11 / the width w2 of section 14b of contact hole 14 on the HTO film 11) of section 14b of contact hole 14 on the HTO film 11 can, for example, lie in a range of approximately 0.5 to 1.5. One reason for this is as follows.

[0057] If the aspect ratio of section 14b of contact hole 14 on HTO film 11 is less than 0.5 and section 14b of contact hole 14 on HTO film 11 is filled with the tungsten film 16, a void appears in the upper section of the tungsten film 16. This void has a large aspect ratio and is difficult to fill with the tungsten film 16. Therefore, if section 14a of contact hole 14 on BPSG film 12 is filled with the tungsten film 16, the void in the upper section of the tungsten film 16 at section 14b of contact hole 14 on HTO film 11 will not be filled and may remain as a void in the tungsten film 16.

[0058] If the aspect ratio of section 14b of the contact hole 14 on the HTO film 11 exceeds 1.5 and section 14b of the contact hole 14 on the HTO film 11 is filled with the tungsten film 16, the tungsten film 16 is furthermore readily deposited on a step (surface that is substantially parallel to the front surface of the semiconductor substrate 10) of step 14c on the side walls of the contact hole 14. Sections of the tungsten film 16 deposited on the steps of step 14c on the side walls of the contact hole 14 contact and bond together, thereby closing an upper section of section 14b of the contact hole 14 on the HTO film 11 and potentially creating a void in the tungsten film 16.

[0059] The aspect ratio (= depth d10 of the contact hole 14 / width w1 of section 14a of the contact hole 14 on the BPSG film 12) of the contact hole 14 is preferably in a range of approximately 0.5 to 1.5. One reason for this is the same as the reason that the aspect ratio of section 14a of the contact hole 14 on the BPSG film 12 can be set in the range described above.

[0060] The width w1 of section 14a of the contact hole 14 on the BPSG film 12 is preferably, for example, 0.5 µm or more and can be as wide as possible without causing contact with the adjacent contact hole 14. Consequently, the embedding property of the tungsten film 16 described below with respect to the contact hole 14 can be improved.

[0061] The width w2 of section 14b of the contact hole 14 on the HTO film 11 is preferably as narrow as possible. One reason for this is as follows: The trench 5 and the contact hole 14 are separated by a predetermined distance L, which suppresses the occurrence of a leakage current. Therefore, the predetermined distance L between the trench 5 and the contact hole 14 can be ensured, and the distance w11 between (mesa section) the trenches 5 is reduced, which allows for further reductions in the size of the unit cell.

[0062] In particular, the width (width of the underside of the contact hole 14) w2 of section 14b of the contact hole 14 on the HTO film 11 is, for example, in a range of approximately 0.3 µm to 1.0 µm. One reason for this is as follows. If the width w2 of section 14b of the contact hole 14 on the HTO film 11 is less than 0.3 µm, embedding the tungsten film (second metal film) 16 into section 14b of the contact hole 14 on the HTO film 11 via a barrier metal (first metal film) 15, which is described below, becomes difficult. If the width w2 of section 14b of the contact hole 14 on the HTO film 11 exceeds 1.0 µm, the emitter electrode (electrode containing aluminum as its main component: first electrode) 17, which is described below, can be embedded in section 14b of the contact hole 14 on the HTO film 11, thus making a contact plug formed by the tungsten film 16 unnecessary.

[0063] The cross-sectional shape of section 14a of the contact hole 14 on the BPSG film 12 can be rectangular, in which the side walls of the contact hole 14 are essentially orthogonal to the front surface of the semiconductor substrate 10. In other words, the width w1 of section 14a of the contact hole 14 on the BPSG film 12 can be uniform in the depth direction. In this case, reductions in the size of the unit cell are possible.

[0064] Furthermore, the cross-sectional shape of section 14a of the contact hole 14 on the BPSG film 12 is preferably a trapezoidal shape, in which a width in the direction of the emitter electrode 17 is wider than a width w1' in the direction of the HTO film 11. In this case, the width in the direction of the emitter electrode 17 corresponds to the width w1 of section 14a of the contact hole 14 on the BPSG film 12 if the cross-sectional shape of section 14a of the contact hole 14 on the BPSG film 12 is rectangular.

[0065] If the cross-sectional shape of section 14a of the contact hole 14 on the BPSG film 12 is trapezoidal, as described above, the width w1 of the emitter electrode 17 side of section 14a of the contact hole 14 on the BPSG film 12 is relatively wide, thus improving the embedding of the tungsten film 16 in the contact hole 14. Furthermore, the width w2 of section 14b of the contact hole 14 on the HTO film 11 is narrower, allowing the distance w11 between the grooves 5 to be reduced.

[0066] The cross-sectional shape of section 14b of the contact hole 14 on the HTO film 11 can be rectangular, in which the side walls of the contact hole 14 are essentially orthogonal to the front surface of the semiconductor substrate 10. In other words, the width w2 of section 14b of the contact hole 14 on the HTO film 11 can be uniform in the depth direction. In this case, reductions in the size of the unit cell are possible.

[0067] The cross-sectional shape of section 14b of the contact hole 14 on the HTO film 11 can be trapezoidal, in which a width w2' in the direction of the BPSG film 12 is wider than a width (the width of the bottom of the contact hole 14) in the direction of the semiconductor substrate 10. The width w2' of the side of the BPSG film 12 of section 14b of the contact hole 14 on the HTO film 11 is narrower by a width of the step (the surface that is substantially parallel to the front surface of the semiconductor substrate 10) of step 14c than the width w1' of the side of the HTO film 11 of section 14a of the contact hole 14 on the BPSG film 12. A width of the side of the semiconductor substrate 10 of section 14b of the contact hole 14 on the HTO film 11 corresponds to the width w2 of section 14b of the contact hole 14 on the HTO film 11, if the cross-sectional shape of section 14b of the contact hole 14 on the HTO film 11 is a rectangular shape.

[0068] If the cross-sectional shape of section 14b of the contact hole 14 on the HTO film 11 is trapezoidal, as described above, the width w2' of an upper end face of section 14b of the contact hole 14 on the HTO film 11 is widened, which improves the embedding property of the tungsten film 16 with respect to section 14b of the contact hole 14 on the HTO film 11. Furthermore, the width of the bottom face of the contact hole 14 is reduced, which allows the distance w11 between the grooves 5 to be decreased.

[0069] In the contact hole 14, the barrier metal 15 is provided along an inner wall (side surfaces of the interlayer insulating film 13 and the front surface of the semiconductor substrate 10) of the contact hole 14. The barrier metal 15 can extend to a surface (i.e., the surface of the BPSG film 12) of the interlayer insulating film 13. The barrier metal 15 exhibits high adhesion to a semiconductor section (the semiconductor substrate 10) and is formed by a metal that creates an ohmic contact with the semiconductor section. In particular, the barrier metal 15 can be, for example, a titanium film (Ti film) or a stacked metal film in which a titanium film and a titanium nitride film (TiN film) are stacked. The thickness of the barrier metal 15 can be, for example, in the range of about 0.1 µm to 0.2 µm and can, in particular, be, for example, 0.15 µm.

[0070] On the junction metal 15, the tungsten film (W-film) 16 is provided as a contact plug such that it is embedded in the contact hole 14. The emitter electrode 17 is located on the front surface of the semiconductor substrate 10 in the active region. The emitter electrode 17 is connected to the emitter region 3 by n + -type and contact area 4 from p + -type is electrically connected via the tungsten film 16 and the barrier metal 15 and is connected to the base region 2 of the p-type via the contact region 4 of the p + -Type electrically connected.

[0071] An electrode structure is formed in which the emitter electrode 17 and a semiconductor section are electrically connected via the barrier metal 15 and the tungsten film 16, which is embedded in the contact hole 14 in this manner, thereby narrowing a trench grid dimension (the distance w11 between the trenches 5). Furthermore, the emitter electrode 17 is electrically insulated from the gate electrode 7 by the interlayer insulating film 13. The emitter electrode 17 is, for example, an aluminum-silicon electrode (Al-Si electrode) containing aluminum as its main component.

[0072] Next, a method for manufacturing the semiconductor device according to the embodiment is described. Fig. Figure 2 is a flowchart outlining the process for manufacturing the semiconductor device according to the embodiment. Fig. Figures 3 to 8 are cross-sectional views of the semiconductor device according to the embodiment during manufacturing. Fig. Figure 9 is a cross-sectional view of another example of a state of the semiconductor device according to the embodiment during manufacturing. Fig. Element structures in semiconductor substrate 10 are not shown in Figures 3 to 9. Fig. Figure 7 schematically represents a state of the tungsten film 16 as seen by a scanning electron microscope (SEM) after a process in step S10 and before a process in step S11. Fig. 2 is being filmed. Fig. Steps 3 to 6 correspond to steps S5, S7, S8 and S10 respectively in Fig. 2.

[0073] First, a predetermined element structure (MOS gate, i.e., the base region 2 of the p-type, the emitter region 3 of the n-type) is deposited on the side of the front surface of the semiconductor substrate (semiconductor wafer) 10. + -Type, contact area 4 from p + -Type, the trench 5, the gate insulation film 6 and the gate electrode 7) of the trench-gate IGBT are formed (step S1). As in Fig. As shown in Figure 3, the next step involves forming the HTO film 11 on the front surface of the semiconductor substrate 10, for example by a CVD process, as the first layer of the interlayer insulating film 13 (step S2). Next, the BPSG film 12 is formed on the front surface of the semiconductor substrate 10, for example by a CVD process, as the second layer of the interlayer insulating film (step S3). Finally, a resist mask 21, in which the formation areas of the contact hole 14 are open, is formed on the interlayer insulating film 13 as an etching mask, which is used in a subsequent etching process (step S4).

[0074] Next, the interlayer insulating film 13 is selectively removed by dry etching using the resist mask 21 as a mask, thereby forming the contact holes 14 (step S5). Sections of the front surface of the semiconductor substrate 10 exposed in the contact holes 14 can be slightly removed by the dry etching in step S5. In a further process in step S5, a natural oxide film (not shown) is formed on a silicon face (Si face) (contact formation site between the barrier metal 15 and the semiconductor substrate 10) exposed in the contact holes 14.

[0075] Furthermore, in the process in step S5, when the contact holes 14 are formed by anisotropic etching, the contact holes 14 have a cross-sectional shape that is rectangular, in which the sidewalls are substantially orthogonal to the front surface of the semiconductor substrate 10. In other words, section 14a of the contact hole 14 on the BPSG film 12 and section 14b in the HTO film 11 both have a cross-sectional shape that is substantially rectangular.

[0076] Furthermore, in step S5 of the process, when the contact holes 14 are formed by isotropic etching, the contact holes 14 have a cross-sectional shape that is trapezoidal, in which the width of the upper end face is slightly wider than the width at the lower side. In other words, section 14a of the contact hole 14 on the BPSG film 12 and section 14b in the HTO film 11 both have a cross-sectional shape that is substantially trapezoidal.

[0077] As in Fig. As shown in Figure 4, the resist mask is removed next (step S6). As a pretreatment for a subsequent barrier metal formation process, the natural oxide film formed during the process in step S5 is removed by wet etching with an aqueous solution of hydrofluoric acid (HF) or an aqueous solution of dilute hydrofluoric acid (step S7). In a process in step S7, the etch rate of the interlayer insulating film 13 by the aqueous solution of hydrofluoric acid or the aqueous solution of dilute hydrofluoric acid is faster at section 14a in the BPSG film 12 than at section 14b in the HTO film 11.

[0078] In step S7, as a consequence of differences in the etch rate for the BPSG film 12 and the HTO film 11, the width w1 of section 14a of the contact hole 14 on the BPSG film 12 becomes wider than the width w2 of section 14b of the contact hole 14 on the HTO film 11, forming a stepped shape and creating the single step 14c on the side walls of the contact hole 14. Conversely, the HTO film 11 is not substantially etched. Therefore, the width w2 of section 14b of the contact hole 14 on the HTO film 11 is maintained at a set width (i.e., target value) during the process in step S5, and the desired characteristics are obtained.

[0079] The width w1 of section 14a of the contact hole 14 on the BPSG film 12 can be varied by controlling the timing of the wet etching. Furthermore, in step S7, the silicon area exposed in the contact holes 14 is not etched, and therefore the depth d10 of the contact hole 14 is maintained at the same depth as before pre-treatment. In this way, the natural oxide film formed during step S5 is removed in step S7, and the width w1 of section 14a of the contact hole 14 on the BPSG film 12 is widened, thus reducing the overall aspect ratio of the contact hole 14.

[0080] Furthermore, in a case where pretreatment is assumed to be dry etching, the dry etch rates of the HTO film 11 and the BPSG film 12 are equal, and therefore the widths w1, w2 of section 14a of the contact hole 14 on the BPSG film 12 and of section 14b in the HTO film 11 become uniformly wider. Therefore, in the present invention, the process in step S7 is carried out by wet etching. Even if the first layer of the interlayer insulating film 13 is a thermal oxide film instead of the HTO film 11, or if the second layer of the interlayer insulating film 13 is a PSG film or an NSG film instead of the BPSG film 12, the width of a section of the PSG film or the NSG film in the contact hole 14 can be made relatively wide by pretreatment with a hydrofluoric acid solution or a dilute hydrofluoric acid solution.

[0081] As in Fig. As shown in Figure 5, a titanium film and a titanium nitride film are next sequentially formed along the inner walls of the contact holes 14 as a barrier metal 15 (step S8). The titanium film and the titanium nitride film can be formed by sputtering or chemical vapor deposition (CVD). As described above, the width w1 of section 14a of the contact hole 14 on the BPSG film 12 is widened during the process in step S7, thereby enabling the barrier metal 15 to be formed with a uniform thickness in a process in step S8, and preventing the barrier metal 15 from growing thick in certain sections.

[0082] The process in step S8 is preferably carried out within, for example, 24 hours after the process in step S7. One reason for this is that if the semiconductor substrate 10 is left (stored) for more than 24 hours after the process in step S7, a natural oxide film thick enough to adversely affect semiconductor device characteristics will reform on the silicon surface exposed in the contact holes 14. Before the process in step S8, if the semiconductor substrate 10 is temporarily stored after the process in step S7, it is sufficient for the storage location of the semiconductor substrate 10 to be other than an environment positively sprayed with oxygen, and may be an environment exposed to the atmosphere.

[0083] Next, an ohmic contact is formed between the junction metal 15 and the semiconductor substrate 10 by curing (heat treatment) (step S9). As in Fig. As shown in Figure 6, the next step involves growing a tungsten film 16 on the barrier metal 15 using a CVD process via a reduction reaction of tungsten hexafluoride (WF6) and hydrogen (H2), and embedding the tungsten film 16 in the contact holes 14 (step S10). In a process within step S10, the tungsten film 16 is grown on the inner wall (side walls and bottom) of each contact hole 14, and sections of the surface of the tungsten film 16 on the facing side walls of the contact hole 14 contact each other, thereby filling a gap between sections of the tungsten film 16 on the side walls and thus filling the contact hole 14 with the tungsten film 16.

[0084] As described above, the width w1 of section 14a of the contact hole 14 on the BPSG film 12 is widened during the process in step S7, thereby reducing the aspect ratio of the contact hole 14. Therefore, in the process in step S10, before the sections of the tungsten film 16 grown on the inner wall of the contact hole 14 contact each other at the facing upper ends of the contact hole 14 and close the contact hole 14, the sections of the surface of the tungsten film 16 on the facing side walls of the contact hole 14 can contact each other. Therefore, no void is formed in the tungsten film 16, and the contact hole 14 can be almost completely embedded with the tungsten film 16 (see Fig. 7).

[0085] Next, the tungsten film 16 is back-etched, leaving the tungsten film 16 only on the barrier metal 15 in the contact hole 14 (step S11). In the process in step S10, for example, assuming that a cavity occurs in the tungsten film 16, the cavity is located in a position that is sufficiently flat from the surface of the tungsten film 16 that the cavity opened at an upper section by the back-etching in step S11 appears to form a groove 20 (see Fig. 9) on the surface of the tungsten film 16 during back-etching. Therefore, even if a cavity occurs in the tungsten film 16 during the process in step S10, fluorine-based gas that is trapped in the cavity by the process in step S11 will be released to the outside.

[0086] While in Fig. 8 a case in which no cavity occurs in the tungsten film 16 is shown, is in Fig. Figure 9 shows a cavity that appears in the tungsten film 16 during the process in step S10, in a state where, after back-etching in step S11, the cavity becomes a groove 20 and appears on the surface of the tungsten film 16. The emitter electrode 17 is subsequently embedded in the groove 20 created on the surface of the tungsten film 16. Next, remaining parts, such as the emitter electrode 17 and the collector area 8, are removed. + -type, the collector electrode 9, etc. is formed. Next, the semiconductor wafer is separated (cut) into individual chips, thereby forming the in Fig. 1 Semiconductor device shown is completed.

[0087] As described above, according to one embodiment, the interlayer insulating film is provided in which a first insulating film (HTO film) and a second insulating film (BPSG film) are sequentially stacked. The second insulating film has a faster etching rate than the first insulating film. It is etched using an aqueous solution containing hydrofluoric acid or dilute hydrofluoric acid, which is used in a wet etching pretreatment to form a barrier metal. Consequently, the pretreatment, performed after the contact holes are formed in the interlayer insulating film, makes the width of a section of the contact hole in the second insulating film wider in a step-like manner than the width of a section in the first insulating film, and the aspect ratio of the contact hole can be reduced.Even when a micropattern contact hole is formed, and unit cell size reductions are achieved, the junction metal can be formed with a uniform thickness along the inner wall of the contact hole. Furthermore, the tungsten film forming a contact plug can be embedded on the junction metal within the contact hole without creating a void within the tungsten film. Therefore, the micropattern contact hole can be formed, enabling unit cell size reductions. Additionally, the trapping of a fluorine-based gas, which adversely affects elemental characteristics, within the tungsten film—the contact plug that electrically connects the front electrode and the semiconductor substrate—can be prevented, thus improving the reliability of the semiconductor device (product).

[0088] For the foregoing, the present invention is not limited to the embodiments described above, and various modifications within a range that does not deviate from the concept of the invention are possible. For example, the invention is applicable to various types of elements in which contact between the front electrode and the semiconductor substrate is formed via a contact connector. In particular, the invention is also applicable, for example, to metal-oxide-semiconductor field-effect transistors (MOSFETs: MOS-type field-effect transistors with an insulated gate formed by a three-layer structure of a metal, an oxide film, and a semiconductor) and reverse-conducting IGBTs (RC-IGBTs). The invention is also applicable to a planar-gate structure instead of a trench-gate structure. Furthermore, the invention is implemented similarly if the conductivity types (n-type, p-type) are reversed. INDUSTRIAL APPLICABILITY

[0089] As described, the semiconductor device and the method for manufacturing a semiconductor device according to the present invention are useful for semiconductor devices in which a contact between the front electrode and the semiconductor substrate is formed by a contact plug, and are particularly suitable for trench-gate IGBTs. EXPLANATION OF REFERENCE MARKS 1 Drift range from n- - Type (second semiconductor area) 2 p-type base region (first semiconductor region) 3 Emitter area from n + -type (fourth semiconductor region) 4 Contact area from p + -Type 5 trenches 6 Gate insulation film 7 Gate electrode 8 Collector area from p + -Type (third semiconductor region) 9 Collector electrode (second electrode) 10 Semiconductor substrate 11 First isolation film (HTO film) 12 Second Isolation Film (BPSG Film) 13 Intermediate layer insulation film 14 contact holes 14a Section of the contact hole on the BPSG film (upper section) 14b Section of the contact hole on the HTO film (lower section) 14c step on the side wall of the contact hole 15 Barrier layer metal (first metal film) 16 Tungsten film (second metal film) 17 Emitter electrode (first electrode) 20 Groove (cavity) L Distance between trench and contact hole w1, w1' Width of the section of the contact hole on the BPSG film w2, w2' Width of the section of the contact hole on the HTO film w11 Distance between ditches

Claims

[1] Semiconductor device comprising: a semiconductor substrate (10) having a first main surface and a second main surface opposite to the first main surface, wherein the semiconductor substrate (10) comprises a first semiconductor region (2) of a second conductivity type, which is provided in a surface layer on one side of the first main surface of the semiconductor substrate (10); a second semiconductor region (1) of a first conductivity type, which is provided on one side of the second main surface of the semiconductor substrate (10), wherein the second semiconductor region (1) is a region of the semiconductor substrate (10) excluding the first semiconductor region (2); an element structure provided on the side of the first main surface of the semiconductor substrate (10) and having a pn junction between the first semiconductor region (2) and the second semiconductor region (1); an intermediate layer insulating film (13) provided on the first main surface of the semiconductor substrate (10) and covering the element structure, wherein the intermediate layer insulating film (13) comprises a first insulating film (11) provided on the first main surface of the semiconductor substrate (10), and a second insulating film (12) provided on top of the first insulating film (11) and consisting of an insulating material having an etching rate that is faster than an etching rate of an insulating material of the first insulating film (11) with respect to hydrofluoric acid or dilute hydrofluoric acid, a contact hole (14) that selectively opens the interlayer insulating film (13) to expose the first main surface of the semiconductor substrate (10), wherein the contact hole (14) comprises a lower section (14b) arranged in the first insulating film (11) and an upper section (14a) arranged in the second insulating film (12) and has a side wall with a step (14c) between the upper section (14a) and the lower section (14b), wherein a width (w1) of the upper section (14a) is greater than a width (w2) of the lower section (14b) in a direction parallel to the first main surface of the semiconductor substrate (10), wherein the upper section (14a) has an aspect ratio in the range of 0.5 to 1.5, wherein the lower section (14b) has an aspect ratio in the range of 0.5 to 1.5; a first metal film (15) which is provided along an inner surface of the contact hole (14), wherein the first metal film (15) exhibits high adhesion to the semiconductor substrate (10) and forms an ohmic contact with the semiconductor substrate (10); a second metal film (16) embedded in the contact hole (14) on top of the first metal film (15); and a first electrode (17) which is provided on the interlayer insulating film (13) and the second metal film (16) and is electrically connected to the first semiconductor area (2) via the second metal film (16) and the first metal film (15). [2] Semiconductor device according to claim 1, wherein the upper section (14a) of the contact hole (14) has a trapezoidal shape in a cross-sectional view in which a width of an upper side facing the first electrode (17) is greater than a width of a lower side facing the lower section (14b) of the contact hole (14). [3] Semiconductor device according to claim 1 or 2, wherein the lower section (14b) of the contact hole (14) has a trapezoidal shape in a cross-sectional shape in which a width of an upper side facing the upper section (14a) of the contact hole (14) is greater than a width of a lower side facing the first semiconductor area (2). [4] Semiconductor device according to any one of claims 1 to 3, wherein the lower section (14b) has an upper side facing the upper section (14a) and a lower side facing the first semiconductor area (2), and the width of the lower side of the lower section (14b) of the contact hole (14) is in a range of 0.3 µm to 1.0 µm. [5] Semiconductor device according to any one of claims 1 to 4, wherein the first insulating film (11) is a silicon glass film. [6] Semiconductor device according to claim 5, wherein the first insulating film (11) contains phosphorus or contains phosphorus and boron. [7] Semiconductor device according to any one of claims 1 to 6, wherein the second insulating film (12) is a high-temperature oxide film or a thermal oxide film. [8] Semiconductor device according to any one of claims 1 to 7, wherein the first metal film (15) contains titanium as the main component. [9] Semiconductor device according to any one of claims 1 to 8, wherein the second metal film (16) contains tungsten as the main component. [10] Semiconductor device according to any one of claims 1 to 9, further comprising: a third semiconductor region (8) in contact with the second semiconductor region (1), which is provided in a surface layer on one side of the second main surface of the semiconductor substrate (10); and a second electrode (9) which is electrically connected to the third semiconductor region (8), wherein the element structure exhibits: the first semiconductor area (2), a fourth semiconductor region (3) of the first conductivity type, which is selectively provided in the first semiconductor region (2), a gate insulating film (6) which is provided in contact with the first semiconductor region (2) at a section between the second semiconductor region (1) and the fourth semiconductor region (3), and a gate electrode (7) which is provided in the first semiconductor layer above the gate insulating film (6). [11] A method for manufacturing a semiconductor device, the method comprising: in a first process (S1) forming a first semiconductor region (2) of a second conductivity type on a second semiconductor region (1) of a first conductivity type, thereby forming a semiconductor substrate (10) with a first main surface and a second main surface, and forming an element structure with a pn junction between the first semiconductor region (2) and the second semiconductor region (1) on one side of the first main surface of the semiconductor substrate (10), wherein the second semiconductor region (1) is a region of the semiconductor substrate (10) excluding the first semiconductor region (2); in a second process (S2, S3) forming an intermediate layer insulating film (13) on the first main surface of the semiconductor substrate (10) covering the element structure, wherein the second process (S2, S3) includes Formation (S2) of a first insulating film (11) as an intermediate insulating film (13) on the first main surface of the semiconductor substrate (10), and Forming (S3) a second insulation film (12) as an intermediate layer insulation film (13) on the first insulation film (11), wherein the second insulating film (12) is formed from an insulating material with an etching rate that is faster than an etching rate of the first insulating film (11) with respect to the aqueous solution; in a third process (S4) forming a resist film on the interlayer isolation film (13) in which a predetermined section is open; in a fourth process (S5) selective removal of the interlayer insulating film (13) to form a contact hole (14) that selectively exposes the first main surface of the semiconductor substrate (10) by performing etching using the resist film as a mask; in a fifth process (S6) removal of the resist film; in a sixth process (S7) removing a natural oxide film covering a section of the first main surface of the semiconductor substrate (10) exposed in the first contact hole by performing wet sets using an aqueous solution containing hydrofluoric acid or dilute hydrofluoric acid, wherein the sixth process (S7) includes Forming a step (14c) on a side wall of the first contact hole, thereby forming a second contact hole with a lower section (14b) arranged on the first insulating film (11) and an upper section (14a) arranged on the second insulating film (12) to increase a width (w1) of the upper section (14a) in a step-like shape which is greater than a width (w2) of the lower section (14b) in a direction parallel to the first main surface of the semiconductor substrate (10), wherein the stage (14c) is formed between the upper section (14a) and the lower section (14b); in a seventh process (S8) forming a first metal film (15) with high adhesion to the semiconductor substrate (10) along an inner surface of the second contact hole, which forms an ohmic contact with the semiconductor substrate (10); in an eighth process (S10) embedding a second metal film (16) onto the first metal film (15) in the second contact hole; and In a ninth process (S10), a first electrode (17) is formed on the interlayer insulating film (13) and the second metal film (16), and the first electrode (17) is electrically connected to the first semiconductor region (2) via the second metal film (16) and the first metal film (15), wherein in the sixth process (S7) an aspect ratio of the lower section (14b) is determined by wet setting in a range of 0.5 to 1.5, wherein In the fourth process (S5), an aspect ratio of the first contact hole is set in a range of 0.5 to 1.

5. [12] Method according to claim 11, wherein the fourth process (S5) comprises forming the first contact hole by anisotropic etching. [13] Method according to claim 11, wherein the fourth process (S5) comprises forming the first contact hole by isotropic etching. [14] Method according to any one of claims 11 to 13, wherein the lower section (14b) has an upper side facing the upper section (14a) and a lower side facing the first semiconductor region (2), and The fourth process (S5) includes producing a width of the lower side of the lower section (14b) in a range of 0.3 µm to 1.0 µm. [15] Method according to any one of claims 11 to 14, wherein the seventh process (S8) comprises forming the first metal film (15) by a sputtering process. [16] Method according to any one of claims 11 to 14, wherein the seventh process (S8) comprises forming the first metal film (15) by a chemical vapor deposition method. [17] Method according to any one of claims 11 to 16, wherein the first insulating film (11) is a silicon glass film. [18] Method according to claim 17, wherein the first insulating film (11) contains phosphorus or contains phosphorus and boron. [19] Method according to any one of claims 11 to 18, wherein the second insulating film (12) is a high-temperature oxide film or a thermal oxide film. [20] Method according to any one of claims 11 to 19, wherein the first metal film (15) contains titanium as the main component. [21] Method according to any one of claims 11 to 20, wherein the second metal film (16) contains tungsten as the main component.

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