Electronic control device and circuit reconfiguration method

Abstract

Electronic control device, comprising: a logic circuit (255) capable of reconfiguring a plurality of arithmetic circuits, including a first circuit and a second circuit; a reconfiguration controller (204) that reconfigures the arithmetic circuits based on reconfiguration commands and verifies the reconfigured arithmetic circuits; and a process controller (202) that sends the reconfiguration commands to the reconfiguration controller (204) and commands the arithmetic circuits to perform operations, wherein the reconfiguration controller (204) reconfigures and verifies the first circuit when a first reconfiguration command is received, The process controller (202) of the first circuit commands to perform an operation when the verification of the first circuit by the reconfiguration controller (204) is complete. After the first circuit has been reconfigured, the process controller (202) sends a second reconfiguration command to the reconfiguration controller (204) and orders the reconfiguration controller (204) to start the reconfiguration of the second circuit until the first circuit has completed its operation.

Description

field of technology

[0001] The present invention relates to an electronic control device and a circuit reconfiguration method. Technical background

[0002] The development of technology aimed at automated vehicle driving is progressing. Automated driving requires environmental perception and vehicle control instead of the driver, necessitating a massive amount of information processing. To handle the increased volume of information, the use of not only a CPU but also a hardware chip is being considered. More specifically, it is expected that multiple processes will be implemented in a single logic circuit using a programmable logic device (PLD), such as a field-programmable gate array (FPGA), where the logic circuit can be reconfigured. When using a logic circuit, a suitable process is required to address software errors.PTL 1 discloses a technique in which, when a software error occurs, the occurrence of the error is detected for each of the partitioned components and circuit setup information is rewritten into units of the partitioned components.

[0003] PTL 2 describes a processor that cyclically executes a multitude of threads for each allocated time period. The processor stores configuration information for operation cells for each thread. Each thread executes a different predetermined number of operation cells sequentially and, in turn, reconfigures an operation cell that completed its last operation within the time period allocated to the current thread, based on stored configuration information for the operation cell corresponding to the next thread. It also simultaneously executes an operation cell with a configuration for the current thread and an operation cell with a configuration for the next thread.

[0004] PTL 3 describes a data processing system with a data processing device that can perform a flexible operation by dynamically setting and modifying internal functions contained in a logic circuit inside the data processing device.

[0005] PTL 4 describes a reconfigurable computing circuit that can dynamically reconfigure its logic configuration.

[0006] PTL 5 describes the avoidance or reduction of the waiting time between processing operations in individual circuits during parallel and successive processing in newly configured circuits when successively reconfiguring multiple circuits within a programmable logic circuit. The data is divided for reconfiguration into a portion that overlaps with the area of ​​the previous circuit and a portion that does not. In true reconfiguration, the non-overlapping portion is reconfigured in parallel with the processing in the previous circuit, and after the completion of processing in the previous circuit, the overlapping portion is reconfigured. List of prior art patent documents PTL 1: JP 2011 – 13 829 A PTL 2: US 2009 / 0 307 470 A1 PTL 3: DE 697 33 251 T2 PTL 4: US 2009 / 0 327 653 A1 PTL 5: JP 2001 - 320 271 A Brief description of the invention: Technical problem

[0007] The aim is to reduce the processing time in a reconfigurable logic circuit. Solution to the problem

[0008] According to a first aspect of the present invention, an electronic control device is provided which comprises: a logic circuit capable of reconfiguring a plurality of arithmetic circuits, including a first circuit and a second circuit; a reconfiguration controller that reconfigures the arithmetic circuits based on reconfiguration commands and verifies the reconfigured arithmetic circuits;and a process controller that sends the reconfiguration commands to the reconfiguration controller and commands the arithmetic circuits to perform operations, wherein, when a first reconfiguration command is received, the reconfiguration controller reconfigures and verifies the first circuit, after the reconfiguration controller has completed its verification of the first circuit, the process controller commands the first circuit to perform an operation, after the reconfiguration of the first circuit has been completed, the process controller sends a second reconfiguration command to the reconfiguration controller and commands the reconfiguration controller to start reconfiguring the second circuit until the operation of the first circuit is completed.

[0009] According to a second aspect of the present invention, a circuit reconfiguration method is specified, which is carried out in a logic circuit in which a plurality of arithmetic circuits, including a first circuit and a second circuit, are reconfigurable, wherein the circuit reconfiguration method includes: reconfiguring and checking the first circuit; after completion of the check of the first circuit, issuing a command to execute an operation to the first circuit; and after completion of the reconfiguration of the first circuit, starting the reconfiguration of the second circuit until the operation of the first circuit is completed. Advantageous effects of the invention

[0010] According to the present invention, the processing time of a reconfigurable logic circuit can be reduced. Brief description of the drawings [ Fig. 1] Fig. Figure 1 is a sketch representing a system configuration of a vehicle on-board system 1. [ Fig. 2] Fig. Figure 2 is a sketch that represents a hardware configuration of a device for controlling autonomous locomotion 2. [ Fig. 3] Fig. Figure 3 is a sketch that represents a functional configuration of the device for controlling autonomous locomotion 2. [ Fig. 4] Fig. Figure 4 is a sketch that represents a functional configuration of a reconfiguration controller 204. [ Fig. 5] Fig. 5(a) is a sketch representing a configuration of an arithmetic unit 206 performing a process of operation type “A”. Fig. 5(b) is a sketch representing a configuration of the arithmetic unit 206 performing a process of operation type “B”. [ Fig. 6] Fig. Figure 6 is a sketch that represents an example of a process information database 3. [ Fig. 7] Fig. Figure 7 is a sketch that represents an example of a circuit management database 4; [ Fig. 8] Fig. Figure 8 is a flowchart that represents an operation of the process controller 202. [ Fig. 9] Fig. Figure 9 is a flowchart that represents an operation of the reconfiguration controller 204. [ Fig. 10] Fig. Figure 10 is a flowchart that represents an operation of the device for controlling autonomous locomotion 2. [ Fig. 11] Fig. Figure 11 is a timing diagram illustrating the operation of the device for controlling autonomous locomotion 2 according to the first embodiment. [ Fig. 12] Fig. Figure 12 is a sketch that represents an example of a circuit management DB 4A according to a modification example 1; [ Fig. 13] Fig. Figure 13 is a timing diagram that represents an operation of the device for controlling autonomous locomotion 2 according to a modification example 2. [ Fig. 14] Fig. Figure 14 is a flowchart that represents an operation of the process controller 202 according to modification example 2. [ Fig. 15] Fig. Figure 15 is a timing diagram representing an operation of the device for controlling autonomous locomotion 2 according to a second embodiment. Description of embodiments FIRST FORM

[0011] In the following, a first embodiment of a device for controlling autonomous locomotion, which is an electronic control device, is described with reference to Fig. 1 to 11 described. <systemkonfiguration>

[0012] Fig. Figure 1 is a sketch depicting a system configuration of a vehicle onboard system 1, including a device for controlling autonomous movement 2. The vehicle onboard system 1 comprises: a camera information acquisition unit 101, mounted on a vehicle 100, which detects conditions outside the vehicle 100 using a camera; a radar information acquisition unit 102, which detects conditions outside the vehicle 100 using radar; and a vehicle position information acquisition unit 103, which detects the position of the vehicle 100 using a receiver of a satellite navigation system, such as GPS. The vehicle onboard system 1 further comprises: a unit for setting up the automated driving 104 of the vehicle 100; and a wireless communication unit 105 for updating information of the vehicle onboard system 1 using a radio interface (over the air, OTA).

[0013] The vehicle on-board system 1 further comprises a device for controlling autonomous movement 2, an auxiliary control unit 106, a brake control unit 107, an engine control unit 108, and a power steering control unit 109. The device for controlling autonomous movement 2, the auxiliary control unit 106, the brake control unit 107, the engine control unit 108, and the power steering control unit 109 are, for example, electronic control units (ECUs).

[0014] The camera information acquisition unit 101, the radar information acquisition unit 102, the vehicle position information acquisition unit 103, the automated driving setup unit 104, the wireless communication unit 105, the autonomous driving control device 2, the auxiliary control unit 106, the brake control unit 107, the engine control unit 108, and the power steering control unit 109 are interconnected via a Controller Area Network (CAN). The camera information acquisition unit 101, the radar information acquisition unit 102, and the vehicle position information acquisition unit 103 all transmit information received from a sensor to the autonomous driving control device 2.The automated driving setup unit 104 sends setup information, such as a destination, route, or speed of travel during automated driving, to the autonomous driving control device 2. Some of the information sent by the automated driving setup unit 104 can be received from an external device, such as a server device 110, via a wireless communication unit 105.

[0015] The autonomous driving control device 2 executes a process for controlling automated driving and, based on the result of this process, issues a control command to the brake control unit 107, the engine control unit 108, and the power steering control unit 109. The auxiliary control unit 106 performs the same control function as the autonomous driving control device 2. The brake control unit 107 controls the braking force of the vehicle 100. The engine control unit 108 controls the driving force of the vehicle 100. The power steering control unit 109 controls the steering of the vehicle 100.

[0016] When the automated driving setup unit 104 receives a request to set up automated driving, the autonomous driving control device 2 calculates a trajectory along which the vehicle 100 will move, based on external information received from the camera information acquisition unit 101, the radar information acquisition unit 102, the vehicle position information acquisition unit 103, and the like. The autonomous driving control device 2 issues commands to the brake control unit 107, the engine control unit 108, and the power steering control unit 109 to control braking force, driving force, steering, and the like, so that the vehicle 100 moves along the calculated trajectory.The brake control 107, the motor control 108 and the power steering control 109 receive the control commands from the device for controlling autonomous movement 2 and output operational signals to actuators (not shown) as targets to be controlled. <Hardware-Konfiguration der Vorrichtung zum Regeln der autonomen Fortbewegung>

[0017] Fig. Figure 2 is a sketch depicting a hardware configuration of the autonomous locomotion control device 2. The autonomous locomotion control device 2 comprises a CPU 251, a ROM 252, a RAM 253, a flash memory 254, a logic circuit 255, and a communication interface 256. The CPU 251 implements a function, described below, by loading a program stored in the ROM 252 into a RAM 253 and executing the loaded program. The flash memory 254 is a non-volatile memory area. The CPU 251 can be a multi-core processor belonging to a lockstep type.

[0018] The logic circuit 255 is a logic circuit that is reconfigurable using a PLD, such as an FPGA. The logic circuit 255 is a logic circuit of which a portion is reconfigurable; that is, it is a partially reconfigurable logic circuit. The communication interface 256 is an interface that performs communication using a predefined protocol, such as CAN. The autonomous locomotion control device 2 is connected to another device via the communication interface 256 and sends and receives data. The communication interface 256 can have two communication ports connected to an external device, or it can have only one communication port. <Funktionale Konfiguration der Vorrichtung zum Regeln der autonomen Fortbewegung>

[0019] Fig. Figure 3 is a sketch illustrating a functional configuration of the autonomous locomotion control device 2. The autonomous locomotion control device 2 comprises: a first communication interface 201-1, a second communication interface 201-2, a process controller 202, a reconfiguration circuit 203, a reconfiguration controller 204, an arithmetic unit 206, a first arithmetic circuit 207-1 through Nth arithmetic circuit 207-N (where N represents any natural number 2 or greater), a process information database 3 (hereinafter referred to as the "process information DB"), a circuit management database 4 (hereinafter referred to as the "circuit management DB"), and a circuit database 5 (hereinafter referred to as the "circuit DB"). Hereinafter, the first communication interface 201-1 and the second communication interface 201-2 are collectively referred to as "communication interface 201".Furthermore, the first arithmetic circuit 207-1 to the Nth arithmetic circuit 207-N are collectively referred to as "arithmetic circuit 207". The communication interface 201 is in . Fig. 2 is implemented with the communication interface 256. The process information DB 3, the circuit management DB 4 and the circuit DB 5 are implemented with the RAM 253 or the flash memory 254.

[0020] The reconfiguration circuit 203 is implemented with the logic circuit 255. The reconfiguration controller 204 and the arithmetic circuit 206 are configured with the reconfiguration circuit 203. The arithmetic circuit 207 is a logic circuit configured with the arithmetic unit 206. In this embodiment, the reconfiguration controller 204 is not reconfigured in the reconfiguration circuit 203, and only the arithmetic unit 206 is reconfigured. In other words, the reconfiguration circuit 203 is partially reconfigurable and commands the arithmetic unit 206 to reconfigure the arithmetic circuit 207, while maintaining the circuit such as the reconfiguration controller 204.

[0021] The device for controlling autonomous locomotion 2 is connected via the first communication interface 201-1 to the camera information acquisition unit 101, the radar information acquisition unit 102, the vehicle position information acquisition unit 103, the automated driving setup unit 104 and the wireless communication unit 105, which are located in Fig. 1 are shown, connected and is connected via the second communication interface 201-2 to the auxiliary control unit 106, the brake control 107, the engine control 108 and the power steering control 109. In Fig. 3. The autonomous locomotion control device 2 has two logical communication interfaces, which include the first communication interface 201-1 and the second communication interface 201-2. However, the autonomous locomotion control device 2 can also have only one logical communication interface that performs both functions.

[0022] The process controller 202 is implemented with a program that is executed by the CPU 251. During a predetermined process period T, the process controller 202 repeatedly executes a process described below. The process controller 202 periodically collects sensor information received from the camera information acquisition unit 101, the radar information acquisition unit 102, and the vehicle position information acquisition unit 103, as well as automated driving setup information received from the automated driving setup unit 104. The process controller 202 determines a process number and process information with reference to the process information database 3, where the process number indicates the number of executions of the process based on the collected sensor information or the automated driving setup information.

[0023] The process controller 202 determines an operation type to be executed by the arithmetic unit 206, based on the process number and process information determined by the process information DB 3. Furthermore, the process controller 202 determines the number of circuits that comprise the arithmetic unit 206 and specific circuit data based on the determined operation type, referencing the circuit management DB 4. The circuit data is stored in the circuit DB 5. This circuit data is written to a circuit area within the reconfiguration circuit 203, configuring the logic circuit 255, such as the arithmetic circuit 207, and forming the arithmetic unit 206, or the like.

[0024] The process controller 202 sends a reconfiguration command, including the circuit data, to the reconfiguration controller 204, instructing the reconfiguration controller 204 to reconfigure the logic circuit 255 of the arithmetic unit 206. Following the reconfiguration of the logic circuit 255, the reconfiguration controller 204 performs an error-checking process on the logic circuit 255, as described below. The process controller 202 sequentially performs a reconfiguration of each arithmetic circuit 207-1, based on the specified number of circuits that comprise the arithmetic unit 206 and the specified circuit data.

[0025] The process controller 202 manages the reconfiguration state of the circuit area of ​​the arithmetic unit 206 and sets reconfiguration control times for each arithmetic circuit 207-N, from the first arithmetic circuit 207-1 to the nth arithmetic circuit 207-N. Based on the result of the operation obtained from the nth arithmetic circuit 207-N (the last reconfigured arithmetic circuit), the process controller 202 outputs a control command for a braking force, a driving force, or the like from the second communication interface 201-2.

[0026] The reconfiguration controller 204 receives the reconfiguration command, including the circuit data, from the process controller 202 and modifies the circuit configuration of the arithmetic unit 206 of the circuit area within the reconfiguration circuit 203. That is, the reconfiguration controller 204 reconfigures the arithmetic circuit 207. After completing the reconfiguration of the arithmetic circuit 207, the reconfiguration controller 204 performs an error check on the configured arithmetic circuit 207. After completing the error check, the reconfiguration controller 204 sends a completion message to the process controller 202. The details of the functional configuration of the reconfiguration controller 204 are described below with reference to Fig. 4 described. The error check on the configured arithmetic circuit 207 by the reconfiguration controller 204 is also referred to as soft error check or “check”. <Algorithmus der Logikschaltung>

[0027] As described above, when a new operation is performed in the reconfiguration circuit 203, the arithmetic circuit is first reconfigured, and then an error check is performed on the reconfigured arithmetic circuit. These steps enable the operation to be performed on the reconfigured arithmetic circuit. Therefore, the time required for reconfiguration and error checking on the arithmetic circuit is also referred to as the time required to prepare for the execution of the arithmetic circuit's operation. In this embodiment, the preparation time is compensated for by an overlap with the time during which another arithmetic circuit is performing an operation. The details are described below. <Funktionale Konfiguration des Rekonfigurationsreglers>

[0028] Fig. Figure 4 is a sketch illustrating a functional configuration of the reconfiguration controller 204. The reconfiguration controller 204 comprises a setting unit 41, a configuration unit 42, a fault monitoring unit 43, and a circuit data buffer unit 44.

[0029] The setting unit 41 is a functional unit that sends and receives data to the process controller 202. After receiving the reconfiguration command, which includes the circuit data, from the process controller 202, the setting unit 41 sends the circuit data to the configuration unit 42 to instruct the arithmetic unit 206 to configure the arithmetic circuit 207. The setting unit 41 sets a time at which the configuration unit 42 configures the arithmetic circuit 207, as well as a time at which the fault monitoring unit 43 performs the fault check. After the configuration unit 42 has configured the arithmetic circuit 207, the setting unit 41 instructs the fault monitoring unit 43 to perform the fault check on the arithmetic circuit 207. After the fault check by the fault monitoring unit 43 has been completed, the setting unit 41 sends a completion message to the process controller 202.

[0030] The configuration unit 42 configures the arithmetic circuit 207 using the circuit data received from the setting unit 41. Fig. Figure 4 shows a connection between the configuration unit 42 and the arithmetic circuit 207, indicated by a dotted line. The dotted line represents an interface or similar connection to a configuration memory of the logic circuit 255. More precisely, the configuration unit 42 configures the arithmetic circuit 207 within the arithmetic unit 206 on the logic circuit 255 by writing the circuit data to the configuration memory.

[0031] The fault monitoring unit 43 is a functional unit for fault checking to verify whether or not a soft error occurs in the logic circuit 255. The fault monitoring unit 43 sends the result of the fault check to the configuration unit 41. More precisely, the fault monitoring unit 43 reads a configuration memory of a section corresponding to the arithmetic circuit 207 and determines, using an error correction function, whether or not an error occurs. According to the embodiment, the logic circuit 255 cannot perform the reconfiguration and fault checking of the arithmetic circuit simultaneously. That is, if the configuration unit 42 is operating, the fault monitoring unit 43 cannot operate. Conversely, if the fault monitoring unit 43 is not operating, the configuration unit 42 cannot operate.

[0032] The circuit data buffer unit 44 is a functional unit that temporarily stores the circuit data received from the process controller 202 by the setting unit 41. After the fault monitoring unit 43 has detected the fault, the setting unit 41 can send the circuit data back to the configuration unit 42 using the circuit data that was temporarily stored in the circuit data buffer unit 44. <Konfigurationsbeispiel für die arithmetische Schaltung in der arithmetischen Einheit>

[0033] Fig. Figure 5 is a sketch that shows a configuration example for the arithmetic circuit 207 in the arithmetic unit 206. Fig. 5(a) is a sketch representing a configuration of the arithmetic unit 206 performing a process of operation type “A”. Fig. Figure 5(b) is a sketch representing a configuration of the arithmetic unit 206 performing a process of operation type "B". The arithmetic unit 206 performing the process of operation type "A" includes a first operation-A circuit 207A-1, which performs a first process of operation A, and a second operation-A circuit 207A-2, which performs a second process of operation A. The arithmetic unit 206 performing the process of operation type "B" includes a first operation-B circuit 207B-1, which performs a first process of operation B, a second operation-B circuit 207B-2, which performs a second process of operation B, and a third operation-B circuit 207B-3, which performs a third process of operation B. In the following, the first Operation-A circuit 207A-1 and the second Operation-A circuit 207A-2 will be referred to collectively as “Operation-A circuit 207A”.Furthermore, the first Operation B circuit 207B-1, the second Operation B circuit 207B-2 and the third Operation B circuit 207B-3 are collectively referred to as the “Operation B circuit 207B”.

[0034] Both the first Operation A circuit 207A-1 and the second Operation A circuit 207A-2 are connected to the reconfiguration controller 204 via the interface with the configuration memory or similar. Operation A circuit 207A is connected to the process controller 202. The first Operation A circuit 207A-1 receives an execution start command for the Operation A process from the process controller 202, and the second Operation A circuit 207A-2 informs the process controller 202 of the result of the Operation A process. Additionally, Operation A circuit 207A receives information from the process controller 202 regarding the time at which the Operation A process switches from the first Operation A circuit 207A-1 to the second Operation A circuit 207A-2 or remains in place.

[0035] The first Operation B circuit 207B-1, the second Operation B circuit 207B-2, and the third Operation B circuit 207B-3 are all connected to the reconfiguration controller 204 via the interface with the configuration memory or similar. Operation B circuit 207B is connected to the process controller 202. The first Operation B circuit 207B-1 receives an execution start command for the Operation B process from the process controller 202, and the third Operation B circuit 207B-3 informs the process controller 202 of the result of the Operation B process.Furthermore, the Operation-B circuit 207B receives information from the process controller 202, the information relating to a time at which the operation process switches from the first Operation-B circuit 207B-1 to the second Operation-B circuit 207B-2 or is maintained, and a time at which the operation process switches from the second Operation-B circuit 207B-2 to the third Operation-B circuit 207B-3 or is maintained. <Verwaltungsinformationen der Prozessinformationsdatenbank>

[0036] Fig. Figure 6 is a sketch illustrating an example of a process information database 3. Process information database 3 is a database referenced by process controller 202, containing the collected sensor information and details of the process executed on the information for setting up automated driving. Process information database 3 has fields for a process number 301 and for process information 302. Process number 301 stores how often the arithmetic unit 206 performs an operation. Process information 302 contains multiple instances of process information, for example, process information 1 and process information 2, and stores information regarding the name of the process executed by the arithmetic unit 206, such as operation A or operation B.Operation A and Operation B can store information regarding a specific operational process related to the control of autonomous locomotion. For example, Operation A can store information regarding sensor fusion, and Operation B can store information regarding the generation of a motion trajectory.

[0037] In the field that is in Fig. The value shown in figure 6 is stored in the field for process number 301, "2". Therefore, two is the number of times the operation is executed by the arithmetic unit 206. Process information 1, for which the reference number 302-1 stands, shows that operation A is executed as the first process of the arithmetic unit 206. Process information 2, for which the reference number 302-2 stands, shows that operation B is executed as the second process of the arithmetic unit 206. The in Fig. The process information database shown in Figure 6 is just an example, and the number of process information units that make up process information 302 is not necessarily 2. That is, process information 302 can include three or more process information units.

[0038] In this embodiment, each operational process executes a predefined operation using the result of the preceding operational process. For example, in Operation A, the result of the operation is determined based on the collected sensor information and the information for setting up automated driving. In Operation B, a predefined process is executed based on the result of Operation A. However, in Operation B, the operation can also be executed using information other than the result of Operation A. <Verwaltungsinformationen der Schaltungsverwaltungsdatenbank>

[0039] Fig. Figure 7 is a sketch illustrating an example of the circuit management DB 4. Circuit management DB 4 is a database accessed by the process controller 202 that stores information regarding the number of partitions in the arithmetic circuit by operation type and the data of the partitioned circuit. Circuit management DB 4 includes fields for Number of Partitions 402 and Circuit Data 403 by operation type 401. Operation type 401 stores information regarding the operation type corresponding to the process information 302 acquired by the process controller 202 with reference to process information DB 3. Number of Partitions 402 stores, depending on operation type 401, how many times the arithmetic circuit 207, which is part of the arithmetic unit 206, has been partitioned.Circuit data 403 stores information regarding circuit data, which has been partitioned into several intersection sets, depending on the operation type 401. More precisely, this information is address information for retrieving corresponding circuit data from the circuit data stored in circuit DB 5.

[0040] In one example, which is in Fig. Figure 7 shows a row where the field "Operation Type" 401 contains "A", and the field "Number of Partitions" 402 contains "2", indicating that two is the number of partitions of Operation A circuit 207A, which is part of the arithmetic unit 206 that performs Operation A. Circuit data 1, represented by reference 403-1, shows information about the first Operation A circuit (207A-1) of Operation A circuit 207A. Circuit data 2, represented by reference 403-2, shows information about the second Operation A circuit (207A-2) of Operation A circuit 207A. Circuit data 3, represented by reference 403-3, contains no information, as it is not used.

[0041] Furthermore, in a row where the field "Operation Type" 401 contains "B", the field "Number of Partitions" 402 contains "3", indicating that three is the number of partitions of the Operation B circuit 207A, which is part of the arithmetic unit 206 that performs Operation B. Circuit data 1, for which the reference number 403-1 stands, shows the information about the first Operation B circuit (207B-1) of Operation B circuit 207B. Circuit data 2, for which the reference number 403-2 stands, shows the information about the second Operation B circuit (207B-2) of Operation B circuit 207B. Circuit data 3, for which the reference number 403-3 stands, shows the information about the third Operation A circuit (207B-3) of Operation B circuit 207B. The in Fig. The circuit management DB 4 shown is only an example, and the number of circuit data units that make up circuit data 403 is not necessarily three. The number of types stored as operation type 401 is not necessarily two. <Flussdiagramm des Prozessreglers>

[0042] Fig. Figure 8 is a flowchart representing an operation of the process controller 202. The process controller 202 performs the operation shown in the following flowchart for each predefined process period T.

[0043] In step S801, the process controller 202 acquires the information, including the process number 301 and the process information 302, with reference to the process information DB 3. Then, in step S802, the process controller 202 assigns "1" to a process ID, which is a loop counter. In step S803, the process controller 202 acquires the operation type based on the process ID and the process information 302 acquired in step S801. The process controller 202 reads the circuit management DB 4 and acquires information regarding the number of partitions 402 and the circuit data 403 that correspond to the acquired operation type. If the process information DB 3 is structured as described in Fig. If the circuit management DB 4 is as shown in 6 and the process ID is "1", then "A" is recorded as the operation type. Fig. Figure 7 shows that the number of partitions is determined to be "2". Then, in step S804, the process controller 202 assigns "1" to a process ID, which is a loop counter.

[0044] In step S805, the process controller 202 sends the reconfiguration command, which includes the circuit data, to the reconfiguration controller 204 based on the description in the circuit management DB 4. If the circuit management DB 4 is structured as described in Fig. As shown in Figure 7 and the circuit ID is "1", the process controller 202 sends the circuit data of the first Operation A circuit to the reconfiguration controller 204, referencing circuit data 1, which is represented by the reference number 403-1. Although not shown in the flowchart, the reconfiguration controller 204 immediately starts reconfiguring the arithmetic unit 206 and performs error checking upon receiving the circuit data. After the reconfiguration and error checking are complete, the reconfiguration controller 204 sends a completion message to the process controller 202.

[0045] Then, in step S806, the process controller 202 determines whether the waiting time for the completion message has been exceeded; in other words, whether the reconfiguration and error checking of the arithmetic unit 206 were completed in time. If the process controller 202 determines that the waiting time has been exceeded, it determines that the process cannot be executed within the specified process period T and terminates the operation as an anomalous process. If the process controller 202 determines that the waiting time has not been exceeded, it also determines in step S807 whether the completion message has been received. If the completion message has been received, the process controller 202 proceeds to step S808. If the completion message has not been received, the process controller 202 proceeds to step S806.

[0046] In step S808, the process controller 202 executes the following process according to the value of the circuit ID. That is, if the circuit ID is "1", the reconfiguration of the first arithmetic circuit 207-1 has just been completed. Therefore, the process controller 202 commands the arithmetic unit 206 to start executing the operation. If the circuit ID is "2" or higher, the process controller 202 commands the arithmetic circuit that has just been reconfigured to adopt the process result of the arithmetic circuit that has just been executed and commands the arithmetic circuit to execute the operation. Therefore, the process controller 202 commands the arithmetic unit 206 to adopt the operation data. For example, the process controller 202 orders the third Operation B circuit 207B-3, which has just been reconfigured, to take over the operation data of the second Operation B circuit 207B-2, which has just been executed.

[0047] Then, in step S809, the process controller 202 determines whether the circuit ID equals a defined value, namely the value in the "Number of Partitions" field 402 of circuit management DB 4. If the process controller 202 determines that the circuit ID equals the value in this field, the reconfiguration of all circuit data corresponding to operation type 401 shown in circuit management DB 4 is complete. Therefore, the process controller 202 proceeds to step S811 and retrieves the operation result from arithmetic unit 206. More precisely, the process controller 202 retrieves the operation result after waiting for the completion of the operation of the Nth arithmetic circuit 207-N. If the process controller 202 determines that the circuit ID is not equal to the value in the field, the process controller 202 advances to step S810, increments the circuit ID and returns to step S805.

[0048] In step S812, which is executed after step S811, process controller 202 determines whether the process ID is equal to a defined value, namely the value in the process number field 301 of process information DB 3. If process controller 202 determines that the process ID is equal to the value in the field, all processes shown in process information DB 3 are completed. Therefore, process controller 202 proceeds to step S814, issues a rule command as the final result, and terminates the process. Fig. 8. Operation shown. If the process controller 202 determines that the circuit ID is not equal to the value in the field, the process controller 202 advances to step S813, increments the circuit ID and returns to step S803. <Flussdiagramm des Rekonfigurationsreglers>

[0049] Fig. Figure 9 is a flowchart illustrating an operation of the reconfiguration controller 204. The reconfiguration controller 204 operates through the joint operation of the setting unit 41, the configuration unit 42, the fault monitoring unit 43, and the circuit data buffer unit 44, which are shown in Fig. Figure 4 is shown. As described above, the reconfiguration controller 204 executes the operation shown in the following flowchart whenever the process controller 204 receives the reconfiguration command, which includes the circuit data, from the process controller 202. The management and setting of the operation time in steps S901 to S905 are performed by the setting unit 41.

[0050] In step S901, the reconfiguration controller 204 writes the circuit data contained in the received reconfiguration command to the arithmetic circuit 207. The reconfiguration controller 204 then starts the reconfiguration of the arithmetic circuit 207, with the configuration unit 42 waiting a predetermined time for the reconfiguration to complete in step S902. When the reconfiguration controller 204 determines in step S902 that the reconfiguration is complete, it proceeds to step S903. In step S903, the reconfiguration controller 204 checks whether the error of the arithmetic circuit 207 configured with the written circuit data has occurred.In other words, the reconfiguration controller 204 reads the configuration memory of the section corresponding to the arithmetic circuit 207 from the fault monitoring unit 43 and checks whether or not the read memory matches the written information.

[0051] Then, in step S904, the reconfiguration controller 204 determines whether or not the error detected in step S903 has occurred. If the reconfiguration controller 204 determines that the error has not occurred, it proceeds to step S905. If the reconfiguration controller 204 determines that the error has been detected, it returns to step S901 and performs the reconfiguration again. When the reconfiguration controller 204 returns to step S901 and rewrites the circuit data to the arithmetic circuit 207, it rewrites the circuit data to the arithmetic circuit 207 using the circuit data that was temporarily stored in the circuit data buffer unit 44. In step S905, the reconfiguration controller 204 reports the completion of the reconfiguration and error checking to the process controller 202.The operation ends after the steps described above. <operationsabfolge>

[0052] Fig. Figure 10 is a flowchart that represents an operation of the device for controlling autonomous locomotion 2. More precisely, it represents Fig. 10 represents the process of the device for controlling autonomous locomotion 2, when the process information DB 3, which is in Fig. 6 is shown, and the circuit management DB 4, which is in Fig. The image shown in 7 can be used. Fig. 10 represents only a single period of time T. However, these processes are executed repeatedly. That is, S1001 at the top left of Fig. 10 to S1039 at the bottom left of Fig. 10 are the processes that correspond to a single period.

[0053] First, the process controller 202 reads the process number 301 and the process information 302 from the process information DB 3 and reads the operation type 401, the number of partitions 402, and the circuit data 403 from the circuit management DB 4 (S1001). To execute operation A of process information 1, for which reference number 302-1 stands, the process controller 202 then sends the reconfiguration command, which includes the circuit data of the first operation A circuit designated by circuit data 1 and for which reference number 403-1 stands, to the reconfiguration controller 204 (S1002). The reconfiguration controller 204 writes the circuit data of the first operation A circuit to the arithmetic unit 206 (S1003).After the reconfiguration in the arithmetic unit 206 is complete (S1004), that is, after the first operation-A circuit 207A-1 has been configured, the reconfiguration controller 204 performs the error check on the first operation-A circuit 207A-1 (S1005). In S1005, the reconfiguration controller 204 reads the information written to the configuration memory of the arithmetic unit 206. Therefore, an arrow is drawn from the arithmetic unit 206 to the reconfiguration controller 204. After the error check is complete (S1006), the reconfiguration controller 204 sends the completion message to the process controller 202 (S1007).

[0054] The process controller 202 then commands the arithmetic unit 206 to start the process of the first operation-A circuit 207A-1 (S1008) and sends the reconfiguration command, including the circuit data of the second operation-A circuit designated by circuit data 2 and reference number 403-2, to the reconfiguration controller 204 (S1009). The reconfiguration controller 204 writes the circuit data of the second operation-A circuit to the arithmetic unit 206 (S1010). Consequently, the execution of the operation in the first operation-A circuit 207A-1 and the writing of the circuit data of the second operation-A circuit are performed simultaneously. After the reconfiguration in the arithmetic unit 206 has been completed (S1011), that is, after the second operation-A circuit 207A-2 has been configured, the reconfiguration controller 204 performs the error check on the second operation-A circuit 207A-2 (S1012).After the error check has been completed (S1013), the reconfiguration controller 204 sends the completion message to the process controller 202 (S1014).

[0055] Then the process controller 202 instructs the second operation-A circuit 207A-2 of the arithmetic unit 206 to accept the operation result of the first operation-A circuit 207A-1 and start the process (S1015). Then the arithmetic unit 206 sends the operation result of the second operation-A circuit 207A-2 to the process controller 202 (S1016).

[0056] Since operation A, designated by process information 1, has ended, the process controller 202 advances to the next process, that is, to operation B, designated by process information 2. To execute operation B of process information 2, for which reference number 302-2 stands, the process controller 202 then sends the reconfiguration command, which includes the circuit data of the first operation B circuit, designated by circuit data 1, for which reference number 403-1 stands, to the reconfiguration controller 204 (S1017). The reconfiguration controller 204 writes the circuit data of the first operation B circuit to the arithmetic unit 206 (S1018). After the reconfiguration in the arithmetic unit 206 has been completed (S1019), that is, after the first operation-B circuit 207B-1 has been configured, the reconfiguration controller 204 performs the error check on the first operation-B circuit 207B-1 (S1020).After the error check has been completed (S1021), the reconfiguration controller 204 sends the completion message to the process controller 202 (S1022).

[0057] The process controller 202 then commands the arithmetic unit 206 to start the process of the first operation-B circuit 207B-1 (S1023) and sends the reconfiguration command, including the circuit data of the second operation-B circuit, designated by circuit data 2, for which the reference number 403-2 stands, to the reconfiguration controller 204 (S1024). The reconfiguration controller 204 writes the circuit data of the second operation-B circuit to the arithmetic unit 206 (S1025). Consequently, the execution of the operation in the first operation-B circuit 207B-1 and the writing of the circuit data of the second operation-B circuit are performed simultaneously. After the reconfiguration in the arithmetic unit 206 has been completed (S1026), that is, after the second operation-B circuit 207B-2 has been configured, the reconfiguration controller 204 performs the error check on the second operation-B circuit 207B-2 (S1027).After the error check has been completed (S1028), the reconfiguration controller 204 sends the completion message to the process controller 202 (S1029).

[0058] The process controller 202 then commands the second operation-B circuit 207B-2 of the arithmetic unit 206 to accept the operation result of the first operation-B circuit 207B-1 and start the process (S1030). Simultaneously, the process controller 202 sends the reconfiguration command, which includes the circuit data of the third operation-B circuit, designated by circuit data 3, for which the reference number 403-3 stands, to the reconfiguration controller 204 (S1031). The reconfiguration controller 204 writes the circuit data of the third operation-B circuit to the arithmetic unit 206 (S1032). Consequently, the execution of the operation in the second operation-B circuit 207B-2 and the writing of the circuit data of the third operation-B circuit are performed simultaneously.After the reconfiguration in the arithmetic unit 206 is completed (S1033), that is, after the third operation B circuit 207B-3 has been configured, the reconfiguration controller 204 performs the error check on the second operation B circuit 207B-3 (S1034). After the error check is completed (S1035), the reconfiguration controller 204 sends the completion message to the process controller 202 (S1036).

[0059] Then, the process controller 202 instructs the third operation-B circuit 207B-3 of the arithmetic unit 206 to accept the operation result of the second operation-B circuit 207B-2 and start the process (S1037). The arithmetic unit 206 then sends the operation result of the third operation-B circuit 207B-3 to the process controller 202 (S1038). The process controller 202 terminates operation B, which is designated by process information 2, and ends all processes. Therefore, the process controller 202 outputs a control command value (S1039) and terminates the operation. This was described above in Fig. The transition scheme shown in 10 is described. <zeitsteuerungsdiagramm>

[0060] Fig. Figure 11 is a timing diagram representing an operation of the device for controlling autonomous locomotion 2. The diagram in Fig. The timing control diagram shown in 11 corresponds to the operation of the device for controlling autonomous locomotion 2, which is in Fig. 10 is shown. Fig. 11. Time increases from left to right. As at the left end in Fig. As shown in 11, it represents Fig. 11. The operation of the process controller 202, the state of the first operation-A circuit 207A-1, the state of the second operation-A circuit 207A-2, the state of the first operation-B circuit 207B-1, the state of the second operation-B circuit 207B-2, and the state of the third operation-B circuit 207B-3 are shown in the order above. Due to space constraints in Fig. However, in section 11, the reconfiguration of the logic circuit is specified as "configuration", and the error checking of the reconfigured logic circuit is specified as "check".

[0061] The process controller 202 starts the periodic process at time t0, reads the process number 301 and the process information 302 from the process information DB 3, and reads the operation type 401, the number of partitions 402, and the circuit data 403 from the circuit management DB 4. When the reading is complete at time t1, the process controller 202 reports the reconfiguration command, including the circuit data of the first operation-A circuit, designated by circuit data 1, for which the reference number 403-1 stands, to the reconfiguration controller 204, and the reconfiguration of the first operation-A circuit 207A-1 is started by the reconfiguration controller 204.

[0062] From time t2, after the reconfiguration and error checking of the first Operation-A circuit 207A-1 have been completed, the process controller 202 executes the following two processes. That is, the process controller 202 commands the first Operation-A circuit 207A-1 to start the process and sends the reconfiguration command, including the circuit data of the second Operation-A circuit, designated by circuit data 2, for which the reference number 403-2 stands, to the reconfiguration controller 204. The reconfiguration of the second Operation-A circuit 207A-2, which receives the message, is started by the reconfiguration controller 204.

[0063] At time t3, the reconfiguration and error checking of the second Operation A circuit 207A-2 are complete, and simultaneously, the operation process of the first Operation A circuit 207A-1 is complete. The process controller 202 then commands the second Operation A circuit 207A-2 to adopt the operation result of the first Operation A circuit 207A-1 and start its process. At time t4, after the operation process of the second Operation A circuit 207A-2 is complete, the process controller 202 sends the reconfiguration command, including the circuit data of the first Operation B circuit (designated by circuit data 1, for which the reference number 403-1 stands), to the reconfiguration controller 204. The reconfiguration of the first Operation B circuit 207A-1 is then started by the reconfiguration controller 204.

[0064] At time t5, after the reconfiguration and error checking of the first Operation B circuit 207B-1 have been completed, the process controller 202 commands the first Operation B circuit 207B-1 to start the process and executes the following process. That is, the process controller 202 sends the reconfiguration command, which includes the circuit data of the second Operation B circuit, designated by circuit data 2, for which the reference number 403-2 stands, to the reconfiguration controller 204. The reconfiguration of the second Operation B circuit 207B-2 is started by the reconfiguration controller 204 in response to the message.

[0065] At time t6, after the reconfiguration and error checking of the second Operation B circuit 207B-2 have been completed, the process controller 202 commands the second Operation B circuit 207B-2 to adopt the operation result of the first Operation B circuit 207B-1 and start the process. However, the operation process of the first Operation B circuit 207B-1 is not yet complete. Therefore, the operation process of the second Operation B circuit 207B-2 cannot be started using the result of the operation process of the first Operation B circuit 207B-1. Furthermore, the process controller 202 reports the reconfiguration command, including the circuit data of the first operation-A circuit, designated by the circuit data 3, for which the reference number 403-3 stands, to the reconfiguration controller 204, and the reconfiguration of the third operation-B circuit 207B-3 is started by the reconfiguration controller 204.

[0066] At time t7, after the operation process of the first Operation B circuit 207B-1 has completed, the second Operation B circuit 207B-2 takes over the operation result of the first Operation B circuit 207B-1 and starts the process. This operation process is completed before time t8. However, at this time, the error checking of the third Operation B circuit 207B-3 is not yet complete. Therefore, the operation of the third Operation B circuit 207B-3 cannot be started. At time t8, after the reconfiguration and error checking of the third Operation B circuit 207B-3 have been completed, the process controller 202 commands the third Operation B circuit 207B-3 to take over the operation result of the second Operation B circuit 207B-2 and start the process.At time t9, after the operation process of the third operation-B circuit 207b-3 has been completed, the process controller 202 issues a control instruction based on the operation result. At time t10, after the output of the control instruction has been completed, the process controller 202 terminates the processes corresponding to a single period of time t.

[0067] According to the first embodiment described above, the following effects can be achieved. (1) The autonomous locomotion control device 2 comprises: the logic circuit 255, which is capable of reconfiguring a plurality of arithmetic circuits, including the first Operation-A circuit 207A-1 and the second Operation-A circuit 207A-2; the reconfiguration controller 204, which reconfigures the arithmetic circuits based on reconfiguration commands and verifies the reconfigured arithmetic circuits; and the process controller 202, which sends the reconfiguration commands to the reconfiguration controller 204 and commands the arithmetic unit to perform operations. When a first reconfiguration command is received, the reconfiguration controller 204 reconfigures and verifies the first circuit (S901, S903 in Fig. 9) When the verification of the first circuit by the reconfiguration controller 204 is complete, the process controller 202 commands the first circuit to perform an operation (S807 in Fig. 8: Yes, S808). After the first circuit has been reconfigured, the process controller 202 sends a second reconfiguration command to the reconfiguration controller 204, instructing the reconfiguration controller 204 to start reconfiguring the second circuit until the execution of a predefined process of the first circuit is complete (S809: NO, S805).

[0068] The process controller 202 partitions and reconfigures the arithmetic circuits that form the arithmetic unit 206, such that the time for which the arithmetic circuit performs the operation overlaps with the time required to prepare for the execution of the operation in the next arithmetic circuit. Therefore, the process controller 202 recovers the time required for preparing for the execution of the operation in the arithmetic circuit, the so-called overhead, thus reducing the processing time required until all operations by the logic circuit 255 are completed from the start of the reconfiguration of the logic circuit 255.

[0069] (2) After the verification of the first circuit has been completed, the process controller 202 sends the second reconfiguration command to the reconfiguration controller until the operation of the first circuit is completed (between time t2 and time t3 in Fig. 11) Therefore, the present invention is even applicable to a case in which the logic circuit 255 according to the embodiment is used, which cannot perform the reconfiguration and error checking of the arithmetic circuits simultaneously. Immediately after the check of the first circuit has been completed, the operation of the first circuit starts. Therefore, it can also be said that after the start of the operation of the first circuit, the process controller 202 sends the second reconfiguration command to the reconfiguration controller until the operation of the first circuit is completed.

[0070] (3) After the reconfiguration of the second circuit is complete, the reconfiguration controller 204 checks the second circuit. Once the check of the second circuit and the operation of the first circuit are complete, the process controller 202 commands the second circuit to perform an operation using the result of the first circuit. Therefore, the operation can be performed using the result of the preceding operation.

[0071] (4) The reconfiguration controller 204 restarts the reconfiguration of the arithmetic circuits if an error is detected during the arithmetic circuit check (S904 in Fig. 9: NO, S901). Therefore, the autonomous locomotion control device 2 can perform the operation in a state in which no error occurs in the reconfigured arithmetic circuits.

[0072] (5) The number and size of each of the arithmetic circuits reconfigured in logic circuit 255 are determined based on the execution time of the operation performed in the arithmetic circuit. As at time t2 to time t3 in Fig. As shown in Figure 11, the operation execution time of the first operation-A circuit 207A-1 can therefore be matched to the time of reconfiguration and error checking, that is, the time required to prepare for the execution of the second operation-A circuit 207A-2.

[0073] (6) The autonomous locomotion control device 2 further includes the circuit management DB 4, which stores information regarding the arithmetic circuits configured in the logic circuit 255. The process controller 202 issues the reconfiguration command to the reconfiguration controller 204 based on the circuit management DB 4. Therefore, the process controller 202 reads the circuit management DB 4, which is generated beforehand, and can issue the reconfiguration command to the reconfiguration controller 204.

[0074] (7) The reconfiguration controller 204 includes the configuration unit 42, which reconfigures the arithmetic circuits, and the fault monitoring unit 43, which checks the reconfigured arithmetic circuits. The configuration unit 42 starts the reconfiguration of the arithmetic circuits after receiving the reconfiguration commands from the process controller. After the reconfiguration by the configuration unit 42 has been completed, the fault monitoring unit 43 starts the check of the reconfigured arithmetic circuits and reports a result of the check to the process controller 202. (Modification example 1)

[0075] In the first embodiment described above, the result of the preceding operation is used for each of the second and subsequent arithmetic circuits executed in the arithmetic unit 206. However, not every arithmetic circuit in the arithmetic unit 206 needs to use the result of the previous operation. In this case, a circuit management DB 4A is used instead of the circuit management DB 4. This DB 4A contains not only all the circuit data but also information regarding whether or not the result of the preceding operation should be used. The process controller 202 determines in S808 of Fig. 8, whether or not to instruct the arithmetic circuit to take over the operation data obtained from the operation just performed, with reference to the circuit management DB 4A.

[0076] Fig. Figure 12 is a sketch that represents an example of the circuit management DB 4A according to a modification example 1. In circuit management DB 4A, the number of circuit data units 403 is greater than in circuit management DB 4. Specifically, in circuit management DB 4A, the circuit data 403 stores information about the circuit data, which has been partitioned into multiple pieces, and whether or not the arithmetic circuit should be instructed to accept the operation data, depending on the operation type 401. More precisely, circuit data 1 includes circuit type 403-11 and whether or not to accept operation data 403-12; circuit data 2 includes circuit type 403-21 and whether or not to accept operation data 403-22; and circuit data 3 includes circuit type 403-31 and whether or not to accept operation data 403-32.

[0077] Operation type A is the first process to be executed. Therefore, regarding whether or not to adopt operation data 403-12, "Not executed" is stored in circuit data 1. After the error check of the first operation A circuit is complete, the process controller 202, which reads the data, commands the first operation A circuit to execute the operation immediately. Additionally, regarding whether or not to adopt operation data 403-22, "Not executed" is stored in circuit data 2 of operation type A. After the error check of the second operation A circuit is complete, the process controller 202, which reads the data, commands the second operation A circuit to execute the operation immediately. For operation type B, regarding whether or not to adopt operation data 403-12, "Executed" is stored in circuit data 1.After the error check of the first operation-B circuit has been completed, the process controller 202, which reads the data, commands the first operation-B circuit 207B-1 to take over the operation result of operation type A, that is, the preceding operation, more precisely the operation result of the second operation-A circuit 207A-2, and to start the process.

[0078] If the arithmetic operation does not use the result of the arithmetic circuit that was just executed, then with this configuration, the operation can be performed immediately after the reconfigured circuit has been checked. This means that unnecessary waiting time can be reduced, and the overall processing time—that is, the time from the start of the reconfiguration until the completion of the operation—can be shortened. (Modification example 2)

[0079] In the first embodiment described above, the process of the next operation type starts after the process of the preceding operation type has completed. However, if the areas of the logic circuit to be reconfigured do not overlap, the reconfiguration and error checking of the logic circuit of the next operation type can be started without waiting for the completion of the process of the preceding operation type. <zeitsteuerungsdiagramm>

[0080] Fig. Figure 13 is a timing diagram representing an operation of the autonomous locomotion control device 2 according to the modification example. Fig. 13. Are time points t0 to t4 and t10 the same as they are in Fig. Figure 11 of the first embodiment is shown. Furthermore, the operations at time t0 to t3 are the same as those described in Figure 11. Fig. Figure 11 illustrates this modification. In this example, the process controller 202 commands the second Operation-A circuit 207A-2 to start the process at time t3 and sends the reconfiguration command, including the circuit data of the first Operation-B circuit, to the reconfiguration controller 204. The reconfiguration of the first Operation-B circuit 207B-1 is then initiated by the reconfiguration controller 204. That is, the reconfiguration of the first Operation-B circuit 207B-1, which in the first embodiment starts at time t4, is brought forward to time t3. The reason why the execution of the second Operation-A circuit 207A-2 and the reconfiguration of the first Operation-B circuit 207B-1 can be carried out simultaneously is that their time domains do not overlap.

[0081] During the operation of the device for controlling autonomous locomotion 2 after time t4, the time after time t4 in the first embodiment is advanced by (t4-t3), that is, shifted to an earlier time. Therefore, the output of the control command in the first embodiment is completed at time t10, but in the modified example, it is completed at a time that is (t4-t3) earlier than time t10. <Operation des Prozessreglers 202>

[0082] Fig. Figure 14 is a flowchart that represents an operation of the process controller 202 according to the modification example. Fig. 14 mainly represents points that compare to those of Fig. 9 differs from the first embodiment and does not represent identical processes. Furthermore, processes that are identical to those of the first embodiment are not repeated in the following description.

[0083] In step S850, which is executed after step S804, the process controller 202 determines whether the area of ​​the circuit in which the operation is performed and the area of ​​the circuit that is subsequently reconfigured overlap. Circuit data stored in circuit DB 5 also includes information about the size of the circuit to be reconfigured. Therefore, the process controller 202 can determine the area configured by each circuit by referring to all circuit data used in the same type of operation. If the process controller 202 determines that the areas overlap, it stops at step S850 and waits for the completion of the operation just performed. If the process controller 202 determines that the areas do not overlap, it proceeds to step S805.If there is no circuit in which the operation is currently being executed, for example, if the first process is being executed in step S850, the process controller 202 decides NO in this step. The processes after step S805 are the same as in the first embodiment. However, if the process controller 202 decides YES in step S809, it proceeds to step S812 without executing step S811. That is, in the first embodiment, the process controller 202 waits until the result of the operation in step S811 is obtained. However, in the first embodiment, the process controller 202 proceeds to step S812 without waiting.

[0084] When the process controller 202 commands the second operation-A circuit 207A-2 to start the operation process at time t3 (S808), as in Fig. As shown in Figure 13, the process controller 202 therefore decides YES in step S809, proceeds to S812, decides NO in S812, and returns to step S803 via step S813. Since the process controller 202 decides NO in step S850, the reconfiguration of the first Operation B circuit 207B-1 is started in step S805. The processes from step S809 to step S850 are executed immediately. Therefore, the timing diagram in Fig. 13 shows that the start of the operation process of the second Operation-A circuit 207A-2 and the start of the reconfiguration of the first Operation-B circuit 207B-1 are executed simultaneously.

[0085] With this configuration, the time required to prepare the arithmetic circuits of different operation types can be made up for, thus reducing the time it takes for all operations to be completed by the logic circuit 255 from the start of the reconfiguration of the logic circuit 255. (Modification example 3)

[0086] In the first embodiment described above, the process controller 202 sends the second reconfiguration command after the reconfiguration of the first circuit has been completed. However, the process controller 202 can send the second reconfiguration command after the verification of the first circuit has been completed, until the execution of a predefined process of the first circuit has been completed. For example, in Fig. 11 The reconfiguration command of the second Operation A circuit 207A-2 will be sent between time t2 and time t3. <Andere Modifikationen>

[0087] The embodiment described above can be further modified as follows. (1) The reconfiguration controller 204 does not necessarily have to include the circuit data buffer unit 44. In this case, if the fault monitoring unit 43 detects a fault, the process controller 202 sends the circuit data again to the reconfiguration circuit 203. (2) The reconfiguration controller 204 can be configured partially or completely outside of the reconfiguration circuit 203. <Zweite Ausführungsform>

[0088] In the following, a second embodiment of a device for controlling autonomous locomotion, which is an electronic control device, is described with reference to Fig. 15. In the following description, components that are identical to those of the first embodiment are designated with the same reference numbers, and differences are mainly described. Points not specifically described are identical to those of the first embodiment. The second embodiment differs from the first embodiment in that the logic circuit can perform the reconfiguration and error checking of the arithmetic circuit simultaneously. <systemkonfiguration>

[0089] The configuration of the autonomous locomotion control device according to the second embodiment is the same as that of the first embodiment. However, a program stored in the ROM 252 of the autonomous locomotion control device 2 differs from that of the first embodiment, and an operation of the process controller 202 also differs from that of the first embodiment. Furthermore, in this embodiment, the setting unit 41 also notifies the reconfiguration controller 204 of the process controller 202 when the reconfiguration of the arithmetic circuit by the configuration unit 42 has been completed. When the message that the reconfiguration of the arithmetic circuit has been completed is received from the reconfiguration controller 204, the process controller 202 sends the reconfiguration command to the reconfiguration controller 204 to start the reconfiguration of the next arithmetic unit. <zeitsteuerungsdiagramm>

[0090] Fig. Figure 15 is a timing diagram representing an operation of the device for controlling autonomous locomotion 2 according to the second embodiment. Fig. 15. Time points t0 to t5, t7 and t8 are the same as they are in Fig. Figure 11 of the first embodiment is shown. The reconfiguration of the first operation-A circuit 207A-1 is started at time t1 and completed at time t31. The process controller 202, which receives the completion message, begins the reconfiguration of the second operation-A circuit 207A-2. The error check of the second operation-A circuit 207A-2 is completed at time t32, which is earlier than time t3, but the operation of the first operation-A circuit 207A-1 is not yet complete. Therefore, the operation of the second operation-A circuit 207A-2 cannot yet be started. Therefore, as in the first embodiment, the process controller 202 waits for the completion of the operation of the first operation-A circuit 207A-1 at time t3 and then starts the operation of the second operation-A circuit 207A-2. At time t4, the operation of the second Operation-A circuit 207A-2 is completed.Therefore, the reconfiguration of the first Operation B circuit 207B-1 can be started.

[0091] At time t33, when the reconfiguration of the first operation B circuit 207B-1 is complete, the reconfiguration of the second operation B circuit 207B-2 is started. Simultaneously, at time t5, when the reconfiguration of the second operation B circuit 207B-2 is complete, the reconfiguration of the third operation B circuit 207B-3 is started. The error check of the second operation B circuit 207B-2 is complete at t34, but the operation of the first operation B circuit 207B-1 is not yet complete. Therefore, the process controller 202 waits for the completion of the operation of the second operation B circuit 207B-1. The second operation B circuit 207B-2 starts the operation at time t7, as in the first embodiment. The error check of the third operation B circuit 207B-3 is completed at time t8 in the first embodiment.However, in this embodiment, the error check is completed before the second operation-B circuit 207B-2 finishes its operation. Therefore, the third operation-B circuit 207B-3 starts its operation at time t35, which is earlier than time t8.

[0092] The start time of the third operation-B circuit 207B-3 is earlier than in the first embodiment. Therefore, time t36, that is, the time of completion of the operation of the third operation-B circuit 207B-3, is also earlier than time t9, that is, the time of completion of the operation of the third operation-B circuit 207B-3 in the first embodiment. This means that the time period Ta from t0 to t37, which contains the control instruction executed after the completion of the operation of the third operation-B circuit 207B-3, is shorter than that of the first embodiment.

[0093] According to the second embodiment described above, the following effects can be achieved.

[0094] (8) The process controller 202 sends the second reconfiguration command after the reconfiguration of the first circuit has been completed. Therefore, if an FPGA capable of performing reconfiguration and error checking simultaneously is used, the processing time of the logic circuit can be further reduced. (Modification examples of the second embodiment)

[0095] In the second embodiment described above, the process controller 202 sends the second reconfiguration command after the reconfiguration of the first circuit has been completed. However, the process controller 202 can send the second reconfiguration command after the reconfiguration of the first circuit has been completed, until the verification of the first circuit has been completed. For example, in Fig. 15 The reconfiguration command of the second Operation A circuit 207A-2 will be sent between time t31 and time t2.

[0096] The present invention is not limited to the embodiments shown and includes various modifications and identical configurations within the scope of the appended claims. For example, the embodiments have been described in detail to provide a good description of the present invention, and the present invention need not necessarily include all the configurations described above. Furthermore, the drawings depict control lines or information lines that were deemed necessary for explanation, but they do not necessarily represent all the control lines or information lines required for the actual production line. It can be assumed that almost all components are actually interconnected.

[0097] The program is stored in ROM 251. However, the program can also be stored in flash memory 254. Furthermore, the autonomous locomotion control device 2 can have an input / output interface (not shown) so that a program can optionally be read from another device via a medium that can be used by the input / output interface and the autonomous locomotion control device 2. Here, "medium" refers, for example, to a storage medium that can be attached to and detached from the input / output interface, a communication medium (i.e., a wired network, a wireless network, an optical network, or the like), or a carrier wave or digital signal that propagates through the network. In addition, some or all of the functions implemented by the program can be implemented by a hardware circuit or an FPGA. List of reference symbols 2 Device for controlling autonomous locomotion 3 Process Information Database 4 Circuit Management Database 5 Circuit database 202 Process controllers 203 Reconfiguration circuit 204 Reconfiguration controllers 206 arithmetic units 207 arithmetic circuit 255 Logic circuit 41 Setting unit 42 Configuration unit 43 Fault monitoring unit 44 Circuit data buffer unit< / zeitsteuerungsdiagramm> < / systemkonfiguration> < / zeitsteuerungsdiagramm> < / zeitsteuerungsdiagramm> < / operationsabfolge> < / systemkonfiguration>

Claims

[1] Electronic control device comprising: a logic circuit (255) capable of reconfiguring a plurality of arithmetic circuits, including a first circuit and a second circuit; a reconfiguration controller (204) that reconfigures the arithmetic circuits based on reconfiguration commands and verifies the reconfigured arithmetic circuits; and a process controller (202) that sends the reconfiguration commands to the reconfiguration controller (204) and commands the arithmetic circuits to perform operations, wherein the reconfiguration controller (204) reconfigures and verifies the first circuit when a first reconfiguration command is received, The process controller (202) of the first circuit commands to perform an operation when the verification of the first circuit by the reconfiguration controller (204) is complete. After the first circuit has been reconfigured, the process controller (202) sends a second reconfiguration command to the reconfiguration controller (204) and orders the reconfiguration controller (204) to start the reconfiguration of the second circuit until the first circuit has completed its operation. [2] Electronic control device according to claim 1, wherein the process controller (202) sends the second reconfiguration command to the reconfiguration controller (204) after the reconfiguration of the first circuit has been completed, until the verification of the first circuit has been completed. [3] Electronic control device according to claim 1, wherein the process controller (202) sends the second reconfiguration command to the reconfiguration controller (204) after the verification of the first circuit has been completed, until the operation of the first circuit has been completed. [4] Electronic control device according to claim 1, wherein the reconfiguration controller (204) checks the second circuit after the reconfiguration of the second circuit is complete, and After completing the verification of the second circuit and the operation of the first circuit, the process controller (202) commands the second circuit to perform an operation using the result of the first circuit. [5] Electronic control device according to claim 1, wherein the reconfiguration controller (204) restarts the reconfiguration of the arithmetic circuits when an error is detected during the verification of the arithmetic circuits. [6] Electronic control device according to claim 1, wherein the number and size of each of the arithmetic circuits that are reconfigured in the logic circuit (255) are determined on the basis of an execution time of the operation that is performed in the arithmetic circuit. [7] Electronic control device according to claim 1, further comprising a circuit management database (4) which stores information regarding the multiple arithmetic circuits configured in the logic circuit (255), wherein the process controller (202) outputs the reconfiguration command based on the circuit management database (4) to the reconfiguration controller (204). [8] Electronic control device according to claim 1, wherein the reconfiguration controller (204) comprises a configuration unit (42) which reconfigures the arithmetic circuits and a fault monitoring unit (43) which checks the reconfigured arithmetic circuits, the configuration unit (42) begins reconfiguring the arithmetic circuits after receiving the reconfiguration commands from the process controller (202), and The fault monitoring unit (43) begins checking the reconfigured arithmetic circuits after the reconfiguration has been completed by the configuration unit (42) and reports a result of the check to the process controller (202). [9] Electronic control device according to claim 1, wherein, if an area where the first circuit is configured and an area where the second circuit is configured do not overlap, the process controller (202) after completion of the reconfiguration of the first circuit sends the second reconfiguration command to the reconfiguration controller (204) and commands the reconfiguration controller (204) to start the reconfiguration of the second circuit until the execution of the first operation is completed. [10] Circuit reconfiguration method performed in a logic circuit (255) in which a plurality of arithmetic circuits, including a first circuit and a second circuit, are reconfigurable, the circuit reconfiguration method comprising: Reconfigure and check the first circuit; Commands to execute an operation by the first circuit after the verification of the first circuit has been completed; and After completing the reconfiguration of the first circuit, start the reconfiguration of the second circuit until the operation of the first circuit is complete.

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