Semiconductor component and power converter

Abstract

Semiconductor device comprising: A circuit element (2) having a front surface and a rear surface and having a planar region; a terminal region (2a) formed above the front surface of the planar region of the circuit element (2) and parallel to the planar region; a semiconductor element (4) having a surface disposed below a surface of the terminal region (2a), the semiconductor element (4) being formed on the front surface of the planar region of the circuit element (2); a resin layer (6) disposed on the semiconductor element (4) and having a plurality of first openings (10) through which the semiconductor element (4) is exposed; a conductive layer (7, 8) disposed on the resin layer (6), having a surface above the surface of the terminal region (2a) and connected to the semiconductor element (4) through the plurality of first openings (10); and a sealing member (9) having a surface parallel to the planar region and integrally sealing the circuit element (2), the semiconductor element (4), the resin layer (6), the conductive layer (7,8) and a part of the terminal region (2a).

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device in which an electrode and a conductive layer provided on a semiconductor element are bonded together with a resin layer therebetween, and to a power converter including the semiconductor device. STATE OF THE ART

[0002] In a conventional semiconductor device, an electrode and any other region located on the semiconductor element are wired with a bonding wire made of aluminum or similar material and then resin-sealed to insulate the circuit. It is known that in a reliability test, a conventional semiconductor device with an aluminum bonding wire or similar material as the connection has a shorter lifespan due to the bonding wire breaking or peeling at an interface between the semiconductor element and the bonding wire, which is a cause of reduced reliability of the semiconductor device.

[0003] For example, Patent Document 1 discloses a semiconductor device in which a semiconductor element and a bonding wire are connected to a metal plate by solder to improve the reliability of the semiconductor device. However, in this structure, only the emitter electrode of the semiconductor element is connected to the metal plate, and the bonding wire is used for the gate electrode and the sensor electrode of the semiconductor element as in a conventional case. This increases the thickness of a sealing resin for sealing the bonding wire, resulting in an increased distance from the front surface of the semiconductor element to the outside of the sealing resin, which deteriorates the heat dissipation properties.

[0004] Against this background, a semiconductor device is desired that connects all electrodes using only the metal layer, without using a bonding wire as an interconnect. As a measure to meet this requirement, Patent Document 2, for example, describes a structure for wiring using a power overlay (POL).

[0005] Patent Document 3 relates to a semiconductor module, and more particularly to a wire-connection connection structure within the semiconductor module.

[0006] Patent Document 4 relates to a packaging material containing a thermosetting resin and a particulate filler and a method for producing the packaging material. STATE OF THE ART Patent Document 1: Japanese Patent Application Laid-Open No. JP 2015-53343A Patent Document 2: Japanese Patent Application Laid-Open No. JP 2015-70269A Patent document 3: US 2015 / 0 130 076 A1 Patent document 4: US 5,298,328 A BRIEF DESCRIPTION OF THE INVENTION Problems to be solved by the invention

[0007] Although a metal layer is used for wiring with the semiconductor element in conventional semiconductor devices, paths are formed around the semiconductor element, and upper and lower portions are wired through the paths. This also generates heat around the semiconductor element, which can thermally affect the semiconductor element. In addition, a terminal for electrical connection to the outside should be formed, and the terminal should be spaced from the back surface of the semiconductor element to ensure insulation properties when the terminal is led out from the side surface of the semiconductor device. The terminal is arranged at a connectable location in the upper portion of the metal layer and is completely sealed with a sealing resin.Therefore, if the heat generated in the semiconductor element is also dissipated to the outside by the metal layer on the front surface of the semiconductor element, the surface of the metal layer of the upper portion of the semiconductor element is flush with or below the surface of the terminal. This position results in an increased distance between the metal layer bonded to the semiconductor element and the sealing resin, which may deteriorate the heat dissipation properties of the semiconductor device.

[0008] The present invention is intended to solve this problem, and an object is to provide a molded-type semiconductor device with high heat dissipation characteristics. Means to solve the problems

[0009] The semiconductor device comprises: a circuit element having a front surface and a back surface and having a planar region; a terminal region formed above the front surface of the planar region of the circuit element and parallel to the planar region; a semiconductor element having a surface located below a surface of the terminal region, the semiconductor element being formed on the front surface of the planar region of the circuit element; a resin layer disposed on the semiconductor element and having a plurality of first openings through which the semiconductor element is exposed; a conductive layer disposed on the resin layer, having a surface located above the surface of the terminal region and connected to the semiconductor element through the plurality of first openings;and a sealing member having a surface parallel to the planar region and integrally sealing the circuit element, the semiconductor element, the resin layer, the conductive layer, and a part of the terminal region; Effect of the invention

[0010] In the semiconductor device according to the present invention, the surface of the conductive layer is located above the surface of the connection region, so that the distance from the conductive layer to the filler can be reduced, which leads to improved heat dissipation properties of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view of a semiconductor device in Embodiment 1 of the present invention; Fig. 2 is a schematic plan view of the semiconductor device in Embodiment 1 of the present invention; Fig. 3 is a schematic plan view of the semiconductor device in Embodiment 1 of the present invention before formation of an insulating resin layer; Fig. 4 is a schematic plan view of the insulating resin layer of the semiconductor device in Embodiment 1 of the present invention; Fig. 5 is a schematic plan view of the semiconductor device in Embodiment 1 of the present invention after formation of the insulating resin layer; Fig. 6 is a schematic plan view of the semiconductor device in Embodiment 1 of the present invention after formation of a conductive layer; Fig. 7 is a schematic plan view of the conductive layer of the semiconductor device in Embodiment 1 of the present invention; Fig. 8 is a schematic plan view of an opening and the surroundings of the semiconductor device in Embodiment 1 of the present invention; Fig. 9 is a schematic plan view of another opening and the surroundings on the semiconductor device in Embodiment 1 of the present invention; Fig. 10 is a schematic cross-sectional view of a semiconductor device in Embodiment 2 of the present invention; Fig. 11 is a schematic cross-sectional view of a semiconductor device in Embodiment 3 of the present invention; Fig. 12 is a schematic plan view of the semiconductor device in Embodiment 3 of the present invention; Fig. 13 is a schematic cross-sectional view of a semiconductor device in Embodiment 4 of the present invention; Fig. 14 is a schematic cross-sectional view of a semiconductor device in Embodiment 5 of the present invention; Fig. 15 is a schematic cross-sectional view of another semiconductor device in Embodiment 5 of the present invention; Fig. 16 is a schematic cross-sectional view of another semiconductor device in Embodiment 5 of the present invention; Fig. 17 is a schematic cross-sectional view of a semiconductor device in Embodiment 6 of the present invention; Fig. 18 is a schematic cross-sectional view of a semiconductor device in Embodiment 7 of the present invention, and Fig. 19 is a block diagram showing a configuration of a power converter system in which a power converter in Embodiment 8 of the present invention is used. DESCRIPTION OF THE EMBODIMENTS

[0011] A general configuration of a semiconductor device according to the present invention will first be described with reference to the drawings. Note that the drawings are schematic and not to scale. The same reference numeral refers to the same or corresponding parts throughout this specification. Embodiment 1

[0012] A semiconductor device in Embodiment 1 of the present invention will be described with reference to Fig. 1 and Fig. 2 described.

[0013] Fig. 1 is a schematic cross-sectional view of the semiconductor device in Embodiment 1 of the present invention. Fig. 2 is a schematic plan view of the semiconductor device in Embodiment 1 of the present invention. Fig. 1 is a schematic section along a Fig. 2 shown dash-dotted line.

[0014] The semiconductor device 100 has - as in Fig. 1, a heat conducting member 1, a lead frame 2, which is a circuit element, a solder 3, which is a connecting element, a semiconductor element 4, a conductive spacer 5, which is a connecting element, an insulating resin layer 6, which is a resin layer, a main circuit conductive layer 7, which is a conductive layer (first conductive layer), a control conductive layer 8, which is a conductive layer (second conductive layer), and a sealing resin 9, which is a sealing element. The distance from the surface of a terminal portion 2a, which is a terminal portion of the lead frame 2 within the sealing resin 9, to the surface of the sealing resin 9 is denoted by h1, the distance from the surface of the semiconductor element 4 to the surface of the sealing resin 9 is denoted by h2, and the distance from the surfaces of the main circuit conductive layer 7 and the control conductive layer 8 to the surface of the sealing resin 9 is denoted by h3.The surface of the sealing resin 9 is parallel to and faces the surface of the terminal portion 2a of the lead frame 2 and the surface of the semiconductor element 4.

[0015] The heat-conducting element 1 includes a metal foil / layer 1a and an insulating layer 1b formed on the surface of the metal foil / layer 1a. The heat-conducting element 1 is an insulating layer with high heat dissipation properties. The insulating layer 1b serves to insulate the metal foil / layer 1a and the lead frame 2 from each other and to dissipate the heat generated in the semiconductor element 4 to the metal foil 1a via the insulating layer 1b. A highly heat-conductive element, such as a copper plate, an aluminum plate, or a copper foil, is used as the metal foil 1a.

[0016] For the insulating layer 1b, a thermosetting resin such as epoxy resin is used, and a highly conductive filler such as silicon dioxide, aluminum oxide or boron nitride is mixed into the insulating layer 1b.

[0017] A lead frame 2 with a predetermined interconnection pattern is provided on the heat-conducting element 1. The lead frame 2 has a front surface and a back surface. The back surface of the lead frame 2 is disposed on the insulating layer 1b of the heat-conducting element 1. A back surface electrode of the semiconductor element 4 is connected to the interconnection pattern on the front surface of the lead frame 2, with solder 3 serving as a connecting element therebetween.

[0018] The lead frame 2, for example, has an interconnection circuit having a planar portion formed from a flat plate-shaped copper plate with a thickness of about 0.6 mm by press molding. The interconnection circuit of the lead frame 2 has the terminal portion 2a and a step portion (slant portion) 2b. The terminal portion 2a is connected via the step portion 2b to the interconnection circuit of the lead frame 2, on which the semiconductor element 4 is arranged. The terminal portion 2a and step portion 2b of the lead frame 2 do not contact the heat conducting member 1 because of the presence of the step portion 2b. Thus, the region between the metal foil 1a of the heat conducting member 1 and the terminal portion 2a and step portion 2b of the lead frame 2 is a region where the sealing resin 9 is used.The step region 2b of the lead frame 2 is a structure for limiting dielectric breakdown along an interface between the metal foil 1a of the heat-conducting element 1 and the sealing resin 9. The terminal region 2a is arranged within the sealing resin 9. The terminal region 2a partially protrudes from the inside to the outside on the outer surface side of the sealing resin 9. The terminal region 2a is formed above the front surface of the planar region of the lead frame 2.

[0019] The step portion 2b of the lead frame 2 is formed, for example, by half blanking (half etching). The height of the step portion 2b of the lead frame 2 is, for example, 0.1 mm or more and 0.3 mm, which is half the thickness of the lead frame 2, or less. Since the height of the step portion 2b of the lead frame 2 is set to 0.1 mm or more, the generation of a void in the sealing resin 9 filled between the heat conduction member 1 and the lead frame 2 is restricted.

[0020] Since the height of the step portion 2b of the lead frame 2 is set to 0.3 mm, which is half the thickness of the lead frame 2 or less, the strength of the lead frame 2 can be secured. Furthermore, since the step portion 2b is provided and the space around the step portion 2b is filled with sealing resin 9, the breakdown voltage between the metal foil 1a of the heat conduction member 1 and the lead frame 2 can be improved.

[0021] Since the step portion 2b is provided in the lead frame 2, the terminal portion 2a of the lead frame 2 inside the sealing resin 9 is disposed above the portion of the front surface (top surface) of the lead frame 2 on which the semiconductor element 4 is mounted. The semiconductor element 4 is disposed on the front surface of the lead frame 2. The surface of the semiconductor element 4 is disposed on the front surface (bottom surface) of the lead frame 2 relative to the surface of the terminal portion 2a of the lead frame 2, that is, the distance (h1) from the surface of the terminal portion 2a of the lead frame 2 inside the sealing resin 9 to the surface of the sealing resin 9 is smaller than the distance (h2) from the surface of the semiconductor element 4 to the surface of the sealing resin 9. Also, the surface of the terminal portion 2a of the lead frame 2 inside the sealing resin 9 is disposed above the surface of the semiconductor element 4.The surface of the semiconductor element 4 is located below the surface of the connection region 2a of the sealing resin 9. Such an arrangement can improve the breakdown voltage between the metal foil 1a of the heat conducting element 1 and the connection region 2a of the lead frame 2 as described above.

[0022] The semiconductor element 4 is, for example, a diode used for an inverter unit that converts an input alternating current (AC) power into direct current (DC) power, a bipolar transistor used for an inverter unit that converts direct current power into alternating current power, an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), or a gate turn-off thyristor (GTO).

[0023] The conductive spacer 5 is formed on the surface of the lead frame 2 corresponding to the area where the semiconductor element 4 is arranged (connected), and is electrically connected to the semiconductor element 4 through the main circuit conductive layer 7 and the control conductive layer 8. As the conductive spacer 5, a metal plate made of copper, aluminum, or the like is arranged at a predetermined position on the surface of the lead frame 2 via solder 3 or the like. The conductive spacer 5 can also be formed by stacking solder 3 instead of the metal plate. For example, since a non-conductive plate is arranged by bonding with an adhesive at a position where electrical connection is not required, the conductive spacer 5 can also be used as a supporting member of the insulating resin layer 6.The height of the conductive spacer 5 is equal to the height of the semiconductor element 4 in a region where the insulating resin layer 6 can be formed thereon.

[0024] For example, a polymer material such as liquid crystal polymer or polyimide is used for the insulating resin layer 6. The insulating resin layer 6 is composed of a single-layer resin layer formed by spin coating, printing, or the like, or a stacked layer comprising a stack of resin layers. The insulating resin layer 6 has a layer thickness that enables electrical insulation of the semiconductor element 4 on the lower surface side of the insulating resin layer 6 from the main circuit conductive layer 7 or the control conductive layer 8 on the surface side of the insulating resin layer 6. Alternatively, the insulating resin layer 6 may have a region of a different thickness formed by laminating (stacking) resin layers at a predetermined location of the insulating resin layer 6 where withstand voltage is required.

[0025] The insulating resin layer 6 is in the form of a sheet and is arranged continuously (across) on the surfaces of the semiconductor elements 4. The insulating resin layer 6 is also arranged continuously on the surface of the semiconductor element 4 and the surface of the conductive spacer 5. The insulating resin layer 6 has openings 10, which are first openings and through which the semiconductor element 4 and the conductive spacer 5 are electrically connected to the main circuit conductive layer 7 and the control conductive layer 8, respectively. The openings 10 are connected to the semiconductor element 4 and the conductive spacer 5 at different opening positions. The main circuit conductive layer 7 and the control conductive layer 8 are wired through the openings 10 of the insulating resin layer 6, for example, byThe openings 10 are filled using a plating method using copper as the material, and then these layers are stacked on the surface of the insulating resin layer 6. The insulating resin layer 6 may have a plurality of openings 10 formed according to a circuit configuration. The openings 10 may have a variety of sizes depending on the intended use.

[0026] The insulating resin layer 6 also has an opening 11, which is a second opening. In plan view, a region (a region not in contact with any semiconductor element 4 or conductive spacer 5) that is not on the front surface of the lead frame 2 and in which the semiconductor element 4 or the conductive spacer 5 is arranged is provided at least partially around the opening 11 (see Fig. 2, Fig. 7, Fig. 8). The opening 11 encloses a narrow gap formed, for example, between the semiconductor elements 4 or between the conductive spacer 5 or the semiconductor element 4 and the conductive spacer 5. When sealed by filling with sealing resin 9, the sealing resin 9 fills the space between the semiconductor elements 4 or between the conductive spacer 5, between which the narrow gap is enclosed, through the opening 11. Thus, the sealing resin 9 is filled on the lower surface side of the insulating resin layer 6.

[0027] The main circuit conductive layer 7 is connected, for example, to the source electrode or the emitter electrode, which is the main electrode of the semiconductor element 4. The control conductive layer 8 is connected, for example, to the gate electrode or the sense electrode, which is the control electrode of the semiconductor element 4. In the present embodiment, the main circuit conductive layer 7 and the control conductive layer 8 are identical in position in the thickness direction (have the same thickness), that is, the time period for stacking a conductive layer by plating or the like is the same. Furthermore, for example, in the case of the semiconductor element 4 as a diode, there is no control electrode, so only the main circuit conductive layer 7 is connected to the main electrode of the diode. In the case of using a plurality of semiconductor elements 4, the main circuit conductive layer 7 connects the semiconductor elements 4 to each other or connects the semiconductor element 4 and the conductive spacer 5 to each other.The control conductive layer 8 connects the control electrode of the semiconductor element 4 and the conductive spacer 5 to each other.

[0028] The main circuit conductive layer 7 and the control conductive layer 8 each have a thickness greater than or equal to the thickness of the insulating resin layer 6. If the main circuit conductive layer 7 and the control conductive layer 8 each have a thickness smaller than the thickness of the insulating resin layer 6 in the opening 10, each conductive layer cannot fill the opening 10 and cannot function as a current path due to an increased resistance as a conductive layer. In addition, excessive heat is generated due to the increased resistance, and accordingly, the generated heat cannot be efficiently dissipated to the outside of the sealing resin 9, which deteriorates the heat dissipation properties.However, the opening 10 can be filled by making the thicknesses of the main circuit conductive layer 7 and the control conductive layer 8 greater than the thickness of the insulating resin layer 6, so that the main circuit conductive layer 7 and the control conductive layer 8 can be formed on the insulating resin layer 6. In addition, the resistance values ​​of the main circuit conductive layer 7 and the control conductive layer 8 can be reduced by making the thicknesses of the main circuit conductive layer 7 and the control conductive layer 8 greater than the thickness of the insulating resin layer 6, so that the heat capacities of the main circuit conductive layer 7 and the control conductive layer 8 also increase, so that a larger amount of heat generated in the semiconductor element 4 or the like can be absorbed. Then, the cooling efficiency can be increased by heat conduction to the upper portion of the sealing resin 9 through the main circuit conductive layer 7 and the control conductive layer 8.

[0029] The distance (h3) from the surfaces of the main circuit conductive layer 7 and the control conductive layer 8 to the surface of the sealing resin 9 is equal to or smaller than the distance (h1) from the surface of the terminal portion 2a of the lead frame 2 inside the sealing resin 9 to the surface of the sealing resin 9. In other words, the surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are arranged on the surface of the sealing resin 9 relative to the surface of the terminal portion 2a of the lead frame 2 inside the sealing resin 9. The surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are located above the surface of the terminal portion 2a of the lead frame 2 inside the sealing resin 9. On the lower surface side of the semiconductor element 4, the surface formed by the semiconductor element 4 or the like is formed.The heat generated is mainly conducted from the lead frame 2 to the heat conducting member 1 on the rear surface of the lead frame 2 and then dissipated to the outside on the side of the lower surface of the sealing resin 9. It is conceivable that on the surface of the semiconductor element 4, the heat from the surfaces of the main circuit conductive layer 7 and the control conductive layer 8, which are connected to the surface of the semiconductor element 4 via the sealing resin 9, is dissipated to the outside via the surface of the sealing resin 9.

[0030] When the semiconductor device has the same external dimensions and the surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are located on the side (bottom side) of the lead frame 2 on which the semiconductor element 4 is arranged relative to the surface of the terminal region 2a of the lead frame 2, the main circuit conductive layer 7 and the control conductive layer 8 each have a smaller thickness. This results in a larger distance between the main circuit conductive layer 7 and the control conductive layer 8 and the surface of the sealing resin 9. Thus, Joule heat generated during current flow through the main circuit conductive layer 7 and the control conductive layer 8 and heat generated in the semiconductor element 4 are jointly conducted to the main circuit conductive layer 7 and the control conductive layer 8.However, due to the large distance from the surface of the semiconductor element 4 to the outside of the sealing resin 9, heat is not efficiently dissipated from the surface of the main circuit conductive layer 7 and the control conductive layer 8 to the outside of the sealing resin 9. Thus, the heat is then conducted to the lead frame 2 and then largely dissipated from the heat conducting member 1 on the back surface of the lead frame 2 to the outside of the sealing resin 9. This results in heat concentration on the heat conducting member 1, thereby deteriorating the heat dissipation properties of the semiconductor device.

[0031] In contrast, in the semiconductor device 100 of Embodiment 1, the surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are disposed above the surface of the terminal portion 2a of the lead frame 2 in the sealing resin 9 (on the surface of the sealing resin 9). Consequently, the thickness of the sealing resin 9 on the main circuit conductive layer 7 and the control conductive layer 8 can be reduced. This allows the distance from the surface of the main circuit conductive layer 7 and the control conductive layer 8 to the surface (outside) of the sealing resin 9 to be reduced, whereby the surfaces of the main circuit conductive layer 7 and the control conductive layer 8 mainly absorb part of the heat conducted through the lead frame 2 and dissipated to the outside by the heat conduction member 1 on the back surface of the lead frame 2, thereby enabling heat dissipation.Thus, the heat generated on the surface of the semiconductor element 4 can be efficiently dissipated outside the sealing resin 9, resulting in improved cooling efficiency. Furthermore, the heat dissipation characteristics can be improved while maintaining the size of the semiconductor device 100. This can improve the reliability of the semiconductor device 100. Especially under conditions requiring high-temperature operation, heat dissipation at a variety of locations is effective.

[0032] The sealing resin 9 ensures the insulation properties between sealed components and also functions as a housing of the semiconductor device 100. The sealing resin 9 integrally seals the lead frame 2, the semiconductor element(s) 4, the conductive spacer 5, the insulating resin layer 6, and the conductive layers 7 and 8. In the sealing resin 9, the front surface side of the lead frame 2 on which the semiconductor element 4 is arranged is the surface side, and the rear surface of the lead frame 2 on which the semiconductor element 4 is not arranged is the bottom surface side. As a method for molding the sealing resin 9, for example, transfer molding, injection molding, compression molding, or any other molding method can be used. The material for the sealing resin 9 can be, for example, an epoxy resin containing a filler, a phenolic resin, or any other resin.

[0033] Next, a method for manufacturing the semiconductor device 100 of Embodiment 1 configured as described above will be described.

[0034] The Fig. 3 to 9 are schematic plan views showing the steps for manufacturing the semiconductor device in Embodiment 1 of the present invention. Fig. The semiconductor device 100 shown in Figure 2 can be manufactured by a resin sealing step which is carried out after the steps of Fig. 3, Fig. 5 and Fig. 6 is carried out.

[0035] Fig. 3 is a schematic plan view of the semiconductor device in Embodiment 1 of the present invention before formation of an insulating resin layer. Fig. 4 is a schematic plan view of the insulating resin layer of the semiconductor device in Embodiment 1 of the present invention. Fig. 5 is a schematic plan view of the semiconductor device in Embodiment 1 of the present invention after formation of the insulating resin layer. Fig. 6 is a schematic plan view of the semiconductor device in Embodiment 1 of the present invention after formation of a conductive layer. Fig. 7 is a schematic plan view of the conductive layer of the semiconductor device in Embodiment 1 of the present invention.

[0036] First, the semiconductor element 4 and the conductive spacer 5 are bonded at predetermined positions on the front surface of the lead frame 2 with solder 3 therebetween, as shown in Fig. 3 (step for arranging the parts).

[0037] Subsequently, the insulating resin layer 6 is formed on the semiconductor element 4 and the conductive spacer 5 is bonded to the front surface of the lead frame 2 as shown in Fig. 5 (formation of the insulating resin layer). Openings 10 are formed in advance in the insulating resin layer 6 at the locations above the semiconductor element 4 and the conductive spacer 5. The openings 10 are provided at multiple locations in the insulating resin layer 6 and each have a shape that can be connected to the main circuit conductive layer 7 and the control conductive layer 8 in a subsequent step according to the electrode shape of the semiconductor element 4 or the shape of the conductive spacer 5.

[0038] Then, the main circuit conductive layer 7 and the control conductive layer 8 are formed on the surface of the insulating resin layer 6 as shown in Fig. 6 (conductive layer forming step). At this time, the semiconductor element 4 and the conductive spacer 5 are electrically connected to the main circuit conductive layer 7 and the conductive layer 8, respectively, through the openings 10 formed in the insulating resin layer 6. The main circuit conductive layer 7 and the control conductive layer 8 have the Fig. 2, which is obtained by stacking, for example, metallic components such as copper by soldering and connecting them to the semiconductor element 4 and the conductive spacer 5.

[0039] Although Fig. 7 shows an exemplary schematic plan view of the main circuit conductive layer 7 and the control conductive layer 8, it is sufficient that the main circuit conductive layer 7 and the control conductive layer 8 have the shape of a conductive layer adapted to an interconnection circuit formed in the front surface of the lead frame 2.

[0040] Subsequently, the lead frame 2, which has undergone the above steps, is sealed with sealing resin 9 (resin sealing step). In the resin sealing step, the heat conducting member 1 and the lead frame 2 manufactured through the above steps are sealed as shown in Fig. 1 is placed in a die. After being placed in the die, sealing resin 9 is molded (filled) by transfer molding, injection compression molding, injection molding, or any other method. At this time, sealing resin 9 fills the space between lead frame 2 and insulating resin layer 6 up to the opening 11 provided in insulating resin layer 6. In the resin sealing step, insulating resin layer 6 does not soften with the heat in the resin sealing process and maintains its shape during the formation of insulating resin layer 6. That is, insulating resin layer 6 is formed from a material that has higher heat resistance than sealing resin 9.

[0041] Fig. 8 is a schematic plan view of an opening and the vicinity of the semiconductor device in Embodiment 1 of the present invention. Fig. 9 is a schematic plan view of another opening and the vicinity of the semiconductor device in Embodiment 1 of the present invention.

[0042] When a portion in contact with the conductive spacer 5 or the like is located around the opening 11, which is the second opening of the insulating resin layer 6, the sealing resin 9 flows as shown in Fig. 8 - in contrast to the absence of such an area, as in Fig. 9—not toward such a region, but in the direction free from such a region, and accordingly, the flow direction 12 of the sealing resin 9 can be appropriately controlled depending on the location where the opening 11 is formed. After the sealing resin 9 is molded, the opening 11 is filled with sealing resin 9.

[0043] The semiconductor device 100 configured as described above, in which the surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are located above the surface of the terminal region 2a of the lead frame 2, can also efficiently conduct the heat generated in the semiconductor element 4 from the surface of the semiconductor element 4 to the outside of the sealing resin 9, resulting in improved cooling efficiency. This can improve the reliability of the semiconductor device 100. Embodiment 2

[0044] Embodiment 2 differs from Embodiment 1 in that the main circuit conductive layer 7 used in Embodiment 1 has a thickness greater than the thickness of the control conductive layer 8. The main circuit conductive layer 7, which is connected to the semiconductor element 4, is thicker than the above-described control conductive layer 8, so that the heat of the semiconductor element 4, which generates a large amount of heat, can be efficiently dissipated. Embodiment 2 is otherwise similar to Embodiment 1, so a detailed description is omitted.

[0045] In this case, too, the surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are above the surface of the terminal portion 2a of the lead frame 2, and accordingly, the heat generated in the semiconductor element 4 can also be efficiently conducted from the surface of the semiconductor element 4 to the outside of the sealing resin 9, resulting in improved cooling efficiency. This can improve the reliability of the semiconductor device.

[0046] Fig. 10 is a schematic cross-sectional view of a semiconductor device in Embodiment 2 of the present invention. As shown in Fig. 10, a semiconductor device 200 includes the heat conducting member 1, the lead frame 2, which is a circuit element, solder 3, which is a connecting element, the semiconductor element 4, the conductive spacer 5, which is a connecting element, the insulating resin layer 6, which is a resin layer, the main circuit conductive layer 7, which is a first conductive layer, the control conductive layer 8, which is a second conductive layer, the sealing resin 9, which is a sealing member, and openings 10, which are first openings. The main circuit conductive layer 7 has a thickness greater than the thickness of the control conductive layer 8. The lead frame 2 has a terminal portion 2a, which is a terminal portion, and a step portion (slant portion) 2b.

[0047] The main circuit conductive layer 7 can, as in Fig. 10, can be thickened, for example, by stacking the main circuit conductive layer 7 by plating or by bonding a thick copper metal plate by pressing. This allows the main circuit conductive layer 7 to be made thicker than the control conductive layer 8.

[0048] The semiconductor device 200 configured as described above, in which the surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are located above the surface of the terminal portion 2a of the lead frame 2, can also conduct the heat generated in the semiconductor element 4 from the surface of the semiconductor element 4 to the outside of the sealing resin 9, resulting in improved cooling efficiency. This can improve the reliability of the semiconductor device 200.

[0049] As described above, the main circuit conductive layer 7 connected to the semiconductor element 4 is thicker than the control conductive layer 8, so that the heat of the semiconductor element 4, which generates a large amount of heat, can be efficiently dissipated. Embodiment 3

[0050] Embodiment 3 differs from Embodiment 2 in that the thickness of the insulating resin layer 6 used in Embodiment 2 is greater on the outer peripheral region of the semiconductor element 4 than outside the outer peripheral region of the semiconductor element 4. Since the insulating resin layer 6 has a greater thickness in the outer peripheral region of the semiconductor element 4, the insulating properties of the semiconductor device can be further improved. Embodiment 3 is similar to Embodiment 2 in other respects, so a detailed description will be omitted.

[0051] In this case, too, the surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are above the surface of the terminal portion 2a of the lead frame 2, and accordingly, the heat generated in the semiconductor element 4 can also be efficiently conducted from the surface of the semiconductor element 4 to the outside of the sealing resin 9, resulting in improved cooling efficiency. This can improve the reliability of the semiconductor device.

[0052] Fig. 11 is a schematic cross-sectional view of a semiconductor device in Embodiment 3 of the present invention. Fig. 12 is a schematic plan view of the semiconductor device in Embodiment 3 of the present invention. As shown in Fig. 11, a semiconductor device 300 includes the heat conducting member 1, the lead frame 2, which is a circuit element, solder 3, which is a connecting member, semiconductor elements 4, the conductive spacer 5, which is a connecting member, the insulating resin layer 6, which is a resin layer, the main circuit conductive layer 7, which is a first conductive layer, the control conductive layer 8, which is a second conductive layer, sealing resin 9, which is a sealing member, openings 10, which are first openings, and a protrusion 13 of the insulating resin layer 6. The main circuit conductive layer 7 has a thickness greater than the thickness of the control conductive layer 8. The protrusion 13 of the insulating resin layer 6 is formed in the outer peripheral region of the semiconductor element 4. The protrusion 13 of the insulating resin layer 6 has a thickness greater than the thickness of the insulating resin layer 6 outside the outer peripheral region of the semiconductor element 4.The ladder frame 2 includes a connection area 2a, which is a connection and step area (slope area) 2b.

[0053] As in Fig. 11 and Fig. As shown in Figure 12, the protrusion 13 is provided in the insulating resin layer 6 on the outer peripheral portion of the semiconductor element 4 to improve the insulating properties of the semiconductor device. In the present embodiment, the protrusion 13 is formed in advance in the portion of the insulating resin layer 6 that contacts the outer peripheral portion of the semiconductor element 4, so that the outer peripheral portion that contacts the semiconductor element 4 mounted on the lead frame 2 is formed as shown in Figure 12. Fig. 11, is thick. And openings 10 are formed by punching or the like in the electrode area, which forms a circuit layer.

[0054] In the semiconductor device 300 configured as described above, the surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are located above the surface of the terminal portion 2a of the lead frame 2, so that the heat generated in the semiconductor element 4 can also be efficiently conducted from the surface of the semiconductor element 4 to the outside of the sealing resin 9, resulting in improved cooling efficiency. This can improve the reliability of the semiconductor device 300.

[0055] In addition, the main circuit conductive layer 7 connected to the semiconductor element 4 is thicker than the above-described control conductive layer 8, so that the heat of the semiconductor element 4, which generates a large amount of heat, can be efficiently dissipated.

[0056] Furthermore, a protrusion 13 is provided in the insulating resin layer 6, which is in contact with the outer peripheral region of the semiconductor element 4 and leads to improved insulating properties of the semiconductor device 300. Embodiment 4

[0057] Embodiment 4 differs from Embodiment 3 in that the heat conduction member 1 used in Embodiment 3 is omitted, and the sealing resin 9 containing a highly thermally conductive filler fills the back surface of the lead frame 2. Thus, the back surface of the lead frame 2 is filled with the sealing resin containing a highly thermally conductive filler, resulting in improved insulation and heat dissipation properties of the semiconductor device. Embodiment 4 is otherwise similar to Embodiment 3, so a detailed description is omitted.

[0058] In this case, too, the surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are above the surface of the terminal portion 2a of the lead frame 2, and accordingly, the heat generated in the semiconductor element 4 can also be conducted from the surface of the semiconductor element 4 to the outside of the sealing resin 9, resulting in improved cooling efficiency. This can improve the reliability of the semiconductor device.

[0059] Fig. 13 is a schematic cross-sectional view of a semiconductor device in Embodiment 4 of the present invention. As shown in Fig. 13, a semiconductor device 400 includes the lead frame 2 as a circuit element, solder 3 as a connecting element, the semiconductor element 4, the conductive spacer 5 as a connecting element, the insulating resin layer 6 as a resin layer, the main circuit conductive layer 7 as a first conductive layer, the control conductive layer 8 as a second conductive layer, the sealing resin 9 as a sealing element, openings 10 as first openings, and the protrusion 13 of the insulating resin layer 6. The main circuit conductive layer 7 has a thickness greater than the thickness of the control conductive layer 8. The protrusion 13 is formed in the outer peripheral portion of the insulating resin layer 6, which is in contact with the semiconductor element 4. Further, the lead frame 2 includes the terminal portion 2a, which is a terminal and step portion (slant portion) 2b.

[0060] As shown in Fig. 13, sealing resin 9 is also provided on the back surface of the lead frame 2, resulting in a structure in which the lead frame 2 is covered with sealing resin 9. A highly thermally conductive filler, e.g., a metal oxide such as silicon dioxide or aluminum oxide, or a nitride such as aluminum nitride or boron nitride, is used for the sealing resin 9. The sealing resin 9 contains a filler containing at least one of the metal oxides and / or the nitride.

[0061] In the present embodiment, the sealing resin 9 covers, as shown in Fig. 13, the sealing resin 9 covers the entire semiconductor device and accordingly serves as a resin package and also serves to ensure the insulation properties of the lead frame 2 and the main circuit conductive layer 7 and to dissipate heat from the semiconductor element 4. Therefore, the distance from the lower surface of the sealing resin 9 to the rear surface of the lead frame 2, that is, the thickness 14 of the sealing resin 9 on the rear surface of the lead frame 2, and the distance from the surface of the main circuit conductive layer 7 to the surface of the sealing resin 9, that is, the thickness 14 of the sealing resin 9 above the main circuit conductive layer 7, are preferably 0.1 mm or more and 1.0 mm or less in terms of heat dissipation and insulation properties of the semiconductor device. If the thickness 14 is less than 0.1 mm, the insulation properties cannot be ensured. If the thickness 14 is greater than 1.0 mm, the heat dissipation properties may deteriorate.Therefore, it is desirable that the range of the thickness 14 is about 0.1 mm or more to 1.0 mm or less.

[0062] In the semiconductor device 400 configured as described above, the surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are located above the surface of the terminal portion 2a of the lead frame 2, so that the heat generated in the semiconductor element 4 can also be efficiently dissipated from the surface of the semiconductor element 4 to the outside of the sealing resin 9, resulting in improved cooling efficiency. This can improve the reliability of the semiconductor device 400.

[0063] As described above, the main circuit conductive layer 7 connected to the semiconductor element 4 is thicker than the control conductive layer 8, so that the heat of the semiconductor element 4, which generates a large amount of heat, can be efficiently dissipated.

[0064] Furthermore, a protrusion 13 is provided in the insulating resin layer 6, which is in contact with the outer peripheral region of the semiconductor element 4 and leads to improved insulation reliability of the semiconductor device 400.

[0065] The back surface of the lead frame 2 is also filled with sealing resin 9 containing a highly thermally conductive filler, resulting in improved insulation properties and heat dissipation properties of the semiconductor device 400. Embodiment 5

[0066] Embodiment 5 differs from Embodiment 3 in that the circuit element 2 used in Embodiment 3 is replaced with an insulating circuit board 15, and the back surface of the insulating circuit board 15 is also filled with sealing resin 9. In this way, the insulating circuit board 15 is used to also fill the back surface of the insulating circuit board 15 with the sealing resin, resulting in improved insulation properties and heat dissipation properties of the semiconductor device. Embodiment 5 is otherwise similar to Embodiment 3, so a detailed description is omitted.

[0067] In this case, too, the surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are located above the surface of the terminal 17 of the insulating circuit board 15, and accordingly, the heat generated in the semiconductor element 4 can also be efficiently conducted from the surface of the semiconductor element 4 to the outside of the sealing resin 9, resulting in improved cooling efficiency. This can improve the reliability of the semiconductor device.

[0068] Fig. 14 is a schematic cross-sectional view of a semiconductor device in Embodiment 5 of the present invention. As shown in Fig. 14, a semiconductor device 500 includes the insulating circuit board 15 as a circuit element, solder 3 as a connecting element, the semiconductor element 4, the conductive spacer 5 as a connecting element, the insulating resin layer 6 as a resin layer, the main circuit conductive layer 7 as a first conductive layer, the control conductive layer 8 as a second conductive layer, the sealing resin 9 as a sealing element, openings 10 as first openings, the projection 13 of the insulating resin layer 6, and the terminal 17 as a terminal region.

[0069] Main circuit conductive layer 7 has a thickness greater than the thickness of control conductive layer 8. The protrusion 13 is formed around the portion of insulating resin layer 6 in contact with semiconductor element 4.

[0070] The insulating circuit board 15 includes metal layers 15c and 15b on the opposite surfaces (front surface, back surface) of an insulating layer 15a. A substrate formed from a filler and a resin, such as a plate-shaped printed circuit board, can be used as the insulating circuit board 15. This may be, for example, a substrate in which rolled material of a metal such as copper is bonded to the opposite sides of a ceramic made of alumina, aluminum nitride, silicon nitride, or the like.

[0071] In the present embodiment, as shown in Fig. 14, the terminal 17 is connected to the metal layer 15c on the front surface of the insulating circuit board 15 with solder 3. Thus, when filled with sealing resin 9, the terminal 17 is held between the molding tools with the insulating circuit board 15 insulated from the lower surface inside the tool (front surface of a lower tool). Sealing resin 9 passes around the back surface of the insulating circuit board 15. The portion of the terminal 17 protruding into the dies is sealed in the sealing resin 9 after sealing with sealing resin 9. The terminal 17 held between the dies protrudes from the inside to the outside of the sealing resin 9 after sealing with sealing resin 9. The surface of the semiconductor element 4 is located on the front surface side of the insulating circuit board 15 relative to the surface of the terminal 17 of the insulating circuit board 15. That is,the distance from the surface of the terminal 17 inside the sealing resin 9 to the surface of the sealing resin 9 is smaller than the distance from the surface of the semiconductor element 4 to the surface of the sealing resin 9.

[0072] As in Fig. As shown in FIG. 14, the sealing resin 9 covers the entire semiconductor device 500 and accordingly serves as a resin package, and also serves to ensure the insulating properties of the insulating circuit board 15 and the main circuit conductive layer 7 and to dissipate the heat of the semiconductor device 4. Thus, the distance from the lower surface of the sealing resin 9 to the back surface of the metal layer 15b of the insulating circuit board 15, i.e., the thickness 14 of the sealing resin 9 on the back surface of the metal layer 15b, and the distance from the surface of the main circuit conductive layer 7 to the surface of the sealing resin 9, i.e., the thickness 14 of the sealing resin 9 above the main circuit conductive layer 7, is preferably 0.1 mm or more and 1.0 mm or less in terms of the heat dissipation properties and the insulating properties of the semiconductor device. If the thickness 14 is less than 0.1 mm, the insulating properties cannot be ensured.If the thickness 14 is greater than 1.0 mm, the heat dissipation properties may deteriorate. Therefore, it is desirable that the thickness 14 be in the range of 0.1 mm or more to 1.0 mm or less.

[0073] Fig. 15 is a schematic cross-sectional view of another semiconductor device in Embodiment 5 of the present invention. As shown in Fig. 15, a semiconductor device 501 includes the insulating circuit board 15 as a circuit element, solder 3 as a connecting element, the semiconductor element 4, the conductive spacer 5 as a connecting element, the insulating resin layer 6 as a resin layer, the main circuit conductive layer 7 as a first conductive layer, the control conductive layer 8 as a second conductive layer, the sealing resin 9 as a sealing element, openings 10 as first openings, the protrusion 13 of the insulating resin layer 6, and the terminal 17 as a terminal portion. The main circuit conductive layer 7 has a thickness greater than the thickness of the control conductive layer 8. The protrusion 13 is formed around a portion of the insulating resin layer 6 that contacts the semiconductor element 4. The semiconductor device 501 further includes a cooler 20 on each of the top and bottom surfaces, with grease 21 sandwiched between them.

[0074] In the surface and lower surface of the semiconductor device, as shown in Fig. 15, a cooler 20 is provided in each case, resulting in improved cooling performance. Depending on the required cooling performance, the cooler 20 can be provided either on the surface or on the lower surface.

[0075] Fig. 16 is a schematic cross-sectional view of another semiconductor device in Embodiment 5 of the present invention. As shown in Fig. 16, a semiconductor device 510 includes the insulating circuit board 15 as a circuit element, solder 3 as a connecting element, the semiconductor element 4, the conductive spacer 5 as a connecting element, the insulating resin layer 6 as a resin layer, the main circuit conductive layer 7 as a first conductive layer, the control conductive layer 8 as a second conductive layer, sealing resin 9 as a sealing element, openings 10 as first openings, the protrusion 13 of the insulating resin layer 6, and the terminal 17 as a terminal portion. The main circuit conductive layer 7 has a thickness greater than the thickness of the control conductive layer 8. The protrusion 13 is formed around the portion of the insulating resin layer 6 that contacts the semiconductor element 4. Furthermore, the semiconductor device 510 has a structure in which the back surface of the metal layer 15c on the back surface of the insulating circuit board 15 is exposed from the sealing resin 9.

[0076] Here, the terminal 17 of the insulating circuit board 15 is arranged in the sealing resin 9 above the region on the front surface of the insulating circuit board 15 on which the semiconductor element 4 is mounted. The semiconductor element 4 is arranged on the front surface of the insulating circuit board 15. The surface of the semiconductor element 4 is arranged on the front surface side of the insulating circuit board 15 relative to the surface of the terminal 17 of the insulating circuit board 15. That is, the distance (h1) from the surface of the terminal 17 of the insulating circuit board 15 inside the sealing resin 9 to the surface of the sealing resin 9 is smaller than the distance (h2) from the surface of the semiconductor element 4 to the surface of the sealing resin 9.Such an arrangement can improve the breakdown voltage between the metal layer 15c on the back surface of the insulating layer of the insulating circuit board 15 and the terminal 17 of the insulating circuit board 15.

[0077] The surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are arranged on the surface of the sealing resin 9 relative to the surface of the terminal 17 of the insulating circuit board 15 within the sealing resin 9. Likewise, the surface of the terminal 17 of the insulating circuit board 15 is arranged in the sealing resin 9 above the surface of the semiconductor element 4. In this way, the heat generated on the surface of the semiconductor element 4 is efficiently conducted to the outside of the sealing resin 9 for dissipation, resulting in improved cooling efficiency. This can improve the reliability of the semiconductor device 500, 501, 510. In particular, heat dissipation at a plurality of locations is effective in such a use state that requires operation at high temperatures.

[0078] In the semiconductor devices 500, 501, 510 configured as described above, the surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are located above the surface of the terminal 17 of the insulating circuit board 15. Accordingly, the heat generated in the semiconductor element 4 can also be efficiently dissipated from the surface of the semiconductor element 4 to the outside of the sealing resin 9, resulting in improved cooling efficiency. This can improve the reliability of the semiconductor device 500, 501, 510.

[0079] As described above, the main circuit conductive layer 7 connected to the semiconductor element 4 is thicker than the control conductive layer 8, so that the heat of the semiconductor element 4, which generates a large amount of heat, can be efficiently dissipated.

[0080] The protrusion 13 is provided in the insulating resin layer 6, which is in contact with the outer peripheral portion of the semiconductor element 4, resulting in improved insulation reliability of the semiconductor devices 500, 501, 510. Embodiment 6

[0081] Embodiment 6 differs from Embodiment 5 in that the insulating circuit board 15 used in Embodiment 5 has a through-hole 16 provided to improve heat dissipation properties. Thus, the through-hole 16 is provided in the insulating circuit board 15, and a copper pillar or the like is inserted into the through-hole 16 to connect the metal layer 15b and the metal layer 15c, resulting in improved thermal conductivity of the metal layer 15c of the insulating circuit board 15. Embodiment 6 is similar to Embodiment 5 in other respects, so a detailed description will be omitted.

[0082] In this case, too, the surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are located above the surface of the terminal 17 of the insulating circuit board 15, and accordingly, the heat generated in the semiconductor element 4 can also be efficiently conducted from the surface of the semiconductor element 4 to the outside of the sealing resin 9, resulting in improved cooling efficiency. This can improve the reliability of the semiconductor device.

[0083] Fig. 17 is a schematic cross-sectional view of a semiconductor device in Embodiment 6 of the present invention. As shown in Fig. 17, a semiconductor device 600 includes the insulating circuit board 15 as a circuit element, solder 3 as a connecting element, the semiconductor element 4, the conductive spacer 5 as a connecting element, the insulating resin layer 6 as a resin layer, the main circuit conductive layer 7 as a first conductive layer, the control conductive layer 8 as a second conductive layer, sealing resin 9 as a sealing element, openings 10 as first openings, the protrusion 13 of the insulating resin layer 6, the through-hole 16, and the terminal 17 as a terminal portion. The main circuit conductive layer 7 has a thickness greater than the thickness of the control conductive layer 8. The protrusion 13 is formed around the portion of the insulating resin layer 6 that contacts the semiconductor element 4.

[0084] The insulating circuit board 15 has the metal layers 15c and 15b on the opposite surfaces (front surface and back surface) of the insulating layer 15a. The insulating circuit board 15 has a through-hole 16 extending through the insulating circuit board 15. A copper pillar or the like is inserted into the through-hole 16, forming a structure in which the metal layer 15c and the metal layer 15b are connected to each other.

[0085] In the present embodiment, as shown in Fig. 17, the terminal 17 is connected to the metal layer 15c on the front surface of the insulating circuit board 15 with solder 3. Thus, when molding the sealing resin 9, the terminal 17 is held between the molds, with the insulating circuit board 15 insulated from the lower surface inside the mold (front surface of the lower mold). The portion of the terminal 17 protruding into the dies is sealed with sealing resin 9 and thereby sealed within the sealing resin 9. The portion of the terminal 17 held between the dies protrudes from the inside to the outside of the sealing resin 9 after being sealed with sealing resin 9. The distance from the surface of the terminal 17 to the surface of the sealing resin 9 is set smaller than the distance from the surface of the semiconductor element 4 to the surface of the sealing resin 9.

[0086] As in Fig. As shown in FIG. 17, the sealing resin 9 covers the entire semiconductor device 600 and accordingly serves as a resin package, and also serves to ensure the insulating properties of the insulating circuit board 15 and the main circuit conductive layer 7 and to dissipate the heat of the semiconductor device 4. Thus, the distance from the lower surface of the sealing resin 9 to the back surface of the metal layer 15b of the insulating circuit board 15, i.e., thickness 14 of the sealing resin 9 on the back surface of the metal layer 15b, and the distance from the surface of the main circuit conductive layer 7 to the surface of the sealing resin 9, i.e., the thickness 14 of the sealing resin 9 above the main circuit conductive layer 7, is preferably 0.1 mm or more and 1.0 mm or less in terms of the heat dissipation properties and the insulating properties of the semiconductor device. If the thickness 14 is less than 0.1 mm, the insulating properties cannot be ensured.If the thickness 14 is greater than 1.0 mm, the heat dissipation properties may deteriorate. Therefore, it is desirable that the thickness 14 be in the range of 0.1 mm or more to 1.0 mm or less.

[0087] In the semiconductor device 600 configured as described above, the surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are located above the surface of the terminal 17 of the insulating circuit board 15, so that the heat generated in the semiconductor element 4 can also be efficiently conducted from the surface of the semiconductor element 4 to the outside of the sealing resin 9, resulting in improved cooling efficiency. This can improve the reliability of the semiconductor device 600.

[0088] As described above, the main circuit conductive layer 7 connected to the semiconductor element 4 is thicker than the control conductive layer 8, so that the heat of the semiconductor element 4, which generates a large amount of heat, can be efficiently dissipated.

[0089] The protrusion 13 is provided in the insulating resin layer 6, which is in contact with the outer peripheral portion of the semiconductor element 4, resulting in improved insulation reliability of the semiconductor device 600. Embodiment 7

[0090] Embodiment 7 differs from Embodiment 1 in that the conductive spacer 5 used in Embodiment 1 for connecting the lead frame 2 to the main circuit conductive layer 7 and the control conductive layer 8 is replaced with a protrusion 2c formed integrally with the lead frame 2. The protrusion 2c is provided on the lead frame 2 to connect the lead frame 2 to the main circuit conductive layer 7 and the control conductive layer 8 using the protrusion 2c as described above, thus preventing poor connection of the lead frame 2 to the main circuit conductive layer 7 and the control conductive layer 8. Embodiment 7 is otherwise similar to Embodiment 1, so a detailed description is omitted.

[0091] Fig. 18 is a schematic cross-sectional view of a semiconductor device in Embodiment 7 of the present invention.

[0092] Referring to the figure, a semiconductor device 700 includes the heat conducting member 1, the lead frame 2 which is a circuit element, solder 3 which is a connecting member, the semiconductor element 4, the conductive spacer 5 which is a connecting member, the insulating resin layer 6 which is a resin layer, the main circuit conductive layer 7 which is a conductive layer (first conductive layer), the control conductive layer 8 which is a conductive layer (second conductive layer), and sealing resin 9 which is a sealing member.

[0093] The lead frame 2 includes the terminal portion 2a, which is a terminal and step portion (slope portion) 2b, and the protrusion 2c. The protrusion 2c serves to electrically / thermally connect the lead frame 2 to the main circuit conductive layer 7 and the control conductive layer 8. In cross-sectional and plan views, the area of ​​the protrusion 2c is larger than the areas of the opening 10 in portions of the insulating resin layer 6 where the lead frame 2 is connected to the main circuit conductive layer 7 and the control conductive layer 8. This prevents poor connection of the lead frame 2 to the main circuit conductive layer 7 and the control conductive layer 8.

[0094] Furthermore, the protrusion 2c may be formed by forging or the like in a step before or after the production by punching of the lead frame 2. Alternatively, the protrusion 2c may be formed by manufacturing the lead frame 2 with a portion thereof having a large thickness, and then reducing the thickness of the portion other than the protrusion 2 by cutting / milling or the like. When manufacturing the protrusion 2c by forging or cutting / milling, a lead frame 2 with a small thickness may not withstand processing by forging or cutting / milling, which may result in breakage or cracking. Therefore, the thickness of the lead frame 2 is preferably 0.3 mm or more.

[0095] In the semiconductor device 700 configured as described above, the surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are located above the surface of the terminal portion 2a of the lead frame 2, so that the heat generated in the semiconductor element 4 can also be efficiently conducted from the surface of the semiconductor element 4 to the outside of the sealing resin 9, resulting in improved cooling efficiency. This can improve the reliability of the semiconductor device 700.

[0096] The protrusion 2c is provided integrally with the lead frame 2 and makes the area of ​​the protrusion 2c larger than the areas of the opening 10 in the areas of the insulating resin layer 6 where the lead frame 2 is connected to the main circuit conductive layer 7 and the control conductive layer 8, thus preventing poor connection of the lead frame 2 to the main circuit conductive layer 7 and the control conductive layer 8. Embodiment 8

[0097] In Embodiment 8, the semiconductor device according to any one of Embodiments 1 to 7 described above is used for a power converter. Although the present invention is not limited to a specific power converter, a case where the present invention is applied to a three-phase inverter as Embodiment 8 will be described below.

[0098] Fig. 19 is a block diagram showing a configuration of a power converter system in which the power converter in Embodiment 8 of the present invention is used.

[0099] The Fig. The power conversion system shown in Figure 19 includes a power source 1000, a power converter 2000, and a load 3000. The power source 1000 is a DC power source and supplies DC power to the power converter 2000. The power source 1000 can be implemented in various ways, e.g., as a DC power system, solar battery, or storage battery, or as a rectifier circuit, AC / DC converter, or the like connected to an AC power system. Alternatively, the power source 1000 can be implemented as a DC / DC converter that converts the DC power from the DC system into a predetermined power.

[0100] The Power Converter 2000 is a three-phase inverter that is connected between Power Source 1000 and Load 3000 and converts the DC power supplied by Power Source 1000 into AC power and supplies the AC power to Load 3000.

[0101] As in Fig.19, the power converter 2000 includes a main conversion circuit 2001 that converts the DC power supplied from the power source 1000 into AC power and outputs the AC power, and a control circuit 2003 that outputs a control signal for controlling the main conversion circuit 2001 to the main conversion circuit 2001.

[0102] The Load 3000 is a three-phase electric motor driven by the AC power supply of the Power Converter 2000. The Load 3000 is not limited to a specific application, but is an electric motor built into various electrical devices and used, for example, as an electric motor for hybrid vehicles, electric vehicles, rail vehicles, elevators, air conditioning systems, or similar.

[0103] The power converter 2000 will be described in detail below. The main conversion circuit 2001 includes a switching element and a freewheeling diode (not shown) incorporated in the semiconductor device 2002. When the switching element is switched, it converts the DC voltage supplied by the power source 1000 into AC voltage and supplies the AC voltage to the load 3000. Although the specific circuit configuration of the main conversion circuit 2001 can be of various types, the main conversion circuit 2001 according to the present embodiment is a two-stage, three-phase full-bridge circuit and can be formed from six switching elements and six freewheeling diodes, each connected in antiparallel to a corresponding one of the six switching elements.The main conversion circuit 2001 includes the semiconductor device 2002 according to any one of Embodiments 1 to 5 described above, which includes internal switching elements and internal freewheeling diodes. Of the six switching elements, two switching elements are connected in series to form upper and lower arms, and each of the upper arms and a corresponding one of the lower arms form a phase (U-phase, V-phase, W-phase) of the full-bridge circuit. The output terminals of the respective upper and lower arms, i.e., three output terminals of the main conversion circuit 2001, are connected to the load 3000.

[0104] The main conversion circuit 2001 also includes a drive circuit (not shown) that drives each switching element. The drive circuit may be incorporated into the semiconductor device 2002, or in another configuration, the drive circuit may be provided separately from the semiconductor device 2002. The drive circuit generates a drive signal for driving the switching element(s) of the main conversion circuit 2001 and supplies the drive signal to each control electrode of the switching elements of the main conversion circuit 2001. Specifically, the drive circuit outputs a drive signal for turning on the switching elements and a drive signal for turning off the switching elements to the control electrode of each switching element according to the control signal from the control circuit 2003, which will be described below.When the switching element is kept in the on state, the drive signal is a voltage signal (ON signal) not less than a threshold voltage of the switching element, and when the switching element is kept in the off state, the drive signal is a voltage signal (OFF signal) not greater than the threshold voltage of the switching element.

[0105] The control circuit 2003 controls the switching elements of the main conversion circuit 2001 so that the desired electric power is supplied to the load 3000. Specifically, the control circuit 2003 calculates a time (ON time) at which each switching element of the main conversion circuit 2001 should be turned on based on the electric power to be supplied to the load 3000. For example, the control circuit 2003 may control the main conversion circuit 2001 through PWM control, in which the turn-on time of the switching element is modulated in accordance with a voltage to be output. Furthermore, the control circuit 2003 outputs a control command (control signal) to a driver circuit of the main conversion circuit 2001 to output an ON signal to the switching element to be turned on and an OFF signal to the switching element to be turned off at each timing.The drive circuit outputs the ON signal or the OFF signal as a drive signal to the control electrode of each switching element according to the control signal.

[0106] In the power converter according to Embodiment 8 configured as described above, the semiconductor device according to any one of Embodiments 1 to 7 is used as the semiconductor device 2002 of the main conversion circuit 2001, resulting in improved reliability.

[0107] Although the present embodiment has described an example in which the present invention is applied to a two-level, three-phase inverter, the present invention is not limited thereto and is applicable to various power converters. Although a two-level power converter is used in the present embodiment, a three-level or multi-level power converter may be used, or the present invention may be applied to a single-phase inverter when a single-phase load current is supplied. When a DC load or the like is supplied with electric power, the present invention can also be applied to a DC / DC converter, an AC / DC converter, or the like.

[0108] A power converter to which the present invention is applied is not limited to a case where the load is an electric motor as described above. Such a power converter can be used as a power source, for example, of an electrical discharge machine, a laser beam machine, an induction heat cooker, or a non-contact feeding system, and also as a power conditioner of a solar power generation system, an energy storage system, or the like. List of reference symbols 1 heat conducting element 1a metal foil / layer 1b Insulating layer 2 ladder frames 2a Connection area 2b Step area 2c lead 3 lots 4 semiconductor element 5 conductive spacer 6 insulating resin layer 7 Main circuit conductive layer 8 Control layer 9 Sealing resin 10, 11 Opening 12 Flow direction 13 lead 14 resin thickness 15 insulating circuit board 16 through holes 17 Connection 100, 200, 300, 400, 500, 501, 510, 600, 700, 2002 semiconductor device 1000 power source 2000 power converters 2001 Main conversion circuit 2003 control circuit 3000 load

Claims

[1] Semiconductor device comprising: A circuit element (2) having a front surface and a rear surface and having a planar region; a connection region (2a) formed above the front surface of the planar region of the circuit element (2) and parallel to the planar region; a semiconductor element (4) having a surface arranged below a surface of the terminal region (2a), the semiconductor element (4) being formed on the front surface of the planar region of the circuit element (2); a resin layer (6) disposed on the semiconductor element (4) and having a plurality of first openings (10) through which the semiconductor element (4) is exposed; a conductive layer (7, 8) disposed on the resin layer (6), having a surface lying above the surface of the terminal region (2a) and connected to the semiconductor element (4) through the plurality of first openings (10); and a sealing element (9) having a surface parallel to the planar region and integrally sealing the circuit element (2), the semiconductor element (4), the resin layer (6), the conductive layer (7,8) and a part of the terminal region (2a). [2] Semiconductor component according to claim 1, comprising a connecting element (5) on the planar region of the circuit part (2) on which the semiconductor element (4) is arranged, wherein the connecting element (5) is flush with the semiconductor element (4) and is exposed through the plurality of first openings (10) through which the semiconductor element (4) is not exposed and is in contact with the conductive layer (7, 8). [3] A semiconductor device according to claim 1 or 2, wherein the resin layer (6) has a second opening (11) which is open, including a region other than a region on the front surface of the circuit element (2) in which the semiconductor element (4) is arranged in plan view, the second opening (2) being filled with the sealing member. [4] A semiconductor device according to any one of claims 1 to 3, wherein the resin layer (6) has a greater thickness in an outer peripheral region of the semiconductor element (4) than outside the outer peripheral region of the semiconductor element (4). [5] A semiconductor device according to any one of claims 1 to 4, wherein the circuit element (2) comprises an insulating circuit board (15) having an insulating layer (15a) and a metal layer (15b, 15c) which are respectively arranged on a front surface and a back surface of the insulating layer (15a). [6] A semiconductor device according to claim 2, wherein the circuit element (2) comprises a lead frame, and wherein the connecting element (5) is formed on the surface of the lead frame. [7] Semiconductor component according to one of claims 1 to 6, wherein the conductive layer (7, 8) comprises: A first conductive layer (7) connected to a main electrode of the semiconductor element (4), and a second conductive layer (8) connected to a control electrode of the semiconductor element (4), wherein the first conductive layer (7) has a thickness which is greater than the thickness of the second conductive layer (8). [8] Semiconductor component according to claim 5 or 6, wherein a rear surface of the circuit part (2) is provided with a heat-conducting element (1), and a lower surface of the heat conducting element (1) is exposed from the sealing element. [9] A semiconductor device according to claim 7, wherein the sealing member contains a filler, wherein the filler contains a metal oxide and a nitride or wherein the filler contains a metal oxide or a nitride. [10] A semiconductor device according to claim 9, wherein a distance from the upper surface of the sealing member to a surface of the first conductive layer (7, 8) and a distance from a lower surface of the sealing member to the back surface of the circuit element (2) is 0.1 mm or more and 1 mm or less. [11] A semiconductor device according to claim 5, wherein the insulating circuit board (15) has a through-hole (16) through which the insulating layer (15a) electrically connects a metal layer (15b, 15c) on the front surface of the insulating layer (15a) to a metal layer (15b, 15c) on the back surface of the insulating layer (15a). [12] A semiconductor device according to any one of claims 1 to 11, comprising a cooler (20) on the surface and a lower surface of the sealing member, or comprising a cooler (20) on the surface or a lower surface of the sealing member. [13] Power converter comprising: A semiconductor device according to one of claims 1 to 12; a main conversion circuit (2001) for converting a supplied electric power and outputting an electric power; and a control circuit (2003) for outputting a control signal to the main conversion circuit (2001) for controlling the Main conversion circuit (2001).

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