Interconnect structure, semiconductor device and method for producing the same

Abstract

Connection structure (3) to be inserted between a semiconductor element (1) and a substrate (2), the connection structure (3) comprising: - a Sn phase (4); - Cu alloy particles (5) containing P in an amount of 1 mass% or more and less than 7 mass%; and - Ag particles (6), - wherein the Cu alloy particles (5) are each coated with a Cu6Sn5 cover layer (7), - wherein the Ag particles (6) are each coated with an Ag3Sn cover layer (8), - wherein the Cu alloy particles (5) and the Ag particles (6) are separated by a Cu 10 Sn3 phase (9) are at least partially bonded to each other, - wherein the total sum of addition amounts of the Cu alloy particles (5) and the Ag particles (6) with respect to the compound structure (3) is equal to 25 mass% or greater and less than 65 mass% and - wherein the mass ratio of the addition amount of the Ag particles (6) to the addition amount of the Cu alloy particles (5) is equal to 0.2 or greater and less than 1.2.

Description

TECHNICAL FIELD

[0001] The present invention relates to an interconnection structure, a semiconductor device and a method for producing the same. STATE OF THE ART

[0002] In recent years, there has been an increasing demand for the reliability of semiconductor devices. In particular, there is a large difference in the thermal expansion coefficient between a semiconductor element and a circuit board, and consequently, it is necessary to improve the reliability of a connection portion interposed between them. In many cases, semiconductor elements have so far used elements composed of silicon (Si), gallium arsenide (GaAs), and the like as base materials, and their operating temperature is between 100°C and 125°C.

[0003] An interconnect material used to connect these semiconductor elements to the printed circuit board is required to have a high melting point that can accommodate multi-step bonding, crack resistance to repeated thermal stress associated with start / stop, and contamination resistance of a semiconductor device. In response to these requirements, 95Pb-5Sn (mass %) is used as an interconnect material in a semiconductor device employing a semiconductor element composed of Si as the base material.

[0004] Furthermore, in a semiconductor device employing a semiconductor element composed of gallium arsenide as the base material, 80Au-20Sn (mass%) is used as the interconnect material. However, 95Pb-5Sn, which contains a large amount of harmful lead (Pb), poses a problem from the perspective of reducing environmental pollution. Furthermore, 80Au-20Sn, which contains a large amount of precious metal, has problems related to rising precious metal prices and supplies. Therefore, there is a high demand for an interconnect material that serves as an alternative to these interconnect materials.

[0005] From the perspective of energy conservation, however, a semiconductor device using a semiconductor element made of silicon carbide (SiC) or gallium nitride (GaN) as the base material is being actively developed as a next-generation semiconductor device. From the perspective of reducing power loss, the operating temperature of this semiconductor device is specified at 175°C or higher, and it is planned to increase it to 300°C in the future. Therefore, it is necessary that the bonding area inserted between the semiconductor element and the circuit board does not crack even when the semiconductor device operates at a higher temperature.

[0006] Therefore, it is necessary to improve the crack resistance of the interconnection portion when the semiconductor device is operated at a high temperature while solving the problem of the conventional interconnection material containing lead or a precious metal.

[0007] In view of the above problem, Patent Document 1 discloses, as a method for joining a semiconductor element and a substrate in a semiconductor unit, a joining method comprising the steps of: applying a joining material containing Cu particles and Sn particles to a joining surface of the semiconductor element or the substrate; making contact between the joining surface of the semiconductor element and the joining surface of the substrate with the joining material interposed therebetween; and heating the resultant at a temperature higher than the melting point of Sn to cause Cu and Sn of the joining material to undergo liquid-phase transition sintering, thereby adjusting the joining material to a composition containing Cu6Sn5 and Cu3Sn;and heating the resultant to convert Cu6Sn5 of the bonding material into Cu3Sn, thereby increasing the proportion of Cu3Sn.;

[0008] Patent Document 2 discloses a semiconductor device comprising: an IC chip; a pad to which the IC chip is bonded through a bonding portion formed of solder; and leads each electrically bonded to the IC chip. The solder includes balls of at least one type selected from the group consisting of Sn balls, In balls, and metal balls having a melting point higher than that of the Sn balls and In balls.

[0009] Patent Document 3 discloses a method for producing solder powder, which includes the following steps: obtaining a first liquid dispersion of a copper powder having an average particle size of 1 to 24 μm and a size distribution range value of less than 1.0; adding a tin metal salt to the first liquid dispersion to prepare a liquid mixture; adjusting the pH of the liquid mixture to 0.1 to 2.0; adding a reducing agent to the pH-adjusted liquid mixture and mixing them to obtain a second liquid dispersion in which tin formed by reduction precipitation of tin ions covers the copper powder;Subjecting the second liquid dispersion to solid-liquid separation and drying the solid content to obtain a solder powder consisting of a central core and a cladding layer covering the central core, in which the central core is made of copper and an intermetallic compound between copper and tin, and the cladding layer is made of tin. In the solder powder, the average particle size is 1 to 30 μm, the variation coefficient of the average particle size is 0.15 or less, and the copper content ratio per 100 mass percent of the total amount of the solder powder is more than 40 mass percent and 70 mass percent or less. STATE OF THE ARTPatent document Patent document 1: JP 2014- 199 852 A Patent document 2: US 2002 / 0 100 986 A1 Patent document 3: JP 2016- 172 912 A BRIEF DESCRIPTION OF THE INVENTIONTechnical problem

[0010] However, Patent Document 1 does not consider the influence of the composition ratio of Cu particles and Sn particles on the crack resistance of a joint portion. The fluidity of Sn is reduced when a large amount of Cu particles is added, and consequently, it is thought that voids are generated in the areas sealed with the particles. When thermal shock is applied to the joint portion containing the voids, cracks are likely to occur.

[0011] Furthermore, a Cu-Sn alloy represented by Cu6Sn5 exhibits a two-phase separation state, although, from a metal phase diagram, there is a solid solution region containing approximately 5 mass% Cu. Therefore, if Sn with a low melting point is not present at the Cu6Sn5 interface, voids will form and may act as starting points for cracks. Therefore, the crack resistance of the joint region formed by the joining method according to Patent Document 1 cannot be said to be sufficient.

[0012] The present invention was conceived to solve the above-mentioned problems, and the object of the present invention is to provide an interconnection structure that has high interconnection reliability, such as resistance to cracking, even during operation of the semiconductor device at a high temperature. Furthermore, another object of the present invention is to provide a semiconductor device having such an interconnection structure and a method for manufacturing the same. Solution to the problem

[0013] According to one embodiment of the present invention, there is provided an interconnection structure to be inserted between a semiconductor element and a substrate, the interconnection structure comprising: a Sn phase; Cu alloy particles containing P in an amount of 1 mass% or more and less than 7 mass%; and Ag particles, wherein the Cu alloy particles are each coated with a Cu6Sn5 top layer, wherein the Ag particles are each coated with an Ag3Sn top layer, wherein the Cu alloy particles and the Ag particles are separated by a Cu 10 Sn3 phase are at least partially bonded to each other, wherein a total sum of addition amounts of the Cu alloy particles and the Ag particles with respect to the connection structure is equal to 25 mass% or greater and less than 65 mass%, and wherein a mass ratio of the addition amount of the Ag particles to the addition amount of the Cu alloy particles is equal to 0.2 or greater and less than 1.2.

[0014] According to one embodiment of the present invention, there is provided a semiconductor device comprising: a semiconductor element; and a substrate, wherein the semiconductor element and the substrate are connected to each other by inserting the above-mentioned connection structure therebetween.

[0015] According to one embodiment of the present invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of: preparing a paste by mixing Sn particles, Cu alloy particles containing P in an amount of 1 mass % or more and less than 7 mass %, Ag particles, and a solvent, wherein the total amount of the Cu alloy particles and the Ag particles is set to 25 mass % or more and less than 65 mass % with respect to a total amount of the Sn particles, the Cu alloy particles, and the Ag particles, and a mass ratio of the Ag particles to the Cu alloy particles is set to 0.2 or more and less than 1.2; applying the paste to a substrate; disposing a semiconductor element on the paste; volatilizing the solvent in the paste by heating at a temperature of 120°C or higher and 200°C or lower;and bonding the semiconductor element and the substrate together by heating to a temperature of 340 °C or higher and a temperature lower than 450 °C; Advantageous effects of the invention

[0016] According to the present invention, an interconnection structure can be provided that has high interconnection reliability, such as high resistance to cracking, even during operation of the semiconductor device at a high temperature. Furthermore, according to the present invention, a semiconductor device having the interconnection structure with high interconnection reliability and a manufacturing method for the same can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The figures show: Fig.1 is a schematic sectional view of a semiconductor device having an interconnection structure according to a first embodiment; Fig. 2 is a flowchart of a method for manufacturing a semiconductor device having an interconnection structure according to the first embodiment; Fig. 3 is a schematic view showing a state of ingredients contained in a paste; Fig. 4 is a schematic view showing the step of applying the paste to a substrate in the method for manufacturing a semiconductor device according to the first embodiment; Fig. 5 is a schematic view showing the step of disposing a semiconductor element on the paste applied to the substrate in the method of manufacturing a semiconductor device according to the first embodiment; Fig.6 is a schematic view showing the step of volatilizing a solvent in the paste by heating in the method for manufacturing a semiconductor device according to the first embodiment; Fig. 7 is a schematic view showing the step of bonding the semiconductor element and the substrate by heating in the method for manufacturing a semiconductor device according to the first embodiment; Fig. 8 a ternary phase diagram of Ag-Sn-Cu; Fig. 9 is a graph showing a relationship between the total amount of Cu alloy particles and Ag particles and the rate of change of the value of a thermal resistance for each Ag / Cu mass ratio; Fig.10 is a graph showing a relationship between the total amount of Cu alloy particles and Ag particles and the rate of change of the value of a thermal resistance for each P content in the Cu alloy particles. DESCRIPTION OF THE EMBODIMENTSFirst Embodiment

[0018] Fig. 1 is a schematic sectional view of a semiconductor device having an interconnection structure according to a first embodiment of the present invention. According to Fig. 1, the semiconductor device has a configuration in which a semiconductor element 1 and a semiconductor substrate 2 are connected to each other by interposing an interconnection structure 3 therebetween. The interconnection structure 3 includes a tin (Sn) phase 4, copper (Cu) alloy particles 5 containing phosphorus (P) in an amount of 1 mass % or more and less than 7 mass %, and silver (Ag) particles 6.

[0019] The surface of each of the Cu alloy particles 5 is coated with a Cu6Sn5 coating layer 7. The surface of each of the Ag particles 6 is coated with an Ag3Sn coating layer 8. The Cu alloy particles 5 and the Ag particles 6 are connected by a Cu 10 Sn3 phase 9 are at least partially bonded to each other. Between the semiconductor element 1 and the connecting structure 3, an Ag layer 10 and an Ag3Sn boundary layer 11 are formed in the specified order from the side of the semiconductor element 1.

[0020] A Cu layer 12 and a Cu6Sn5 barrier layer 13 are formed between the substrate 2 and the interconnect structure 3 in the specified order from the substrate 2 side. Furthermore, voids 14, which are generated during the semiconductor device manufacturing process, are present in the interconnect structure 3. Furthermore, fine Cu-P compound particles, which are generated during the semiconductor device manufacturing process, are dispersed in the interconnect structure 3.

[0021] In the interconnection structure 3 according to the first embodiment, the total addition amounts of the Cu alloy particles 5 and the Ag particles with respect to the interconnection structure 3 is 25 mass % or greater and less than 65 mass %, preferably 30 mass % or greater and 60 mass % or less. When the total addition amounts of the Cu alloy particles 5 and the Ag particles 6 is less than 25 mass %, Sn is insufficient for the Cu alloy particles 5 and the Ag particles 6, and a low melting point phase is observed in the interconnection structure 3. On the other hand, when the total addition amounts of the Cu alloy particles 5 and the Ag particles 6 is 65 mass % or greater, a large number of voids are generated in the interconnection structure 3, and cracks are likely to occur.

[0022] In the joint structure 3 according to the first embodiment, a mass ratio (Ag / Cu mass ratio) of the addition amount of the Ag particles 6 to the addition amount of the Cu alloy particles 5 is 0.2 or greater and less than 1.2, preferably 0.3 or greater and 1.1 or less. If the Ag / Cu mass ratio is less than 0.2 or 1.2 or greater, a large number of voids are generated in the joint structure 3, and cracks are likely to occur.

[0023] The cross-sectional thickness of the connecting structure 3 is preferably 20 µm or greater and 150 µm or less, more preferably 30 µm or greater and 130 µm or less. When the cross-sectional thickness of the connecting structure 3 falls within the above-mentioned ranges, the connecting structure 3 has few voids and can exhibit excellent crack resistance.

[0024] If the phosphorus content of the Cu alloy particles 5 is less than 1 mass% or equal to 7 mass% or higher, a large number of voids are generated in the joint structure 3, and cracks are likely to occur. The phosphorus content of the Cu alloy particles 5 is preferably equal to 2 mass% or higher and equal to 6 mass% or lower. The shape of the Cu alloy particles 5 is not particularly limited, but is preferably spherical. The average particle diameter of the Cu alloy particles 5 is preferably equal to 5 μm or larger and equal to 50 μm or smaller, more preferably equal to 7 μm or larger and equal to 40 μm or smaller.

[0025] When the average particle diameter of the Cu alloy particles 5 falls within the above-mentioned ranges, a solvent easily leaks out from gaps between the Cu alloy particles 5, the Ag particles 6, and the Sn particles, and an oxide layer on the surface of each of the Cu alloy particles 5 is easily removed with the solvent.

[0026] Therefore, a compound with Sn can form. In addition, the thickness of the C U6 Sn5 coating layer 7 coated on the surface of each of the Cu alloy particles 5 is not particularly limited, but is preferably 3 µm or larger and 20 µm or smaller.

[0027] The shape of the Ag particles 6 is not particularly limited, but is preferably spherical. The average particle diameter of the Ag particles 6 is preferably 5 μm or larger and 50 μm or smaller, more preferably 7 μm or larger and 40 μm or smaller. When the average particle diameter of the Ag particles 6 falls within the above-mentioned ranges, a solvent easily leaks from gaps between the Cu alloy particles 5, the Ag particles 6, and the Sn particles, and an oxide layer on the surface of each of the Ag particles 6 is easily removed with the solvent.

[0028] Therefore, a compound with Sn can be formed. The thickness of the Ag3Sn coating layer 8 coated on the surface of each of the Ag particles 6 is not particularly limited, but is preferably 5 μm or larger and 30 μm or smaller.

[0029] As used herein, the mean particle diameter is a value measured by using an apparatus based on a particle diameter analysis laser diffraction / scattering method described in JIS-Z-8825.

[0030] The thickness of the Ag3Sn interface layer 11 is not particularly limited, but is preferably equal to or greater than 5 µm and equal to or less than 30 µm.

[0031] The thickness of the Cu6Sn5 interface layer 13 is not particularly limited, but is preferably equal to or greater than 3 µm and equal to or less than 20 µm.

[0032] As used herein, the thickness of each of the Cu6Sn5 cap layer 7, the Ag3Sn cap layer 8, the Ag3Sn interface layer 11, and the Cu6Sn5 interface layer 13 is a value measured by measuring a cross section of a bonding portion by using a scanning electron microscope (SEM) device.

[0033] The semiconductor element 1 may be a conventional semiconductor element made of silicon (Si) as a base material, but it is preferably a wide band gap semiconductor element made of a wide band gap semiconductor material such as silicon carbide (SiC), a gallium nitride (GaN)-based material, or diamond having a band gap larger than that of silicon. The Ag layer 10 is formed on the semiconductor element 1 to ensure a connection property with the interconnection structure 3. The thickness of the Ag layer 10 is not particularly limited as long as the connection property with the interconnection structure 3 can be ensured.

[0034] Examples of a material for the substrate 2 include silicon nitride (Si3N4), aluminum nitride (AlN), and a copper-molybdenum alloy. The Cu layer 12 is formed on the substrate 2 to ensure a connection property with the interconnection structure 3. The thickness of the Cu layer 12 is not specifically limited as long as the connection property with the interconnection structure 3 can be ensured. Furthermore, the Cu layer 12 only requires Cu as a main ingredient, and the Cu layer 12 may contain a Cu alloy such as Cu-Mo, Cu-Cr, Cu-W, Cu-P, Cu-Sn, or Cu-Zn.

[0035] Next, a method for manufacturing a semiconductor device having an interconnection structure according to the first embodiment will be described. Fig. 2 is a flowchart of the method for manufacturing a semiconductor device having an interconnection structure according to the first embodiment.

[0036] First, Sn particles, Cu alloy particles containing P in an amount of 1 mass% or more and less than 7 mass%, Ag particles and a solvent are mixed to prepare a paste (S1). Fig. Figure 3 is a schematic view showing the state of the ingredients contained in the paste. As shown in Fig. 3, Sn particles 17, the Cu alloy particles 5 and the Ag particles 6 are in a paste 16 in a state in which they are dispersed in a solvent 18.

[0037] A method for producing the Sn particles 17, the Cu alloy particles 5, and the Ag particles 6 used here is not particularly limited, and a known method such as a sputtering method can be used. As a solvent 18, a solvent used for a known bonding material paste can be used, and examples thereof include terpineol, diethylene glycol monobutyl ether, methyl ethyl ketone, and isophorone.

[0038] The solvent 18 is preferably contained in the paste 16 in a range of 10 mass% or more and 30 mass% or less. The total amount of the Cu alloy particles 5 and the Ag particles 6 contained in the paste 16 with respect to the total amount of the Sn particles 17, the Cu alloy particles 5, and the Ag particles 6 is 25 mass% or more and less than 65 mass%, preferably 30 mass% or more and 60 mass% or less.

[0039] When the total amount of Cu alloy particles 5 and Ag particles 6 is less than 25 mass%, Sn is insufficient for Cu alloy particles 5 and Ag particles 6, and a low melting point phase is observed in the joint structure 3. On the other hand, when the total amount of Cu alloy particles 5 and Ag particles 6 is 65 mass% or more, a large number of voids are generated in the joint structure 3, and cracks are likely to occur.

[0040] A mass ratio (Ag / Cu mass ratio) of the Ag particles 6 contained in the paste 16 to the Cu alloy particles 5 contained therein is 0.2 or greater and less than 1.2, preferably 0.3 or greater and 1.1 or less. If the Ag / Cu mass ratio is less than 0.2 or 1.2 or greater, a large number of voids are generated in the joint structure 3, and cracks are likely to occur.

[0041] Next, the prepared paste 16 is applied to the Cu layer 12 of the substrate 2 (S2), as shown in Fig.4. It is only necessary that the application thickness of the paste 16 be adjusted appropriately so that the interconnect structure 3 has a desired cross-sectional thickness. The method for applying the paste 16 is not particularly limited as long as the paste 16 can be uniformly applied with a desired application thickness, and examples thereof include an application method using a doctor blade and an application method using an applicator.

[0042] As in Fig.Next, as shown in Figure 5, the semiconductor element 1 is placed on the paste 16 deposited on the Cu layer 12 of the substrate 2 so that the Ag layer 10 of the semiconductor element 1 is brought into contact with the paste 16 (S3). To place the semiconductor element 1 on the paste 16 with high accuracy, an apparatus capable of automatically detecting the upper surface of the paste 16, for example, a chip mounter manufactured by Athlete FA Corporation, may be used.

[0043] As in Fig.Next, as shown in Figure 6, a laminate comprising the semiconductor element 1, the paste 16, and the substrate 2 is heated to a temperature of 120°C or higher and 200°C or lower to volatilize the solvent 18, thereby removing the solvent 18 from the paste 16 (S4). A resulting paste-like dry body 19 consists of the Sn particles 17, the Cu alloy particles 5, and the Ag particles 6.

[0044] Heating can be performed in any atmosphere, such as a vacuum atmosphere, an atmospheric atmosphere, or an inert gas atmosphere, but it is necessary to perform the heating in such a way that the Sn particles 17 do not melt. It is only necessary that the heating temperature be appropriately set in a range of 120°C or more and 200°C or less depending on the boiling point of the solvent 18.

[0045] As in Fig.7, the laminate comprising the semiconductor element 1, the pasty dry body 19, and the substrate 2 is finally heated to a temperature of 340°C or higher and a temperature lower than 450°C to bond the semiconductor element 1 and the substrate 2 by inserting the bonding structure 3 therebetween (S5). In this step, the Sn particles 17 melt when the heating temperature reaches 232°C. When the Sn particles 17 are melted, the Ag3Sn bonding layer 11 forms at the interface with the Ag layer 10 of the semiconductor element 1, and the C bonding layer 12 forms at the interface with the Cu layer 12 of the substrate 2. U6 Sn5 interface 13.

[0046] At the same time, the Cu6Sn5 coating layer 7 forms to cover the surface of each of the Cu alloy particles 5, and the Ag3Sn coating layer 8 forms to cover the surface of each of the Ag particles 6. Dissolved oxygen is present in a considerable amount in the Cu alloy particles 5. This oxygen deteriorates the bonding properties. However, when the Cu6Sn5 coating layer 7 is formed, the P contained in the Cu alloy particles 5 acts as a deoxidizer and preferentially reacts with oxygen to form a phosphorus oxide. This phosphorus oxide is evaporated when the heating temperature reaches 270°C.

[0047] It is possible that some of the P contained in the Cu alloy particles 5 does not react with oxygen and precipitates in the joint structure 3 as fine Cu-P joint particles. When the P content of the Cu alloy particles 5 is 1 mass% or higher and less than 7 mass%, the joint reliability is not adversely affected. Subsequently, when the heating temperature reaches 340°C or higher and less than 450°C, a phase transition occurs between the Cu6Sn5 covering layer 7 and the Ag3Sn covering layer 8, so that the Cu 10 Sn3 phase 9 forms.

[0048] The Cu alloy particles 5 and the Ag particles 6 are separated by the Cu 10Snz3 phase 9 is at least partially bonded to each other, and consequently, the voids 14 that act as starting points for cracks are reduced. As a result, cracks are less likely to form in the interconnect structure 3, even when the semiconductor device is operated at high temperatures.

[0049] In the semiconductor device having the interconnection structure 3 manufactured in the manner described above, cracks are less likely to occur even during high-temperature operation, and the semiconductor device has high reliability.

[0050] In the above, the manner of connecting the semiconductor element and the substrate to each other has been described, but the present invention is not limited thereto. For example, the present invention can also be applied to a manner of connecting the semiconductor element and a lead frame to each other, a manner of connecting the substrate and cooling fins to each other, and the like. Furthermore, the present invention is not limited to the case where a semiconductor element and a substrate are connected to each other, and a plurality of semiconductor elements and elements may be arranged on a substrate and connected to each other at the same time. ExamplesExample 1

[0051] Sn particles with an average particle diameter of 20 µm, Cu alloy particles with a P content of 5 mass% and an average particle diameter of 20 µm, Ag particles, and terpineol as a solvent were mixed together to prepare a paste.

[0052] In this case, the total amount of Cu alloy particles and Ag particles was specified as 50 mass% relative to the total amount of Sn particles, Cu alloy particles, and Ag particles, and the Ag / Cu mass ratio was specified as 0.67 (the number was rounded to the second decimal place). Furthermore, the amount of solvent relative to the paste was specified as 20 mass%. The Sn particles, Cu alloy particles, and Ag particles used here were prepared by an atomization method, and their shapes were all spherical.

[0053] A stainless steel metal mask with an opening dimension of 10 mm × 10 mm was placed on a direct bonded copper (DBC) substrate with a dimension of 20 mm × 20 mm. Then, the paste prepared above was applied to the resultant substrate using a doctor blade with a thickness of 150 µm. The DBC substrate used was a DBC substrate with a structure in which a 0.4 mm thick Cu layer was formed on each surface of a 0.6 mm thick ceramic (Si3N4).

[0054] On the paste applied on the DBC substrate, a semiconductor element in which an Ag layer with a thickness of 7 µm was formed on one surface of a silicon carbide (SiC) with a dimension of 10 mm × 10 mm and a thickness of 0.3 mm was arranged such that an upper surface of the paste and the Ag layer were brought into contact with each other.

[0055] Next, a laminate comprising the DBC substrate, the paste, and the semiconductor element was heated to 180 °C in a vacuum reflow oven to volatilize the terpineol in the paste.

[0056] Subsequently, the laminate comprising the DBC substrate, the pasty dry body, and the semiconductor element was heated to 340 °C in the vacuum reflow oven at a temperature elevation rate of 30 °C / min and then naturally cooled to obtain a semiconductor device.

[0057] To nondestructively investigate the void generation status in an interconnection structure of the obtained semiconductor device, a lateral surface of the interconnection structure was observed using a scanning acoustic tomograph (SAT) (FineSAT III, manufactured by Hitachi Power Solutions Co., Ltd.). The observed image was binarized using binarization software (Photoshop, produced by Adobe Systems Incorporated) to calculate a void percentage.

[0058] Those with a void percentage of less than 10% were rated as having satisfactory initial bonding properties (◯), and those with a void percentage of 10% or more were rated as having unsatisfactory initial bonding properties (×). The results are shown in Table 1. Examples 2 to 4 and Comparative Examples 1 to 3

[0059] Each semiconductor device was obtained in the same manner as in Example 1, except that the junction temperature was changed to those shown in Table 1. The generation status of voids in the junction structure of the obtained semiconductor device was evaluated in the same manner as in Example 1. The results are shown in Table 1. Table 1 Connection temperature percentage of cavities Initial connection property Presence or absence of Cu 10 Sn3 phase Comparison example 1 300 °C 50 % × missing Comparison example 2 330 °C 40 % × missing Example 1 340 °C 8 % ◯ available Example 2 380 °C 6 % ◯ available Example 3 400 °C 5 % ◯ available Example 4 440 °C 7 % ◯ available Comparison example 3 450 °C 52 % × missing

[0060] As can be seen from Table 1, the initial joining properties were unsatisfactory at a joining temperature lower than 340 °C. The reason for this can be imagined as follows. When a Cu6Sn5 cap layer, an Ag3Sn cap layer, a Cu6Sn5 boundary layer, and an Ag3Sn boundary layer formed with heating, a volume reduction of about 10% occurred, resulting in the formation of voids.

[0061] At a joining temperature of 340 °C or higher and lower than 450 °C, the voids were abruptly reduced, and the initial joining property was satisfactory. When analyzing the composition of a cross section of each of these joining structures, a Cu 10 Sn3 phase formed between the Cu6Sn5 cap layer and the Ag3Sn cap layer.

[0062] The reason for this can be imagined as follows: At a junction temperature of 340 °C or higher, a phase transition occurred between the Cu6Sn5 cap layer and the Ag3Sn cap layer, and the Cu 10 Sn3 phase and a Sn-rich molten phase (eutectic Sn-Cu-Ag phase) were formed. The mechanism by which the Cu 10 Sn3 phase is also formed from a Fig. 8 shown ternary phase diagram of Ag-Sn-Cu.

[0063] At a joining temperature of 450 °C, the initial joining properties were unsatisfactory. A compositional analysis of a cross-section of this joining structure revealed no Cu 10 Sn3 phase was observed. The reason for this can be thought of as follows. On the surface of each of the Cu alloy particles, a Cu3Sn capping layer was formed instead of the Cu6Sn5 capping layer, and the above-mentioned phase transition did not occur. Examples 5 to 13 and Comparative Examples 4 to 22

[0064] Each semiconductor device was obtained in the same manner as in Example 1, except that the total amount of Cu alloy particles and Ag particles and the Ag / Cu mass ratio were changed as shown in Tables 2 and 3, and the bonding temperature was changed to 400 °C.

[0065] A junction structure was cut from the obtained semiconductor device and heated to 300 °C by differential scanning calorimetry (DSC). Thus, it was determined whether or not a melting peak with a melting point of 210 °C to 240 °C, derived from the Sn phase, appeared. Those with a detected melting peak were judged to have a low-melting-point phase, and those without a detected melting peak were judged to have no low-melting-point phase.

[0066] Specifically, when the compound structure was heated in the atmosphere at a temperature elevation rate of 10 °C / min from room temperature to 300 °C, and the melting peak value was less than 20 mJ / mg up to a temperature of 210 °C to 240 °C, it was determined that no low-melting-point phase existed. When the melting peak value was 20 mJ / mg or higher, it was determined that a low-melting-point phase existed. The results are shown in Tables 2 and 3.

[0067] The generation status of voids in the interconnection structure of the obtained semiconductor device was evaluated in the same manner as in Example 1. The results are shown in Tables 2 and 3.

[0068] In addition, the initial thermal resistance of the semiconductor device was measured using a laser flash method. Next, to simulate high-temperature operation of the semiconductor device, the semiconductor device was cycled at 175°C for 30 seconds using a liquid tank-type thermal shock tester, after being held at 50°C for 30 seconds. This process was repeated 100,000 cycles.

[0069] After 100,000 cycles, the thermal resistance value was measured, and a change rate relative to the initial thermal resistance value was calculated according to the following expression. The results are shown in Tables 2 and 3. When the change rate of the thermal resistance value is 10% or more, it can be determined that the crack resistance of the semiconductor device during high-temperature operation is unsatisfactory.

[0070] Rate of change (%) of thermal resistance value = (initial thermal resistance value - thermal resistance value after 100,000 cycles) / initial thermal resistance value × 100 Table 2 Ag particles (mass %) Cu alloy particles (mass%) Sn particles (mass %) Cu alloy particles + Ag particles (mass%) Ag / Cu mass ratio P content (mass%) in Cu alloy particles Presence or absence of the low melting point phase Initial connection property Rate of change (%) of thermal resistance value Example 5 10,0 15,0 75 25 0,67 5 missing ◯ 7 Example 6 20,1 29,9 50 50 0,67 5 missing ◯ 6 Example 7 25,3 37,7 37 63 0,67 5 missing ◯ 6 Example 8 4,2 20,8 75 25 0,20 5 missing ◯ 8 Example 9 8,3 41,7 50 50 0,20 5 missing ◯ 7 Example 10 10,5 52,5 37 63 0,20 5 missing ◯ 7 Example 11 13,1 11,9 75 25 1,10 5 missing ◯ 9 Example 12 26,2 23,8 50 50 1,10 5 missing ◯ 8 Example 13 33,0 30,0 37 63 1,10 5 missing ◯ 8 Table 3 Ag particles (mass %) Cu alloy particles (mass %) Sn particles (mass % Cu alloy particles + Ag particles (mass %) Ag / Cu mass ratio P content (mass %) in Cu alloy particles Presence or absence of the low melting point phase Initial connection property Rate of change (%) of thermal resistance value Comparative example 4 Comparative 2,0 3,0 95 5 0,67 5 available ◯ 35 example 5 4,0 6,0 90 10 0,67 5 available ◯ 33 Comparison example 6 9,2 13,8 77 23 0,67 5 available ◯ 20 Comparison example 7 26,1 38,9 35 65 0,67 5 missing × 18 Comparative example 8 28 42 30 70 0,67 5 missing × 24 Comparison example 9 3,3 19,7 77 23 0,17 5 available × 40 Comparison example 10 3,6 21,4 75 25 0,17 5 missing × 38 Comparative example 11 7,3 42,7 50 50 0,17 5 missing × 34 Comparison example 12 9,2 53,8 37 63 0,17 5 missing × 28 Comparison example 13 9,4 55,6 35 65 0,17 5 missing × 32 Comparative example 14 3,8 19,2 77 23 0,20 5 available ◯ 23 Comparison example 15 10,8 54,2 35 65 0,20 5 missing × 18 Comparison example 16 12,0 11,0 77 23 1,10 5 available ◯ 24 Comparative example 17 34,0 31,0 35 65 1,10 5 missing × 20 Comparative example 18 12,5 10,5 77 23 1,20 5 available × 24 Comparative example 19 13,6 11,4 75 25 1,20 5 missing × 17 Comparison example 20 27,3 22,7 50 50 1,20 5 missing × 18 Comparative example 21 34,4 28,6 37 63 1,20 5 missing × 20 Comparative example 22 35,5 29,5 35 65 1,20 5 missing × 40

[0071] As can be seen from Table 2, in the case where the Cu alloy particles containing 5 mass% P were used, when the total amount of the Cu alloy particles and the Ag particles was set to 25 mass% or more and less than 65 mass% and the Ag / Cu mass ratio was set to 0.2 or more and less than 1.2, a semiconductor device was obtained in which no low melting point phase was observed in the interconnection structure and which had satisfactory initial interconnection property and crack resistance.

[0072] On the other hand, as can be seen from Table 3, even in the case where the Cu alloy particles containing 5 mass% P were used, when the total amount of the Cu alloy particles and the Ag particles was set to be less than 25 mass% or 65 mass% or more, or when the Ag / Cu mass ratio was set to be less than 0.2 or 1.2 or more, a low melting point phase was observed in the joint structure, and the initial joint property was not satisfactory, and moreover, the crack resistance was not satisfactory in any case. Examples 14 to 19 and Comparative Examples 23 to 36

[0073] Each semiconductor device was obtained in the same manner as in Example 1, except that the total amount of the Cu alloy particles and the Ag particles and the P content in the Cu alloy particles were changed as shown in Tables 4 and 5, and the bonding temperature was changed to 400 °C.

[0074] The presence or absence of the low melting point phase and the generation status of voids in the interconnection structure, as well as the rate of change of the thermal resistance value of the obtained semiconductor device were evaluated in the same manner as in Example 5. The results are shown in Tables 4 and 5. Table 4 Ag particles (mass%) Cu alloy particles (mass %) Sn particles (mass %) Cu alloy particles + Ag particles (mass%) Ag / Cu mass ratio P content (mass %) in Cu alloy particles Presence or absence of the low melting point phase Initial connection property Rate of change (%) of thermal resistance value Example 14 10,0 15,0 75 25 0,67 1 missing ◯ 9 Example 15 20,1 29,9 50 50 0,67 1 missing ◯ 8 Example 16 25,3 37,7 37 63 0,67 1 missing ◯ 8 Example 17 10,0 15,0 75 25 0,67 6,5 missing ◯ 8 Example 18 20,1 29,9 50 50 0,67 6,5 missing ◯ 7 Example 19 25,3 37,7 37 63 0,67 6,5 missing ◯ 9 Table 5 Ag particles (mass %) Cu alloy particles (mass %) Sn particles (mass %) Cu alloy particles + Ag particles (mass %) Ag / Cu mass ratio P content (mass %) in Cu alloy particles Presence or absence of the low melting point phase Initial connection property Rate of change (%) of thermal resistance value Comparison example 23 9,2 13,8 77 23 0,67 0,8 available × 25 Comparison example 24 10,0 15,0 75 25 0,67 0,8 missing × 20 Comparative example 25 20,1 29,9 50 50 0,67 0,8 missing × 18 Comparative example 26 25,3 37,7 37 63 0,67 0,8 missing × 19 Comparative example 27 26,1 38,9 35 65 0,67 0,8 missing × 30 Comparative example 28 9,2 13,8 77 23 0,67 1 available ◯ 22 Comparative example 29 26,1 38,9 35 65 0,67 1 missing × 24 Comparison example 30 9,2 13,8 77 23 0,67 6,5 available ◯ 20 Comparison example 31 26,1 38,9 35 65 0,67 6,5 missing × 18 Comparison example 32 9,2 13,8 77 23 0,67 7 available ◯ 25 Comparison example 33 10,0 15,0 75 25 0,67 7 missing × 17 Comparative example 34 20,1 29,9 50 50 0,67 7 missing × 19 Comparison example 35 25,3 37,7 37 63 0,67 7 missing × 21 Comparison example 36 26,1 38,9 35 65 0,67 7 missing × 28

[0075] As can be seen from Table 4, even in the case where the Cu alloy particles containing 1 mass% or 6.5 mass% of P were used, when the total amount of the Cu alloy particles and the Ag particles was set to 25 mass% or more and less than 65 mass% and the Ag / Cu mass ratio was set to 0.2 or more and less than 1.2, a semiconductor device in which no low melting point phase was observed in the interconnection structure and which had satisfactory initial interconnection property and crack resistance was obtained.

[0076] On the other hand, as can be seen from Table 5, even in the case where the Ag / Cu mass ratio was specified as 0.67, when the total amount of the Cu alloy particles and the Ag particles was specified as less than 25 mass% or 65 mass% or more, or when the Cu alloy particles with a P content of less than 1 mass% or 7 mass% or more were used in the joint structure, a phase with a low melting point was observed, and the initial joining property was not satisfactory, and moreover, the crack resistance was not satisfactory in any case.

[0077] Here, Fig.9 shows a graph obtained by plotting the respective Ag / Cu mass ratios, where the vertical axis represents the change rate (%) of the thermal resistance value in Tables 2 and 3, and the horizontal axis represents the total (mass %) of addition amounts of the Cu alloy particles and the Ag particles with respect to the compound structure. In addition, Fig. 10 shows a graph obtained by plotting each P content (mass %) in the Cu alloy particles, wherein the vertical axis represents the change rate (%) of the thermal resistance value in Tables 4 and 5, and the horizontal axis represents the total sum (mass %) of addition amounts of the Cu alloy particles and the Ag particles with respect to the compound structure.

[0078] With Fig. 9 and Fig.10, it was confirmed that in the semiconductor device in which the Cu alloy particles containing P in an amount of 1 mass% or more and less than 7 mass% were used, the total sum of addition amounts of the Cu alloy particles and the Ag particles was set to 25 mass% or more and less than 65 mass% with respect to the connection structure, and the Ag / Cu mass ratio was set to 0.2 or more and less than 1.2, the rate of change of the thermal resistance value was less than 10%. EXPLANATION OF REFERENCE SYMBOLS 1 semiconductor element 2 Substrat 3 Connection structure 4 Sn phase 5 Cu alloy particles 6 Ag particles 7 Cu6Sn5 top layer 8 Ag3Sn top layer 9 Cu 10 Sn3 phase 10 Ag layer 11 Ag3Sn interface 12 Cu layer 13 Cu6Sn5 interface 14 Cavity 15 Cu-P compound particles 16 Paste 17 Sn particles 18 Solvents 19 pasty dry body

Claims

[1] Connection structure (3) to be inserted between a semiconductor element (1) and a substrate (2), the connection structure (3) comprising: - a Sn phase (4); - Cu alloy particles (5) containing P in an amount of 1 mass% or more and less than 7 mass%; and - Ag particles (6), - wherein the Cu alloy particles (5) are each coated with a Cu6Sn5 cover layer (7), - wherein the Ag particles (6) are each coated with an Ag3Sn cover layer (8), - wherein the Cu alloy particles (5) and the Ag particles (6) are separated by a Cu 10 Sn3 phase (9) are at least partially bonded to each other, - wherein the total sum of addition amounts of the Cu alloy particles (5) and the Ag particles (6) with respect to the compound structure (3) is equal to 25 mass% or greater and less than 65 mass% and - wherein the mass ratio of the addition amount of the Ag particles (6) to the addition amount of the Cu alloy particles (5) is equal to 0.2 or greater and less than 1.

2. [2] The interconnection structure (3) according to claim 1, wherein the interconnection structure (3) comprises Cu-P interconnection particles (15) distributed in a dispersed manner. [3] Semiconductor device comprising: - a semiconductor element (1); and - a substrate (2), wherein the semiconductor element (1) and the substrate (2) are connected to one another by inserting the connecting structure (3) according to claim 1 or 2 therebetween. [4] Semiconductor unit according to claim 3, - wherein the semiconductor unit comprises an Ag layer (10) and an Ag3Sn boundary layer (11) formed in the specified order from the semiconductor element side between the semiconductor element (1) and the connecting structure (3), and - wherein the semiconductor unit comprises a Cu layer (12) and a Cu6Sn5 boundary layer (13) formed in the specified order from the side of the substrate between the substrate (2) and the connecting structure (3). [5] A method of manufacturing a semiconductor device comprising the following steps: - producing a paste (16) by mixing Sn particles (17), Cu alloy particles (5) containing P in an amount of 1 mass% or more and less than 7 mass%, Ag particles (6) and a solvent (18), wherein the total amount of the Cu alloy particles (5) and the Ag particles (6) with respect to a total amount of the Sn particles (17), the Cu alloy particles (5) and the Ag particles (6) is specified as 25 mass% or more and less than 65 mass%, wherein the mass ratio of the Ag particles (6) to the Cu alloy particles (5) is specified as 0.2 or more and less than 1.2; - applying the paste (16) to a substrate (2); - arranging a semiconductor element (1) on the paste (16); - volatilizing the solvent (18) in the paste (16) by heating to a temperature of 120°C or higher and 200°C or lower; and - bonding the semiconductor element (1) and the substrate (2) to each other by heating to a temperature of 340 °C or higher and a temperature lower than 450 °C.

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