SEMICONDUCTOR COMPONENT AND SEMICONDUCTOR COMPONENT IDENTIFICATION METHOD

Abstract

Semiconductor component with: a first external terminal (31) to which a first voltage (IN) is to be applied; a second external terminal (32) to which a second voltage (GND) is to be applied; a third external terminal (33); a fourth external terminal (34) to which a supply voltage (VCC) is to be applied; a first wiring (17) connected to the first external terminal; a second wiring (18) connected to the second external terminal; a first internal block circuit (11) connected to the first wiring (17); a first resistor (12) and a first switching element (14) connected in series between the first wiring (17) and the second wiring (18); a second resistor (13) connected between the first wiring (17) and the second wiring (18); and a test circuit (20) which controls the first switching element (14), wherein the first switching element (14) switches on or off based on a test signal to be applied to the third external terminal (33), wherein the first external terminal (31) is an input terminal to which a control signal for controlling the first internal block circuit (11) is input, and wherein the test circuit (20) controls the first switching element (14) by inverting and transmitting the test signal from the third external terminal (33) when the supply voltage is supplied from the fourth external terminal (34).

Description

TECHNICAL FIELD

[0001] The invention relates to a semiconductor device and a semiconductor device identification method. STATE OF THE ART

[0002] Semiconductor devices have markings on their resin surfaces to enable the product types of the individual devices to be identified. Some semiconductor devices with different configurations or electrical characteristics may appear identical when packaged in a single housing. In addition, the markings on the semiconductor devices may be hidden from view when mounted on substrates, making it difficult to identify the product types of the semiconductor devices. In one method for product identification in such a situation, a semiconductor device is provided with a resistance element having a specific resistance value corresponding to a product type, and the resistance value of the resistance element is measured at external terminals (see, for example, Patent Document 1). State of the art documentPatent document

[0003] Patent document 1: JP 2015 - 68 810 A Further semiconductor components are known from the documents JP 2015 - 68 810 A and DE 10 2006 002 521 A1. OVERVIEW OF THE INVENTIONTechnical Problem

[0004] Some semiconductor devices may be provided with a resistance element that has a predetermined resistance value that cannot be changed due to the specifications (electrical properties) of the semiconductor device. In such a case, adjusting the resistance value for the purpose of enabling product identification is difficult.

[0005] The present disclosure aims to provide a semiconductor device and a method for identifying a semiconductor device, respectively, each enabling product identification by a resistance value even when the predetermined resistance value cannot be changed. Solution to the problem

[0006] A first aspect of the present disclosure provides a semiconductor device having the features of claim 1, comprising: a first external terminal to which a first voltage is to be applied; a second external terminal to which a second voltage is to be applied; a third external terminal; a first wiring connected to the first external terminal; a second wiring connected to the second external terminal; a first internal block circuit connected to the first wiring; a first resistor and a first switching element connected in series between the first wiring and the second wiring; and a second resistor connected between the first wiring and the second wiring.The first switching element switches on or off based on a test signal that is to be applied to the third external terminal.

[0007] A further (third) aspect of the present disclosure provides methods according to claims 15, 16, 17, and 18 for identifying a semiconductor device. The method is for product identification of the semiconductor device. The method includes: a first step of turning off the first switching element; and a second step of detecting a resistance value of the second resistor based on a voltage between the first external terminal and the second external terminal. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram of a semiconductor device according to a first embodiment. Fig. Figure 2 shows a layout of a portion of the semiconductor device shown in Fig. 1 is shown. Fig.3 is a circuit diagram of a semiconductor device according to a second embodiment. Fig. 4 is a circuit diagram of a semiconductor device according to a third embodiment. Fig. 5 is a circuit diagram of an example of a second internal block circuit shown in Fig. 4 is shown. Fig. 6 is a circuit diagram of a semiconductor device according to a fourth embodiment. Fig. 7 is a circuit diagram of a semiconductor device according to a fifth embodiment. Fig. 8 is a plan view of a power module including a semiconductor device. Fig. 9 is a partial plan view of a power module with a semiconductor device. Fig. 10 is a bottom view of a power module including a semiconductor device. Fig. 11 is a plan view of an upper switching driver of a semiconductor device. Fig. 12 is a plan view of a bottom switching driver of a semiconductor device. Fig. 13 is a schematic circuit diagram of the power module used in Fig. 8 is shown. Fig. 14 is a circuit diagram showing part of the circuits of the power module used in Fig. 8 is shown. Fig. 15 is a circuit diagram showing an example of a first test circuit (test circuit). Fig. 16 is a circuit diagram showing an example of a second test circuit. Fig. 17 is a circuit diagram showing an example of a test circuit according to a variation. Fig. 18 is a circuit diagram showing an example of a test circuit according to a modification. Fig. 19 is a circuit diagram of a semiconductor device according to a modification. MODE FOR CARRYING OUT THE INVENTION

[0008] Embodiments of semiconductor devices are described below with reference to the drawings. The embodiments are provided for the purpose of illustrating some configurations and implementations for carrying out the technical ideas.

[0009] As used herein, "an element A is connected to an element B" means that elements A and B are physically and directly connected, or elements A and B are indirectly connected through another element that does not affect or impair the electrical communication or connection therebetween.

[0010] Similarly, the phrase "an element C is between elements A and B" as used herein means that elements A and C or elements B and C are directly connected to each other or that they are indirectly connected to each other via another element that does not affect or impair electrical communication therebetween. First embodiment

[0011] With reference to Fig. 1 and Fig. 2, a semiconductor device 1a according to a first embodiment is described. Fig. 1 shows a circuit diagram of a main part of the semiconductor device 1a and also shows a schematic configuration of a resistance measuring device 100. In one example, the resistance measuring device 100 may be a hand-held test device.

[0012] The semiconductor device 1a is a module composed of a plurality of electrical elements such as transistors and resistors, and sealed with a sealing resin. Fig. 1, the semiconductor device 1a includes an internal block circuit 11, which is an example of a first internal block circuit, a first resistor 12, a second resistor 13, a transistor 14, which is an example of a first switching element, a first diode 15, a second diode 16, a first wiring 17, a second wiring 18, a third wiring 19, and a test circuit 20, which is an example of a first test circuit.

[0013] The semiconductor device 1a also includes a plurality of terminals extending from the sealing resin, including a first external terminal 31, a second external terminal 32, a third external terminal 33, which is an example of an external sensor terminal, and a fourth external terminal 34. The first external terminal 31 is an input terminal to which a control signal for controlling the internal block circuit 11 of the semiconductor device 1a is input. The second external terminal 32 is a ground (GND) terminal. The third external terminal 33 outputs a fault signal to the outside upon detection of a fault in the semiconductor device 1a. Furthermore, the third external terminal 33 of this embodiment receives a test signal applied for identifying the product type of the semiconductor device 1a or for testing the electrical property.The fourth external terminal 34 is a terminal to which a supply voltage or source voltage VCC is applied. The first external terminal 31 is connected to the first wiring 17, the second external terminal 32 is connected to the second wiring 18, and the fourth external terminal 34 is connected to the third wiring 19. The first wiring 17 receives a first voltage applied to the first external terminal 31 for inputting a control signal. In one example, the first voltage is a control voltage of 3.3 to 5.0 volts. The second wiring 18 receives a second voltage at a ground potential via the second external terminal 32.

[0014] The internal block circuit 11 may include a power transistor 11X, a gate drive circuit 11Y for driving the power transistor 11X, and a Schmitt trigger 11Z. The gate drive circuit 11Y is connected between the power transistor 11X and the Schmitt trigger 11Z. The power transistor 11X may be, for example, an insulated gate bipolar transistor (IGBT). The control terminal of the power transistor 11X is a gate terminal 11g connected to the first wiring 17. The power transistor 11X may be a MOSFET or any other transistor. The control terminal of the power transistor 11X receives a gate control signal, whose pulses are input at a frequency of 2 kHz or higher, via the first external terminal 31 and the gate drive circuit 11Y.In one example, the frequency of the gate control signal is preferably within a range of 5 kHz to 20 kHz, inclusive.

[0015] The first resistor 12 and the transistor 14 as a switching element are connected in series between the first wiring 17 and the second wiring 18. The transistor 14 can be, for example, an NMOSFET. The source of the transistor 14 is connected to the second wiring 18, and the gate, which is, for example, the control terminal, of the transistor 14 is connected to the third external terminal 33 via the test circuit 20.

[0016] The second resistor 13 is connected between the first wiring 17 and the second wiring 18. When the transistor 14 is turned on, the first resistor 12 and the second resistor 13 are connected between the first wiring 17 and the second wiring 18. In other words, the first resistor 12 and the second resistor 13 are connected in parallel. The first resistor 12 and the second resistor 13, connected in parallel, have a combined resistance that matches the predetermined resistance specified by the specifications of the semiconductor device 1a. In one example, the specified resistance is 5 kΩ.

[0017] When the transistor 14 is off, only the second resistor 13 is connected between the first wiring 17 and the second wiring 18. The second resistor 13 has a resistance value determined based on the specifications (electrical characteristics) of the semiconductor device 1a, which is used to identify the product type of the semiconductor device 1a. In addition, the first resistor 12 has a resistance value determined such that the combined resistance value of the first resistor 12 and the second resistor 13 matches the specified resistance value.

[0018] More specifically, the resistance value of the second resistor 13 is first determined based on the specifications of the semiconductor device 1a. Then, the resistance value of the first resistor 12 is determined so that, when combined with the second resistor 13, it matches the specified resistance value. In one example, the resistance value of the first resistor 12 is 5.03 kΩ, and the resistance value of the second resistor 13 is 800 kΩ. In another example, the resistance value of the first resistor 12 is 5.26 kΩ, and the resistance value of the second resistor 13 is 100 kΩ.

[0019] In one example, both the first resistor 12 and the second resistor 13 may be polysilicon resistors. The second resistor 13 has a greater resistance than the first resistor 12. The resistance of a polysilicon resistor depends on the ion implantation dose. For example, the amount of ions in the second resistor 13 is smaller than the amount of ions in the first resistor 12.

[0020] The first diode 15 and the second diode 16 are provided for the purpose of electrostatic protection of the internal block circuit 11. The cathode of the first diode 15 is connected to the third wiring 19, and the anode of the first diode 15 is connected to the first wiring 17. The cathode of the second diode 16 is connected to the first wiring 17, and the anode of the second diode 16 is connected to the second wiring 18.

[0021] The test circuit 20 is connected to the third wiring 19, to the third external terminal 33, and to the control terminal (gate) of the transistor 14. The test circuit 20 controls turning on and off the transistor 14 according to the state of the third external terminal 33. For example, when the power supply voltage VCC is supplied but no test signal is applied to the third external terminal 33 (open state), the test circuit 20 turns on the transistor 14. On the other hand, when the power supply voltage VCC is supplied and a test signal of a predetermined level is applied to the third external terminal 33, the test circuit 20 supplies a gate signal voltage to the gate of the transistor 14, thereby turning off the transistor 14.

[0022] The circuit of the Fig.1 may be implemented as an IC, and the layout of the first resistor 12, the second resistor 13, the first diode 15, the second diode 16 and the first external terminal 31 for such a circuit will be described below. Fig. 2 shows an example of the layout of the first resistor 12, the second resistor 13, the first diode 15, the second diode 16 and the first external terminal 31.

[0023] In the module of the semiconductor device 1a, the second wiring 18 and the third wiring 19 are arranged closer to the module edge than the first external terminal 31. The second wiring 18 is arranged closer to the module center of the semiconductor device 1a than the third wiring 19. The second wiring 18 and the third wiring 19 extend parallel to each other.

[0024] The first diode 15, the second diode 16, and the first resistor 12 are arranged closer to the module edge of the semiconductor device 1a than the first external terminal 31. The first diode 15, the second diode 16, and the first resistor 12 are connected to the first wiring 17, which is connected to the first external terminal 31. On the first wiring 17, the first diode 15, the second diode 16, and the first resistor 12 are arranged in order or magnitude closer to the first external terminal 31.

[0025] The second resistor 13 is connected to the first wiring 17, which is not shown in the figure. The second resistor 13 is connected to the first wiring 17 at a location farther from the first external terminal 31 than the first resistor 12. As can be seen from Fig. 3 or Fig. 2, the second resistor 13 has a smaller surface area than the first resistor 12.

[0026] Next, the operation of the semiconductor device 1a will be described below with reference to Fig. 1. The semiconductor component 1a has a normal mode for normal operation and a test mode for product identification of the semiconductor component 1a using the resistance measuring device 100.

[0027] In the normal mode, the supply voltage VCC is applied to the third wiring 19 via the fourth external terminal 34. According to the logic input to the first external terminal 31, a drive voltage is applied via a drive voltage terminal to turn the power transistor 11X on or off. In the normal mode, no test signal is applied to the third external terminal 33, and the test circuit 20 thus turns on the transistor 14. As a result, the first resistor 12 is connected in parallel with the second resistor 13, so that the combined resistance of the first resistor 12 and the second resistor 13, which are connected in parallel, pulls the first external terminal 31 down to the level of the second wiring 18.The resistance value of the combined resistor that pulls down the first external terminal 31 is equal to the predetermined resistance value required by the specifications of the semiconductor device 1a.

[0028] In the test mode, the supply voltage VCC is applied to the third wiring 19 via the fourth external terminal 34. In addition, a first probe 101 of the resistance measuring device 100 is connected to the first external terminal 31, and a second probe 102 is connected to the second external terminal 32. In this state, a test signal is input to the third external terminal 33, whereupon the test circuit 20 turns off the transistor 14. The resistance measuring device 100 then measures the resistance value of the second resistor 13 between the first external terminal 31 and the second external terminal 32. The product type of the semiconductor device 1a can be identified based on the measured resistance value of the second resistor 13.More specifically, semiconductor devices with identical packages (modules) may differ in specifications, such as configurations or the electrical characteristic values ​​of the electrical elements. Each such semiconductor device has a second resistor 13 set to a resistance value that is unique for the type of devices with the same specifications. Accordingly, determining the resistance value of the second resistor 13 enables the specifications of the semiconductor device 1a to be identified. In the test mode, the test circuit 20 deactivates the first resistor 12 so that only the second resistor 13 remains active. Subsequently, the resistance value of the second resistor 13 can be measured using the resistance measuring device 100. The product type of the semiconductor device 1a can be identified by the measured resistance value of the second resistor 13.In this way, in the test mode for performing product identification of the semiconductor device 1a, a method for identifying the semiconductor device 1a includes a first step of turning off the transistor 14 and a second step of measuring the resistance value of the second resistor 13 between the first external terminal 31 and the second external terminal 32.

[0029] Without the supply voltage VCC applied to the third wiring 19, the test circuit 20 does not operate. As a result, no gate signal voltage is applied to the gate of the transistor 14, and thus the transistor 14 turns off. In this state, by connecting the first probe 101 to the first external terminal 31 and the second probe 102 to the second external terminal 32 as in the test mode described above, the resistance measuring device 100 can measure the resistance value of only the second resistor 13 connected between the first external terminal 31 and the second external terminal 32. The product type of the semiconductor device 1a can be identified based on the measured resistance value of the second resistor 13. In this way, product identification of the semiconductor device 1a is possible using the resistance measuring device 100 without the supply voltage VCC.

[0030] The present embodiment can achieve the following advantages.

[0031] (1-1) In the normal mode, the first resistor 12 is activated by turning on the transistor 14, so that the predetermined resistance value (5 kΩ) required by the specifications of the semiconductor device 1a is provided by the combined resistance value of the first resistor 12 and the second resistor 13. When the power supply voltage VCC is not applied, the transistor 14 is turned off. Accordingly, of the first resistor 12 and the second resistor 13, only the second resistor 13 is connected between the first wiring 17 and the second wiring 18. In this state, the resistance value of the second resistor 13 can be measured by the resistance measuring device 100 from the voltage between the first external terminal 31 and the second external terminal 32.In the test mode, when the transistor 14 is off, the resistance value of the second resistor 13 can be measured by the resistance measuring device 100 from the voltage between the first external terminal 31 and the second external terminal 32. Accordingly, the second resistor 13 can be designed to have any resistance value unique to the type of specifications (electrical characteristics) of the semiconductor device 1a, so that the semiconductor device 1a can be identified by the resistance value of the second resistor 13. That is, for the purpose of product identification of the semiconductor device 1a, a resistor with a predetermined resistance value that pulls down the level of the first external terminal 31 can be used.In this way, the semiconductor device 1a can be identified by using a resistance value even in a case where a certain resistance value should not be changed.

[0032] (1-2) The second resistor 13 has a resistance value smaller than the resistance value of the first resistor 12. This means that the second resistor 13 has a smaller area than the area of ​​the first resistor 12, which is effective for reducing the size of the semiconductor device 1a.

[0033] (1-3) The first wiring 17 has a shorter length between the first external terminal 31 and the first resistor 12 than between the first external terminal 31 and the second resistor 13. In this configuration, the first resistor 12, which is effective to suppress rapid surges in an external voltage of the semiconductor device 1a, is arranged near the first external terminal 31. This can reduce the influence on the first resistor 12 induced by the resistance or inductance of the first wiring 17 connecting the first resistor 12 and the first external terminal 31. Second embodiment

[0034] With reference to Fig.3, a semiconductor device 1b according to a second embodiment is described. In the description of this embodiment, components similar to those of the first embodiment are denoted by the same reference numerals, and a description thereof will be partially or entirely omitted.

[0035] The semiconductor device 1b of this embodiment differs from the semiconductor device 1a of the first embodiment in that each of the following components is provided in a plurality: the first external terminal 31, the second external terminal 32, the internal block circuit 11, the first resistor 12, the second resistor 13, the first wiring 17 and the second wiring 18. For ease of description, Fig. 3 the first diode 15 and the second diode 16 are not shown.

[0036] As it is in Fig.3, the semiconductor device 1b includes N number of internal block circuits 11, N number of first resistors 12, N number of second resistors 13, N number of pieces of first wiring 17, and N number of first external terminals 31. Fig. 3 denotes each of a plurality of identical components by a like reference numeral (e.g., “11” for the internal block circuits), with the suffix (1 to N) to distinguish the individual components.

[0037] The semiconductor device 1b also includes a piece of second wiring 18, a second external terminal 32, a third external terminal 33, and a fourth external terminal 34, as well as a test circuit 20. The test circuit 20 is connected to the control terminal of each of the transistors 14-1, ... 14-N. The test circuit 20 outputs a control signal to the control terminal of each of the transistors 14-1, ... 14-N. The third external terminal 33 is connected to the test circuit 20 via a wiring 27A. The fourth external terminal 34 is connected to the third wiring 19. The test circuit 20 is connected to the third wiring 19.

[0038] At least one of the number N of second resistors 13-1, ... 13-N has a resistance value that is unique to the product type of the semiconductor device 1b. On the other hand, the combined resistance values ​​of the pairs of corresponding resistors, namely the combined resistance value of the first resistor 12-1 and the second resistor 13-1, ... , the combined resistance value of the first resistor 12-N and the second resistor 13-N, are all the same. Also, as in the first embodiment, the value of the combined resistance is equal to the predetermined resistance value required by the specifications of the semiconductor device 1b. In one example, the resistance value of the combined resistance is 5 kΩ. The resistance value of each of the first resistors 12-1, ... 12-N is set according to the resistance value of a corresponding second resistor 13-1, ...13-N and the specified value.

[0039] Next, the operation of the semiconductor device 1b will be described. In the normal mode, the power supply voltage VCC is applied to the third wiring 19 via the fourth external terminal 34. According to the logic input from each of the first external terminals 31-1, ... 31-N, a drive voltage is applied via a drive voltage terminal to turn on or off a corresponding one of the power transistors 11X-1, ... 11X-N. In the normal mode, no test signal is applied to the third external terminal 33, and the test circuit 20 thus turns on each of the transistors 14-1, ... 14-N. As a result, the first resistors 12-1, ... 12-N are each connected in series or parallel with the second resistors 13-1, ... 13-N, and the combined resistance value of the respective series or parallel connected first resistors 12-1, ... 12-N and second resistors 13-1, ... 13-N draws a corresponding one of the first external terminals 31-1, ...31-N down to the level of the second wiring 18 ("pulls down"). The resistance value of the combined resistor, or resistance value, that pulls down each of the first external terminals 31-1, ... 31-N is equal to the predetermined resistance value specified by the specifications of the semiconductor device 1a.

[0040] In the test mode, or when the supply voltage VCC is not applied to the third wiring 19, the transistors 14-1, ... 14-N are turned off. As a result, of the first resistors 12-1 ... 12-N and the second resistors 13-1, ... 13-N, only the second resistors 13-1, ... 13-N are connected between the first wiring 17 and the second wiring 18. Next, the first probe 101 of the resistance measuring device 100 is connected to the first external terminal 31-1, and the second probe 102 is connected to the second external terminal 32 to measure the resistance value of the second resistor 13-1. Subsequently, the first sensor 101 of the resistance measuring device 100 is sequentially connected to the first external terminals 31-2, ... 31-N to sequentially measure the second resistance 13-2, ... second resistance 13-N, with the second sensor 102 remaining connected to the second external terminal 32.

[0041] The product type of semiconductor device 1b can be identified using the resistance values ​​of the second resistors 13-1, ... 13-N in combination. More specifically, the resistance values ​​of the second resistors 13-1, ... 13-N are measured by the resistance measuring device 100. The obtained set of resistance values ​​is then compared with a number of predetermined sets of resistance values ​​for second resistors 13-1, ... 13-N to search for a match. The found match provides the product type of semiconductor device 1b, since each of the predetermined sets of resistance values ​​is associated with particular or unique specifications of the semiconductor device 1b.

[0042] The present embodiment can achieve the following advantages in addition to those achieved by the first embodiment.

[0043] (2-1) Since the semiconductor device 1b is identified by combining the resistance values ​​of a plurality of second resistors 13, a larger number of resistance values ​​can be used for product identification of a larger number of types of semiconductor devices 1b. This enables the identification of a wider variety of semiconductor devices 1b with identical packages. Third embodiment

[0044] With reference to Fig. 4 and Fig. 5, a semiconductor device 1c according to a third embodiment is described. In the description of this embodiment, components similar to those of the first embodiment are denoted by the same reference numerals, and a description thereof is partially or entirely omitted.

[0045] The semiconductor device 1c of the present embodiment includes a first internal block circuit 11A and a second internal block circuit 11B. The first internal block circuit 11A has the same configuration as the internal block circuit 11 of the first embodiment.

[0046] Unlike the first internal block circuit 11A, the second internal block circuit 11B has a circuit for a control system. The second internal block circuit 11B operates, for example, on or by means of the supply voltage VCC.

[0047] As it is in Fig.4, the semiconductor device 1c includes an analog switch 41, which is an example of a switching unit. The analog switch 41 has a first terminal connected to the second internal block circuit 11B. The analog switch 41 also has a second terminal connected to a node N1 connecting the first resistor 12 and the drain of the transistor 14. The analog switch 41 may include a PMOSFET and an NMOSFET connected in parallel and configured to turn on or off in a complementary relationship with the transistor 14. Alternatively, the analog switch 41 may include only one of a PMOSFET and an NMOSFET.

[0048] In one example, the second internal block circuit 11B is a temperature measuring circuit 40 as shown in Fig.5. The temperature measuring circuit 40 measures the temperature of a driver IC for the power transistor 11X and includes an analog temperature sensor (hereinafter "temperature sensor 42"), a signal transmission circuit 43, and a constant current source 44.

[0049] The temperature sensor 42 includes a plurality of diodes connected in series. The anode of one diode is connected to the constant current source 44, and the cathode of another diode is connected to ground. The constant current source 44 is connected to the third wiring 19 (see Fig. 5).

[0050] The signal transmission circuit 43 includes a voltage follower circuit 45 and an inverting amplifier circuit 46. The voltage follower circuit 45 has a first input terminal connected to a node N2 connecting the constant current source 44 and the temperature sensor 42. The voltage follower circuit 45 has a second input terminal connected to the output terminal of the voltage follower circuit 45.

[0051] The inverting amplifier circuit 46 includes resistors 47 and 48 and an operational amplifier 46a. The operational amplifier 46a has an inverting input terminal connected to the output terminal of the voltage follower circuit 45 via the resistor 47. The resistor 48 is connected between the inverting input terminal and the output terminal of the operational amplifier 46a. The non-inverting input terminal of the operational amplifier 46a is connected to receive a reference voltage.

[0052] The analog switch 41 has a first terminal connected to a detection terminal 49 connected to a node N3 between the voltage follower circuit 45 and the inverting amplifier circuit 46. Thus, the output voltage of the temperature sensor 42 is input to the analog switch 41.

[0053] Next, the operation of the semiconductor device 1c will be described. The semiconductor device 1c has a normal mode for normal operation, a first test mode for product identification of the semiconductor device 1c using the resistance measuring device 100, and a second test mode for measuring the internal voltage of the second internal block circuit 11B using a voltage measuring device (not shown).

[0054] In the normal mode, the operation of the semiconductor device 1c is similar to the normal mode operation of the semiconductor device 1a of the first embodiment. In this mode, the analog switch 41 is turned off. Likewise, the operation of the semiconductor device 1c in the first test mode is similar to the test mode operation of the semiconductor device 1a of the first embodiment. Specifically, the test circuit 20 and the second internal block circuit 11B do not operate without the application of the power supply voltage VCC to the fourth external terminal 34, so the transistor 14 is turned off and the analog switch 41 is not turned on.In this state, the resistance value of the second resistor 13 connected between the first external terminal 31 and the second external terminal 32 can be measured by the resistance measuring device 100, as in the test mode of the first embodiment, by connecting the first probe 101 to the first external terminal 31 and the second probe 102 to the second external terminal 32. The product type of the semiconductor device 1a can be identified based on the measured value of the second resistor 13. In this way, product identification of the semiconductor device 1c is possible using the resistance measuring device 100 without the power supply voltage VCC.

[0055] However, when the supply voltage VCC is applied to the fourth external terminal 34, the test mode signal is only input from the third external terminal 33. This does not cause both the transistor 14 and the analog switch 41 to turn off. Consequently, product identification cannot be performed.

[0056] In the second test mode, the supply voltage VCC is applied to the fourth external terminal 34. In this state, in response to a test mode signal input from the third external terminal 33, the test circuit 20 turns off the transistor 14 and turns on the analog switch 41. As a result, the analog switch 41 transfers the internal voltage of the second internal block circuit 11B to the node N1 between the first resistor 12 and the transistor 14. This internal voltage appears at the first external terminal 31. Accordingly, the voltage measuring device can measure the internal voltage of the second internal block circuit 11B by measuring the voltage between the first external terminal 31 and the second external terminal 32.As described above, the method for testing the semiconductor device 1c in the second test mode includes a first step of turning off the transistor 14 and turning on the analog switch 41, and a second step of detecting the voltage of the second internal block circuit 11B based on the voltage between the first external terminal 31 and the second external terminal 32.

[0057] The present embodiment can achieve the following advantages in addition to those achieved by the first embodiment.

[0058] (3-1) In the second test mode, the internal voltage of the second internal block circuit 11B can be measured at the first external terminal 31 and the second external terminal 32, which can be used to perform a pre-shipment inspection of the second internal block circuit 11B. Fourth embodiment

[0059] With reference to Fig. 6, a semiconductor device 1d according to a fourth embodiment is described. In the description of this embodiment, components similar to those of the first embodiment are denoted by the same reference numerals, and a description thereof is partially or entirely omitted.

[0060] The semiconductor device 1d according to this embodiment includes a first transistor 14A, which is an example of a first switching element, a second transistor 14B, which is an example of a second switching element, a first test circuit 20A, a second test circuit 20B, and a fifth external terminal 35. The first transistor 14A has the same configuration as the transistor 14 of the first embodiment, and the first test circuit 20A has the same configuration as the test circuit 20 of the first embodiment.

[0061] As it is in Fig. As shown in Figure 6, the second transistor 14B is connected between the second resistor 13 and the second wiring 18. In one example, the second transistor 14B may be an NMOSFET. The second resistor 13 and the second transistor 14B are connected in series between the first wiring 17 and the second wiring 18.

[0062] The first test circuit 20A is connected to the third wiring 19, to the third external terminal 33, and to the control terminal (gate) of the first transistor 14A. The first test circuit 20A controls the turning on and off of the first transistor 14A based on a test signal input to the third external terminal 33.

[0063] The second test circuit 20B is connected to the third wiring 19, to the fifth external terminal 35, and to the control terminal (gate) of the second transistor 14B. The second test circuit 20B controls the turning on and off of the second transistor 14B based on a test signal input to the fifth external terminal 35. The second test circuit 20B may have the same configuration as the first test circuit 20A.

[0064] The following describes the operation of the semiconductor device 1d. The semiconductor device 1d has a normal mode for normal operation and first to third test modes. The first test mode is used for product identification of the semiconductor device 1d using the resistance measuring device 100. The second test mode is used for leakage current measurement using a current measuring device (not shown) to measure the leakage current from the gate terminal 11g of the Schmitt trigger 11Z in the first internal block circuit 11A to the first wiring 17. The third test mode is used to measure the resistance value of the first resistor 12 using the resistance measuring device 100.

[0065] In the normal mode, the power supply voltage VCC is applied to the fourth external terminal 34. In this state, both the first transistor 14A and the second transistor 14B are turned on by applying no test signal to either the third external terminal 33 or the fifth external terminal 35. As a result, the first resistor 12 and the second resistor 13 are connected in parallel, so that the combined resistance of the first resistor 12 and the second resistor 13, which are connected in parallel, pulls down the first external terminal 31 to the level of the second wiring 18. The value of the combined resistance that pulls down the first external terminal 31 is equal to the predetermined resistance specified by the specifications of the semiconductor device 1a.

[0066] In the first test mode, the resistance measuring device 100 is prepared by connecting the first probe 101 to the first external terminal 31 and the second probe 102 to the second external terminal 32. In addition, a test signal is applied to both the third external terminal 33 and the fifth external terminal 35. The test signal applied to the third external terminal 33 is a control signal for turning off the first transistor 14A. The test signal applied to the fifth external terminal 35 is a control signal for turning on or off the second transistor 14B. In addition, the supply voltage VCC is applied to the fourth external terminal 34.

[0067] In the first test mode, the first test circuit 20A turns off the first transistor 14A in response to the test signal received from the third external terminal 33. As a result, of the first resistor 12 and the second resistor 13, only the second resistor 13 is connected between the first wiring 17 and the second wiring 18. Subsequently, the resistance measuring device 100 can measure the resistance value of the second resistor 13 between the first external terminal 31 and the second external terminal 32. As shown above, the method for testing the semiconductor device 1d in the first test mode includes a first step of turning off the first transistor 14A and turning on the second transistor 14B, and a second step of measuring the resistance value of the second resistor 13 between the first external terminal 31 and the second external terminal 32.

[0068] Similar to the semiconductor device 1a of the first embodiment, the semiconductor device 1d includes the second resistor 13, which is set to a resistance value unique to the type of specifications of the semiconductor device 1d. Accordingly, the product type of the semiconductor device 1d can be identified using the resistance value of the second resistor 13.

[0069] In the second test mode, the current measuring device is prepared by connecting the first sensor (not shown) to the first external terminal 31 and the second sensor (not shown) to the second external terminal 32. In addition, a test signal is applied to both the third external terminal 33 and the fifth external terminal 35. In addition, the supply voltage VCC is applied to the fourth external terminal 34.

[0070] In the second test mode, the first test circuit 20A turns off the first transistor 14A in response to the test signal from the third external terminal 33, and the second test circuit 20B turns off the second transistor 14B in response to the test signal from the fifth external terminal 35. As a result, the first wiring 17 is disconnected from the second wiring 18. Subsequently, the current or resistance measuring device 100 can measure the leakage current flowing through the first wiring 17 in the first internal block circuit 11A, more specifically, the leakage current from the gate terminal 11g of the Schmitt trigger 11Z to the first wiring 17.

[0071] In the third test mode, the resistance measuring device 100 is prepared by connecting the first probe 101 to the first external terminal 31 and the second probe 102 to the second external terminal 32. In addition, a test signal is applied only to the fifth external terminal 35. The supply voltage VCC is applied to the fourth external terminal 34.

[0072] In the third test mode, the second test circuit 20B turns off the second transistor 14B in response to the test signal received from the fifth external terminal 35. As a result, of the first resistor 12 and the second resistor 13, only the first resistor 12 is connected between the first wiring 17 and the second wiring 18. Subsequently, the resistance measuring device 100 can measure the resistance value of the first resistor 12 between the first external terminal 31 and the second external terminal 32.

[0073] The present embodiment can achieve the following advantages in addition to the advantages achieved by the first embodiment.

[0074] (4-1) When there is a current path (e.g., resistance) connecting the first wiring 17 and the second wiring 18, a current flows from the first wiring 17 to the second wiring 18. In this state, it is not possible to measure the leakage current from the gate terminal 11g of the Schmitt trigger 11Z to the first wiring 17. In view of this, the present embodiment provides the second test mode in which both transistors 14A and 14B are turned off, so that the current path between the first wiring 17 and the second wiring 18 is cut off. In this state, the leakage current from the Schmitt trigger 11Z can be accurately measured by measuring the current through the first wiring 17. Fifth embodiment

[0075] With reference to Fig. 7, a semiconductor device 1e according to a fifth embodiment is described. In the description of this embodiment, components similar to those of the fourth embodiment are denoted by the same reference numerals, and a description thereof will be partially or entirely omitted.

[0076] The semiconductor device 1e of the present embodiment is similar to the semiconductor device 1d of the fourth embodiment and includes a first internal block circuit 11A, a second internal block circuit 11B, and an analog switch 41. The first internal block circuit 11A has the same configuration as the internal block circuit 11 of the fourth embodiment. The second internal block circuit 11B has the same configuration as the second internal block circuit 11B of the third embodiment.

[0077] The first terminal of the analog switch 41 is connected to the second internal block circuit 11B, and the second terminal of the analog switch 41 is connected to a node N1 between the first resistor 12 and the first transistor 14A. The inverting control terminal of the analog switch 41 is connected to the control terminal (gate) of the second transistor 14B.

[0078] The semiconductor device 1e additionally includes a switching control circuit 20C that controls the first transistor 14A, the second transistor 14B, and the analog switch 41 to turn on and off, respectively. The switching control circuit 20C is electrically connected to the first test circuit 20A and the second test circuit 20B and controls the turning on and off of the first transistor 14A, the second transistor 14B, and the analog switch 41 based on the combinations of the test signals applied to the third external terminal 33 and the fifth external terminal 35, as shown in Table 1 below. [Table 1] Test signal input Switch control mode Test signal to third external terminal Test signal to fifth external terminal First transistor Second transistor Analog switch Normal mode 0 0 A A OUT OF First test mode 0 1 OUT OF A OUT OF Second test mode 1 1 OUT OF OUT OF OUT OF Third test mode 1 0 OUT OF OUT OF A

[0079] Table 1 shows the state of each test signal input to the third external terminal 33 and the fifth external terminal 35. The state “0” indicates that the test signal is not applied, and the state “1” indicates that the test signal is applied.

[0080] The operation of the semiconductor device 1e will be described below. The semiconductor device 1e has a normal mode for normal operation, a first test mode for product identification of the semiconductor device 1e using the resistance measuring device 100, a second test mode for measuring the leakage current in the first internal block circuit 11A, and a third test mode for measuring the internal voltage of the second internal block circuit 11B. The operation mode is selected by combining the test signals supplied to the third external terminal 33 and the fifth external terminal 35 from among the four operation modes, including the normal mode, the first test mode, the second test mode, and the third test mode.

[0081] The normal mode, the first test mode, and the second test mode of the semiconductor device 1e will not be described because they are basically similar to the normal mode, the first test mode, and the second test mode of the fourth embodiment, respectively. The difference lies in that the operation of the analog switch 41 is additionally involved. That is, in the normal mode and the first test mode, the second transistor 14B is turned on, and thus the analog switch 41 is turned off in the normal mode, the first test mode, and the second test mode. In the first test mode, a test signal is applied only to the fifth external terminal 35. In the second test mode, a test signal is applied to both the third external terminal 33 and the fifth external terminal 35.

[0082] In the third test mode, the supply voltage VCC is applied to the fourth external terminal 34. In the third test mode, a test signal is applied only to the third external terminal 33. As a result, the first wiring 17 is disconnected from the second wiring 18. At the same time, the second internal block circuit 11B is active, so that the internal voltage of the second internal block circuit 11B is applied to the node N1 between the first resistor 12 and the transistor 14 via the analog switch 41. Consequently, the internal voltage appears at the first external terminal 31. The voltage measuring device (not shown) can measure the internal voltage of the second internal block circuit 11B by measuring the voltage between the first external terminal 31 and the second external terminal 32.As shown above, the method of testing the semiconductor device 1e in the third test mode includes a first step of turning off the first transistor 14A and the second transistor 14B and turning on the analog switch 41, and a second step of detecting the voltage of the second internal block circuit 11B based on the voltage between the first external terminal 31 and the second external terminal 32.

[0083] The present embodiment can achieve the following advantages in addition to those achieved by the fourth embodiment.

[0084] (5-1) In the third test mode, both the first transistor 14A and the second transistor 14B are turned off, and the internal voltage of the second internal block circuit 11B is applied to the node N1. In this state, the internal voltage of the second internal block circuit 11B is not affected by the first resistor 12 and the second resistor 13, and thus can be accurately measured. Configuration examples of semiconductor devices 1a to 1e of the first to fifth embodiments

[0085] With reference to Fig.8 to 14, a power module 50 is described as an example of a specific configuration for implementing the semiconductor devices 1a to 1e of the first to fifth embodiments. The power module 50 can be used in various drive circuits, including an inverter circuit for driving a compressor in an air conditioner outdoor unit, an inverter circuit for driving a refrigerator compressor, and an inverter circuit for driving a fan. The drive circuit can drive, for example, a three-phase AC motor.

[0086] Fig. Figure 8 is a top view of the power module 50. Fig. 9 is a partial plan view of the power module 50, with a sealing resin 53 to be described later shown in phantom lines. Fig. 10 is a bottom view of the power module 50. Fig. 11 is a plan view of an upper switching driver 60U of the power module 50. Fig. 12 is a plan view of a lower switching control 60L of the power module 50. As shown in Fig.As shown in Figures 8 to 10, the power module 50 includes a plurality of leads 51, a cooling plate 52, and the sealing resin 53. The sealing resin 53 has a rectangular shape in plan view. In one example, the sealing resin 53 has a longitudinal length of 38 mm, a width of 24 mm (in a direction perpendicular to the longitudinal direction of the sealing resin 53), and a thickness of 3.5 mm. The plurality of leads 51 extend from the longitudinal sides of the sealing resin 53. Each lead 51 is substantially L-shaped as viewed from the direction perpendicular to the longitudinal direction. The cooling plate 52 is exposed on a surface of the sealing resin 53 facing the thickness direction. The exposed surface of the cooling plate 52 is rectangular in plan view, with the longitudinal direction coinciding with the longitudinal direction of the sealing resin 53.

[0087] Each of the plurality of terminals 51 extending from the sealing resin 53 has a terminal for connection to a circuit board (not shown) when the power module 50 is mounted on the circuit board. In one example, the terminals of the plurality of terminals 51 include a P, a U, a V, a W, a NU, a NV, a NW, a VBU, a VBV, a VBW, a HINU, a HINV, a HINW, a HVCC, a first GND, a LINU, a LINV, a LINW, an LVCC, a FO, a CIN, a second GND, a VOT, a first NC, and a second NC terminal.

[0088] As it is in Fig.As shown in Figure 13, the power module 50 includes a U-phase switching arm 54U, a V-phase switching arm 54V, a W-phase switching arm 54, and a control circuit 60 for controlling these switching arms 54U, 54V, and 54W. The U-phase switching arm 54U, the V-phase switching arm 54V, and the W-phase switching arm 54 are connected in parallel. The control circuit 60 includes an upper switching driver 60U and a lower switching driver 60L.

[0089] Each of the switching branches 54U, 54V, and 54W includes an upper switching element 55 and a lower switching element 56. The upper switching element 55 and the lower switching element 56 are connected in series. The upper switching element 55 has a first terminal to which the supply voltage is fed, a second terminal connected to the lower switching element 56, and a control terminal. The lower switching element 56 has a first terminal connected to the second terminal of the upper switching element 55, a second terminal connected to ground, and a control terminal. In one example, the upper switching element 55 and the lower switching element 56 may be IGBTs. The upper switching element 55 and the lower switching element 56 are each connected to a diode 57. In one example, diode 57 may be a fast recovery diode.

[0090] In the switching branches 54U, 54V, and 54W, the collectors of the respective upper switching elements 55 are connected to each other and electrically connected to the P terminal. The P terminal is used to supply the drive voltage VDD to the upper switching elements 55. In the U-phase switching branch 54U, the emitter of the upper switching element 55 and the collector of the lower switching element 56 are electrically connected to the U terminal. In addition, the emitter of the lower switching element 56 is electrically connected to the NU terminal. The U terminal is an output terminal of the U-phase switching branch 54U. In the V-phase switching branch 54V, the emitter of the upper switching element 55 and the collector of the lower switching element 56 are electrically connected to the V terminal. In addition, the emitter of the lower switching element 56 is electrically connected to the LV terminal. The V terminal is an output terminal of the V-phase switching branch 54V.In the W-phase switching branch 54W, the emitter of the upper switching element 55 and the collector of the lower switching element 56 are electrically connected to the W terminal. In addition, the emitter of the lower switching element 56 is electrically connected to the NW terminal. The W terminal is an output terminal of the W-phase switching branch 54W. The gate of each upper switching element 55 is connected to the upper switching driver 60U, and the gate of each lower switching element 56 is connected to the lower switching driver 60L.

[0091] As it is in Fig. 9 and Fig.As shown in Figure 11, the upper switching driver 60U is electrically connected to the VBU, VBV, VBW, HINU, HINV, HINW, HVCC, and the first GND terminals. The HVCC terminal is used to supply the supply voltage VCC to the upper switching driver 60U. The HINU terminal, the HINV terminal, and the HINW terminal receive a gate signal voltage applied from an external gate driver circuit (not shown). The upper switching driver 60U applies the received gate signal voltages to the gates of the upper switching elements 55.

[0092] As it is in Fig.As shown in Figure 11, the upper switch driver 60U includes pads for electrically connecting to the VBU, VBV, VBW, HINU, HINV, HINW, HVCC, and the first GND terminals. These pads may include pads arranged in an array along an outer edge of the upper switch driver 60U or pads arranged near the central portion of the upper switch driver 60U, in a plan view.

[0093] The upper switching driver 60U shown in the figure includes a plurality of second resistors 13 which, with reference to Fig. 1 to Fig. 2. In the Fig.In the example shown in Figure 11, the second resistors 13 are arranged along the direction in which the pads for connection to the HVCC terminal are arranged. Additionally, the second resistors 13 are vertically adjacent to the pads for the HINU, HINV, and HINW terminals, as viewed in that figure.

[0094] The lower switching driver 60L is electrically connected to the LINU, LINV, LINW, LVCC, FO, CIN, the second GND, and the VOT terminals. The LVCC terminal is used to supply the supply voltage VCC to the lower switching driver 60L. The LINU, LINV, and LINW terminals receive a gate signal voltage applied by an external gate driver circuit. The lower switching driver 60L applies the received gate signal voltages to the gates of the lower switching elements 56.

[0095] As it is in Fig.As shown in Figure 12, the lower switch driver 60L includes pads for electrically connecting to the LINU, LINV, LINW, LVCC, FO, CIN, second GND, and VOT terminals. The pads may include those disposed along an outer edge of the lower switch driver 60L.

[0096] The lower switching driver 60L shown in the figure includes a plurality of second resistors 13 which, with reference to Fig. 1 and Fig. 2. In the Fig. In the example shown in Figure 12, two of the second resistors 13 are arranged between the pads for the LINU and LINV terminals. Additionally, a second resistor 13 is arranged to the right of the pad for the LINW terminal, as viewed in that figure.

[0097] Fig.14 shows an exemplary configuration for implementing the upper switching driver 60U and the lower switching driver 60L, which drive the U-phase switching branch 54U. Fig. 14 shows an example of the circuits (hereinafter "control circuit 60X") of the upper switching driver 60U and the lower switching driver 60L for controlling the U-phase switching arm 54U.

[0098] As it is in Fig. As shown in Fig. 14, a portion of the control circuit 60X corresponding to the upper switching driver 60U includes, in order from the input (HINU terminal) to the output (HOU terminal), a first resistor 612, a second resistor 613, a transistor 614, a Schmitt trigger 62, a level shifter 63, a controller 64, a pulse generator 65, a level shifter 66, a filter circuit 67, an RS flip-flop circuit 68, and a driver 69.

[0099] The first resistor 612 and the second resistor 613 pull the HINU terminal down toward ground. Accordingly, when the HINU terminal is open, an upper input signal HINU, input from the gate drive circuit as a gate signal voltage, transitions to a low level (the logic level for turning off the upper switching element 55). This prevents the possibility of the upper switching element 55 being inadvertently turned on. The first resistor 612 and the second resistor 613 correspond to the first resistor 12 and the second resistor 13 of the semiconductor devices 1a to 1e, respectively.

[0100] Transistor 614 corresponds to transistor 14 of semiconductor devices 1a to 1e. Transistor 614 acts as a switch to connect and disconnect first resistor 612. The gate electrode of transistor 614 is connected to a test circuit 820, which will be described later.

[0101] Schmitt trigger 62 passes the high-level input signal HINU, which is input to the HINU terminal, to level shifter 63. Schmitt trigger 62 has a threshold voltage that exhibits a specific hysteresis. This configuration can improve noise resistance.

[0102] The level shifter 63 shifts the output signal of the Schmitt trigger 62 to the appropriate voltage level (VCC-GND) for input to the controller 64 and provides the resulting signal as an output.

[0103] The controller 64 controls whether the output signal of the level shifter 63 is to be passed to the pulse generator 65 or not (and thus whether the upper switching element 55 is to be activated or not) based on an error signal from an error protection unit or circuit 80 or an external signal from the FO terminal. In the example shown in the figure, the controller 64 includes an upper controller 64H and a lower controller 64L. The upper controller 64H is connected to the level shifter 63 and controls the upper switching element 55. In the power module 50 shown in Fig.As shown in Figures 8 to 12, the upper controller 64H is implemented as the upper switching driver 60U. In this example, an error signal from the error protection unit 80 to the controller 64 is input to the lower controller 64L, but not to the upper controller 64H. However, it should be noted that the present disclosure is not limited to such a configuration. In an alternative configuration, an error signal from the error protection unit 80 may be input to the upper controller 64H.

[0104] The pulse generator 65 generates pulse signals including an on-signal SON and an off-signal SOFF according to the output signal from the controller 64. More specifically, the pulse generator 65 changes the on-signal SON to a high level for a predetermined on-time period TON1 when triggered by a rising edge of the output signal from the controller 64. Furthermore, the pulse generator 65 changes the off-signal SOFF to a high level for a predetermined off-time period TON2 when triggered by a falling edge of an output signal from the controller 64. The output signal of the controller 64 (the signal responsive to the upper input signal HINU) as well as the on-time period TON1 and the off-time period TON2 are adjusted to prevent the on-signal SON and the off-signal SOFF from being high or high at the same time. That is,Assuming that the power module 50 is operating normally, one of the on signal SON and the off signal SOFF is high and the other is low.

[0105] The level shifter 66 shifts the level of the signals from a low-potential block, which includes the pulse generator 65, to a level for a high-potential block, which includes the filter circuit 67, the RS flip-flop circuit 68, and the driver 69. Specifically, the level shifter 66 receives pulses of the on signal SON and the off signal SOFF from the pulse generator 65 belonging to the low-potential block. The level shifter 66 shifts the level of each signal and outputs the resulting signals as a first shifted signal and a second shifted signal to the filter circuit 67. The high-potential block operates between the boost voltage VBU applied to the VBU terminal and a switching voltage VS applied to the U terminal.

[0106] The filter circuit 67 filters the first shifted signal and the second shifted signal received from the level shifter 66 and outputs the resulting signals to the RS flip-flop circuit 68.

[0107] The RS flip-flop circuit 68 has a set terminal (S terminal), a reset terminal (R terminal), and an output terminal (Q terminal). The S terminal receives a set signal SSET, which is the first shifted signal after filtering by the filter circuit 67. The R terminal receives a reset signal SRESET, which is the second shifted signal after filtering by the filter circuit 67. The Q terminal outputs an output signal SQ. The RS flip-flop circuit 68 changes the output signal SQ to a high level when triggered by a falling edge of the set signal SSET, and changes the output signal SQ to a low level when triggered by a falling edge of the reset signal SRESET. The set signal SSET and the reset signal SRESET are both input from the level shifter 66.

[0108] As it is in Fig.As shown in Figure 14, the driver 69 generates an upper output signal HOU responsive to the output signal of the RS flip-flop circuit 68 and outputs the upper output signal HOU to the gate of the upper switching element 55. The upper output signal HOU functions as the boost voltage VBU at the high level and as the switching voltage VS at the low level.

[0109] A portion of the control circuit 60X corresponding to the lower switching driver 60L includes, in the following order from the input (LINU terminal) to the output (LOU terminal), a first resistor 712, a second resistor 713, a transistor 714, a Schmitt trigger 72, a level shifter 73, a delay circuit 74, and a driver 75. In the present embodiment, the controller 64 of the upper switching driver 60U is provided between the level shifter 73 and the delay circuit 74. Note that the controller of the lower switching driver 60L may be provided separately from the controller 64 of the upper switching driver 60U. In this case, the controller of the lower switching driver 60L may be provided between the delay circuit 74 and the driver 75.This allows the controller to turn off the lower switching element 56 more quickly because the delay circuit 74 is not arranged in between.

[0110] The first resistor 712 and the second resistor 713 pull the LINU terminal down to ground. Accordingly, when the LINU terminal is open, a lower input signal LINU, input from the gate driver circuit as a gate signal voltage, is switched to a low level (the logic level for turning off the lower switching element 56). This prevents the possibility of the lower switching element 56 being inadvertently turned on. The first resistor 712 and the second resistor 713 correspond, respectively, to the first resistor 12 and the second resistor 13 of the semiconductor devices 1a to 1e. The resistance of the resistor 71 is equal to the combined resistance of the first resistor 12 and the second resistor 712, respectively, and the second resistor 13 and the second resistor 713, respectively.

[0111] Transistor 714 corresponds to transistor 14 of semiconductor devices 1a to 1e. Transistor 714 acts as a switch to connect and disconnect first resistor 712. The gate electrode of transistor 714 is connected to a test circuit 820, which will be described later.

[0112] Schmitt trigger 72 passes the lower input signal LINU, input to the LINU terminal, to level shifter 73. Schmitt trigger 72 has a threshold voltage that exhibits a specific hysteresis. This configuration can improve noise resistance.

[0113] The level shifter 73 shifts the output signal of the Schmitt trigger 72 to the appropriate voltage level (VCC-GND) for input to the controller 64 and outputs the resulting signal.

[0114] The controller 64 controls whether or not to pass the output signal of the delay circuit 74 to the driver 75 (and thus whether or not to activate the lower switching element 56) in response to an error signal from the error protection circuit 80 or in response to an external error signal from the FO terminal.

[0115] The lower controller 64L is connected to the level shifter 73 and controls the lower switching element 56. In the power module 50, which is Fig. 8 to 12, the lower controller 64L is implemented as the lower switching driver 60L.

[0116] The delay circuit 74 provides the output signal received from the controller 64 to the driver 75 with a predetermined time delay (corresponding to the circuit delay occurring in the pulse generator 65, the level shifter 66 and the RS flip-flop circuit 68 of the upper switching driver 60U).

[0117] Based on the output signal of the controller 64, which is delayed by the delay circuit 74, the driver 75 outputs a lower output signal LOU to the gate of the lower switching element 56. The lower output signal LOU functions as the supply voltage VCC at the high level and functions as the ground voltage VGND at the low level.

[0118] The fault protection circuit 80 includes a thermal shutdown (TSD) circuit 81, an undervoltage lockout (UVLO) circuit 82, a low-pass filter circuit 83, a short-circuit protection circuit 84, a fault signal generating circuit 86, a transistor 87, a Schmitt trigger 88, and a level shifter 89.

[0119] The thermal shutdown circuit 81 switches a thermal shutdown signal from the logic level indicating normal operation (e.g., low level) to the logic level indicating abnormal operation (e.g., high level) when the junction temperature at the lower switching driver of the power module 50 exceeds a predetermined (“preterminal”) threshold temperature.

[0120] The undervoltage lockout circuit 82 switches an undervoltage lockout signal from the logic level indicating normal operation (e.g., low level) to the logic level indicating abnormal operation (e.g., high level) when the source voltage VCC falls below a predetermined threshold voltage.

[0121] The low-pass filter circuit 83 is electrically connected to a detection terminal CIN outside the power module 50. The low-pass filter circuit 83 outputs a detected voltage CIN. The detected voltage CIN is supplied to the short-circuit protection circuit 84 via the CIN terminal.

[0122] The short-circuit protection circuit 84 switches a short-circuit protection signal from the logic level indicating normal operation (e.g., low level) to a logic level indicating abnormal operation (e.g., high level) when the detected voltage CIN exceeds a predetermined threshold voltage.

[0123] The error signal generation circuit 86 monitors the thermal shutdown signal from the thermal shutdown circuit 81, the undervoltage lockout signal from the undervoltage lockout circuit 82, the short-circuit protection signal from the short-circuit protection circuit 84, and the external error signal from the FO terminal. When a fault occurs in any of the thermal shutdown circuit 81, the undervoltage lockout circuit 82, and the short-circuit protection circuit 84, or upon receipt of an external error signal, the error signal generation circuit 86 changes the error signal from the logic level indicating normal operation (e.g., low level) to the logic level indicating abnormal operation (e.g., high level). The error signal generated by the error signal generation circuit 86 is output to the lower controller 64L in the controller 64.

[0124] In response to the error signal, the controller 64 may limit the current flowing through the upper switching element 55 and / or the lower switching element 56.

[0125] Transistor 87 serves as an open-drain output stage for outputting an external fault signal via the FO terminal. Transistor 87 may be, for example, an NMOSFET. While no fault occurs in power module 50, fault signal generation circuit 86 turns off transistor 87. As a result, the external fault signal is switched to a high level. On the other hand, when a fault is detected in power module 50, that is, when at least one of thermal shutdown circuit 81, undervoltage lockout circuit 82, and short-circuit protection circuit 84 detects a fault, fault signal generation circuit 86 turns on transistor 87. As a result, the external fault signal is switched to a low level.

[0126] The Schmitt trigger 88 passes an external error signal (e.g., an external error signal output from the FO terminal of another power module 50) received at the FO terminal to the level shifter 89. The Schmitt trigger 88 has a threshold voltage with a specific hysteresis. This configuration can improve noise resistance.

[0127] The level shifter 89 shifts the output signal of the Schmitt trigger 88 to the appropriate voltage level (VCC-GND) for input to the controller 64 and outputs the resulting signal.

[0128] A bootstrap circuit 58U includes a bootstrap diode 58BU and a bootstrap capacitor 59BU. The anode of the bootstrap diode 58BU is connected via a resistor 58R to the terminal to which the supply voltage VCC is applied. The bootstrap capacitor 59BU is connected between the cathode of the bootstrap diode 58BU and the emitter of the upper switching element 55. The bootstrap capacitor 59BU is electrically connected to the VBU terminal and the U terminal.

[0129] Test circuit 820 corresponds to test circuit 20 of semiconductor devices 1a to 1e. Test circuit 820 receives the output signal from short-circuit protection circuit 84 and the signal from the FO terminal. The output signal of test circuit 820 is input to the gate electrodes of transistors 614 and 714.

[0130] The bootstrap circuit 58U generates a boost voltage VB (drive voltage for the high-potential block including driver 69) at the connection node (VB terminal) between the bootstrap diode 58BU and the bootstrap capacitor 59BU. Resistor 58R limits the current supplied from an external power source to the bootstrap diode 58BU via the HVCC terminal. This limits the charging current supplied to the bootstrap capacitor 59BU.

[0131] When the upper switching element 55 is turned off and the lower switching element 56 is turned on, the switching voltage VS at the low level (GND) appears at the U terminal. In this state, the electric current flows from the terminal to which the power supply voltage VCC is applied through the bootstrap diode 58BU, the bootstrap capacitor 59BU, and the lower switching element 56. Consequently, the bootstrap capacitor 59BU, which is provided between the VBU terminal and the U terminal, is charged. At this stage or in this state, the boost voltage VB appearing at the VBU terminal (ie, the charging voltage of the bootstrap capacitor 59BU) is equal to the voltage value calculated by subtracting the forward bias voltage drop Vf of the bootstrap diode 58Vf or 58BU from the supply voltage VCC (VCC - Vf).

[0132] On the other hand, when the upper switching element 55 is turned on and the lower switching element 56 is turned off while the bootstrap capacitor 59BU is being charged, the switching voltage VS is raised from the low level (GND) to the high level (HV). The boost voltage VB is raised from the high level (HV) of the switching voltage VS to a voltage level higher (= HV + VCC - Vf) by the value corresponding to the charging voltage of the bootstrap capacitor 59BU. Therefore, the boost voltage VB can be suitably used as the drive voltage of the high-potential block (RS flip-flop circuit 68 and driver 69) or the level shifter 66 to control the on / off operation (specifically, power-on control) of the upper switching element 55. Configuration example of the first test circuit (test circuit) and second test circuit

[0133] With reference to Fig. 15 and Fig.16, a configuration example of the first test circuit (test circuit) and a configuration example of the second test circuit used in the semiconductor devices 1a to 1e will be described below.

[0134] Fig. 15 shows an exemplary configuration of the first test circuit 20A (test circuit 20). The test circuit 20 includes a first voltage dividing resistor 21A, a second voltage dividing resistor 22A, a bipolar transistor 23Q, a transistor 23M, a resistor 24, a NOT circuit 25, a filter circuit 26, and a latch circuit 28. The test circuit 20 removes noise from the test signal applied to the third external terminal 33 and outputs the resulting signal to the gate of the first transistor 14A (transistor 14). As shown in Fig.As shown in Figure 15, an example of the third external terminal 33 is the FO terminal, to which an external error signal is input from outside the semiconductor devices 1a to 1e. The bipolar transistor 23Q may be, for example, an NPN transistor. The transistor 23M may be, for example, an NMOSFET.

[0135] Both the first voltage dividing resistor 21A and the second voltage dividing resistor 22A are connected in series to the transistor 23M between the wiring 27A connected to the third external terminal 33 and the second wiring 18. More specifically, a first terminal of the first voltage dividing resistor 21A is connected to the wiring 27A, and a second terminal of the first voltage dividing resistor 21A is connected to the drain of the transistor 23M. Furthermore, a first terminal of the second voltage dividing resistor 22A is connected to the source of the transistor 23M, and a second terminal of the second voltage dividing resistor 22A is connected to the second wiring 18. As in the transistor 87 shown in Fig.As shown in Figure 14, the gate of transistor 23M is connected to the error signal generating circuit 86. Accordingly, transistor 23M is turned on and off by the error signal generating circuit 86. In the test mode, a test signal is applied to the CIN terminal, thus turning on transistor 23M.

[0136] The base of bipolar transistor 23Q is connected to node N4 between the second terminal of first voltage dividing resistor 21A and the first terminal of second voltage dividing resistor 22A. Bipolar transistor 23Q and resistor 24 are connected in series between third wiring 19 and second wiring 18. More specifically, a first terminal of resistor 24 is connected to third wiring 19, and a second terminal of resistor 24 is connected to the collector of bipolar transistor 23Q. The emitter of bipolar transistor 23Q is connected to second wiring 18.

[0137] The input terminal of NOT circuit 25 is connected to node N5, which connects the second terminal of resistor 24 and the collector of bipolar transistor 23Q. The output terminal of NOT circuit 25 is connected to filter circuit 26. Filter circuit 26 can be, for example, a low-pass filter.

[0138] The output terminal of filter circuit 26 is connected to latch circuit 28. Latch circuit 28 is connected to the CIN terminal, to which the detected voltage CIN is input. The output terminal of latch circuit 28 is connected to the gate of transistor 14.

[0139] Fig.16 shows an exemplary configuration of the second test circuit 20B. The second test circuit 20B includes a first voltage divider resistor 21B, a second voltage divider resistor 22B, a filter circuit 26, and a comparator 29. The second test circuit 20B removes noise from the test signal applied to the fifth external terminal 35 and outputs the resulting signal to the gate of the second transistor 14B. In one example, the fifth external terminal 35 may be a LINW terminal, from which the gate signal voltage is applied to the lower switching element 56 of the W-phase switching branch 54W in the semiconductor devices 1a to 1e.

[0140] The first voltage divider resistor 21B and the second voltage divider resistor 22B are connected in series between the wiring 27B connected to the fifth external terminal 35 and the second wiring 18. More specifically, a first terminal of the first voltage divider resistor 21B is connected to the wiring 27B, and a second terminal of the first voltage divider resistor 21B is connected to a first terminal of the second voltage divider resistor 22B. A second terminal of the second voltage divider resistor 22B is connected to the second wiring 18.

[0141] A first input terminal of comparator 29 is connected to node N6, which connects the second terminal of first voltage divider resistor 21B and the first terminal of second voltage divider resistor 22B. A second input terminal of comparator 29 receives the reference voltage. The output terminal of comparator 29 is connected to filter circuit 26. The output terminal of filter circuit 26 is connected to the gate of second transistor 14B.

[0142] As described above, the first test circuit 20A (test circuit 20) and the second test circuit 20B are connected to the exit terminals of the semiconductor devices 1a to 1e. This means that an additional resistance element can be added, particularly for product identification, without requiring the provision of additional external terminals solely for product identification, and thus without an undesirable increase in size. Variations

[0143] The embodiments have been described merely for the purpose of illustrating possible implementations of the semiconductor device and the method for identifying a semiconductor device according to the present disclosure and are not intended to impose any limitations. The semiconductor device and the method for identifying a semiconductor device according to the present disclosure may be implemented by any of the following variations of the embodiments described above or by any combination of two or more variations that do not conflict with each other.

[0144] The configuration of the semiconductor device 1b according to the second embodiment can be used in any of the third, fourth and fifth embodiments.

[0145] For example, the semiconductor device 1b of the second embodiment may have a number N of second external terminals 32 instead of a single second external terminal 32.

[0146] The third embodiment can be equipped with separate test circuits, one for controlling the switching on and off of transistor 14, and another for the analog switch 41. This makes it possible to control the switching of transistor 14 and analog switch 41 separately.

[0147] In the fourth and fifth embodiments, a test signal for turning off the second transistor 14B in the normal mode can be input to the fifth external terminal 35. In this case, the first resistor 12 provides a resistance value that matches the predetermined resistance value of the semiconductor devices 1d and 1e in the normal mode.

[0148] In any embodiment, the test circuit 20 (first test circuit 20A) may be any other circuit that switches the transistor 14 (first transistor 14A) on and off, and is not limited to the circuit shown in Fig. 2. In addition, the second test circuit 20B may be any other circuit that switches the second transistor 14B on and off, and is not limited to the circuit configuration shown in Fig. 2. The test circuit 20 (first test circuit 20A) and the second test circuit 20B can be modified as shown in Fig. 17 or Fig. 18 is shown.

[0149] As it is in Fig.As shown in Figure 17, the test circuit 20 (first test circuit 20A) and the second test circuit 20B can be modified to include a Schmitt trigger 90 and a filter circuit 91. The Schmitt trigger 90 supplies a test signal from the third external terminal 33 to the control terminal of the transistor 14. The Schmitt trigger 90 has a threshold voltage with a specific hysteresis. This configuration can improve noise resistance. The output terminal of the Schmitt trigger 90 is connected to the filter circuit 91. The filter circuit 91 may be, for example, a low-pass filter (LPF). Accordingly, the test signal applied to the third external terminal 33 is supplied to remove noise and to the control terminal of the transistor 14.

[0150] As it is in Fig.As shown in Figure 18, the test circuit 20 (first test circuit 20A) and the second test circuit 20B can be modified to include an amplifier circuit 92 and a filter circuit 93. The amplifier circuit 92 has a first input terminal connected to the third external terminal 33. The amplifier circuit 92 receives a reference voltage applied to a second input terminal. The output terminal of the amplifier circuit 92 is connected to the filter circuit 93. The filter circuit 93 may be, for example, a low-pass filter. Accordingly, the test signal applied to the third external terminal 33 is amplified by the amplifier circuit 92, and then noise is removed by the filter circuit 93. The resulting signal is supplied to the control terminal of the transistor 14.

[0151] In the above-described embodiments, the semiconductor devices 1a to 1e may be provided with an internal control circuit that controls the turning on and off of the transistor 14 (first transistor 14A) and the second transistor 14B. Then, the test circuit 20 (first test circuit 20A) and the second test circuit 20B may be omitted. In this case, the third and fifth embodiments may further be provided with an analog switch changeover circuit (not shown) for controlling the turning on and off of the analog switch 41.

[0152] The third and fifth embodiments may be configured to measure the internal voltages of a plurality of circuits in the second internal block circuit 11B. In this case, each of the plurality of circuits may be equipped with an analog switch 41 that operates according to the measured value of the internal voltage of the circuit. The individual analog switches 41 may be controlled separately to enable the internal voltages of the respective circuits to be measured. Fig.19 shows a configuration example of the semiconductor device 1c of the third embodiment, which is capable of measuring the internal voltages of a plurality of circuits in the second internal block circuit 11B. The second internal block circuit 11B includes a temperature measuring circuit 40, an overvoltage protection circuit 94, a thermal shutdown circuit 95, an undervoltage lockout circuit 96, an internal reference voltage generation circuit 97, and the logic circuit 98. An analog switch 41 is provided for each of the temperature measuring circuit 40, the overvoltage protection circuit 94, the thermal shutdown circuit 95, the undervoltage lockout circuit 96, the reference voltage generation circuit 97, and the logic circuit 98. Each analog switch 41 has a second terminal connected to the node N1 between the first resistor 12 and the transistor 14.Another analog switch 41 is provided for the test circuit 20 for measuring the internal voltage of the test circuit 20. This analog switch 41 has a second terminal connected to the node N1.

[0153] Turning on and off of the analog switches 41 is controlled by the analog switch switching circuit 99. For example, the analog switch switching circuit 99 can be provided within the semiconductor device 1c. The analog switch switching circuit 99 is connected to a sixth terminal 36. The analog switch switching circuit 99 outputs a control signal to the inverting control terminals of the respective analog switches 41. Alternatively, the analog switch switching circuit 99 can be provided outside the semiconductor device 1c.

[0154] When the semiconductor device 1c of this modification operates in the third test mode, the analog switch switching circuit 99 turns on the analog switch 41 of the circuit selected for measurement and turns off the analog switches 41 of all other circuits of the second internal block circuit 1B. In this way, the internal voltage of the selected circuit can be measured by measuring the voltage at the first external terminal 31 and the second external terminal 32. The semiconductor device 1e can be modified in the same way.

[0155] Clause 1. Semiconductor device with: a first external terminal to which a first voltage is to be applied; a second external terminal to which a second voltage is to be applied; a third external terminal; a first wiring connected to the first external terminal; a second wiring connected to the second external terminal; a first internal block circuit connected to the first wiring; a first resistor and a first switching element connected in series between the first wiring and the second wiring; and a second resistor connected between the first wiring and the second wiring, wherein the first switching element switches on or off based on a test signal to be applied to the third external terminal.

[0156] Clause 2. The semiconductor device according to clause 1, wherein the first external terminal is an input terminal to which a control signal for controlling the first internal block circuit is input.

[0157] Clause 3. A semiconductor device according to clause 1 or 2, wherein a resistance value of the second resistor is greater than a resistance value of the first resistor.

[0158] Clause 4. A semiconductor device according to any one of clauses 1 to 3, wherein the first switching element has a control terminal electrically connected to an external sensor terminal that generates an external output upon detection of a fault in the semiconductor device.

[0159] Clause 5. The semiconductor device according to any one of clauses 1 to 4, wherein a length of the first wiring between the first external terminal and the first resistor is smaller than a length of the first wiring between the first external terminal and the second resistor.

[0160] Clause 6. The semiconductor device according to any one of clauses 1 to 5, further comprising a test circuit that turns the first switching element on and off based on the test signal, and that turns the first switching element on based on a supply of a drive voltage.

[0161] Clause 7. A semiconductor device according to any one of clauses 1 to 6, further comprising: a switching unit connected to a node between the first resistor and the first switching element; and a second internal block circuit that is electrically connected to the switching unit.

[0162] Clause 8. A semiconductor device according to Clause 7, wherein the second internal block circuit comprises a temperature measuring circuit.

[0163] Clause 9. A semiconductor device according to clause 7 or 8, further comprising a test circuit that switches both the first switching element and the switching unit on and off based on the test signal, the test circuit comprising: a first test mode for turning on the first switching element and turning off the switching unit based on the test signal; a second test mode for switching off the first switching element and switching on the switching unit based on the test signal; and a normal mode for turning on the first switching element and turning off the switching unit based on a supply of a drive voltage.

[0164] Clause 10. The semiconductor device according to any one of clauses 1 to 8, further comprising: a second switching element connected between the second resistor and the second wiring.

[0165] Clause 11. The semiconductor device according to Clause 10, wherein the second switching element has a control terminal electrically connected to an external terminal other than any one of the external sensor terminal that generates an external output upon detection of a fault in the semiconductor device, the first external terminal, and the second external terminal.

[0166] Clause 12. Semiconductor device according to Clause 10 or 11, further comprising: a first test circuit that switches the first switching element on and off based on the test signal and that switches the first switching element on based on a supply of a drive voltage; and a second test circuit that switches the second switching element on and off based on the test signal and that switches the second switching element on or off based on a supply of a drive voltage.

[0167] Clause 13. Semiconductor component according to Clause 12, further with a switching unit connected to a node between the first resistor and the first switching element; and a second internal block circuit electrically connected to the switching unit, wherein the first test circuit or the second test circuit switches the switching unit on and off based on the test signal, wherein the semiconductor device has a normal mode selected based on a supply of a drive voltage, and a first test mode, a second test mode and a third test mode selected based on the test signal, wherein in the normal mode the first switching element is switched on, the second switching element is switched on or off and the switching unit is switched off, wherein in the first test mode the first switching element is switched off, the second switching element is switched on and the switching unit is switched off, wherein in the second test mode both the first switching element and the second switching element are switched off and the switching unit is switched on, and wherein in the third test mode both the first switching element, the second switching element and the switching unit are switched off.

[0168] Clause 14. A semiconductor device according to any one of clauses 1 to 13, wherein the first internal block circuit includes a power transistor.

[0169] Clause 15. A semiconductor device according to any one of clauses 1 to 14, wherein a plurality of sets are provided, each including the first external terminal, the second external terminal, the first wiring, the second wiring, the first internal block circuit, the first resistor, the second resistor and the first switching element.

[0170] Clause 16. A semiconductor device according to clause 15, wherein at least one of the plurality of first resistors has a different resistance value compared to a resistance value or resistance values ​​of the remaining first resistors, and wherein at least one of the plurality of second resistors has a different resistance value compared to a resistance value or resistance values ​​of the remaining second resistors.

[0171] Clause 17. Semiconductor device with: a first external terminal to which a first voltage is to be applied; a second external terminal to which a second voltage is to be applied; a third external terminal; a first wiring connected to the first external terminal; a second wiring connected to the second external terminal; a first internal block circuit connected to the first wiring; a first resistor and a first switching element connected in series between the first wiring and the second wiring; and a second resistor connected between the first wiring and the second wiring.

[0172] Clause 18. A method for product identification of a semiconductor device according to any one of clauses 1 to 8 and 17, the method comprising: a first step of switching off the first switching element; and a second step of detecting a resistance value of the second resistor between the first external terminal and the second external terminal.

[0173] Clause 19. A method for product identification of a semiconductor device according to any one of clauses 7 to 9, the method comprising: a first step of switching off the first switching element and switching on the switching unit; and a second step of detecting a voltage of the second internal block circuit based on a voltage between the first external terminal and the second external terminal.

[0174] Clause 20. A method for product identification of a semiconductor device according to any one of clauses 10 to 13, the method comprising: a first step of turning off the first switching element and turning on the second switching element; and a second step of detecting a resistance value of the second resistor between the first external terminal and the second external terminal.

[0175] Clause 21. A method for product identification of a semiconductor device according to any one of clauses 10 to 13, the semiconductor device further comprising: a switching unit connected to a node between the first resistor and the first switching element; and a second internal block circuit electrically connected to the switching unit, the method comprising: a first step of turning off both the first switching element and the second switching element and turning on the switching unit; and a second step of detecting a voltage of the second internal block circuit based on a voltage between the first external terminal and the second external terminal.

Claims

[1] Semiconductor component with: a first external terminal (31) to which a first voltage (IN) is to be applied; a second external terminal (32) to which a second voltage (GND) is to be applied; a third external terminal (33); a fourth external terminal (34) to which a supply voltage (VCC) is to be applied; a first wiring (17) connected to the first external terminal; a second wiring (18) connected to the second external terminal; a first internal block circuit (11) connected to the first wiring (17); a first resistor (12) and a first switching element (14) connected in series between the first wiring (17) and the second wiring (18); a second resistor (13) connected between the first wiring (17) and the second wiring (18); and a test circuit (20) which controls the first switching element (14), wherein the first switching element (14) switches on or off based on a test signal to be applied to the third external terminal (33), wherein the first external terminal (31) is an input terminal to which a control signal for controlling the first internal block circuit (11) is input, and wherein the test circuit (20) controls the first switching element (14) by inverting and transmitting the test signal from the third external terminal (33) when the supply voltage is supplied from the fourth external terminal (34). [2] The semiconductor device according to claim 1, wherein a resistance value of the second resistor is greater than a resistance value of the first resistor. [3] A semiconductor device according to claim 1 or 2, wherein the first switching element has a control terminal electrically connected to an external sensor terminal that generates an external output upon detection of a fault in the semiconductor device. [4] The semiconductor device according to any one of claims 1 to 3, wherein a length of the first wiring between the first external terminal and the first resistor is smaller than a length of the first wiring between the first external terminal and the second resistor. [5] A semiconductor device according to any one of claims 1 to 4, further comprising: a switching unit connected to a node between the first resistor and the first switching element; and a second internal block circuit that is electrically connected to the switching unit. [6] A semiconductor device according to claim 5, wherein the second internal block circuit comprises a temperature measuring circuit. [7] A semiconductor device according to claim 5 or 6, further comprising a test circuit that switches both the first switching element and the switching unit on and off based on the test signal, the test circuit comprising: a first test mode for turning on the first switching element and turning off the switching unit based on the test signal; a second test mode for switching off the first switching element and switching on the switching unit based on the test signal; and a normal mode for turning on the first switching element and turning off the switching unit based on a supply of a drive voltage. [8] A semiconductor device according to any one of claims 1 to 6, further comprising: a second switching element connected between the second resistor and the second wiring. [9] The semiconductor device according to claim 8, wherein the second switching element has a control terminal electrically connected to an external terminal other than any one of the external sensor terminal that generates an external output upon detection of a fault in the semiconductor device, the first external terminal, and the second external terminal. [10] A semiconductor device according to claim 8 or 9, further comprising: a first test circuit that switches the first switching element on and off based on the test signal and that switches the first switching element on based on a supply of a drive voltage; and a second test circuit that switches the second switching element on and off based on the test signal and that switches the second switching element on or off based on a supply of a drive voltage. [11] A semiconductor device according to claim 10, further comprising a switching unit connected to a node between the first resistor and the first switching element; and a second internal block circuit electrically connected to the switching unit, wherein the first test circuit or the second test circuit switches the switching unit on and off based on the test signal, wherein the semiconductor device has a normal mode selected based on a supply of a drive voltage, and a first test mode, a second test mode and a third test mode selected based on the test signal, wherein in the normal mode the first switching element is switched on, the second switching element is switched on or off and the switching unit is switched off, wherein in the first test mode the first switching element is switched off, the second switching element is switched on and the switching unit is switched off, wherein in the second test mode both the first switching element and the second switching element are switched off and the switching unit is switched on, and wherein in the third test mode both the first switching element, the second switching element and the switching unit are switched off. [12] A semiconductor device according to any one of claims 1 to 11, wherein the first internal block circuit includes a power transistor. [13] A semiconductor device according to any one of claims 1 to 12, wherein a plurality of sets are provided each including the first external terminal, the second external terminal, the first wiring, the second wiring, the first internal block circuit, the first resistor, the second resistor and the first switching element. [14] The semiconductor device of claim 13, wherein at least one of the plurality of first resistors has a different resistance value compared to a resistance value of the remaining first resistors, and wherein at least one of the plurality of second resistors has a different resistance value compared to a resistance value of the remaining second resistors. [15] A method for product identification of a semiconductor device according to any one of claims 1 to 6, the method comprising: a first step of switching off the first switching element; and a second step of detecting a resistance value of the second resistor between the first external terminal and the second external terminal. [16] A method for product identification of a semiconductor device according to any one of claims 5 to 7, the method comprising: a first step of switching off the first switching element and switching on the switching unit; and a second step of detecting a voltage of the second internal block circuit based on a voltage between the first external terminal and the second external terminal. [17] A method for product identification of a semiconductor device according to any one of claims 8 to 11, the method comprising: a first step of turning off the first switching element and turning on the second switching element; and a second step of detecting a resistance value of the second resistor between the first external terminal and the second external terminal. [18] A method for product identification of a semiconductor device according to any one of claims 8 to 11, wherein the semiconductor device further comprises: a switching unit connected to a node between the first resistor and the first switching element; and a second internal block circuit electrically connected to the switching unit, the method comprising: a first step of turning off both the first switching element and the second switching element and turning on the switching unit; and a second step of detecting a voltage of the second internal block circuit based on a voltage between the first external terminal and the second external terminal.

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