SEMICONDUCTOR DEVICE

Abstract

Semiconductor device (10, 10', 70, 80, 91a, 91b), comprising: an active region (1, 101) arranged on a semiconductor substrate (7, 107); and a termination region (6, 106) which is arranged in the semiconductor substrate (7, 107) and surrounds an edge of the active region (1, 101), wherein the active area (1,101) comprises: a first cell area (2, 102) in which a first bipolar transistor (20) with insulated gate electrode (28) is arranged, and a second cell area (3, 103) arranged next to the first cell area (2, 102), wherein the second cell area (3, 103) comprises: a first region in which a second bipolar transistor (30) with an insulated gate electrode (38) is arranged, wherein the second bipolar transistor (30) with an insulated gate electrode (38) has a smaller arithmetic area than the first bipolar transistor (20) with an insulated gate electrode, and a second area that separates the first cell area (2, 102) and the first area, wherein The second area includes: a first gate electrode layer (13) arranged over an oxide film on the semiconductor substrate (7, 107) and having an installation resistance area (17), and an emitter electrode (52, 152) of the second bipolar transistor (30) with an insulated gate electrode (38) which is arranged over an insulating intermediate layer film (44, 144) on the first gate electrode layer (13), wherein the termination region (6, 106) comprises a gate runner (15, 115) arranged above the oxide film on the semiconductor substrate (7, 107), wherein the gate runner (15, 115) surrounds an edge of the active region (1, 101) and is connected to a plurality of first gate electrodes (28) of the first insulated-gate bipolar transistor, wherein the first gate electrode layer (13) comprises: a first gate electrode layer section (17a) which is electrically connected to a plurality of second gate electrodes (38) of the second bipolar transistor (30) with insulated gate electrode (38), and a second gate electrode layer section (17b) in the second region, which has a planar shape extending from the first gate electrode layer section (17a) to the gate runner (15, 115), wherein the second gate electrode layer section (17b) electrically connects the first gate electrode layer section (17a) and the gate runner (15, 115), wherein the installation resistance area (17) comprises the first gate electrode layer section (17a) and the second gate electrode layer section (17b), and the second gate electrode layer section (17b) has a resistance value in the range of 10 Ω to 5000 Ω.

Description

TECHNICAL AREA

[0001] The present invention relates to a semiconductor device. STATE OF THE ART

[0002] In IPMs (Intelligent Power Modules), a circuit area for protecting the main IGBT is provided on a single semiconductor substrate with an IGBT (bipolar transistor with insulated gate electrode, hereinafter referred to as the main IGBT) as the main semiconductor element. The circuit area for protecting the main IGBT is typically a circuit area that detects an overcurrent (OC) (see, for example, patent document 1).

[0003] The current-sensing region is an IGBT (hereinafter referred to as the measuring IGBT) comprising unit cells (functional units of an element), each with a similar structure to the unit cells of the main IGBT, but with fewer unit cells than the main IGBT (e.g., one-thousandth of the number of unit cells in the main IGBT). The measuring IGBT is arranged in parallel to the main IGBT within a predetermined region of the semiconductor substrate. When the main IGBT is switched on, the collector-emitter current flowing through the measuring IGBT is determined by the ratio of the number of unit cells in the measuring IGBT to the number of unit cells in the main IGBT, such that the current flowing through the measuring IGBT is smaller than the collector-emitter current flowing through the main IGBT.

[0004] The collector-emitter current flowing through the measuring IGBT is detected by a control IC (integrated circuit) connected via a wire to a main electrode of the measuring IGBT. Based on the amount of collector-emitter current flowing through the measuring IGBT, the control IC determines whether an overcurrent is flowing between the collector and emitter of the main IGBT. The control IC has an overcurrent protection function to block the collector-emitter current of the main IGBT by switching off gates of the main IGBT and suppressing its operation if an overcurrent is detected between the collector and emitter of the main IGBT.

[0005] The structure of a conventional semiconductor device is described. Fig. Figure 28 is a top view of an arrangement of the conventional semiconductor device, seen from a front side of a semiconductor substrate. Fig. 29 and Fig. Figure 30 are enlarged top views near the current measuring area in Fig. 28. In Fig. 28 to 30 a contact hole 145 a gate runner metal layer and a gate runner 115, as well as a contact hole 146 of an extended section of the gate runner metal layer 53 an extended section 116 of the gate runner 115 are indicated by a thick line.

[0006] Furthermore, in Fig. Figures 28 to 30 do not show the gate runner metal layer 5 and the extended section of the gate runner metal layer. Fig. Numbers 29 to 30 show the same area in Fig. 28, however, the hatched sections differ. In Fig. 28 and Fig. 29 are p + -like isolation areas 141, 142 are indicated by hatching. In Fig. 30 are a scanning polysilicon layer 113 containing polysilicon (Poly-Si), and the gate runner 115 is indicated by hatching. Fig. 31 is a sectional view of the structure along the section line AA-AA' in Fig. 29 and Fig. 30.

[0007] One in Fig. The conventional semiconductor device 110 shown in Figures 28 to 31 comprises a main IGBT 120 and a sensing IGBT 130, which serves as a current sensing region and detects a current flowing in the main IGBT 120. These devices are arranged on a semiconductor substrate (semiconductor chip) 107. The main IGBT 120 and the sensing IGBT 130 are gate-trench type IGBTs with identical structures. An active region 101, comprising first and second cell regions 102 and 103, and an edge termination region 106, which surrounds an edge of the active region 101, are arranged on the semiconductor substrate 107.

[0008] In the first cell area 102 there is a p + -like area (hereinafter referred to as p) +-like insulating region) 141 is arranged in the semiconductor substrate 107 such that it surrounds an edge of the first cell region 102. In a region of the first cell region 102, surrounded by the p + The unit cells of the main IGBT 120 are arranged in an insulating region 141. The first cell region 102 is separated from regions that differ from the first cell region 102 by a pn junction between the p + -like insulating area and an n - -like drift region 121 isolated. The first cell region 102 is a section of the active region 101 without the second cell region 103 and occupies a large part of the surface of the active region 101.

[0009] Furthermore, in the first cell region 102, an emitter electrode 151 of the main IGBT 120 is arranged on a front surface of the semiconductor substrate 107. The emitter electrode 151 of the main IGBT 120 covers substantially the entire area of ​​the first cell region 102. An emitter terminal 111 is configured as a section of the emitter electrode 151. A gate terminal 112 is arranged near a boundary between the first cell region 102 and the edge termination region 106. The gate terminal 112 is connected to the gate runner 115. Unit cells of the measuring IGBT 130 are arranged in the second cell region 103.

[0010] The second cell area 103 comprises a detection area 104, in which the unit cells of the measuring IGBT 130 are arranged, and an extraction area 105 for extracting the hole current. In the extraction area 105, the p +-like insulating areas 141, 142 are each optionally arranged in the semiconductor substrate 107. The p + The -like insulating area 141 surrounds an edge of the detection area 104. The p + -like insulating area 142 is separated from the p + -like insulating area 141 between the p + The detection area 104 is arranged in a -like isolation region 141 and the detection region 104 and surrounds a boundary of the detection region 104. The detection region 104 of the second cell region 103 is separated from regions that differ from the detection region 104 by a pn junction between the p + -like isolation area 142 and the n - -like drift area 121 isolated.

[0011] In the extraction area 105, the scanning polysilicon layer 113 is arranged on the front surface of the semiconductor substrate 107 above a field oxide layer 143. The scanning polysilicon layer 113 surrounds an edge of the detection area 104. The scanning polysilicon layer 113 serves as an extended section 116 of the gate runner 115 described below. The capacitance formed by the scanning polysilicon layer 113, the insulating interlayer film 144, and the emitter electrode 152 of the measuring IGBT 130 is part of the gate-emitter capacitance (CGE) of the measuring IGBT 130. The emitter electrode 152 of the measuring IGBT 130 is arranged such that it spans substantially the entire area of ​​the second cell region 103 and extends onto the scanning polysilicon layer 113 with the insulating interlayer film 144 in between.

[0012] A scanning emitter connection surface 114, formed by a section of the emitter electrode 152, is located in the extraction region 105. The polysilicon-containing gate runner 115 is located in the edge termination region 106 and surrounds an edge of the active region 101. The gate runner 115 also includes a section (hereinafter referred to as the extended section) 116 that extends along an outer edge of the second cell region 103 to the second cell region 103. The extended section 116 of the gate runner 115 surrounds an edge of the second cell region 103. A single polysilicon layer formed from the gate runner 115 and the extended section 116 of the gate runner 115 extends along an outer edge of the first cell region 102 and surrounds an edge of the first cell region 102.

[0013] In Fig. 29 and Fig. In section 30, an inner edge (edges closest to the detection area 104) of the scanning polysilicon layer 113 is indicated by a dashed line and reference numeral 113a. An inner edge (edges closest to the active area 101) of the gate runner 115, the inner edge surrounding an edge of the active area 101, and an outer edge (edges closest to the ends of the semiconductor substrate 107) of the gate runner 115 are each indicated by dashed lines and reference numerals 115a and 115b, respectively. Edges of the extended section 116 of the gate runner 115 and the edges of the active area 10 are marked with reference numeral 116a. The scanning polysilicon layer 113 is integrally formed with the gate runner 115 and the extended section 116 of the gate runner 115. The gate runner 115 is electrically connected to a gate metal runner 153 via the contact hole 146 formed in the insulating interlayer film 14.Gate electrodes 128, 138 of the main IGBT 120 and the measuring IGBT 130 are electrically connected to the gate runner 115.

[0014] As a conventional semiconductor device, a trench-gate type IGBT was also proposed, wherein the trench-gate type IGBT has emitter-contact trenches between gate trenches in which gate electrodes are embedded, the emitter-contact trenches penetrating an emitter region and a base region and reaching a drift region. In the trench-gate type IGBT, an emitter electrode and a semiconductor region are electrically connected via a conductive layer embedded in the emitter-contact trenches (see, for example, Patent Document 2). In Patent Document 2, the effective gate width is smaller than that of a trench-gate type IGBT without emitter-contact trenches, resulting in a small collector-emitter current and controlling a saturation current.

[0015] Publication US 2017 / 0111037A1 describes a semiconductor device with multiple semiconductor switching elements arranged on a single semiconductor substrate. This substrate consists of a semiconductor material with a larger band gap than silicon. On the front face of the substrate, several electrolytic pads are placed in a predefined arrangement, with each pad electrically connected to the switching elements. A plated layer connects multiple lead pins to all electrolytic pads via solder joints to bring the voltages to the outside.

[0016] Publication US 2018 / 0269296A1 discloses a semiconductor device with a semiconductor body having a first and an opposing second surface. A transistor cell structure is integrated within the semiconductor body. A gate contact structure comprises a gate lead electrically connected to a gate electrode layer of the transistor cell, and a gate pad coupled to the gate lead. A gate resistor structure is positioned between the gate pad and the gate electrode layer. The electrical resistance of this resistor structure is greater than that of the gate electrode layer.

[0017] Publication US 2010 / 0001785A1 discloses an arrangement for temperature measurement comprising a power semiconductor transistor and a component with two connecting leads, which is integrated into the semiconductor body and thermally coupled to the transistor. The component is connected to the control and load electrodes of the transistor and has a temperature-dependent resistance used to determine the internal temperature of the transistor. Patent document 1: Japanese publication no. 2015-179705 Patent document 2: Japanese patent no. 5025071 DESCRIPTION OF THE INVENTION TASK TO BE SOLVED BY THE INVENTION

[0018] During package assembly to mount the semiconductor substrate 107 onto a base substrate, or during product assembly to install the package into a product, electrostatic discharge (ESD) occurs due to contact or close proximity between conductive objects (between a person and components or between components). The occupied area of ​​the measurement IGBT 130 is small compared to the arithmetic area of ​​the semiconductor substrate 107, and therefore the gate-emitter capacitance CGE is extremely low and the ESD tolerance is low. If a gate voltage Vg (e.g., approximately 80 V), which is at least equal to the breakdown voltage between the gates and emitters in the measurement IGBT 130, is applied, dielectric breakdown of the gate insulating film 137 occurs in the gate grooves of the measurement IGBT 130.

[0019] Meanwhile, the gate-emitter capacitance CGE of the measuring IGBT 130 increases, thereby reducing the ratio of the gate voltage Vg to the electric charge Q of the gate insulating film 137 of the measuring IGBT 130 (Q = CGE × Vg), which can increase the ESD tolerance of the measuring IGBT 130. However, even when the gate-emitter capacitance CGE of the measuring IGBT 130 is increased, the measurement voltage applied between the collector and the emitter of the measuring IGBT 130 still rises transiently during a switching transition time. This transient increase in the measurement voltage occurs because the gate current Ig flowing into the gate of the measuring IGBT 130 during the switching transition time is large.

[0020] The gate current Ig flowing into the gate of the measuring IGBT 130 is calculated by multiplying the gate-emitter capacitance CGE of the measuring IGBT 130 by dV / dt (voltage change rate per unit of time) of the gate-emitter voltage (Ig=CGE×dV / dt). Fig. 24 is an equivalent circuit diagram of a circuit. Fig. Figure 25 is a diagram showing the results of a simulation of current / voltage waveforms of the conventional semiconductor device. Fig. 26 is a diagram showing the results of a simulation of voltage waveforms of measurement voltages applied to a Fig. The measuring resistor shown in section 24 is applied over time. Fig. 25 and Fig. Figure 26 shows a horizontal axis representing the same elapsed time.

[0021] The in Fig. The circuit shown in Figure 24 comprises the main IGBT 120 and the measuring IGBT 130, which are connected in parallel, and a measuring resistor 161. One end of the measuring resistor 161 is connected to the emitter of the measuring IGBT 130. The other end of the measuring resistor 161 is connected to the emitter of the main IGBT 120. The other end of the measuring resistor 161 is further connected, via a gate voltage source 166, to the gates of the measuring IGBT 130 and the gates of the main IGBT 120.

[0022] The collector of the main IGBT 120 and the collector of the measuring IGBT 130 are connected via a load inductance 162 to a load L1 and a positive electrode of a bus voltage source 163. A negative electrode of the bus voltage source 163 is connected to the emitter of the main IGBT 120 and the emitter of the measuring IGBT 130. A diode 164 is connected antiparallel to the load inductance 162 between the collector and emitter of the main IGBT 120 and between the collector and emitter of the measuring IGBT 130.

[0023] When the main IGBT 120 and the measuring IGBT 130 are switched off, diode 162 serves to return the current flowing to the collectors of the IGBTs 120 and 130. An inductive load 165, assuming the inductance L2 of the wiring, is connected between diode 164 and the collector of the main IGBT 120 and between diode 164 and the collector of the measuring IGBT 130. The gate voltage Vg from the gate voltage source 166 is applied to the gates of the main IGBT 120 and the measuring IGBT 130 via a gate resistor 167. The gate resistor 167 is an external resistor Rgext, such as an integrated circuit (IC) connected to the main IGBT 120 and the measuring IGBT 130 of the semiconductor device.

[0024] Current / voltage waveforms during combined switching off of the main IGBT 120 and the measuring IGBT 130, using the in Fig. The 24 circuits shown were simulated and are in Fig. Figure 25 shows the measuring IGBT 130. It has a similar structure to the main IGBT 120 and is therefore operated in parallel with the main IGBT 120 under similar conditions (switching on or off).

[0025] Results of the simulation of voltage waveforms of the voltage (measurement voltage) VSC applied during the switching off of the main IGBT 120 and the measurement IGBT 130, using the in Fig. The 24 circuits shown were simulated and are in Fig. Figure 26 shows the measuring voltage VSC applied to the measuring resistor 161. This is a potential difference between the ends of the measuring resistor 161 corresponding to a resistance value RSC of the measuring resistor 161 due to the collector-emitter current ICE (represented by the reference numeral 181b in Figure 26). Fig. The voltage VSC applied to the measuring resistor 161 is detected, for example, by an external control IC. (25 displayed area) of the measuring IGBT 130, which flows through the measuring resistor 161.

[0026] The in Fig. The results shown in section 26 confirm that when the collector-emitter voltage VCE of the measuring IGBT 130 increases (see Fig. 25), the measurement voltage VSC applied to the measuring resistor 161 increases transiently. A transient increase in the measurement voltage VSC applied to the measuring resistor 161 occurs because the gate current Ig of the measuring IGBT 130 increases due to dV / dt (which is in Fig. 25 (area designated with reference numeral 181a) of the collector-emitter voltage VCE of the measuring IGBT 130 increases. In the following, a temporarily high measuring voltage VSC is referred to as the "transient measuring voltage". A Fig. The area designated 26 with reference numeral 182 represents a peak voltage (maximum value) of the transient measurement voltage. A factor contributing to the increase in the gate current Ig of the measurement IGBT 130 is the increase in dV / dt of the measurement IGBT 130 and the gate-emitter capacitance CGE of the measurement IGBT 130.

[0027] With regard to this conventional example, a ratio between the ESD tolerance of the measuring IGBT 130 and the transient measuring voltage was measured. Fig. Figure 27 is a diagram showing measurement results for the relationship between the ESD tolerance of the IGBT under test and the transient measurement voltage. Data points in Fig. 27 in a direction from the origin to an endpoint of arrow 183 indicate that the gate-emitter capacitance CGE of the measuring IGBT 130 increases. Based on the in Fig. The results shown in 27 confirmed that when the gate-emitter capacitance CGE of the measuring IGBT 130 increases to ensure ESD tolerance (tolerance against the ESD breakdown voltage described below) during the switching transition time of the measuring IGBT 130, the transient measuring voltage applied between the collector and emitter of the measuring IGBT 130 increases.

[0028] In this way, the increase in the ESD tolerance of the measurement IGBT 130 and the reduction in the transient measurement voltage due to the fluctuation of the gate-emitter capacitance CGE of the measurement IGBT 130 are in a de-off relationship. Fig. Figure 27 shows an approximation line 185, which illustrates the relationship between the transient sensor voltage and the ESD tolerance of the measuring IGBT. The improvement in the trade-off relationship between increasing the ESD tolerance and decreasing the transient sensor voltage increases in one direction (down and to the right), as indicated by arrow 184. As described above, in a case where the transient sensor voltage increases, even if a low current, at most equal to the rated current, flows between the collector and emitter of the main IGBT 120, the overcurrent protection function can easily be triggered due to faulty operation, and the operation of the main IGBT 120 can be suspended due to the overcurrent protection function.

[0029] To solve the problems associated with the conventional techniques described above, one objective of the present invention is to provide a semiconductor device which can improve the trade-off relationship between reducing the transient sensor voltage and improving the ESD tolerance of the current sensing range. SOLUTION TO THE TASK

[0030] To solve the problems described above and achieve a specific goal, a semiconductor device according to the present invention has the following features. An active region and a termination region are arranged on a semiconductor substrate. The termination region surrounds an edge of the active region. The active region comprises a first cell region in which a first bipolar transistor with an insulated gate electrode is arranged, and a second cell region arranged adjacent to the first cell region. The second cell region comprises a first region in which a second bipolar transistor with an insulated gate electrode is arranged, which has a smaller arithmetic area than that of the first bipolar transistor with an insulated gate electrode, and a second region that separates the first cell region from the first cell region.The second area comprises a first gate electrode layer, which is arranged on the semiconductor substrate over an oxide film and has an installation resistance area, and an emitter electrode of the second bipolar transistor with an insulated gate electrode, which is arranged on the first gate electrode layer over an insulating interlayer film.

[0031] The termination region includes a gate runner positioned across the oxide film on the semiconductor substrate. The gate runner surrounds an edge of the active region. The gate runner is electrically connected to the first gate electrodes of the first insulated-gate bipolar transistor. The first gate electrode layer has first and second gate electrode layer sections, which are contained within the installation resistor region. The first gate electrode layer section is electrically connected to the second gate electrodes of the second insulated-gate bipolar transistor. The second gate electrode layer section in the second region has a planar shape extending from the first gate electrode layer section to the gate runner; and the second gate electrode layer section has a resistance value in the range of 10 Ω to 5000 Ω and connects the first gate electrode layer section and the gate runner.

[0032] Furthermore, the semiconductor device according to the present invention is characterized in relation to the invention described above in that the second gate electrode layer section has a planar shape that extends linearly from the first gate electrode layer section to the gate runner, and that the second gate electrode layer section connects the first gate electrode layer section and the gate runner.

[0033] Furthermore, the semiconductor device according to the present invention is characterized in relation to the invention described above in that the second gate electrode layer section has a planar shape that extends in a meandering manner from the first gate electrode layer section to the gate runner, and that the second gate electrode layer section connects the first gate electrode layer section and the gate runner.

[0034] Furthermore, the semiconductor device according to the present invention is characterized in relation to the invention described above in that the second gate electrode layer section has a planar shape which extends in an L-shape along an outer edge of the second region from the first gate electrode layer section to the gate runner, and that the second gate electrode layer section connects the first gate electrode layer section and the gate runner.

[0035] Furthermore, the semiconductor device according to the present invention is characterized in relation to the invention described above in that the second gate electrode layer section has two second gate electrode layer sections between the first gate electrode layer section and the gate runner, which are connected in parallel.

[0036] Furthermore, the semiconductor device according to the present invention is characterized in relation to the invention described above in that the gate runner has an extended section that extends along an outer edge of the second region and surrounds an edge of the first region. The second gate electrode layer section has a planar shape that extends from the first gate electrode layer section to the extended section of the gate runner, and the second gate electrode layer section connects the first gate electrode layer section and the extended section of the gate runner.

[0037] Furthermore, the semiconductor device according to the present invention is characterized in relation to the invention described above in that a third region is arranged in the active region, which is a section without the first cell region and the second cell region, and is arranged adjacent to the termination region. In the third region, a second gate electrode layer is arranged above the oxide film on the semiconductor substrate. A gate contact surface is arranged above the insulating interlayer film on the second gate electrode layer. The second gate electrode layer has third and fourth gate electrode layer sections. The third gate electrode layer section is located opposite the gate contact surface transversely across the insulating interlayer film.In the third area, the fourth gate electrode layer section has a planar shape extending from the third gate electrode layer section to the gate runner, and the fourth gate electrode layer section establishes an electrical connection between the third gate electrode layer section and the gate runner.

[0038] Furthermore, the semiconductor device according to the present invention is characterized in relation to the invention described above in that the first bipolar transistor with insulated gate electrode is a trench-gate structure, wherein the first gate electrodes extend in a depth direction of the semiconductor substrate.

[0039] According to the invention described above, the input voltage at the gate of the second insulated-gate bipolar transistor is divided by the second gate electrode layer section and becomes smaller. As a result, the voltage values ​​of pulses with ESD waveforms do not easily exceed the gate insulation withstand voltage of the second insulated-gate bipolar transistor, and dielectric breakdown of the gate insulating films of the measured IGBT does not easily occur. Furthermore, according to the invention described above, the second gate electrode layer section does not become the second gate-emitter capacitance of the insulated-gate bipolar transistor, thus making it possible to suppress the transient measured voltage to a low value. IMPACT OF THE INVENTION

[0040] The semiconductor device according to the present invention achieves an improvement in the trade-off between increasing the ESD tolerance of the current sensing range and reducing the transient measurement voltage. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a top view of an arrangement of a semiconductor device according to a first embodiment, seen from a front side of a semiconductor substrate. Fig. Figure 2 is an enlarged top view of a second cell area in Fig. 1. Fig. Figure 3 is an enlarged top view of the second cell area in Fig. 1. Fig. Figure 4 is an enlarged top view of the second cell area in Fig. 1. Fig. Figure 5 is an enlarged top view of the second cell area in Fig. 1. Fig. 6 is a sectional view of a structure along the section line AA' in Fig. 2. Fig. Figure 7 is a sectional view of the structure along the section line BB' in Fig. 2. Fig. Figure 8 is a top view of an example of an arrangement of a section of a semiconductor device according to a second embodiment, seen from a front side of a semiconductor substrate. Fig. Figure 9 is a top view of an example of an arrangement of a section of the semiconductor device according to the second embodiment, seen from the front of the semiconductor substrate. Fig. Figure 10A is a top view of an example of an arrangement of a section of the semiconductor device according to the second embodiment, seen from the front of the semiconductor substrate. Fig. Figure 10B is a top view of an example of an arrangement of a section of the semiconductor device according to the second embodiment, seen from the front of the semiconductor substrate. Fig. Figure 11 is a top view of an example of an arrangement of a section of the semiconductor device according to the second embodiment, seen from the front of the semiconductor substrate. Fig. Figure 12A is a top view of an example of an arrangement of a section of the semiconductor device according to the second embodiment, seen from the front of the semiconductor substrate. Fig. Figure 12B is a top view of an example of an arrangement of a section of the semiconductor device according to the second embodiment, seen from the front of the semiconductor substrate. Fig. Figure 13 is a top view of an example of an arrangement of a section of a semiconductor device according to a third embodiment, seen from a front side of a semiconductor substrate. Fig. Figure 14 is a top view of an example of an arrangement of a section of the semiconductor device according to the third embodiment, seen from the front of the semiconductor substrate. Fig. Figure 15 is a top view of an example of an arrangement of a section of the semiconductor device according to the third embodiment, seen from the front of the semiconductor substrate. Fig. Figure 16 is a top view of an arrangement of a section of a semiconductor device according to a fourth embodiment, seen from a front side of a semiconductor substrate. Fig. Figure 17 is a top view of an arrangement of a section of the semiconductor device according to the fourth embodiment, seen from the front of the semiconductor substrate. Fig. Figure 18 is a circuit diagram of a machine model of an ESD evaluation device for evaluating the ESD tolerance of a measuring IGBT. Fig. Figure 19 is a circuit diagram of a machine model of an ESD evaluation device for evaluating the ESD tolerance of the measuring IGBT. Fig. Figure 20 is a properties diagram showing a relationship between resistance values ​​of a measuring resistor of a first example and an ESD tolerance of the measuring IGBT. Fig. Figure 21 is a properties diagram showing a relationship between resistance values ​​of a measuring resistor of the first example and an ESD tolerance of the measuring IGBT. Fig. Figure 22 is a diagram showing the results of a simulation of ESD waveforms of a measurement IGBT of a second example. Fig. Figure 23 is a diagram showing the results of a simulation of a relationship between the ESD tolerance of a measurement IGBT and a transient measurement voltage of a third example. Fig. 24 is an equivalent circuit diagram of a circuit. Fig. Figure 25 is a diagram showing the results of a simulation of current / voltage waveforms of a conventional semiconductor device. Fig. 26 is a diagram showing the results of a simulation of voltage waveforms of measurement voltages applied to a Fig. The measuring resistor shown in section 24 is applied over time. Fig. Figure 27 is a diagram showing measurement results for a relationship between the ESD tolerance of the measuring IGBT and the transient measuring voltage. Fig. Figure 28 is a top view of an arrangement of a conventional semiconductor device, seen from a front side of a semiconductor substrate. Fig. Figure 29 is an enlarged top view near a current measuring area in Fig. 28. Fig. Figure 30 is an enlarged top view near the current measuring area in Fig. 28. Fig. 31 is a sectional view of the structure along the section line AA-AA' in Fig. 29 and Fig. 30. FORMS OF EXECUTION OF THE INVENTION

[0041] In the following, embodiments of the semiconductor device according to the present invention are described in detail with reference to the drawings. In this description and the accompanying drawings, layers and regions are designated with prefixes n or p to indicate that the majority charge carriers are electrons or holes. Additional signs + or - appended to n or p indicate that the impurity concentration is higher or lower, respectively, than in layers or regions without + or -. In the following description of the embodiments and the accompanying drawings, identical main components are designated with the same reference numerals and are not described repeatedly. (First embodiment)

[0042] A construction of a semiconductor device according to a first embodiment is described. Fig. Figure 1 is a top view of an arrangement of the semiconductor device according to the first embodiment, seen from a front side of a semiconductor substrate. Fig. 2, Fig. 3, Fig. 4 and Fig. Figure 5 shows enlarged top views of a second cell area 3 in Fig. 1. In Fig. In sections 1 to 5, contact holes 45 of a gate-runner metal layer 53 and a gate-runner 15, as well as contact holes 46 of an extended section 54 of a gate-runner metal layer 53 and an extended section 16 of the gate-runner 15, are indicated by a bold line. Fig. Figures 1 to 4 do not show the gate runner metal layer 53 and the extended section 54 of the gate runner metal layer 53.

[0043] Fig. Numbers 2 to 5 show the same area in Fig. 1. However, individual sections are hatched differently. In Fig. 1 and Fig. 2 are first and second p + -like isolation areas 41, 42 are indicated by hatching. In Fig. 3 and Fig. 4 are the gate runner 15 and a scanning polysilicon layer 13 containing polysilicon (Poly-Si), indicated by hatching. In Fig. 5 are emitter electrodes 51, 52, the gate runner metal layer (metal layer) 53 and the extended section 54 of the gate runner metal layer 53 indicated by hatching. Fig. 6 and Fig. Figure 7 shows sectional views of the structure along section line AA' and section line BB'. Fig. 2.

[0044] A semiconductor device 10 according to the one described in Fig. The first embodiment shown in Figures 1 to 5 comprises, on a semiconductor substrate (semiconductor chip) 7, a main IGBT (first IGBT) 20 and a current sensing region that detects a current flowing through the main IGBT 20. The current sensing region comprises a measuring IGBT (second IGBT) 30, which has unit cells (functional units of an element) that each have a similar structure to the structure of each unit cell of the main IGBT 20, wherein the measuring IGBT 30 has fewer unit cells than the main IGBT 20. An equivalent circuit diagram of the semiconductor device 10 according to the first embodiment corresponds to a section enclosed by a rectangle and designated by reference numeral 91b in Figure 1. Fig. As specified in Figure 19. The main IGBT 20 and the measuring IGBT 30 are gate-trench type IGBTs with a similar structure. While it is preferred that the main IGBT 20 and the measuring IGBT 30 have unit cells with the same configuration, the configuration may differ. A collector-emitter current ratio can be set when the main IGBT 20 and measuring IGBT 30 are switched on. Preferably, the switch-on voltages of the main IGBT 20 and the measuring IGBT 30 are identical.

[0045] An active region 1 and an edge termination region 6 are arranged in the semiconductor substrate 7. The active region 1 has first and second cell regions 2, 3 and is substantially rectangular and planar. The edge termination region 6 surrounds an edge of the active region 1. The edge termination region 6 is a region between the active region 1 and the ends of the semiconductor substrate 7, where the edge termination region 6 attenuates an electric field on a front face of the semiconductor substrate 7 and maintains a breakdown voltage. The breakdown voltage is a threshold voltage at which no faulty operation or damage to a component occurs. A stress-resistant structure, such as a field limiting ring (FLR) 61 or a field plate 63 (see Figure 1), is located in the edge termination region 6. Fig. 7) etc. arranged.

[0046] In the first cell area 2, the first p described below is +-like insulating region 41 is arranged in the semiconductor substrate 7 such that it surrounds an edge of the first cell region 2. In a region of the first cell region 2, the first p + The unit cells of the main IGBT 20 are arranged in an insulating area 41. The first cell area 2 is an operating area of ​​the main IGBT 20. The first cell area 2 is a section of the active area 1 excluding the second cell area 3 and occupies a large portion of the surface of the active area 1. In particular, the first cell area 2 has a substantially rectangular planar surface with a section that is recessed inwards in plan view.

[0047] Furthermore, in the first cell region 2, the emitter electrode 51 of the main IGBT 20 is arranged on a front surface of the semiconductor substrate 7. The emitter electrode 51 covers substantially the entire area of ​​the first cell region 2. An emitter terminal 11 is designed as a section of the emitter electrode 51. Near a boundary between the first cell region 2 and the edge termination region 6, a gate terminal metal layer 55 is located (see Fig. 17) on the front surface of the semiconductor substrate 7 above the insulating interlayer film 44. A gate terminal 12 is designed as a section of the gate terminal metal layer 55. Input terminals for applying a gate voltage to the gate electrodes 28, 38 are electrically connected to the gate terminal 12.

[0048] An edge of the gate terminal surface metal layer 55 is surrounded by sections (hereinafter referred to as extended sections) 16', 54', which extend from the gate runner 15 and from the gate runner metal layer 53 respectively (see Fig. 16, Fig. 17). The extended section 54' of the gate-runner metal layer 53 is connected to the extended section 16' of the gate-runner 15 via a contact hole 46' of the insulating intermediate film 44. The first p + The insulating region 41, which is of a type, extends substantially over the entire surface area of ​​a region of the semiconductor substrate 7 in a region surrounded by the extended section 16' of the gate runner 15. The gate terminal metal layer 55 is electrically connected to the gate runner 15, which contains polysilicon.

[0049] The unit cells of the measuring IGBT 30 are arranged in the second cell region 3. The second cell region 3 has a substantially rectangular planar shape and is in contact with the edge termination region 6. Specifically, the second cell region 3 is arranged in the recessed section of the first cell region 2, with three edges of the second cell region 3 facing the first cell region 2 and one remaining edge facing the edge termination region 6. The second cell region 3 comprises a detection region (first region) 4, in which the unit cells of the measuring IGBT 30 are arranged, and an extraction region (second region) 5 for extracting the hole current. A main current flowing in the measuring IGBT 30 (the collector-emitter current) is extracted from the detection region 4 and detected.

[0050] Based on the amount of main current flowing through the measuring IGBT 30 and the number of unit cells of the measuring IGBT 30, a main current flowing through the main IGBT 20 is calculated, and it is determined whether the main current through the main IGBT 20 is an overcurrent. The main IGBT 20 is not located in the second cell region 3. The detection region 4, for example, has a substantially rectangular planar shape. The extraction region 5, for example, surrounds an edge of the detection region 4 in a substantially rectangular shape. In the extraction region 5, the first and second p + -like insulating areas 41, 42 arranged separately from each other in surface areas of the semiconductor substrate 7

[0051] The first p +The -like isolation area 41 occupies a large part of the surface of the extraction area 5 and surrounds, for example, an edge of the detection area 4 in an essentially rectangular shape. The first p + The isolation area 41, which is similar to the extraction area 5, extends to the first cell area 2. The second p + -like insulating area 42 is between the first p + -like insulating area 41 and the detection area 4 are arranged and surround an edge of the detection area 4. The first and second p + -like insulating areas 41, 42 are each electrically connected to the emitter electrode 51 of the main IGBT 20 and the emitter electrode 52 of the measuring IGBT 30.

[0052] The first cell region 2 is separated from regions that differ from the first cell region 2 by a pn junction between the first p + -like insulating area 41 and an n - -like drift area 21 (see Fig. 5, Fig. 6) isolated. Detection area 4 of the second cell region 3 is separated from regions that differ from detection area 4 by a pn junction between the second p + -like isolation area 42 and the n - -like drift area 21 isolated. In addition, the first and second p + -like insulating areas 41, 42 have the function of drawing the hole current (holes) to the emitter electrodes 51, 52 or the hole current (holes) that occurs in the edge termination area 6 and flows in the semiconductor substrate 7 towards the first and second cell areas 2, 3 when an avalanche breakdown occurs in the edge termination area 6 during the switching off of the main IGBT 20.

[0053] Furthermore, in extraction region 5, the scanning polysilicon layer (first gate electrode layer) 13, which contains polysilicon (poly-Si), is arranged on the front face of the semiconductor substrate 7 above a field oxide layer 143. The scanning polysilicon layer 13 substantially covers a total area of ​​the extraction region 5 above the field oxide layer 43b. The scanning polysilicon layer 13 has a scanning capacitance region 18 and an internal resistance region 17, which contain polysilicon (see Fig. 4) The installation resistance area 17 and the sampling capacitance area 18 are arranged separately from each other. In Fig. 4 are areas of the installation resistance range 17 and the sampling capacitance range 18, each surrounded by a bold colon-dash line and a bold dashed line.

[0054] The installation resistance area 17 is a connection area of ​​the gate electrodes 38 of the measuring IGBT 30 (see Fig. 6, Fig. 7) and the gate runner 15. The installation resistor area 17 comprises a first section (first gate electrode layer section) 17a, which is electrically connected to the gate electrodes 38 of the measuring IGBT 30 (see Fig. 7), and a second section (second gate electrode layer section) 17b, which connects the first section 17a to the gate runner 15 (see Fig. 3, Fig. 4) The series resistance of the first and second sections 17a, 17b of the installation resistance range 17 acts as the installation resistance of the measuring IGBT 30 and one resistance value of this is a sum of the resistance values ​​of the first and second sections 17a, 17b of the installation resistance range 17.

[0055] The built-in resistor 17 is electrically connected as a built-in resistor of the measuring IGBT 30 between the gate electrodes 28 of the main IGBT 20 and the gate electrodes 38 of the measuring IGBT 30. The first section 17a of the built-in resistor 17 surrounds an edge of the detection area 4. The shape of the contour of an outer edge of the first section 17a of the built-in resistor 17 is essentially a rectangular shape that is larger than the detection area 4.

[0056] The outer edge edges 13b of the first section 17a of the installation resistance area 17 are advantageously separated from the detection area 4 in a second direction Y described below. This separation of the outer edge edges 13b of the first section 17a of the installation resistance area 17 from the detection area 4 makes it possible to reduce any imbalance in installation resistance values ​​that arise due to grooves 36 of the measuring IGBT 130. Inner edge edges (edges closest to the detection area 4) 13a of the first section 17a of the installation resistance area 17 extend from the extraction area 5 to the detection area 4 and are connected to the gate electrodes 38 of the measuring IGBT 30 (see Fig. 7).

[0057] The second section 17b of the installation resistor area 17 is arranged between the first section 17a of the installation resistor area 17 and the gate runner 15, connecting the first section 17a of the installation resistor area 17 and the gate runner 15. The second section 17b of the installation resistor area 17 is a surface connected to the gate runner 15 and is arranged such that it has line symmetry centered on an axis (axis parallel to the section line B-B') that forms a right angle with the gate runner 15, e.g., in the extraction area 5, wherein the second section 17b is parallel to the axis and extends in a linear shape in a direction (hereinafter referred to as the first direction) X parallel to the front face of the semiconductor substrate 7.

[0058] The resistance of the built-in resistor area 17 is higher the longer the length w1 of the second section 17b is in the first direction X, the narrower the width w2 of the second section 17b is in the direction (hereinafter the second direction) Y perpendicular to the first direction X and parallel to the front surface of the semiconductor substrate 7, and the thinner the thickness t of the built-in resistor area 17 is in a direction (thickness direction Z) perpendicular to the front surface of the semiconductor substrate 7 (see Fig. 7) The resistance value of the first section 17b of the installation resistance range 17 is calculated by ρ×w1 / (w2×t). Here, ρ is a specific resistance of the scanning polysilicon layer 13, w1 is the length of the second section 17b of the installation resistance range 17 in the first direction X, and (w2×t) is the surface area of ​​the second section 17b of the installation resistance range 17. The resistance value of the installation resistance range 17 is advantageously in a range of approximately 10 Ω to 5000 Ω.

[0059] The sampling capacitance area 18 is arranged at a distance from the installation resistance area 17, separated by a predetermined distance w3, and the sampling capacitance area 18 surrounds an edge of the installation resistance area 17. Fig. Figures 2 to 4 show the outer edges of the first section 17a of the installation resistance region 17 by a bold double-dotted line with reference numeral 13b. An inner edge of the scanning capacitance region 18 is shown by a bold dashed line with reference numeral 13c. The scanning capacitance region 18 is connected to the extended section 16 of the gate runner 15 described below. The capacitance formed by the scanning capacitance region 18, the insulating interlayer film 44, and the emitter electrode 152 is part of the gate-emitter capacitance CGE of the measuring IGBT 130. The emitter electrode 52 of the measuring IGBT 30 extends on the scanning polysilicon layer 13 above the insulating interlayer film 44 (see Figure 2). Fig. 6). Furthermore, the sampling capacitance range 18 can be omitted if the capacitance of the measuring IGBT 30 is to be reduced.

[0060] The emitter electrode 52 of the measuring IGBT 30 essentially spans a total area of ​​the second cell region 3. The emitter electrode 52 of the measuring IGBT 30 is spaced apart from the emitter electrode 51 of the main IGBT 20. The scanning emitter connection area 14, a portion of the emitter electrode 52, is exposed in the opening 48b of a passivation film 47 and is formed by a section of the emitter electrode 52. For example, the built-in resistor region 17 is located between the scanning emitter connection area 14 and the gate runner 15. The scanning emitter connection area 15 is opposite the scanning capacitance region 18, with the insulating interlayer film lying between them.

[0061] The gate runner 15 is located in the edge termination region 6 and surrounds an edge of the active region 1. The gate runner 15 also includes the section (hereinafter referred to as the extended section) 16, which extends along an outer edge of the second cell region 3. The extended section 16 of the gate runner 15 is a section of the scanning polysilicon layer 13. The extended section 16 of the gate runner 15 surrounds an edge of the second cell region 3. A single polysilicon layer formed from the gate runner 15 and the extended section 16 of the gate runner 15 extends along an outer edge of the first cell region 2 and surrounds an edge of the first cell region 2.

[0062] The gate-runner metal layer 53 and the extended section 54 of the gate-runner metal layer 53 are oriented towards the gate-runner 15 and the extended section 16 of the gate-runner 15 respectively in the thickness direction Z via the intervening insulating intermediate layer film 44, wherein the gate-runner metal layer 53 and the extended section 54 are in contact with the gate-runner 15 and the extended section 16 of the gate-runner 15 via the contact holes 45, 46 which penetrate the insulating intermediate layer film 44 in the thickness direction Z.

[0063] In Fig. 2 to 4, an inner edge (edges closest to detection area 4) of the scanning polysilicon layer 13 is indicated by a dashed line with reference symbol 13a. Fig. References 2 to 5 are an inner edge (edges closest to the active region 1) of a section of the gate runner 15 surrounding an inner edge of the active region 1, and an outer edge (edges closest to the ends of the semiconductor substrate 7) of the gate runner 15, each indicated by dashed lines with reference symbols 15a and 15b. Edges of the extended section 16 of the gate runner 15 in the active region 1 are marked with reference symbol 16a. The gate electrodes 28 and 38 of the main IGBT 20 and the measuring IGBT 30 (see Fig. 6, Fig. 7) are electrically connected to the gate runner 15.

[0064] A cross-sectional view of the structure of the semiconductor device 10 according to the first embodiment is described. As in Fig. 6 and Fig. Figure 7 shows the unit cells of the main IGBT 20 in the semiconductor device 10 according to the first embodiment, contained in the first cell region of the active region 1, and the unit cells of the measuring IGBT 30 are contained in the second cell region of the active region 1. The unit cells of the main IGBT 20 are connected by p-like base regions 22, n + -like emitter regions 24, p + The unit cells of the main IGBT 20 have a general gate-trench structure with the gate electrodes 28 embedded in the grooves 26 via the gate-insulating films 27, and extending in a depth direction (the thickness direction Z) of the semiconductor substrate 7.

[0065] The unit cells of the main IGBT 20 are arranged in the first cell region 2, with one region of them being separated from the first p +is surrounded by a -like insulating region 41. The p-like base regions 22, which n + -like emitter regions 24 and the p + -like contact areas 25 are arranged in surface areas of the front face of the semiconductor substrate 7. The n + -like emitter regions 24 and the p + -like contact regions 25 are arranged between adjacent trenches 26 of the trenches 26 (mesa regions), at positions that are less deep from the front face of the semiconductor substrate 7 than the p-like base regions 22. In a mesa region near the outer edge of the first cell region 2, there are no n + -like emitter regions 24, but only the p + -like contact areas 25 arranged.

[0066] In semiconductor substrate 7, the n -The p-like drift region 21 is located at a lower position from the front face of the semiconductor substrate 7 than the p-like base regions 22. Regions (hereinafter referred to as storage regions) 23, which store charge (holes) that become minority charge carriers during an ON state, can be located between the p-like base regions 22 and the n-like drift region 21. The storage regions 23 are n-like regions with a contaminant concentration that is lower than the contaminant concentration of the n-like drift regions 21. The trenches 26 are arranged, for example, in a striped pattern extending in the first direction X, as described below. The gate electrodes 28 are located in the trenches above the gate insulating films 27.

[0067] One of the unit cells of the main IGBT 20 is formed by one of the trenches 26 in which the gate electrodes 28 are embedded, and a mesa area adjacent to one of the trenches 26. The first p + -like insulating area 41 is connected to the p-like base areas 22 and the p + -like contact areas 25 near the outer edge of the first cell area 2 are connected. A depth of the first p + The insulating area 41 of a type is deeper than the depth of the trenches 26. The emitter electrode 51 of the main IGBT 20 is connected to the n via contact holes that penetrate the insulating interlayer film 44 in the thickness direction Z. + -like emitter regions 24, the p + -like contact areas 25 and the first p + -like insulating area 41 connected.

[0068] The emitter electrode 51 can be electrically connected to the n via a metal barrier and contact plugs. + -like emitter regions 24, the p +-like contact areas 25 and the first p + The metal barrier comprises a metal that exhibits high adhesion to a semiconductor region (the semiconductor substrate 7) and forms an ohmic contact with the semiconductor region. In particular, the metal barrier can, for example, be a stacked film in which a titanium film (Ti) and a titanium nitride film (TiN) are stacked successively. The contact plugs are, for example, a metal film containing tungsten (W), which exhibits high embedding properties, with the contact plugs being embedded via the metal barrier in contact holes of the insulating interlayer film 44.

[0069] The emitter electrode 51 is, for example, an aluminum-silicon (Al-Si) electrode. The emitter electrode 51 is electrically insulated from the gate electrode 28 by the insulating interlayer film 44. The emitter electrode 51 is covered by the passivation film 47. The emitter termination surface 11, formed by a section of the emitter electrode 51, is exposed in an opening 48a of the passivation film 47. A p is located in a surface layer on a back surface of the semiconductor substrate 7. + A collector region 29 of the main IGBT 20 is arranged such that an entire area of ​​the back surface of the semiconductor substrate 7 is covered. A collector electrode 56 of the main IGBT 20 is arranged such that an entire area of ​​the back surface of the semiconductor substrate 7 is covered.

[0070] The unit cells of the measuring IGBT 30 are arranged in a region of the detection region 4 of the second cell region 3, which is separated from the second p + The unit cells of the measuring IGBT 30 are surrounded by p-like base regions 32, n. + -like emitter regions 34, p + The unit cells of the measuring IGBT 30, similar to the unit cells of the main IGBT 20, have a general gate-trench structure with the gate electrodes 38 embedded in the trenches 36 and extending in the depth direction of the semiconductor substrate 7.

[0071] The n + -like emitter regions 34 and the p +-like collector regions 35 are arranged between adjacent trenches 36 of the trenches 36 (mesa regions), at positions that are less deep from the front face of the semiconductor substrate 7 than the p-like base regions 32. In a mesa region near the outer edge of the detection region 4 of the second cell region 3, there are no n + -like emitter regions 34, but only the p + -like collector regions 35 are arranged. At a deeper position from the front surface of the semiconductor substrate 7, where the p-like base regions 32 are located, the n extends - -like drift area 21 from the first cell area 2.

[0072] Storage regions can be arranged between the p-like base regions 32 and the n-like drift region 21. The following explains one reason why the storage regions can be omitted in the measurement IGBT 30. By omitting storage regions in the measurement IGBT 30, an injection-enhanced (IE) effect in the measurement IGBT 30 can be reduced, and a decrease in the turn-off tolerance due to minority carrier storage can be suppressed.

[0073] The trenches 36 are arranged, for example, in a striped pattern extending in the first direction X, which corresponds to the direction in which the trenches 26 of the main IGBT 20 extend. The gate electrodes 38 are embedded in the trenches 36 above the gate insulating films 37. One of the unit cells of the measuring IGBT 30 is formed by one of the trenches 36 in which the gate electrodes 38 are embedded and a mesa region adjacent to one of the trenches 36. Depths of the p-like base regions 32, the n + -like emitter regions 34, the p + The collector areas 35 and the trenches 36 are identical to the depths of the corresponding parts of the main IGBT 20.

[0074] The second p + -like insulating area 42 is connected to the p-like base areas 32 and the p + -like collector areas 35 near the outer edge of the second cell area 3 are connected. A depth of the second p +-like insulating area 42 is equal to the depth of the first p + -like insulating region 41. The p-like base region 32 and the p + -like collector area 35 can extend in the first direction X from the detection area 4 to the extraction area 5 in the second p + -like isolation area 42 extend. The second p + -like isolation area 42 extends from extraction area 5 and can reach from the trenches 36 a trench 36 which is located closest to extraction area 5, or can be contained in this trench 36.

[0075] The emitter electrode 52 of the measuring IGBT 30 is connected to the n via contact holes that penetrate the insulating intermediate layer film 44 in the thickness direction Z. + -like emitter regions 34, the p + -like collector areas 35 and the second p +-like insulating area 42 in contact. The emitter electrode 52 can be electrically connected to the n via a metal barrier and contact plug. + -like emitter regions 34, the p + -like collector areas 35 and the second p + -like insulating area 42. The materials of the emitter electrode 53, the metal barrier and the contact plug are similar to the materials of the emitter electrode 51 of the main IGBT 20, the metal barrier and the contact plug.

[0076] The emitter electrode 52 is electrically insulated from the gate electrode 38 by the insulating interlayer film 44. The emitter electrode 52 is covered by the passivation film 47. The scanning emitter connection surface 14, formed by a section of the emitter electrode 52, is exposed in the opening 48b of the passivation film 47. The scanning emitter connection surface 14 can, for example, be located in the extraction area 5 of the second cell region 3. +The collector area 29 and the collector electrode 56 of the main IGBT 20 each serve as p + -like collector area and as collector electrode of the measuring IGBT 30.

[0077] In extraction area 5 of the second cell area 3, the first and second p + -like insulating regions 41, 42 are arranged separately from each other in a surface layer of the semiconductor substrate 7 on the front face of the semiconductor substrate 7. The first and second p + -like insulating regions 41, 42 are isolated from each other by a local insulating film 43a, for example by a field oxide layer or a local oxidation of silicon (LOCOS) on the front surface of the semiconductor substrate 7. The first p + The -like isolation area 41 extends from the extraction area 5 to the outer edge of the first cell area 2. The second p + The -like isolation area 42 is arranged closer to the detection area 4 than the first p +-like isolation area 41 and extends from the extraction area 5 into an outer edge area of ​​the detection area 4.

[0078] In the extraction region 5, the installation resistance region 17 and the sampling capacitance region 18 of the sampling polysilicon layer 13 are arranged on the front face of the semiconductor substrate 7 above the field oxide layer 43b. The first section 17a of the installation resistance region 17 is adjacent to the second p + -like insulating area 41 in the thickness direction Z transversely across the field oxide layer 43b and the local insulating film 43a opposite. The first section 17a of the installation resistance area 17 extends, for example, in the first direction X to the ends of the trenches 36 of the measuring IGBT 30 in order to be in contact with the gate electrodes 38.

[0079] The second section 17b of the installation resistance area 17 is located closer to the edge termination area 6 than the first section 17a of the installation resistance area 17 and is connected to the first section 17a of the installation resistance area 17. The second section 17b of the installation resistance area 17 is adjacent to the first p + -like insulating area 41 in the thickness direction Z transversely across the intervening field oxide layer 43b. The scanning capacitance area 18 is arranged closer to the first cell area 2 than the installation resistance area 17 and is spaced apart from the installation resistance area 17. The scanning capacitance area 18 lies adjacent to the first p + -like insulating area 41 in thickness direction Z across the intervening field oxide layer 43b opposite.

[0080] The second section 17b of the installation resistance region 17 extends to the edge termination region 6 and is connected to the gate runner 15. The scanning polysilicon layer 18 serves as the extended section 16 of the gate runner 15 and is connected to the gate runner 15. The emitter electrode 52 of the measuring IGBT 30 extends from the detection region 4 across the insulating interlayer film 44 on the first and second sections 17a, 17b of the installation resistance region 17 and on the scanning capacitance region 18. The emitter electrode 51 of the main IGBT 20 extends across the scanning capacitance region 18, from the first cell region 2 across the insulating interlayer film 44.

[0081] The first and second sections 17a, 17b of the installation resistance region 17 and the sampling capacitance region 18 are electrically isolated from the emitter electrodes 51, 52 by the insulating interlayer film 44. The gate runner metal layer 53 and the extended section 54 of the gate runner metal layer 53 are each connected to the gate runner 15 and the extended section 16 of the gate runner 15 via the contact holes 45, 46 of the insulating interlayer film 44. While in Fig. 6 and Fig. Figure 7 shows a case in which two contact holes 45, 46 are arranged; the number of contact holes 45, 46 can be changed in various ways.

[0082] In the edge termination region 6, the field limiting ring 61 is arranged singly or in plurality in a concentric shape in a surface layer of the semiconductor substrate 7 at the front face of the semiconductor substrate 7, surrounding an edge of the active region 1. A polysilicon layer 62 is arranged on each field limiting ring 61 above the field oxide layer 43b. The field plate 63 is arranged on the polysilicon layer 62 above the dielectric interlayer film 44. The field plate 63 is connected to the polysilicon layer 62 via a contact hole in the dielectric interlayer film 44.

[0083] For example, a circuit arrangement of a machine model of ESD (electrostatic discharge) is assumed, which is located between the gate terminal 112 and the sample emitter terminal 114 of the IGBT 120, 130 of the conventional setup (see Fig. 24, 28 to 31). The machine model of the ESD is an RLC circuit (resistor (R), inductor (Lm) and capacitor (C)), which is arranged as in Fig. Figure 18 shows that the IGBT is connected to the gate terminal 112. Therefore, the ESD waveform oscillates under the resonance conditions of the RLC circuit (see Figure 18). Fig. 22).

[0084] If the voltage of the first pulse of the ESD waveform, due to the oscillation, has a voltage value greater than the gate insulation withstand voltage of the measuring IGBT 130, a dielectric breakdown of the gate insulating films 137 in the gate grooves 136 of the measuring IGBT 130 occurs. Therefore, the ESD tolerance of the measuring IGBT 130 must be set such that the voltage value of the first pulse of the ESD waveform does not exceed the gate insulation withstand voltage of the measuring IGBT 130.

[0085] On the other hand, according to the first embodiment, the high installation resistance formed by the second section of the installation resistance area, which contains polysilicon, is connected to the gates of the measuring IGBT. Due to this installation resistance area, the dV / dt of the first ESD pulse voltage decreases, thus reducing the peak voltage of the first pulse of the ESD waveform. As a result, the peak voltage of the first pulse of the ESD waveform does not simply exceed the gate insulation withstand voltage of the measuring IGBT, and dielectric breakdown of the gate insulating films in the gate grooves of the measuring IGBT does not readily occur, thereby increasing the ESD tolerance.

[0086] Furthermore, according to the first embodiment, the built-in resistor section, which contains polysilicon, is arranged so that the gate-emitter capacitance CGE of the measuring IGBT does not decrease. Therefore, the transient measurement voltage, which increases proportionally to the magnitude of the gate-emitter capacitance CGE of the measuring IGBT, can be set approximately the same as in the conventional design without a built-in resistor, even when the ESD tolerance is increased by the built-in resistor section. As a result, only the ESD tolerance can be increased while keeping the transient measurement voltage low, thus improving the trade-off between increasing the ESD tolerance of the current sensing range and reducing the transient measurement voltage. (Second example)

[0087] The following describes the construction of a semiconductor device according to a second embodiment. Fig. 8, Fig. 9, Fig. 10A, Fig. 10B, Fig. 11, Fig. 12A and Fig. Figure 12B shows top views of examples of arrangements of a section of the semiconductor device according to the second embodiment, seen from the front face of the semiconductor substrate. An arrangement of an entire surface of a semiconductor device 10' according to the second embodiment, seen from the front face of the semiconductor substrate 7, is similar to that of the semiconductor device 10 according to the first embodiment (see Figure 12B). Fig. 1). In Fig. 8 to 12 is the second cell range 3 in Fig. Figure 1 is enlarged, and the scanning polysilicon layer 13 and the gate runner 15 are indicated by hatching. In Fig. 8 to 12 is a section of the second section 17b of the installation resistance range 17, outlined by a bold colon-dash line. In Fig. Emitter electrodes 51 and 52 are not shown in figures 8 to 12 (see Fig. 1, Fig. 4, Fig. 5).

[0088] The semiconductor device 10' according to the second embodiment differs from the semiconductor device 10 according to the first embodiment in that the arithmetic area occupied by the first section 17a' of the installation resistor area 17 in the extraction area 5 is small. It is sufficient if the first section 17a' of the installation resistor area 17 is positioned such that it connects the second section 17b of the installation resistor area 17 and the gate electrodes 38 of the measuring IGBT 30. For example, the first section 17a' of the installation resistor area 17 is positioned along a boundary between the detection area 4 and the extraction area 5 and surrounds an edge of the detection area 4 with a substantially rectangular shape. The shape of a contour of an outer edge of the first section 17a of the installation resistor area 17 is substantially rectangular, slightly larger than the detection area 4.

[0089] The second section 17b of the installation resistor area 17, similar to the first embodiment, has a linear, planar shape extending in the first direction X. The second section 17b of the installation resistor area 17 is, similar to the first embodiment, arranged between the first section 17a of the installation resistor area 17 and the gate runner 15 and connects the first section 17a of the installation resistor area 17 and the gate runner 15. Fig. 8).

[0090] The first section 17a' of the installation resistor range 17 and the extended section 16 of the gate runner 15 can be connected by the second section 17b' of the installation resistor range 17 ( Fig. 9) In this case, for example, the second section 17b' of the installation resistor area 17 is arranged between the first section 17a' of the installation resistor area 17 and the extended section 16 of the gate runner 15. The scanning emitter terminal area 14 is arranged in the emitter electrode 52 in a region surrounded by the extended section 16 of the gate runner 15.

[0091] Furthermore, a second section 19 of the installation resistor area 17 can have a planar shape that extends in a meandering manner in an X-direction or a Y-direction from the first section 17a' of the installation resistor area 17 to the gate runner 15 ( Fig. 10A, Fig. 10B). In this case, the second section 19 of the installation resistance area 17 is preferably connected to the first section 17a' of the installation resistance area 17 at a position opposite a center of the detection area 4.

[0092] An arithmetic area occupied by the sampling capacity range 18' in the extraction range 5 can be increased by the amount of the arithmetic area occupied by the first range 17a' of the installation resistance range 17, is reduced ( Fig. 8, Fig. 9, Fig. 10A, Fig. 10B). The setup can be such that no sampling capacitance area 18' is arranged in the extraction area 5 and only the extended section 16 of the gate runner 15 is provided ( Fig. 11, Fig. 12A, Fig. 12B). In a case where the scanning capacitance region 18' is not arranged and only the extended section 16 of the gate runner 15 (hatched section provided along the contact hole 46) is provided, the scanning polysilicon layer 13 between the semiconductor substrate 7 and the scanning emitter contact surface 14, which are opposite each other in depth direction, is not present over the intervening insulating interlayer film and field oxide layer ( Fig. 11, Fig. 12A, Fig. 12B).

[0093] Furthermore, in a case where the sampling capacitance area 18' is not provided in the extraction area 5 and only the extended section 16 of the gate runner 15 is provided, a second section 19' of the installation resistor area 17 may have a first end connected to the gate runner 15, extending such that it substantially encircles and surrounds an edge of the first section 17a' of the installation resistor area 17, and the installation resistor area 17 may have a second end connected to the first section 17a' ( Fig. 12B). In this case, the second end of the second section 19' of the installation resistance area 17 is preferably connected to the first section 17a' of the installation resistance area 17 at a position opposite the center of the detection area 4.

[0094] Although not shown, the semiconductor devices 10' can be found according to the in Fig. 10A and Fig. 10B second embodiment on the semiconductor device 10' according to the Fig. The second embodiment shown in Figure 9 is used, wherein the planar shape is such that the second section 19 of the built-in resistor area 17 extends in a meandering fashion from the first section 17a' of the built-in resistor area 17 to the extended section 16 of the gate runner 15. The semiconductor device 10' according to the one shown in Figure 9 Fig. The second embodiment shown in 11 can be applied to the semiconductor device 10' according to the one described in Fig. The second embodiment shown in Figure 9 is applied, wherein the sampling capacity area 18' is not arranged and only the extended section 16 of the gate runner 15 is arranged.

[0095] The semiconductor devices 10' according to the in Fig. 10A, Fig. 10B and Fig. The second embodiment shown in 11 can be applied to the semiconductor device 10' according to the [reference to be added]. Fig. The second embodiment shown in Figure 9 is used, wherein the planar shape is such that the second section 19 of the built-in resistor area 17 meanders from the first section 17a' of the built-in resistor area 17 to the extended section 16 of the gate runner 15, and wherein no sampling capacitance area 18' and only the extended section 16 of the gate runner 15 are arranged. In the semiconductor device 10 according to the first embodiment, the sampling capacitance area 18 can be omitted and instead the extended section 18 of the gate runner 15 of the semiconductor device 10' can be arranged according to the first embodiment shown in Figure 9. Fig. The second embodiment shown in 11 is arranged.

[0096] As described above, according to the second embodiment, the mounting resistance area acts as the mounting resistance of the measuring IGBT when the first section of the mounting resistance area and the gate runner are electrically connected by the second section of the mounting resistance area. Therefore, similar effects to the first embodiment can be achieved even if the planar shapes of the first and second sections of the mounting resistance area and the sampling capacitance area are modified in different ways. (Third embodiment)

[0097] The following describes the construction of a semiconductor device according to a third embodiment. Fig. 13, Fig. 14 and Fig. Figure 15 shows top views of examples of arrangements of a section of the semiconductor device according to the third embodiment, seen from the front face of the semiconductor substrate. An arrangement of an entire surface of a semiconductor device 70 according to the third embodiment, seen from the front face of the semiconductor substrate 7, is similar to that of the semiconductor device 10 according to the first embodiment (see Figure 15). Fig. 1). In Fig. 13 to 15 is the second cell range 3 in Fig. Figure 1 is enlarged, and the scanning polysilicon layer 13 and the gate runner 15 are indicated by hatching. In Fig. Sections 13 to 15 of the second sections 71, 73, 74, 73', 74' of the installation resistance area 17 are outlined by a bold colon-dash line. Fig. Emitter electrodes 51 and 52 are not shown in figures 13 to 15 (see Fig. 1, Fig. 4, Fig. 5).

[0098] The semiconductor device 70 according to the third embodiment differs from the one in Fig. 8 Semiconductor device 10' shown in the second embodiment, in that in the extraction area 5 the second section 71 of the built-in resistor area 17 has a narrow width w11, is extended to a greater length and has a high resistance. In the semiconductor device 70 according to the one shown in Fig. In the third embodiment shown in Figure 13, a sampling capacitance area 72 is connected to the gate runner 15. The sampling capacitance area 72 is not connected to the extended section 16 of the gate runner 15. The sampling capacitance area 72 occupies a large portion of the surface of the extraction area 5.

[0099] The detection area 4 is arranged further away from the gate runner 15 than the sampling capacitance area 72, and its edge is surrounded by the extraction area 5. The first section 17a' of the built-in resistor area 17 is arranged along the boundary between the detection area 4 and the extraction area 5, similar to the second embodiment, and surrounds an edge of the detection area 4 with a substantially rectangular shape. The shape of an outer edge contour of the first section 17a' of the built-in resistor area 17 is, similar to the second embodiment, substantially rectangular, and slightly larger than the detection area 4.

[0100] The first section 17a' of the installation resistor area 17 can be arranged with a constant width w12 around an entire edge of the detection area 4, or with a different width w12' along a predetermined edge of its rectangular shape. The second section 71 of the installation resistor area 17 has a planar L-shape. For example, the second section 71 of the installation resistor area 17 extends from the gate runner 15 and between the sampling capacitance area 72 and the extended section 16 of the gate runner 15 along two edges of the outer edge of the second cell area 3, opposite the first cell area 2.

[0101] A first end of the L-shape of the second section 71 of the installation resistor area 17 is connected to the gate runner 15. A second end of the L-shape of the second section 71 of the installation resistor area 17 is connected to the first section 17a' of the installation resistor area 17. The sampling capacitance area 72 can surround an edge of the first section 17a' of the installation resistor area 17, along three edges of the first section 17a'. The sampling emitter termination area 14 is located between the first section 17a' of the installation resistor area 17 and the gate runner 15. The sampling emitter termination area 14 lies opposite the sampling capacitance area 72 across the insulating interlayer film.

[0102] The in Fig. 14 and Fig. The semiconductor devices 70 shown in the third embodiment (15) differ from those shown in Fig. The semiconductor device 70 shown in Figure 13, according to the third embodiment, is characterized in that two of the second sections of the installation resistor range 17 are arranged in a planar L-shape in the extraction region 5. A combined resistor of the two second sections of the installation resistor range 17 acts as the installation resistor of the measuring IGBT 30. The two second sections of the installation resistor range 17 are arranged, for example, as follows.

[0103] As in Fig. As shown in Figure 14, the first second section 73 of the installation resistor area 17 extends from the gate runner 15 and between the sampling capacitance area 72' and the extended section 16 of the gate runner 15 along two edges of the boundary of the second cell area 3, opposite the first cell area 2. A first end of the L-shape of the first section 73 of the installation resistor area 17 is connected to the gate runner 15. A second end of the L-shape of the first second section 73 of the installation resistor area 17 is connected to the first section 17a' of the installation resistor area 17, which is connected to its side closest to the gate runner 15.

[0104] A second second section 74 of the installation resistor area 17 is arranged at a position opposite the first second section 73 of the installation resistor area 17 across the sampling capacitance area 72'. The second second section 74 of the installation resistor area 17 extends between the sampling capacitance area 72' and the extended section 16 of the gate runner 15 from one direction of the gate runner 15, and from the three edges of the border of the second cell area 3 opposite the first cell area 2, the second second section 74 extends along one edge where the first second section 73 is not arranged, and is connected to one edge.

[0105] A first end of the L-shape of the second subsection 74 of the installation resistor area 17 is connected to the gate runner 15 via a section 75 of the scanning polysilicon layer 13. A second end of the L-shape of the second subsection 74 of the installation resistor area 17 is connected to the first section 17a' of the installation resistor area 17, which is connected to the side of the first section 17a' near the extended section 16 of the gate runner 15. The scanning capacitance area 72', for example, has a substantially rectangular planar shape.

[0106] As in Fig. As shown in Figure 15, the second ends of the L-shape of the second sections 73', 74' of the installation resistor range 17 can both be connected to the first section 17a' of the installation resistor range 17 and the sampling capacitance range 72'. In this case, for example, the first ends of the L-shape of the second sections 73', 74' of the installation resistor range 17 are each connected to different parts of the gate runner 15. The first and second second ends of the L-shape of the second sections 73', 74' of the installation resistor range 17 are both connected to the first section 17a' of the installation resistor range 17.

[0107] As described above, similar effects to those in the first and second embodiments can be achieved according to the third embodiment. Furthermore, according to the third embodiment, in the extraction area, the second section of the installation resistance area has a narrow width and is extended to a greater length, thereby allowing the installation resistance of the measuring IGBT to be set to a higher resistance. (Fourth example)

[0108] The following describes the construction of a semiconductor device according to a fourth embodiment. Fig. 16 and Fig. Figure 17 shows top views of arrangements of a section of the semiconductor device according to the fourth embodiment, seen from the front face of the semiconductor substrate. An arrangement of a total surface of a semiconductor device 80 according to the fourth embodiment, seen from the front face of the semiconductor substrate 7, is similar to that of the semiconductor device 10 according to the first embodiment (see Figure 17). Fig. 1). Fig. 16 and Fig. Figure 17 shows enlarged top views near the gate connection surface 12 of the main IGBT in Fig. 1. Fig. Figures 16 to 17 show the same area in Fig. 1. However, the hatched areas differ. In Fig. 16 are the emitter electrode 51 and the gate terminal metal layer 55 (see Fig. 17) not shown.

[0109] In Fig. 16 are a polysilicon layer 83 and the gate runner 15, indicated by hatching. In Fig. Figure 17 shows the gate runner metal layer 53, the extended section 54' of the gate runner metal layer 53, and the gate terminal surface metal layer 55 with hatching. Fig. 16 is a region of a second section 81b of an installation resistance region 81, outlined by a bold colon-dash line. In Fig. 16 and Fig. 17 are contact holes in the insulating intermediate layer film 44 including the contact holes 45 of the gate runner metal layer 53 and the gate runner 15, the contact holes 46' of the extended section 54' of the gate runner metal layer 53 and the extended section 16' of the gate runner 15 and a contact hole 45' of the gate terminal surface metal layer 55 and the polysilicon layer 83 are shown by bold lines.

[0110] The semiconductor device 80 according to the fourth embodiment differs from the semiconductor device 10 according to the first embodiment in that, instead of the second cell region 3, a region (third region) is arranged in which the gate terminal area 12 is located in the polysilicon layer 83. An equivalent circuit diagram of the semiconductor device 80 according to the fourth embodiment corresponds to a section enclosed by a rectangle and designated by reference numeral 91a in Fig. The scanning polysilicon layer 83 is located on the front face of the semiconductor substrate 7 above the field oxide layer 143. The polysilicon layer 83 includes the onboard resistor area 81 and the extended section 16' of the gate runner 15. The onboard resistor area 81 is a connection area that electrically connects the gate terminal metal layer 55 and the gate runner 15, which are spaced apart from each other.

[0111] In the semiconductor device 80 according to the fourth embodiment, the built-in resistor 81 is connected to the gate electrodes 28 of the main IGBT 20 via the gate runner 15. The built-in resistor 81 comprises a first section (third gate electrode layer section) 81a, which is electrically connected to the gate terminal 38, and a second section (fourth gate electrode layer section) 81b, which connects the first section 81a to the gate runner 15. The first section 81a of the built-in resistor 81 lies transversely across the insulating interlayer film 44 opposite an entire area of ​​the gate terminal 12. The gate terminal 12 is formed by a portion of the gate terminal metal layer 55 that is exposed in an opening of the passivation film 47. The gate contact surface metal layer 55 is arranged over the gate insulating films 44 on the polysilicon layer 83.

[0112] It is sufficient if the first section 81a of the installation resistance area 81 lies across the insulating interlayer film 44 opposite an entire area of ​​the gate terminal 12, and it is sufficient if the shape of a contour of an outer edge of the first section 81a of the installation resistance area 81 has a substantially rectangular shape that is at least slightly larger than the gate terminal 12. The second section 81b of the installation resistance area 81 connects the first section 81a of the installation resistance area 81 and the extended section 16' of the gate runner 15. In the semiconductor device 80 according to the fourth embodiment, similar to the second embodiment, a resistance value of the first section 81a of the installation resistance area 81 is smaller than a resistance value of the second section 81b, and the second section 81b of the installation resistance area 81 mainly functions as the installation resistor of the measuring IGBT 30.

[0113] The second section 81b of the installation resistor area 17 is, for example, arranged between the first section 81a of the installation resistor area 17 and the extended section 16' of the gate runner 15 and has a linear, planar shape extending from the first section 81a of the installation resistor area 17 to the extended section 16' of the gate runner 15. The second section 81b of the installation resistor area 81, not shown, can, for example, be arranged between the first section 81a of the installation resistor area 81 and the gate runner 15 and can connect the first section 81a of the installation resistor area 81 and the gate runner 15.

[0114] The extended section 16' of the gate runner 15 has a substantially U-shaped planar form, and the ends of the U-shape are each connected to different parts of the gate runner 15. The gate runner 15 and the extended section 16' of the gate runner 15 form a substantially rectangular planar form that surrounds an edge of the built-in resistor area 81.

[0115] The semiconductor device 80 according to the fourth embodiment can be applied to the semiconductor devices 10, 10', 70 according to the first to third embodiments, and the installation resistor areas 17, 81 can be arranged both in the second cell area 3 and in an area in which the gate terminal area 12 is arranged.

[0116] As described above, according to the fourth embodiment, even when the gate terminal and gate runner are connected through the mounting resistor area, similar effects to those of the first three embodiments can be achieved. Furthermore, according to the fourth embodiment, a setup is formed in which the gate resistor is also connected to the main IGBT, while the mounting resistor area is added to the area where the gate terminal is located, thus forming a setup in which the gate resistor is connected to the measuring IGBT. As a result, one Miller period of the gate voltage of the main IGBT increases, and the switching loss decreases. Therefore, adding the mounting resistor area between the gate runner of the measuring IGBT and the detection area can prevent the switching loss from worsening. (First example)

[0117] The ESD tolerance of the measuring IGBT 30 was checked. Fig. 18 and Fig. 19 are circuit diagrams of machine models of ESD evaluation devices for evaluating the ESD tolerance of the measuring IGBT. Fig. 20 and Fig. Figure 21 are property diagrams showing a relationship between the resistance values ​​of a measuring resistor in the first example and the ESD tolerance of the measuring IGBT. Fig. 20 and Fig. 21 are each measurements taken using the in Fig. 18, Fig. 19 ESD evaluation circuits shown 90a, 90b were obtained.

[0118] One in Fig. Semiconductor device 91a shown in Figure 18 corresponds to semiconductor device 80 according to the fourth embodiment (see Figure 18). Fig. 16, Fig. 17) and comprises the main IGBT 20 and the measuring IGBT 30, which are connected in parallel, and the installation resistor RG, which is connected between a switch 92 and the gates of the main IGBT 20. The installation resistor RG of the semiconductor device 91b corresponds to the second section 81b of the installation resistor range 81.

[0119] If switch 92 of the in Fig. When the ESD evaluation circuit 90a shown in Figure 18 is switched on, a charge stored in a capacitor 96, up to a constant voltage, is applied to the main IGBT 20 and the measuring IGBT 30 (this voltage, which has become constant, is referred to below as the applied ESD voltage). Furthermore, while the emitter of the measuring IGBT 30 is grounded, the emitter of the main IGBT 20 is not grounded, and therefore charge is only supplied between the gate and emitter of the measuring IGBT 30.

[0120] A positive electrode of the power source 93 is connected to the switch 92, and a negative electrode is grounded. The conductor inductance 94, which assumes the inductance Lm of the device's wiring, and a resistive load 95, which assumes the resistance Rm of the wiring, are connected in series between the positive electrode of the power source 93 and the switch 92. The capacitor 96, which assumes a parasitic capacitance due to wiring, etc., between the positive and negative electrodes of the power source 93, is connected between the positive electrode of the power source 93 and the conductor inductance 94.

[0121] The in Fig. The ESD evaluation circuit 90b shown in Figure 19 differs from the one in Figure 19. Fig. The ESD evaluation circuit 90a shown in Figure 18 is characterized by the fact that the built-in resistor RG is connected between the gates of the main IGBT 20 and the gates of the measuring IGBT 30. A Fig. Semiconductor device 91b shown in 19 corresponds to the semiconductor device 10 according to the first embodiment (see Fig. 2 to 5) and comprises the main IGBT 20 and the measuring IGBT 30, which are connected in parallel, and the installation resistor RG, which is connected between the gates of the main IGBT 20 and the gates of the measuring IGBT 30. The installation resistor RG of the semiconductor device 91b corresponds to the second section 17b of the installation resistor range 17.

[0122] In capacitor 96 of the in Fig. In the ESD evaluation circuit 90b shown in Figure 19, a charged charge is applied to the gate of the measuring IGBT 30 via the measuring resistor RG when the switch 92 is turned on. If the voltage at this time exceeds the gate insulation withstand voltage of the measuring IGBT 30, a dielectric breakdown of the gate insulating film 37 occurs.

[0123] A relationship between the resistance value of the built-in resistor RG of the measuring IGBT 30 and the ESD tolerance, when the resistance value of the built-in resistor RG of the semiconductor device 91a is determined using the values ​​given in Fig. The different modifications to the ESD evaluation circuit 90a shown in section 18 (first example below) are described in the following. Fig. Figure 20 shows the results of the simulation of a relationship between the resistance value of the installation resistor RG of the measuring IGBT 30 of the respective semiconductor devices 91a, 91b and a peak voltage between the gates and emitter of the measuring IGBT 30 using the results shown in Figure 20. Fig. 18 and Fig. The ESD evaluation circuits shown in Figure 19, 90a and 90b, are in Fig. 21 shown.

[0124] Based on the in Fig. The results presented in 20 confirmed that the higher the resistance value of the installation resistor RG, the higher the ESD tolerance of the measuring IGBT 30 can be set. The direction of an arrow in Fig. 20 indicates a direction in which the ESD tolerance of the measuring IGBT 30 increases. Furthermore, based on the in Fig. The results shown in Figure 20 confirm that the ESD breakdown voltage of the measured IGBT 30 increases proportionally to the resistance value of the installation resistor RG. Based on the results shown in Fig. The results presented in Figure 21 confirmed that the higher the resistance value of the built-in resistor RG, the lower the peak voltage between the gates and emitter of the measuring IGBT 30 can be set. It was shown that with both ESD evaluation circuits 90a and 90b in Fig. 18 and Fig. 19 essentially the same result was achieved.

[0125] In Fig. 20 and Fig. Figure 21 indicates the horizontal axes of the resistance values ​​[Ω] of the built-in resistor RG. Fig. 20 denotes a vertical axis in arbitrary units (au) of an applied ESD voltage (hereinafter ESD breakdown voltage) that was applied to the measuring IGBT 30 during the dielectric breakdown of the gate insulating film 3. Fig. 21 denotes a vertical axis in arbitrary units the peak voltage between the gates and emitter of the measuring IGBT 30. (Second example)

[0126] Next, a relationship between the ESD voltage applied to the measurement IGBT 30 and the resistance value of the built-in resistor RG was verified. Results of a simulation of the ESD waveform generated by the gate of the measurement IGBT 30 when the resistance value of the built-in resistor RG of the semiconductor device 91b was used, based on the values ​​in Fig. The ESD evaluation circuit 90b shown and described above (second example below) is modified in various ways, as shown in 19, are in Fig. 22 shown. Fig. Figure 22 is a diagram showing the results of a simulation of ESD waveforms from the measurement IGBT of the second example. Fig. 22 denotes a horizontal axis representing elapsed time [seconds (s)] and a vertical axis representing, in arbitrary units, a gate-emitter voltage of the measuring IGBT 30. ESD waveforms generated by the gate of a conventional example (see Fig. Figures 28 to 31 are not shown. The conventional example differs from the second example in that the conventional example does not include the installation resistor RG (the second section 81b of the installation resistor range 81) of the present invention.

[0127] In the conventional example, the voltage applied to the gate of the measuring IGBT 130 oscillated, as did the voltage resulting from the first pulse (corresponding to the one in Fig. The applied ESR voltage occurring at point 22 (designated with reference numeral 99) was large. Thus, dielectric breakdown of the gate insulating films 37 of the measured IGBT 130 was confirmed when the resistance value exceeded the gate insulation withstand voltage of the measured IGBT 130. On the other hand, based on the Fig. The results shown in the second example confirm that, while the voltage applied to the gate of the measuring IGBT 130 oscillated, the voltage value of the first pulse was reduced compared to the conventional example. Furthermore, it was found that the voltage value of the first pulse could be reduced by increasing the resistance value of the polysilicon-containing installation resistor RG. It is conceivable that if this first pulse voltage peak is small, the dielectric breakdown of the gate insulating films 37 does not occur readily, and the ESD tolerance is increased.

[0128] From the results in Fig. It is now evident from Figure 21 that the ESD evaluation circuit 90a of the semiconductor device 91a and the ESD evaluation circuit 90b of the semiconductor device 91b have the same first pulse voltage peak, and therefore the same effect on the ESD tolerance is conceivable for the semiconductor device 91a and the semiconductor device 91b. When the built-in resistor RG is added to the semiconductor device 91a, the gate-emitter capacitance CGE of the main IGBT 20 is large, while the gate resistance of the main IGBT 20 and the measuring IGBT 30 increases, thereby increasing the Miller switching period and worsening the switching loss.

[0129] On the other hand, when the built-in resistor RG is added to the semiconductor device 91b, the gate-emitter capacitance CGE in the measuring IGBT 30 is small, at 1 / 1000, relative to the main IGBT 20, while the gate resistance only of the measuring IGBT 30 increases, resulting in an extremely small Miller switching period in the measuring IGBT 30. Therefore, even with the addition of the built-in resistor RG to the semiconductor device 91b, the increase in the Miller switching period is reduced, thus minimizing the deterioration of the switching loss. Accordingly, assuming low switching loss, adding the built-in resistor RG to the semiconductor device 91b is desirable.

[0130] Preferably, the resistance value of the built-in resistor 17 can be set in a range of approximately 10 Ω to 5000 Ω. This is due to two reasons. First, if the resistance value of the built-in resistor RG, which contains polysilicon, is high, heat from the current flowing through it concentrates at the resistor, making it susceptible to damage. Unlike the damage occurring in the detection area 104 of the conventional example, in the present invention, as described above, thermal destruction occurs at the built-in resistor RG due to heat concentration at the resistor, thus reducing the ESD tolerance (corresponding to the ESD breakdown voltage on the vertical axis). Fig. 20). A second reason is that if the installation resistance RG is greater than 5000 Ω, the Miller switching period of the gate voltage of the measured IGBT 30 increases and the switching loss worsens. Therefore, the effects of both thermal destruction and switching loss can be reduced if the resistance value of the installation resistance RG is at most 5000 Ω. (Third example)

[0131] Next, a relationship was established between the ESD tolerance of the measuring IGBT 30 and a transient measuring voltage (the measuring voltage VSC applied to the measuring resistor 161, see Fig. 24) evaluated. Results of a simulation of a relationship between the resistance value (150 Ω, 200 Ω, 250 Ω) of the built-in resistor RG of the semiconductor device 91a, the ESD tolerance of the measuring IGBT 30 and the transient measuring voltage using the in Fig. The 18 ESD evaluation circuits shown (third example) 90a are in Fig. 23 are shown. Furthermore, in Fig. 23 Results of a simulation of a relationship between the ESD tolerance of the measurement IGBT 130 and the transient measurement voltage of the conventional example using the in Fig. 24 shown circuit diagrams. Fig. Figure 23 is a diagram showing the results of a simulation of the relationship between the ESD tolerance of the measurement IGBT and the transient measurement voltage of the third example. Fig. Figure 23 shows a horizontal axis and a vertical axis, each displaying results in arbitrary units.

[0132] From the in Fig.The results shown in Figure 23 demonstrate that in the conventional example, increasing the capacitance between the gates and emitters of the measuring IGBT 130 increases the ESD tolerance, but the transient measurement voltage also increases. In the third example, however, the installation resistor RG is included. Therefore, compared to the conventional example under identical conditions (except for the absence of the installation resistor RG), the ESD tolerance alone could not be increased while the transient measurement voltage remained unchanged. Furthermore, the third example confirmed that increasing the installation resistor RG of the measuring IGBT 30 only increased the ESD tolerance, while maintaining the transient measurement voltage. Thus, adding the installation resistor RG allows for an improved trade-off between the transient measurement voltage and the ESD tolerance.

[0133] The present invention can be modified in various ways, without being limited to the embodiments described above, within a scope that does not deviate from the spirit of the invention. Furthermore, the present invention is implemented in a similar manner if the conductivity types (n-type, p-type) are interchanged. COMMERCIAL APPLICABILITY

[0134] As described above, the semiconductor device according to the present invention is useful for semiconductor devices that have a measuring IGBT on a single semiconductor substrate with a main IGBT, which detects an overcurrent flowing in the main IGBT, and is particularly useful for IPMs that have a built-in control IC. REFERENCE MARK LIST 1 active area 2 active area of ​​the first cell area 3 active area of ​​the second cell area 4 Detection area of ​​the second cell area of ​​the active area 5 Extraction area of ​​the second cell area of ​​the active area 6 Edge finishing area 7 Semiconductor substrate 10, 10', 70, 80, 91a, 91b Semiconductor device 11 Emitter connection area 12 Gate connection area 13 scanning polysilicon layer 13b outer edge edges of the first section of the installation resistance area 14 Sampling emitter connection area 15 Gate Runners 16, 16' extended section of the Gate Runner 17, 81 Installation resistance range 17a, 17a', 81a first section of the installation resistance range 17b, 17b', 19, 19', 71, 73, 73', 74, 74', 81b second section of the installation resistance range 18, 18' sampling capacity range 21 n - -like drift range 22, 32 p-like basal regions 23 Storage area 24, 34 n + -like emitter regions 25, 35 p + -like contact areas 26, 36 trenches 27, 37 insulating interlayer films 28, 38 Gate electrodes 29 p + -like collector area 41, 42 p + -like isolation areas 43a local insulating film 43b Field oxide layer 44 insulating interlayer film 45, 46, 46' Contact holes 47 Passivation film 48a, 48b Openings of the passivation film 51, 52 emitter electrodes 53 Gate-runner metal layer 54, 54' extended section of the gate runner metal layer 55 Gate contact pads metal layer 56 Collector electrode 61 Field boundary ring 62 Polysilicon layer 63 Field plate 72, 72' sampling capacity ranges 75 Section of the polysilicon layer 83 Polysilicon layer 90a, 90b ESD evaluation circuits 92 switches 93 Power source 94 Conductor inductance 95 resistance load 96 Capacitor RS measuring resistor X direction parallel to the front surface of the semiconductor substrate (first direction) Y direction perpendicular to the first direction and parallel to the front surface of the semiconductor substrate (second direction) Z Thickness direction w1 Length of the second area of ​​the installation resistance area w2 Width of the second area of ​​the installation resistance range w3 Distance between built-in resistance range and sampling capacitance range w11 Width of the second area of ​​the installation resistance range t Thickness of the installation resistance area

Claims

[1] Semiconductor device (10, 10', 70, 80, 91a, 91b), comprising: an active region (1, 101) arranged on a semiconductor substrate (7, 107); and a termination region (6, 106) which is arranged in the semiconductor substrate (7, 107) and surrounds an edge of the active region (1, 101), wherein the active area (1,101) comprises: a first cell area (2, 102) in which a first bipolar transistor (20) with insulated gate electrode (28) is arranged, and a second cell area (3, 103) arranged next to the first cell area (2, 102), wherein the second cell area (3, 103) comprises: a first region in which a second bipolar transistor (30) with an insulated gate electrode (38) is arranged, wherein the second bipolar transistor (30) with an insulated gate electrode (38) has a smaller arithmetic area than the first bipolar transistor (20) with an insulated gate electrode, and a second area that separates the first cell area (2, 102) and the first area, wherein The second area includes: a first gate electrode layer (13) arranged over an oxide film on the semiconductor substrate (7, 107) and having an installation resistance area (17), and an emitter electrode (52, 152) of the second bipolar transistor (30) with an insulated gate electrode (38) which is arranged over an insulating intermediate layer film (44, 144) on the first gate electrode layer (13), wherein the termination region (6, 106) comprises a gate runner (15, 115) arranged above the oxide film on the semiconductor substrate (7, 107), wherein the gate runner (15, 115) surrounds an edge of the active region (1, 101) and is connected to a plurality of first gate electrodes (28) of the first insulated-gate bipolar transistor, wherein the first gate electrode layer (13) comprises: a first gate electrode layer section (17a) which is electrically connected to a plurality of second gate electrodes (38) of the second bipolar transistor (30) with insulated gate electrode (38), and a second gate electrode layer section (17b) in the second region, which has a planar shape extending from the first gate electrode layer section (17a) to the gate runner (15, 115), wherein the second gate electrode layer section (17b) electrically connects the first gate electrode layer section (17a) and the gate runner (15, 115), wherein the installation resistance area (17) comprises the first gate electrode layer section (17a) and the second gate electrode layer section (17b), and the second gate electrode layer section (17b) has a resistance value in the range of 10 Ω to 5000 Ω. [2] Semiconductor device (10, 10', 70, 80, 91a, 91b) according to claim 1, wherein the second gate electrode layer section (17b) has a planar shape extending linearly from the first gate electrode layer section (17a) to the gate runner (15, 115), wherein the second gate electrode layer section (17b) connects the first gate electrode layer section and the gate runner (15, 115). [3] Semiconductor device (10, 10', 70, 80, 91a, 91b) according to claim 1, wherein the second gate electrode layer section (17b) has a planar shape which meanders from the first gate electrode layer section to the gate runner (15, 115), wherein the second gate electrode layer section connects the first gate electrode layer section and the gate runner (15, 115). [4] Semiconductor device (10, 10', 70, 80, 91a, 91b) according to claim 1, wherein the second gate electrode layer section has a planar shape extending in an L-shape along an outer edge of the second region from the first gate electrode layer section to the gate runner (15, 115) and connecting the first gate electrode layer section and the gate runner (15, 115). [5] Semiconductor device (10, 10', 70, 80, 91a, 91b) according to claim 1, wherein the second gate electrode layer section (17b) has two second gate electrode layer sections (73, 74) between the first gate electrode layer section (17a) and the gate runner (15, 115) which are connected in parallel. [6] Semiconductor device (10, 10', 70, 80, 91a, 91b) according to claim 1, wherein the gate-runner (15, 115) has an extended section that extends along an outer edge of the second region and surrounds an edge of the first region (17a), and wherein the second gate electrode layer section (17b) has a planar shape extending from the first gate electrode layer section (17a) to the extended section of the gate runner (15, 115), and wherein the second gate electrode layer section (17b) connects the first gate electrode layer section (17a) and the extended section of the gate runner (15, 115). [7] Semiconductor device (10, 10', 70, 80, 91a, 91b) according to claim 1, further comprising: a third area in the active area (1, 101), which is a section without the first cell area (2, 102) and the second cell area (3, 103), and which is located next to the termination area (6, 106); a second gate electrode layer (83) in the third region, which is arranged over the oxide film on the semiconductor substrate (7, 107); and a gate terminal area (12, 38, 112) which is arranged over the insulating intermediate layer film (44, 144) on the second gate electrode layer, wherein the second gate electrode layer (83) comprises: a third gate electrode layer section (81a) which is opposite the gate contact surface (12, 38, 112) across the insulating intermediate layer film (44, 144), and a fourth gate electrode layer section (81b) in the third region, which has a planar shape extending from the third gate electrode layer section (81a) to the gate runner (15, 115), wherein the fourth gate electrode layer section (81b) electrically connects the third gate electrode layer section (81a) and the gate runner (15, 115). [8] Semiconductor device (10, 10', 70, 80, 91a, 91b) according to any one of claims 1 to 7, wherein the first bipolar transistor (20) with insulated gate electrode (28) is a trench-gate structure which has the first gate electrodes (28) extending in the depth direction of the semiconductor substrate (7, 107).

Images