semiconductor device and electrical power conversion device that it uses
The semiconductor device structure addresses misalignment in SiC power MISFETs by using a p-type potential-fixing layer to stabilize the depletion layer, ensuring high reliability and performance with improved withstand voltage and reduced switching losses.
Patent Information
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2019-10-21
- Publication Date
- 2026-03-26
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Abstract
Description
Technical field
[0001] The present invention relates to a power semiconductor device and an electrical power conversion device using the power semiconductor device, a motor system, a motor vehicle and a railway vehicle. State of the art
[0002] In the prior art, a metal insulator semiconductor field-effect transistor (MISFET) of an electrical power metal insulator film semiconductor field-effect transistor, which is a type of power semiconductor device, is mainly a power MISFET using a silicon substrate (Si substrate) (hereinafter referred to as Si power MISFET).
[0003] In contrast, a power MISFET (hereinafter referred to as a SiC power MISFET) using a silicon carbide substrate (SiC substrate) (hereinafter referred to as a SiC substrate) can exhibit a higher withstand voltage and lower losses compared to a Si power MISFET. Therefore, special attention is being paid to the area of power saving or environmentally friendly inverter technology.
[0004] The SiC power MISFET can reduce the on-resistance at the same withstand voltage compared to the Si power MISFET. This is because silicon carbide (SiC) has an electric field strength at dielectric breakdown approximately seven times that of silicon (Si), resulting in a thinner epitaxial drift layer. However, considering the original characteristics that were intended to be maintained from silicon carbide (SiC), it is still possible to achieve sufficient performance. Given the high energy efficiency required, a further reduction in on-resistance is desirable.
[0005] With reference to the high parasitic channel resistance of a doubly diffused metal-oxide-semiconductor (DMOS) structure in the prior art, publication WO 2015 / 177 914 A1 (PTL 1) discloses that by trenching a groove within the body layer on a substrate in a (0001) plane, a trench is formed, such that an (11-20) plane or a (1-100) plane with high channel mobility is used to widen the effective channel width (hereinafter referred to as trench-type DMOS). Without affecting the reliability of the bottom section of the trench when power is switched off, the parasitic channel resistance can therefore be reduced, and the on-resistance can be lowered.
[0006] Publication WO 2016 / 116 998 A1 (PTL 2) discloses a structure in which the tensile strength of the trench-type DMOS is increased by forming a flat defect region with the same polarity as the body layer (hereinafter referred to as the electric field relaxation layer) on the substrate surface. Publication JP 2018 - 037 621 A (PTL 3) discloses a semiconductor device with an n-type current distribution layer spaced apart from an n-type source region that extends from the surface of an n-type epitaxy layer to above the depth of a p-type first body layer and overlaps both regions. A p-type second body layer lies below this, also above the depth of the first body layer. Trenches extend from the source region through the first body layer to the current distribution layer and are shallower than the first body layer. A gate electrode is arranged in the trenches over a gate insulating film and, in a top view, lies within the area formed by the first and second body layers. Publication JP 2011 - 060 930 A (PTL 4) discloses a SiC semiconductor device comprising a SiC substrate with a first and second main surface, a first SiC layer of a first conductor type on the first main surface, a first SiC region of the second conductor type, a second SiC region of the first conductor type, and a third SiC region of the second conductor type on the first region. A fourth SiC region of the second conductor type is provided between opposing first SiC regions, with an intervening first SiC layer. A gate insulating film is continuous across the surfaces of the first SiC region, the first SiC layer, and the fourth SiC region; a gate electrode, covered by an intermediate layer of insulation, is located on this surface. A first electrode is electrically connected to the second and third SiC regions, and a second electrode is located on the second main surface of the substrate. The publication JP 2004 - 022 693 A (PTL 5) discloses a semiconductor device comprising a semiconductor layer of the first conduction type, base regions of the second conduction type selectively formed in pairs on the surface, source regions of the first conduction type selectively formed therein, and an electric field attenuation region of the second conduction type between the base regions on the surface. Gate electrodes are arranged between the source regions and the field attenuation region via a gate insulating film. A source electrode is connected to the source regions; the field attenuation region is insulated from the gate and source electrodes by an insulating layer. List of prior art patent literature PTL 1: WO 2015 / 177 914 A1 PTL 2: WO 2016 / 116 998 A1 PTL 3: JP 2018 - 037 621 A PTL 4: JP 2011 - 060 930 A PTL 5: JP 2004 - 022 693 A Summary of the invention: Technical problem
[0007] To form a trench bottom section in the DMOS of the PTL 1 trench type in the body layer, it is necessary to form a current diffusion layer with a higher concentration than the body layer. Since the current diffusion layer has a significantly higher concentration than the epitaxial layer, it is difficult to form a depletion layer, which is necessary to ensure the device has a high withstand voltage, and consequently, the withstand voltage is expected to decrease. Due to the misalignment of the relative formation position between the current diffusion layer and the body layer (referred to below as misalignment), a high-concentration region forms in the JFET area located between the body layers. As a result of the inhibition of depletion, the withstand voltage, determined by the weakest cell in the chip, is likely to be significantly reduced.
[0008] The relaxation layer of the electric field of PTL 2 is formed on the surface of the substrate and consequently has no effect on the misalignment of the current diffusion layer.
[0009] One object of the present invention is to create a semiconductor device which can be expected to have high performance and high reliability by improving the withstand voltage reduction due to the trench-type DMOS current diffusion layer. Solution to the problem
[0010] According to one embodiment of the present invention, a semiconductor device is provided comprising: a SiC substrate of the first conductivity type; an epitaxial layer of the first conductivity type formed on a first main surface of the SiC substrate and having an impurity concentration lower than the impurity concentration of the SiC substrate; a drain region formed on a second surface facing the first main surface of the SiC substrate; a first and a second body layer of the second conductivity type formed on the epitaxial layer; and a first source region of the first conductivity type formed on the first body layer.a first drain region of the first conductivity type, which is in contact with the first body layer and a JFET region, which is the epitaxial layer inserted through the first and second body layers, and which has an impurity concentration higher than the impurity concentration of the epitaxial layer; a second region of the second conductivity type formed on the JFET region; a first trench formed such that it extends to the first source region, the first body layer, and the first region; an insulating film formed on an inner wall of the first trench; and a gate electrode formed on the insulating film of the first trench. Advantageous effects of the invention
[0011] A highly reliable, high-performance semiconductor device is created.
[0012] Other problems and new features will become apparent from the description and accompanying drawings of this patent description. Brief description of the drawings [ Fig. 1] Fig. Figure 1 is a top view of a main part of a semiconductor chip on which several SiC power MISFETs are mounted. [ Fig. 2A] Fig. 2A is a top view of a main part of the SiC power MISFET. [ Fig. 2B] Fig. Figure 2B is a top view of a main part of a termination section of the SiC power MISFET. [ Fig. 3A] Fig. 3A is a cross-sectional view of the main part of the SiC power MISFET along line AA' of Fig. 2A. [ Fig. 3B] Fig. 3B is a cross-sectional view showing the main part of the SiC power MISFET along line BB' of Fig. 2A represents. [ Fig. 4] Fig. Figure 4 is a cross-sectional view of the main part of the SiC power MISFET along line CC' of Fig. 2A. [ Fig. 5] Fig. Figure 5 is a diagram describing a depletion layer structure of the SiC power MISFET in the trench-type (non-misaligned) DMOS when the channel is off. [ Fig. 6] Fig. Figure 6 is a diagram showing the depletion layer structure of the SiC power MISFET in the trench-type (misaligned) DMOS when the channel is off. [ Fig. 7] Fig. Figure 7 is a diagram showing the depletion layer structure of the SiC power MISFET (with misalignment) according to embodiment 1 when the channel is switched off. [ Fig. 8] Fig. Figure 8 is a diagram illustrating a manufacturing process of a silicon carbide semiconductor device according to embodiment 1. [ Fig. 9] Fig. Figure 9 is a cross-sectional view of a main part of a silicon carbide semiconductor device in process P1. [ Fig. 10A] Fig. Figure 10A is a cross-sectional view of a main part of the silicon carbide semiconductor device in process P2. [ Fig. 10B] Fig. Figure 10B is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P2. [ Fig. 10C] Fig. Figure 10C is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P2. [ Fig. 10D] Fig. Figure 10D is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P2. [ Fig. 11] Fig. Figure 11 is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P2. [ Fig. 12] Fig. Figure 12 is a cross-sectional view of the main part of the silicon carbide semiconductor device at the same location as shown in Figure 12. Fig. 6 during the manufacturing process of the silicon carbide semiconductor device following Fig. 11. [ Fig. 13] Fig. Figure 13 is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P2. [ Fig. 14] Fig. Figure 14 is a top view of the main part of the silicon carbide semiconductor device in process P4. [ Fig. 15A] Fig. Figure 15A is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P4, extending along line AA' from Fig. 14 has been taken. [ Fig. 15B] Fig. Figure 15B is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P4 along line BB' of Fig. 14. [ Fig. 16] Fig. Figure 16 is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P4, extending along line AA' from Fig. 14 has been taken. [ Fig. 17] Fig. Figure 17 is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P5. [ Fig. 18] Fig. Figure 18 is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P5. [ Fig. 19] Fig. Figure 19 is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P5. [ Fig. 20] Fig. Figure 20 is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P6. [ Fig. 21] Fig. Figure 21 is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P6. [ Fig. 22] Fig. Figure 22 is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P6. [ Fig. 23] Fig. Figure 23 is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P6. [ Fig. 24] Fig. Figure 24 is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P6. [ Fig. 25] Fig. Figure 25 is a cross-sectional view of the main part of a SiC power MISFET in embodiment 2. [ Fig. 26] Fig. Figure 26 is a diagram showing a depletion layer structure of the SiC power MISFET of the DMOS trench type (without misalignment) when the channel is turned on. [ Fig. 27] Fig. Figure 27 is a diagram showing the depletion layer structure of the SiC power MISFET (without misalignment) according to embodiment 2 when the channel is turned on. [ Fig. 28] Fig. Figure 28 is a cross-sectional view of the main part of the silicon carbide semiconductor device in a manufacturing process of the silicon carbide semiconductor device according to embodiment 2. [ Fig. 29] Fig. Figure 29 is a diagram showing the depletion layer structure of the SiC power MISFET (with large misalignment) according to embodiment 1 when the channel is switched off. [ Fig. 30] Fig. Figure 30 is a diagram showing a depletion layer structure of a SiC power MISFET (with large misalignment) according to embodiment 3 when the channel is switched off. [ Fig. 31] Fig. Figure 31 is a diagram showing a depletion layer structure of a SiC power MISFET according to embodiment 4 when the channel is turned on. [ Fig. 32] Fig. Figure 32 is a diagram showing the depletion layer structure of the SiC power MISFET according to embodiment 1 when the channel is turned on. [ Fig. 33] Fig. Figure 33 is a diagram representing a depletion layer structure of a SiC power MISFET obtained by combining embodiments 1, 2, 3 and 4 when the channel is turned on. [ Fig. 34] Fig. Figure 34 is a diagram showing a depletion layer structure of the SiC power MISFET (with orientation) obtained by combining embodiments 1, 2, 3 and 4 when the channel is switched off. [ Fig. 35] Fig. Figure 35 is a cross-sectional view of a main part of a SiC power MISFET according to embodiment 5. [ Fig. 36] Fig. Figure 36 is a cross-sectional view of the main part of the SiC power MISFET according to embodiment 5. [ Fig. 37] Fig. Figure 37 is a top view of a main part of a silicon carbide semiconductor device according to embodiment 6. [ Fig. 38] Fig. Figure 38 is a circuit diagram of an electrical power conversion device (inverter). [ Fig. 39] Fig. Figure 39 is a circuit diagram of the electrical power conversion device (inverter). [ Fig. 40] Fig. Figure 40 is a configuration diagram of an electric motor vehicle. [ Fig. 41] Fig. 41 is a circuit diagram of a boost converter. [ Fig. 42] Fig. Figure 42 is a configuration diagram of a railway vehicle. Description of embodiments
[0013] In the drawings used in the following embodiments, hatching may be added to facilitate understanding, even if the drawings are top views. In all drawings used to illustrate the following embodiments, those with essentially the same function are given the same reference numerals, and their repeated descriptions are omitted. Embodiments of the present invention are described in detail below with reference to the drawings. embodiment 1< <siliziumcarbid-halbleitervorrichtung>>
[0014] A structure of a silicon carbide semiconductor device according to embodiment 1 is described with reference to Fig. 1 described. Fig. Figure 1 is a top view of a main part of a semiconductor chip on which several SiC power MISFETs are mounted.
[0015] As in Fig. Figure 1 shows a semiconductor chip 1 on which the silicon carbide semiconductor device is mounted, with active regions (a SiC power MISFET training region and an element training region) positioned below a source wiring electrode 2 where several n-channel SiC power MISFETs are connected in parallel, and a peripheral training region surrounding the active regions in the top view. Within the peripheral training region are several p-type floating field limiting rings (FLRs) 3 configured to surround the active regions in the top view, and an n-type guard ring 4 configured to surround the multiple p-type FLRs 3 in the top view.
[0016] A gate electrode, a source region of n ++ -type and a channel region of the SiC power MISFET and the like are formed on the surface side of the active regions of the n-type silicon carbide epitaxy substrate (SiC epitaxy substrate) (hereinafter referred to as SiC expitaxy substrate) and a drain region of the n + The SiC power MISFET type is formed on the side of the rear surface of the SiC epitaxy substrate.
[0017] When multiple p-type FLRs 3 are formed in the periphery of the active regions, sections with maximum electric field move sequentially to the p-type FLRs 3 on the outer side when the power is switched off and move away from the outermost p-type FLR 3. Therefore, it is possible to cause the silicon carbide semiconductor device to exhibit a high withstand voltage. Fig. Figure 1 is an example in which three FLRs 3 of the p-type are formed, but the present invention is not limited thereto. A protective ring 4 of the n ++ The -type has a function of protecting the SiC power MISFET formed in the active area.
[0018] Several SiC power MISFETs 6, which are formed in the active area, have striped patterns in the top view and the gate electrodes of all SiC power MISFETs are electrically connected to gate wiring electrodes 8 by a feeder wiring (gate bus lines), each of which is connected with striped patterns.
[0019] The multiple SiC power MISFETs are covered with source wiring electrodes 2, and consequently, the sources and potential-fixing layers of the SiC power MISFET body layers are connected to the source wiring electrodes 2. The source wiring electrode 2 is connected to external wiring via a source opening section 7, which is provided on a passivation film that protects the semiconductor chip 1. The gate wiring electrodes 8 are configured to be separate from the source wiring electrodes 2 and are connected to the gate electrodes of the SiC power MISFETs. In the same way, the gate wiring electrodes 8 are also connected to the external wiring via gate opening sections 5, which are provided on the passivation film that protects the semiconductor chip 1. The drain region from n + -Type formed on the side of the rear surface of the n-type SiC epitaxy substrate is electrically connected to a drain wiring electrode (not shown) formed on the entire rear surface of the n-type SiC epitaxy substrate.
[0020] Next, the structure of the SiC power MISFET in the present embodiment will be described. Fig. 2A is a top view of a main part of the SiC power MISFET.
[0021] An n-type epitaxial layer 101 made of silicon carbide (SiC) with a lower impurity concentration than an n-type SiC substrate + -type is formed on a surface (first main surface) of a SiC substrate 107 of n + -type formed, which is made of silicon carbide (SiC). The epitaxial layer 101 of n - The -type functions as a drift layer. The thickness of the epitaxial layer 101, for example, is approximately 5 to 50 µm.
[0022] A p-type body layer (potential well region) 102 with a predetermined depth from the surface of the epitaxial layer 101 is formed in the epitaxial layer 101. Source regions 103 of n + -Type with a predetermined depth from the surface of the epitaxial layer 101, which contain nitrogen as defects, are formed in the body layers 102 of the p-type.
[0023] A section of the epitaxial layer 101, inserted between an adjacent body layer 102a and a body layer 102b, is referred to as the JFET region 104. Current diffusion layers 105 of n + -Type with a predetermined depth are formed from the surface of the epitaxial layer 101 such that they extend to the p-type body layers 102 and the JFET region 104. A p-type potential fixation layer 130 is formed in a section of a region located between a current diffusion layer 105a of n + -type and a current diffusion layer 105b of n + -type is inserted. The p-type potential fixing layer 130 can be in contact with the current diffusion layers 105 and need not necessarily be positioned in the middle between the current diffusion layer 105a and the current diffusion layer 105b, which are adjacent to each other.
[0024] Several trenches 106 are from the source areas 103 from n ++ -Type to the current diffusion layers 105 from n + -type formed over the p-type body layers 102. The soil surfaces of the trenches 106 are in contact with the p-type body layers 102. Although in Fig. Although not shown in Figure 2A, a gate insulation film 110 and an insulation film 117 are formed on the grooves 106, as described below. A gate electrode 111 is formed on the gate insulation film 110.
[0025] Fig. Figure 2B shows a top view of a termination region of an element formation section. The JFET region 104 is terminated by the p-type body layers 102, and the p-type potential-fixing layer 130 may or may not be connected to the body layers 102 that form termination sections. If a potential-fixing layer 130 is not connected to the body layers 102, the potential of the p-type potential-fixing layer 130 is fixed to a value that is essentially the same as the gate potential when the gate is off. The potential of the potential-fixing layer 130 is determined by a capacitance voltage division between a pn diode and a gate insulating film with respect to the gate potential, since, in general, the capacitance of the pn diode is much lower.When connected to the body layers 102, the potential-fixing layer 130 is connected to source electrodes via the p-type body layers 102, and its potential is fixed at the source potential. When the potential-fixing layer 130 and the body layers 102 are not connected, the gap width d1 between the p-type potential-fixing layer 130 and the p-type body layer 102 in a periodic structure is preferably smaller than the gap width d2. This is because a wider gap reduces the withstand voltage, thus preventing breakage of a termination section caused by a decrease in the withstand voltage.
[0026] With reference to Fig. 3A to Fig. Section 5 describes in detail the structure of embodiment 1. Fig. 3A represents a cross-sectional structure in a plane perpendicular to the main surface of the SiC substrate with line AA' on the main surface of the substrate, passing through an area where the trenches are parallel to the longitudinal direction of the trenches in Fig. 2A are trained. As in Fig. As shown in Figure 3A, apart from a source contact area (metal silicide layer) 113, the insulating film 117 is formed on a substrate main surface 134 with a flat section 139 of the surface of the JFET area 104, which is inserted between the body layers 102, and the gate electrode 111 is formed on the gate insulating film 110 and the insulating film 117 such that it extends to the source areas 103, the body layers 102 and the current diffusion layers 105, and is connected to adjacent trenches.
[0027] Meanwhile, it states Fig. 3B represents a cross-sectional structure in a plane perpendicular to the main surface of the SiC substrate with the line BB' on the main surface of the substrate, passing through an area where the trenches are not parallel to the longitudinal direction of the trenches in Fig. 2A are formed. The insulating film 117 is present on the entire main surface of the substrate except for the source contact area 113, and the gate electrode 111 is formed on the insulating film 117 such that it extends to the source areas 103, the body layers 102, the current diffusion layers 105, the JFET area 104 and the p-type potential fixing layer 130.
[0028] Fig. Figure 4 represents a cross-sectional structure in a plane perpendicular to the surface of the SiC substrate with the line CC' on the main surface of the substrate, passing through a region where the potential fixation layer 130 of p-type is perpendicular to the longitudinal direction of the trenches in Fig. 2A is formed. The insulating film 117 is present on the surface of the SiC substrate, and the gate electrode 111 is connected to adjacent cells on the insulating film 117. The p-type potential-fixing layer 130 with a predetermined depth is formed on the surface of the SiC substrate and is connected to adjacent cells. In the termination section of the active region, as described above, the potential-fixing layer 130 can be separated from the p-type + -Type connected to a Body Layer 120 or not.
[0029] For example, the depth of the p-type body layer 102 from the surface of the epitaxial layer 101 (a first depth L1) is approximately 0.5 to 2.0 µm. The depth of the source region 103 from the surface of the epitaxial layer 101 is approximately 0.5 to 2.0 µm. ++ The surface layer of epitaxial layer 101 (a third depth L3) is, for example, approximately 0.1 to 1.0 µm. A depth of the current diffusion layer 105 of n + The surface type of epitaxial layer 101 (a fourth depth L4) is, for example, approximately 0.1 to 1.0 µm. A width W1 of a section with which the current diffusion layer 105 is separated from the n + The depth of the trench 106 from the surface of the epitaxial layer 101 (a sixth depth L6) is shallower than the depth of the p-type body layer 102 from the surface of the epitaxial layer 101 (the first depth L1) and is, for example, approximately 0.1 to 1.5 µm. The length of the trench 106 in a direction parallel to the channel length is, for example, approximately 0.5 to 3.0 µm. The length of the trench 106 in a direction parallel to the channel width is, for example, approximately 0.1 to 2.0 µm. The trench spacing in a direction parallel to the channel width is, for example, approximately 0.1 to 2.0 µm. The depth of a body-layer contact region 109 from the p ++ The depth of the p-type surface of the epitaxial layer 101 (a second depth L2) is, for example, approximately 0.1 to 0.5 µm. The depth of the p-type potential fixation layer 130 is, for example, approximately 0.1 to 2.0 µm, and its width is narrower than that of the JFET region 104, being, for example, approximately 0.1 to 5.0 µm. The distance between the current diffusion layer 105 and the n + The thickness of the p-type potential-fixing layer 130 can be arbitrarily defined and is, for example, approximately 0 to 2.0 µm. The film thickness of the gate insulation film 110 is, for example, 0.005 µm to 0.015 µm. The film thickness of the thick insulation film 117 is necessarily thicker than that of the gate insulation film 110 and is, for example, approximately 0.1 to 3.0 µm.
[0030] Furthermore, “-” and “ + "Symbols that indicate relative impurity concentrations with a conductivity type of n-type or p-type, and for example, the impurity concentration of impurities of n-type takes on an order of "n - ", „n", „n + " and "n ++ " to.
[0031] A preferred range of the impurity concentration of the SiC substrate 107 from n + The -type is, for example, 1 × 10 18 up to 1 × 10 21 cm -3 A preferred region of the defect concentration of the epitaxial layer 101 from n - The -type is, for example, 1 × 10 14 up to 1 × 10 17 cm -3 For example, a preferred range of the impurity concentration of the p-type body layer 102 is 1 × 10 16 up to 1 × 10 19 cm -3 For example, a preferred range of the maximum impurity concentration of the p-type body layer 102 is 1 × 10 17 up to 1 × 10 19 cm -3 A preferred region of the impurity concentration of the source region 103 from n ++ The -type is, for example, 1 × 10 19 up to 1 × 10 21 cm -3 A preferred region of the impurity concentration of the current diffusion layer 105 from n + The -type is, for example, 5 × 10 16 up to 5 × 10 18 cm -3 A preferred region of the impurity concentration of the body-layer contact area 109 from p ++ The -type, for example, is in the range of 1 × 10 19 up to 1 × 10 21 cm -3 A preferred region of maximum defect concentration in the p-type potential fixation layer 130 is higher than the defect concentration in the current diffusion layer 105. + -type and is 1 × 10 16 up to 1 × 10 19 cm -3 .
[0032] Next, the features of the configuration of the SiC power MISFET according to embodiment 1 will be described with reference to Fig. 5 to 7 described.
[0033] The structure of the depletion layer of the trench-type DMOS in the prior art, when the channel is switched off, is described with reference to Fig. As described in Figure 5, a depletion layer end section 140a, extending from a SiC epitaxy substrate surface 141 on the upper part of the JFET region 104, and depletion layer end sections 140b and 140c, extending from the body layers 102, develop according to the increase of the applied drain-source voltage. The depletion layer end section 140a, extending from the SiC epitaxy substrate surface 141, and the depletion layer end sections 140b and 140c, extending from the body layers 102, come into contact with each other to isolate the JFET region by depletion.Consequently, the potential of the JFET region 104 is reduced, and the gate-drain withstand voltage, determined by the electric field applied to the gate insulation film 110, and a principal withstand voltage, determined by the electric field mainly applied to a junction between the body layer 102 and the JFET region 104 or the epitaxial layer 101, can be increased. Here, the current diffusion layer 105 exhibits a high concentration compared to the JFET region 104, and consequently, the depletion layer hardly develops in the current diffusion layer 105. If a misalignment occurs in the current diffusion layer 105, the depletion is therefore strongly affected, and the withstand voltage is significantly reduced.
[0034] With reference to the DMOS of the trench type in the prior art, the structure of the depletion layer, if a misalignment occurs in the flow diffusion layer 105, is described with reference to Fig. As described in Figure 6, if the current diffusion layer 105 is shifted to the horizontal right side of the substrate, the starting point of the end section 140a of the depletion layer becomes far from the body layer 102 on the left side, and consequently, the bond between the end section 140a and the end section 140b of the depletion layer becomes difficult. As a result, the potential remains near the surface of the gate insulation film 110, and the potential of the JFET region 104 acts as the drain potential. A high electric field is applied to the gate insulation film 110 or to a junction between the body layer 102 and the JFET region 104, leading to dielectric breakdown. The withstand voltage of the power device is determined by the minimum withstand voltage of several cells arranged in parallel (called the minimum ring model).Misalignment is required to assume misalignments with all a displacement of the body layer 102 and a displacement of the current diffusion layer 105 with respect to the reference mark of the lithography and the rotation of the mask, and in particular in a device with a large width of the JFET area 104 the stand voltage reduction accompanied by the misalignment becomes noticeable.
[0035] The improvement of the structure of the depletion layer by the device structure of embodiment 1 is described with reference to Fig. 7 described. In the device of Fig. 7 is also in the same way as in Fig. 6 the current diffusion layer 105 shifted to the horizontal right side of the substrate. In contrast to the trench-type DMOS, which in Fig. As shown in Figure 6, a terminal section 140d of the depletion layer develops from the p-type potential-fixing layer 130 instead of the terminal section 140a of the depletion layer from the SiC substrate surface. The starting point of terminal section 140d of this depletion layer lies at a lower position from the SiC epitaxy substrate surface 141, and consequently, the development receives hardly any influence from the current diffusion layer 105. Even if the current diffusion layer 105 is misaligned, depletion is still possible, and consequently, the tensile strength of the entire element, which is determined by the minimal ring model, is improved.
[0036] In the region where the p-type potential-fixing layer 130 is present, a pn diode of the JFET region 104 is inserted in series with the potential-fixing layer 130 in a drain-gate electrode, and consequently, the feedback capacitance is significantly improved. By appropriately designing an aspect ratio of the p-type potential-fixing layer 130 to the p-type body layer 102, the depletion can be adjusted so that the feedback capacitance-drain-voltage characteristic can be controlled to a preferred characteristic. Consequently, the reliability for dynamic characteristics such as reduced switching losses and fault ignition is improved. As described above, according to the structure of embodiment 1, it becomes possible to create a device that simultaneously achieves lower losses and higher reliability than a prior art MOS structure or a trench MOS structure.
[0037] Since it is possible to improve the withstand voltage and switching characteristics while maintaining the advantages of the trench-type DMOS with high channel mobility and wide channel width, it is possible to create a SiC power MISFET with high reliability and high performance. <<Verfahren zur Herstellung der Siliziumcarbid-Halbleitervorrichtung> >
[0038] The process for manufacturing the silicon carbide semiconductor device according to embodiment 1 describes a sequence of processes with reference to the following drawings. Fig. Figure 8 is a process diagram illustrating a method for manufacturing the semiconductor device according to embodiment 1. <Prozess P1>
[0039] In process P1, an epitaxial layer (drift layer) is formed. As in Fig. As shown in Figure 9, the 4H-SiC substrate 107 is first removed from the n + -type prepared. Defects of the n-type are introduced into the SiC substrate 107 by the n + -type introduced. The n-type defects are, for example, nitrogen (N), and the defect concentration of the n-type defects is, for example, in the range of 1 × 10 18 up to 1 × 10 21 cm -3 The SiC substrate 107 from n + The -type has an anisotropic polar plane consisting of a silicon plane and a carbon plane. In the present embodiment, the surface of the SiC substrate 107 is of the n + -Type one (0001) silicon plane and the embodiment does not limit the use of a carbon plane at all.
[0040] Next, the n-type epitaxial layer 101 made of silicon carbide (SiC) is deposited on a surface of the SiC substrate 107 by the n + -type (first main surface) formed by an epitaxial growth process. n-type defects with a lower defect concentration than the SiC substrate 107 of the n + -Type are inserted into epitaxial layer 101 by n - -Type introduced. The defect concentration of the epitaxial layer 101 from n - The type depends on the element classification of the SiC power MISFET, but is, for example, in the range of 1 × 10 14 up to 1 × 10 17 cm -3 The thickness of epitaxial layer 101 of n - -Type is, for example, 5 to 50 µm. According to the process above, the SiC epitaxy substrate is combined with the SiC substrate 107 from n + -type and the epitaxial layer 101 from n - -Type trained. <Prozess P2>
[0041] In process P2, various defects are implanted. As in Fig. As shown in figure 9, a drain area 108 is formed by n + -Type with a predetermined depth (seventh depth L7) from the rear surface of the SiC substrate 107 from n + -Type (second main surface) on the rear surface of the SiC substrate 107 from n + -type formed. The defect concentration of the drain area 108 from n + The -type, for example, is in the range of 1 × 10 19 up to 1 × 10 21 cm -3 .
[0042] As in Fig. As shown in 10A, next a mask M11 is applied to the surface of the epitaxial layer 101 by n - -type. The thickness of mask M11 is, for example, approximately 1.0 to 3.0 µm. The width of mask M11 in the element formation area is, for example, approximately 1.0 to 10.0 µm. An inorganic material such as a SiO2 film, a Si film, or a SiN film, or an organic material such as a resist film or a polyimide film can be used as the mask material.
[0043] Next, p-type defects, for example aluminum atoms (Al), are ion-implanted into the n-type epitaxial layer 101 through mask M11. Consequently, the p-type body layers 102 in the element formation area of epitaxial layer 101 are n-type. - -type. Although not shown, the p-type FLRs 3 are formed simultaneously in the periphery of the element formation area. The structure of the termination section is not limited to this and can, for example, be a transition termination extension structure (JTE structure). The p-type FLRs 3 can be formed using a different mask than the one shown in the present process.
[0044] The depth of the p-type body layer 102 from the surface of the epitaxial layer 101 (the first depth L1) is, for example, approximately 0.5 to 2.0 µm. The defect concentration of the p-type body layer 102 is, for example, in the range of 1 × 10 16 up to 1 × 10 19 cm -3 The maximum defect concentration of the body layer 102 of the p-type, for example, is in the range of 1 × 1 17 up to 1 × 10 19 cm -3 .
[0045] As in Fig. As shown in Figure 10B, after mask M11 is removed, masks M12 are formed. The thickness of mask M12 is, for example, approximately 0.5 to 3.0 µm. The width of mask M12 in the element formation area is, for example, approximately 2.0 to 10.0 µm. Mask M12 is formed, for example, with a resist film.
[0046] Next, p-type defects, for example aluminum atoms (Al), are introduced into the epitaxial layer 101 of the n - The p-type potential fixation layer 130 is ion-implanted through the masks M12. Consequently, the p-type potential fixation layer 130 is formed in the JFET region 104 between the p-type body layers 102. The depth of the p-type potential fixation layer 130 from the surface of the epitaxial layer 101 is, for example, approximately 0.1 to 2.0 µm. The defect concentration of the p-type potential fixation layer 130 is, for example, in the range of 1 × 10⁻⁶. 16 up to 1 × 10 19 cm -3 .
[0047] The process for forming the p-type body layer 102 and the p-type potential fixation layer 130 can be self-aligned. As in Fig. As shown in Figure 10C, a mask MSA1 is formed and a mask MSA2 is formed such that they partially overlap. The p-type body layers 102 are formed through masks MSA1 and MSA2 by ion implantation. As shown in Fig. As shown in the 10D diagram, after the selective removal of mask MSA2, masks MSA3 are formed to partially overlap with masks MSA1. The p-type potential fixation layer 130 is formed through masks MSA1 and MSA3 by ion implantation. A material that does not etch when masks MSA2 and MSA3 are removed is used for masks MSA1. For example, a SiO2 film, a Si film, or a SiN film can be used for masks MSA1, and a resist film can be used for masks MSA2 and MSA3. The thickness of masks MSA1, MSA2, and MSA3 is, for example, approximately 0.5 to 3.0 µm. The width of mask MSA1 is, for example, approximately 1.0 to 5.0 µm. The widths of masks MSA2 and MSA3 are each values obtained by subtracting the overlap width with masks MSA1 from the values of masks M11 and M12, respectively.The overlap width of mask MSA1 with mask MSA2 or MSA3 is 0.3 µm to 4.7 µm. This overlap width is preferably larger than the assumed misalignment width of the lithography apparatus used. With the above refinement, the accuracy of the relative positions of the p-type body layers 102 and the p-type potential fixation layer 130 can be improved, the tensile stress and element loss can be reduced, and the yield can be increased.
[0048] As in Fig. As shown in Figure 11, after all masks on the substrate have been removed, masks M13 are formed, for example, with a resist film. The thickness of mask M13 is, for example, approximately 0.5 to 3.0 µm. The width of mask M13 is, for example, approximately 0.5 to 4.0 µm. Mask M13 is located in the formation sections of source areas 103 from n ++ -type open. Although not shown, the mask M13 is provided with an opening section in an area where a protective ring 4 is formed around the circumference of the FLR 3. n-type impurities, for example nitrogen atoms (N) and phosphorus atoms (P), are ion-implanted into the p-type body layers 102 through the masks M13, the source regions 103 of the n ++ -Type are formed and, although not shown, the protective ring 4 is formed by the n ++ -Type trained in the peripheral training area.
[0049] As in Fig. As shown in Figure 12, the masks M13 are removed next to form a mask M14. The mask M14 is formed, for example, with a resist film. The thickness of the mask M14 is, for example, approximately 0.5 to 3.0 µm. The mask M14 opens the formation section of the body-layer contact area 109 from p ++ -Type. p-type defects are ion-implanted into the p-type body layers 102 through the mask M14 to isolate the body-layer contact area 109 from the p ++ -type to form. A depth of the body-layer contact area 109 from p ++ The defect concentration of the surface of the p-type body layer 102 (the second depth L2) is, for example, approximately 0.1 to 0.5 µm. ++ -Type is, for example, a size of 1 × 10 19 up to 1 × 10 21 cm -3 .
[0050] As in Fig. As shown in Figure 13, the mask M14 is removed next, and a mask M15 is formed, for example, with a resist film. The thickness of the mask M15 is, for example, approximately 1 to 4 µm. The mask M15 opens the formation section of the current diffusion layer 105 from n + -Type. The n-type defects are incorporated into epitaxial layer 101 by the n - -type and the body layer 102 of the p-type through the mask M15 ion-implanted to the current diffusion layer 105 of the n + -type to train. <Prozess P3>
[0051] In process P3, an activation cure is performed. After the masks M15 are removed (though not shown), a carbon film (C-film) is deposited on the surface and back surface of the SiC epitaxy substrate, for example, by a plasma CVD process. The thickness of the carbon film (C-film) is approximately 0.03 µm. Once the surface and back surface of the SiC epitaxy substrate are covered with the carbon film (C-film), the SiC epitaxy substrate undergoes heat treatment at a temperature of 1500 °C or higher for approximately 2 to 3 minutes. Consequently, any defect implanted into the SiC epitaxy substrate is activated. After the heat treatment, the carbon film (C-film) is removed, for example, by an oxygen plasma treatment. <Prozess P4>
[0052] In process P4, trenches are formed. Fig. Figure 14 shows a top view of a main part of SiC power MISFETs connected in parallel, Fig. 15A is a cross-sectional view of the main part along line AA' in Fig. 14, which runs through an area where ditches have been formed, and Fig. 15B is a cross-sectional view of the main part along line BB' of Fig. 14, which runs through an area where the ditches are not formed. As in Fig. 15A and Fig. As shown in Figure 15B, masks M16 are formed with an insulating film, for example, a silicon oxide film. The thickness of the mask M16 is preferably greater than that of the gate insulating film 110 formed in the following processes and is, for example, about 0.01 to 4 µm. The mask M16 is provided with an opening section in the area where the grooves 106 are formed in the following processes ( Fig. 15A). The subsequent processes will be carried out with reference to Fig. 16 to 24 described the cross-sectional views of the main part along line AA' of Fig. There are 14.
[0053] As in Fig. Figure 16 shows the trenches 106, which extend to the source area 103 from n ++ -type, to the body layer 102 of the p-type and to the current diffusion layer 105 of the n + -type, formed using an anisotropic dry etching process. The depth of the formed trench is shallower than the depth of the p-type body layer 102. The depth of the formed trench is, for example, approximately 0.1 to 1.5 µm. The length in the direction parallel to the channel length of the trench is, for example, approximately 0.5 to 3.0 µm. The length in the direction parallel to the channel width of the trench is, for example, approximately 0.1 to 1.0 µm. The trench spacing in the direction parallel to the channel width is, for example, approximately 0.1 to 1.0 µm. In the dry etching process, the shoulder of the opening section of the mask M16 is rounded to form the insulating film 117, which not only improves the insulating film reliability between the gate electrode and the JFET area 104, which is inserted between the body layers 102 or between the gate electrode and the source area 103, but also functions as a field insulating film. <Prozess P5>
[0054] In process P5, a gate stack is formed. As in Fig. As shown in Figure 17, the gate insulation film 110 is formed on the surface of the epitaxial layer 101, the surface of the trench 106, and the surface of the thick insulation film 117 by an isotropic deposition process. The gate insulation film 110 has a uniform film thickness on a bottom surface 135 and a side surface 133a. The gate insulation film 110 is formed with a SiO2 film, which is formed, for example, by a thermal CVD process. The thickness of the gate insulation film 110 is, for example, approximately 0.005 to 0.15 µm. The gate insulation film 110 can be selectively thickened only in the bottom section of the trench. Here, the gate insulation film 110 can be formed, for example, using a carbon layer on the main surface of the substrate by thermal oxidation. The film thickness of the isolation film 117 can be equal to or less than the film thickness of the gate isolation film 110, but is preferably thicker.In particular, if the film thickness of the insulating film 117 is equal to or more than three times the film thickness of the gate insulating film 110, the electric field of the insulating film can be effectively reduced.
[0055] As in Fig. As shown in Figure 18, a polycrystalline silicon (Si) film 111A is subsequently formed on the gate insulating film 110. The polycrystalline silicon (Si) film 111A is deposited along the surface of the insulating film 110, which was deposited in the previous process. If the insulating film 110 is thick, the polycrystalline silicon (Si) film 111A will not form along the shape of the surface of the SiC substrate and will separate, consequently reducing the concentration of the electric field at the upper corner section of the trench and improving the withstand voltage. The thickness of the polycrystalline silicon (Si) film 111A is, for example, approximately 0.01 to 4 µm. The polarity of the polycrystalline silicon (Si) film 111A can be n-type or p-type and can be adjusted according to the threshold voltage.
[0056] As in Fig. As shown in Figure 19, the polycrystalline silicon (Si) film 111A is next processed by dry etching using a mask M17 (photoresist film) to form the gate electrode 111. Additionally, a polycrystalline silicon (Si) film 111B on the p-type potential-fixing layer 130, which is inserted between the p-type body layers 102, can be exposed by dry etching. <Prozess P6>
[0057] In process P6, various electrodes are formed. As in Fig. As shown in Figure 20, an intermediate layer insulation film 112 is formed on the surface of the body layers 102, for example by a plasma CVD process, so that the gate electrode 111 and the gate insulation film 110 are covered.
[0058] As in Fig. As shown in Figure 21, the intermediate layer insulation film 112, the gate insulation film 110 and the insulation film 117 are next processed by the dry etching process using a mask M18 (photoresist film) and a section of the source area 103 is removed. ++ -Type and an opening section CNT_S, which separates the body layer contact area 109 from p ++ -Type reached, will be trained.
[0059] As in Fig. As shown in Figure 22, after the mask M18 has been removed, metal silicide layers 113 are applied to the respective surfaces of a section of the source area 103 from n ++ -Type exposed on the bottom surface of the opening section CNT_S and the body layer contact area 109 from p ++ -type, formed. Although not shown, nickel (Ni) is first deposited as the first metal film, for example by a sputtering process, to cover the intermediate insulating film 112 and the interior (the side surface and the bottom surface) of the opening section CNT_S on the surface of the epitaxial layer 101. The thickness of the first metal film is, for example, about 0.05 µm. Subsequently, the first metal film and the epitaxial layer on the bottom surface of the opening section CNT_S are reacted by performing a silicide heat treatment at 600 °C to 1000 °C, and, for example, a nickel silicide layer (NiSi layer) is formed as the metal silicide layer 113 on the respective surfaces of a section of the source areas 103 from n ++ -Type and of the body-layer contact area 109 from p ++ -Type, which are exposed at the bottom surface of an opening section CNT. Subsequently, an unreacted first metal film is removed by a wet etching process. For example, hydrogen sulfide peroxide is used as the wet etching agent.
[0060] Although not shown, the next step involves processing the intermediate layer insulation film 112 using a mask (photoresist film) and forming the opening section CNT_G, which reaches the gate electrode 111. The opening section CNT_G is provided to connect the gate wiring electrode 8 and the gate electrode 111.
[0061] As in Fig. 23, next a third metal film, for example a laminate film comprising a titanium film (Ti film), a titanium nitride film (TiN film) and an aluminum film (Al film), is applied to the opening section CNT_S, reaching the metal silicide layer 113, which is located on a section of the source areas 103 from n ++ -type and the respective surfaces of the body layer contact areas 109 from p ++ -type, and the intermediate layer insulating film 112, including the interior of the opening section CNT_G (not shown), which reaches the gate electrode 111. The thickness of the aluminum film (Al-film) is preferably, for example, 2.0 µm or more. Subsequently, the source wiring electrode 2, which is connected to a section of the source regions 103 from n ++ -type and the body-layer contact area 109 from p ++ -Type is electrically connected via the metal silicide layer 113 in the opening section CNT_S, and the gate wiring electrode 8, which is electrically connected to the gate electrode 111 via the opening section CNT_G, is formed by machining the third metal film.
[0062] Although not shown, a SiO2 film or a polyimide film is next deposited as a passivation film to cover the gate wiring electrode 8 and the source wiring electrode 2.
[0063] Although not shown, the next step is passivation by manipulating a passivation film. Here, a source electrode opening section 7 and a gate electrode opening section 5 are formed.
[0064] Although not shown, a second metal film is applied next to drain area 108 from n + -Type, for example, deposited by a sputtering process. The thickness of this second metal film is, for example, approximately 0.1 µm.
[0065] As in Fig. As shown in Figure 24, the second metal film and the drain area 108 are shown next. + -Type brought to reaction by performing a laser silicide heat treatment to form a metal silicide layer 115, so that the drain area 108 from n + -type is covered. Subsequently, a drain wiring electrode 116 is formed to cover the metal silicide layer 115. The drain wiring electrode 116 is formed by depositing a laminate film of a Ti film, a Ni film and a gold film (Au film) with a thickness of 0.5 to 1.0 µm.
[0066] Then an external wiring is electrically connected to the source wiring electrode 2, the gate wiring electrode 8 or the drain wiring electrode 116.
[0067] According to embodiment 1, as described above, the influence of the misalignment of the current diffusion layer 105 is reduced by forming the p-type potential fixing layer 130, and consequently the improvement in the withstand voltage obtained from the minimal ring model is achieved, thus significantly improving the reliability of the MISFET.
[0068] In the general DMOS structure and the trench-type DMOS, a layer inserted between the insulating film 117 and the gate insulating film 110, and facing the gate electrode 111, forms a capacitor as the main part of the feedback capacitance in the current diffusion layers 105 and the epitaxial layer 101. As shown in Fig. Figure 24 shows that, however, in the structure of embodiment 1, a section where the p-type potential-fixing layer 130 is present has the same value as a section where the pn junction is inserted in series. Therefore, the capacitance of the section can be ignored, and the feedback capacitance is significantly reduced. This effect leads to a reduction in switching losses and the prevention of faulty ignition. As described in the present embodiment, the p-type potential-fixing layer 130 can be configured to be self-aligned with respect to the p-type body layers 102. Therefore, the JFET resistance value does not increase significantly.
[0069] From the above, by forming the p-type potential-fixing layer 130 without degrading the low channel resistance as in the general trench-type MOS structure, the withstand voltage, which is a problem, is improved, so that more satisfactory switching characteristics can be achieved. Therefore, it is possible to provide a very reliable and low-loss SiC power MISFET compared to the prior art trench-type DMOS. Consequently, it is possible to provide a silicon carbide semiconductor device with high reliability and a fabrication method for it. Design 2
[0070] Fig. Figure 25 is a cross-sectional view of a main part of a SiC power MISFET according to embodiment 2 and is, in particular, an enlarged view of the area surrounding a JFET region 204. The difference from embodiment 1 is that a p-type electric field relaxation layer 231 is located directly below the surface of the SiC substrate and separated from a current diffusion layer 205. + -type to the JFET area 204 and to a p-type potential-fixing layer 230. By simultaneously using the p-type potential-fixing layer 230 and the p-type electric field relaxation layer 231, it is therefore possible to obtain the large improvement in withstand voltage while minimizing the disadvantage of each method. As in PTL 2, an electric field relaxation layer 231 is effective for improving the withstand voltage of the trench-type DMOS and protecting the gate insulation film 110. However, as described above, with respect to the misalignment of the current diffusion layer 205, the withstand voltage is not sufficiently high. As in the depletion layer distribution diagram of the trench-type DMOS in the prior art of Fig. As shown in Figure 26, when the channel is switched on (reference 240 denotes an end section of the depletion layer), a compromise relationship exists in which, due to the built-in potential between the electric field relaxation layer 231 and the epitaxial layer, the depletion layer also develops from the substrate surface over the JFET region 204 to narrow the current path, thus increasing the JFET resistance. Although not shown, even if the p-type potential-fixing layer 230 is present as a single body, the depletion layer develops from the p-type potential-fixing layer 230, and consequently, the same compromise relationship exists.Since both of the two structures have the depletion layer formed in the same position, a large improvement in withstanding voltage can be achieved by simultaneously using the p-type electric field relaxation layer 231 and the p-type potential fixing layer 230, compared to a case where only one structure is applied, while suppressing a new increase in resistance.
[0071] The depletion layer distribution according to the structure of embodiment 2, when the channel is switched on, is determined using Fig. As described in Figure 27, the p-type potential-fixing layer 230 is located in a region where the depletion layer of the n-type electric field relaxation layer 231 is present. Therefore, the increase in the depletion layer width, i.e., the JFET resistance, due to the addition of the p-type potential-fixing layer 230 is small. However, if the advantage of the significant improvement in withstand voltage provided by the p-type potential-fixing layer 230 is used to widen the JFET width, which is defined by the gap width of a p-type body layer 202, a lower JFET resistance can be obtained. From the above, by simultaneously using the p-type electric field relaxation layer 231 and the p-type potential-fixing layer 230, it is possible to realize the SiC power MISFET with lower loss and higher withstand voltage.
[0072] Although detailed descriptions are omitted, in Fig. Reference numeral 25 to 27 denotes a body layer of the p-type, reference numeral 206 denotes a trench, reference numeral 210 denotes a gate insulation film and reference numeral 217 denotes an insulation film. <<Verfahren zur Herstellung der Siliziumcarbid-Halbleitervorrichtung> >
[0073] The method for manufacturing the silicon carbide semiconductor device according to embodiment 2 is described with reference to Fig. 28 only described in the main points.
[0074] The formation process of the relaxation layer 231 of the p-type electric field can be inserted into any process as long as the process takes place after a body layer formation process and before an activation process in embodiment 1. Fig. 28, for example, represents an example where the p-type electric field relaxation layer 231 is formed after the n-type current diffusion layer 205 is formed in the process of embodiment 1.
[0075] The processes up to the formation of the n-type current diffusion layer 205 and the removal of all masks are the same as in embodiment 1. Subsequently, masks M21 are formed, for example, using resist films. p-type impurities, for example, aluminum atoms (Al), are ion-implanted through the masks M21, and the p-type electric field relaxation layer 231 is formed. The thickness of the masks M21 is, for example, about 1 to 4 µm. The aperture width of the mask M21 preferably has a width in which the entire surface of the n-type current diffusion layer 205 can be embedded. The impurity concentration of the p-type electric field relaxation layer 231 is higher than the concentration of the n-type current diffusion layer 205 at the same point on the substrate and is, for example, in the range of 1 × 10⁻⁶. 16 up to 1 × 10 19 cm -3 .
[0076] The p-type electric field relaxation layer 231 can be implanted two or more times using the same mask as the p-type current diffusion layer 205 and a mask that opens the JFET region 204. Here, the current diffusion layer 205 is self-aligned, and consequently, the influence on the channel can be minimized.
[0077] By utilizing the p-type electric field relaxation layer 231 and the p-type potential-fixing layer 230 together, the depletion layer structure is effectively used to demonstrate both high withstand voltage and low loss. The area where the insulating film is exposed to the n-type region is reduced, and consequently, the feedback capacitance is also reduced, thus reducing switching losses and preventing faulty ignition. embodiment 3
[0078] Fig. Figure 30 is a cross-sectional view of a main part of a SiC power MISFET according to embodiment 3 and is in particular an enlarged view of the area surrounding a JFET region 304. The difference from embodiment 1 described above is that a p-type potential fixing layer 330 is formed in a position that is deeper than the n-type current diffusion layer 305.
[0079] For comparison Fig. 29 represents a structure of an impoverishment layer if there is a greater misalignment than in the Fig. The example shown in Figure 7 illustrates this in the structure of embodiment 1. If the n-type current diffusion layers 105 are also present beneath the p-type potential-fixing layer 130, the terminal section 140d of the depletion layer cannot develop from the p-type potential-fixing layer 130. This is because the depletion layer cannot be blocked by the p-type potential-fixing layer 130, and the withstand voltage is significantly reduced.
[0080] In embodiment 3, as in Fig. As shown in Figure 30, the p-type potential fixing layer 330 is designed to be deeper than the n-type current diffusion layer 305. If misalignment occurs, causing the n-type current diffusion layer 305 to overlap with the p-type potential fixing layer 330, a depletion layer 340 can be reliably blocked. For a detailed description of Fig. Reference 30 is omitted, but reference 302 denotes a p-type body layer, reference 306 denotes a trench, reference 310 denotes a gate insulation film, and reference 317 denotes an insulation film.
[0081] As described above, the trench-type DMOS using the structure of embodiment 3 reliably prevents the significant reduction in withstand voltage caused by the misalignment of the n-type current diffusion layer 305, and consequently it is possible to realize a SiC power MISFET with low loss, high withstand voltage and high withstand voltage efficiency and a manufacturing method thereof. Design 4
[0082] Fig. Figure 31 represents a depletion layer structure of a SiC power MISFET according to embodiment 4 when the channel is switched on. The difference from embodiment 1 described above is that an n-type region 432 with a higher concentration than a JFET region 404 (hereinafter referred to as the counter) is formed directly below a p-type potential fixing layer 430.
[0083] For comparison Fig. 32 represents a depletion layer structure in the structure of embodiment 1 when the channel is switched on. If the potential fixing layer 130 is of the p-type, an end section 140e of the depletion layer develops even when the channel is switched on. Since the JFET region 104 is an n-type region with a low concentration, the end section 140e of the depletion layer extends to a depth greater than that of the JFET region 404, thus increasing the resistance of the JFET region.
[0084] As in Fig. In contrast to the structure of the present embodiment, as shown in Figure 31, the current path is not narrowed because a high-concentration n-type counter 432 is present, a depletion layer end 440e of the p-type potential-fixing layer 430 is located within the n-type counter 432, and the current path is not narrowed. The current can diffuse to the center of the JFET region via the high-density n-type counter 432, thus reducing the loss. In the structure of embodiment 4, the straight line connecting the p-type body layer 402 and the p-type potential-fixing layer 430 also becomes a low-concentration region, and consequently, depletion can be carried out in the same way as in the structure of embodiment 1, so that the high withstand voltage effect is not lost.
[0085] Using the relaxation layer of the electric field of embodiment 2 and the deep potential fixing layer of embodiment 3, it is possible to realize a power device with higher performance. The description is made with reference to Fig. 33 and Fig. 34, which represent the structure of the depletion layer of the DMOS of the trench type, in which a p-type electric field relaxation layer 431, a p-type deep potential fixing layer 430a, and the n-type counter 432 are formed when the channel is on or off. When the channel is on, as in Fig. As shown in Figure 33, by appropriately designing the concentration of the n-type counter 432, a lower loss can be achieved compared to the case of using only the p-type relaxation layer 431. When the channel is switched off, as in Fig. As shown in Figure 34, the high withstanding stress can be demonstrated, with the depletion layer extending from the side surface of the deep potential-fixing layer 430a of the p-type, even if a current diffusion layer 405 of the n-type exhibits a large misalignment. Detailed descriptions of Fig. References 31 to 34 are omitted, but reference 406 denotes a trench, reference 410 denotes a gate insulation film, and reference 417 denotes an insulation film.
[0086] From the above, by forming the counter 432 of the n-type with a higher concentration than the JFET area 404 directly below the potential fixing layer 430 of the p-type, the resistance of the JFET area is reduced and it is possible to realize the SiC power MISFET with the lower power loss and the higher withstand voltage. <<Verfahren zur Herstellung der Siliziumcarbid-Halbleitervorrichtung> >
[0087] A method for fabricating the silicon carbide semiconductor device according to embodiment 4 is described. Although not shown, according to embodiments 1, 2, or 3, when the potential-fixing layer 430 is formed of the p-type, the same mask is used as in the p-type potential-fixing layer 430, and the present embodiment is realized by ion implantation of n-type defects with a higher energy than that of the p-type potential-fixing layer. Design 5
[0088] Fig. Figure 35 is a cross-sectional view of a main part of a SiC power MISFET according to embodiment 5. The difference from embodiment 1 described above is that the central sections of a gate electrode 511, an insulating film 517, and an intermediate insulating film 512 are open, and a source electrode 2 is connected to a p-type potential-fixing layer 530. The p-type potential-fixing layer 530 can be connected to the source electrode 2 via a p-type body layer 502 and a p-type body layer contact area 509. ++ -type in the termination structure, however, it is generally likely that the p-type region will float due to high resistance when switching at high speed. In the structure of embodiment 5, the potential of the p-type potential fixing layer 530 is directly fixed to the source potential across its entire perimeter, and consequently, reliability can be improved when switching at high speed.
[0089] As in Fig. Figure 36 shows that the source electrode 2 and the p-type potential-fixing layer 530 are not connected via a silicide layer. Instead, the source electrode 2 can be connected in such a way that it protrudes from the p-type potential-fixing layer 530. Here, the source electrode 2 can function as a Schottky junction diode, and by reducing the current of the integrated body diode, the expansion of crystal defects during reverse excitation can be prevented, thus improving long-term reliability.
[0090] Detailed descriptions of Fig. References 35 to 36 are omitted, but reference 501 denotes an n-type epitaxial layer, reference 502 denotes a p-type body layer, and reference 503 denotes an n-type source region. ++ -Type, a reference symbol 505 designates a current diffusion layer of n + -Type, a reference numeral 506 denotes a trench, a reference numeral 507 denotes a SiC substrate of n + -Type, a reference numeral 508 designates a drain area of n + -Type, a reference numeral 509 designates a body-layer contact area from p ++ -Type, a reference numeral 510 denotes a gate insulation film, a reference numeral 513 denotes a metal silicide layer, a reference numeral 515 denotes a metal silicide layer and a reference numeral 516 denotes a drain wiring electrode. <<Verfahren zur Herstellung der Siliziumcarbid-Halbleitervorrichtung> >
[0091] The difference between a method for manufacturing a silicon carbide semiconductor device according to embodiment 5 and embodiment 1 is described.
[0092] When the gate electrode 511 is processed, a mask that is also open on the p-type potential-fixing layer 530 is used for etching. In a process for etching the intermediate insulating film 512, a gate insulating film 510, and the insulating film 517 to form a metal silicide layer 513, etching is performed using the mask that is open directly on the p-type potential-fixing layer 530. Alternatively, after the metal silicide layer 513 has formed, a contact section of the p-type potential-fixing layer 530 can also be open through a different mask. In this case, it is possible to establish contact with the p-type potential-fixing layer 530 without forming silicide. The opening width on the p-type potential-fixing layer 530 is, for example, 0.5 to 5.0 µm.
[0093] According to embodiment 5, a much more reliable silicon carbide semiconductor device than the trench-type DMOS structure and a fabrication method for it can be implemented in the same way as in embodiment 1. Furthermore, according to the present embodiment, the potential of the p-type potential-fixing layer 530 is fixed to the source potential, and the reliability during high-speed switching can be improved. If a suitable aperture width is used without the need for silicide in contact with the p-type potential-fixing layer 530, a Schottky junction diode can also be incorporated to prevent degradation during reverse excitation. In addition to high withstand voltage, low loss, and high-speed switching, a SiC power MISFET with long-term reliability can be implemented. Design 6
[0094] Fig. Figure 37 is a top view of a main part of a SiC power MISFET according to embodiment 6. The difference from embodiment 1 described above is that the p-type potential fixing layers 630 do not have a strip shape and are arranged parallel at a specific distance and are located on the longitudinal extent of the trench.
[0095] The p-type potential-fixing layer 630 improves the withstand voltage and also increases the resistance of the JFET region. In embodiment 6, by promoting depletion only near the formation area of the trenches 606, where electric fields are most concentrated, the significant improvement in withstand voltage can be achieved while minimizing the increase in loss. Detailed descriptions of Fig. 37 is omitted, but a reference 603 denotes a source range of n ++ -Type, a reference symbol 605 denotes a current diffusion layer of n + -Type and a reference numeral 609 designates a body-layer contact area from p ++ -Type. <<Verfahren zur Herstellung der Siliziumcarbid-Halbleitervorrichtung> >
[0096] A method for manufacturing a silicon carbide semiconductor device according to embodiment 6 can be implemented by changing the shape of an opening section of a mask, when the p-type potential-fixing layer 630 is formed in embodiment 1, from a strip shape to an island shape. The grid spacing of the trenches of the p-type potential-fixing layer 630 in a direction perpendicular to the longitudinal direction is preferably the same as the grid spacing of the trenches 606, but the period can, for example, be doubled. The width of the trench of the p-type potential-fixing layer 630 in the direction perpendicular to the longitudinal direction is, for example, in the range of 0.3 µm to 1.0 µm.
[0097] In this way, according to embodiment 5, a much more reliable silicon carbide semiconductor device than the trench-type DMOS structure and a manufacturing method for it can be realized in the same way as in embodiment 1, and the increase in loss can also be minimized.
[0098] Here, a semiconductor device with the SiCMISFET described in embodiments 1 to 6 can be used in various devices. Fig. Figure 38 is a circuit diagram that shows an example of an electrical power conversion device (inverter).
[0099] As in Fig. Figure 38 shows an inverter 802 comprising SiCMISFETs 804, which are switching elements, and diodes 805. In each individual phase, the SiCMISFETs 804 and the diodes 805 are connected antiparallel between an electrical power potential (Vcc) and an input potential to a load (a three-phase motor in this example) 801 (upper branch), and the SiCMISFETs 804 and the diodes 805 are connected antiparallel between an input potential of the load 801 and a reference potential (GND) (lower branch). That is, with respect to the load 801, two SiCMISFETs 804 and two diodes 805 are provided in each individual phase, and six switching elements 804 and six diodes 805 are provided in three phases. A control circuit 803 is connected to a gate electrode of each SiCMISFET 804 and the SiCMISFETs 804 are controlled by the control circuit 803.By controlling a current flowing through the SiCMISFETs 804, which configure the inverter 802, with the control circuit 803 it is therefore possible to drive the load 801.
[0100] One function of the SiCMISFETs 804, which configure the inverter 802, is described below. To control and drive the load 801, for example, a motor, it is necessary to input a sine wave of a desired voltage into the load 801. The control circuit 803 controls the SiCMISFETs 804 to perform a pulse-width modulation (PWM) operation, which dynamically changes the pulse width of a square wave. The output square wave is smoothed by passing it through the inductor, so that it becomes a desired pseudo-sine wave. The SiCMISFETs 804 have a function of generating a square wave to perform this PWM operation.
[0101] Using the semiconductor device described in embodiments 1 to 6 as SiCMISFETs 804, the performance of an electrical power conversion device, such as an inverter, can be increased. Using a semiconductor device with long-term reliability such as SiCMISFET 804 can extend the service life of the electrical power conversion device, such as an inverter. Consequently, it is possible to achieve higher performance and an extension of the service life of the motor system ( Fig. 39) using the electrical power conversion device using the semiconductor device described in embodiments 1 to 6.
[0102] Fig. Figure 39 is a circuit diagram representing another example of an electrical power conversion device (inverter). An inverter 902 has SiCMISFETs 904, which are switching elements. In this example, a load 901 is a three-phase motor. In each individual phase, the SiCMISFETs 904 are connected between an electrical power potential (Vcc) and an input potential of the load (for example, a motor) 901 (upper branch), and the SiCMISFETs 904 are connected between the input potential of the load 901 and the reference potential (GND) (lower branch). That is, in the load 901, two SiCMISFETs 904 are provided in each individual phase, and six switching elements 904 are provided in three phases. Therefore, a control circuit 903 is connected to each gate electrode of the SiCMISFETs 904 and the SiCMISFETs 904 are controlled by the control circuit 903.By controlling a current flowing through the SiCMISFETs 904, which configure the inverter 902, with the control circuit 903 it is therefore possible to drive the load 901.
[0103] One function of the SiCMISFET 904, which configures the inverter 902, is described below. As a function of the SiCMISFET, the SiCMISFET 904 generates a square wave for performing a pulse width modulation operation and also plays a role in the diode 805 in the inverter. Fig. 38. In inverter 902, for example, if the load 901 includes an inductor such as a motor, when the SiCMISFET 904 is switched off, the energy stored in the inductor is necessarily released (return current). In the electrical power conversion device of Fig. 38 The diode 805 plays such a role, while in the electrical power conversion device of Fig. 39 of the SiCMISFET 904 plays such a role. That is, a synchronous rectification drive is used. Here, the synchronous rectification drive refers to a method for turning on the gate of the SiCMISFET 904 at the time of reverse flow in order to cause the SiCMISFET 904 to be reverse-biased.
[0104] Therefore, the conduction loss during reverse current flow is determined not by a diode characteristic, but by a characteristic of the SiCMISFET 904. When synchronous rectification driving is performed, a period of inactivity is required to prevent a short circuit between the upper and lower branches, during which both the upper and lower SiCMISFETs are switched off. During this inactivity period, a built-in pn-type diode, formed by a drift layer and a p-type body layer of the SiCMISFET 904, is driven. Here, SiC exhibits a shorter charge carrier path than Si, and the loss during the inactivity period is small. The effect is, for example, the same as when diode 805 operates as a SiC Schottky junction diode.
[0105] In a manner similar to the SiCMISFET 904, using the semiconductor device described in embodiments 1 to 6, the loss during reverse current flow can be reduced, and consequently, no diode is required. Therefore, it is possible to reduce the size of an electrical power conversion device, such as an inverter. Using a semiconductor device with the long-term reliability of the SiCMISFET 904, it is possible to extend the service life of the electrical power conversion device, such as the inverter. The electrical power conversion device using the semiconductor devices described in embodiments 1 to 6 can be a motor system.Consequently, it is possible to achieve higher performance and an extension of the number of years for the use of the motor system using the electrical power conversion device using the semiconductor devices described in embodiments 1 to 6.
[0106] The above engine system can be used for motor vehicles such as hybrid vehicles, electric vehicles, and fuel cell vehicles. A motor vehicle using the engine system is referred to as follows: Fig. 40 and Fig. 41 described. Fig. Figure 40 is a schematic diagram that illustrates an example of an electric vehicle configuration, and Fig. Figure 41 is a circuit diagram that shows an example of a boost converter used in an electric motor vehicle.
[0107] As in Fig. As shown in Figure 40, the electric vehicle comprises a three-phase motor 1003, which is capable of inputting and outputting power to a drive shaft 1002, to which a drive wheel 1001a and a drive wheel 1001b are connected, an inverter 1004, which drives the three-phase motor 1003, a battery 1005, a boost converter 1008, a relay 1009 and an electrical control unit 1010, and the boost converter 1008 is connected to an electrical power line 1006, to which the inverter 1004 is connected, and to an electrical power line 1007, to which the battery 1005 is connected.
[0108] The three-phase motor 1003 comprises a synchronous generator motor with a rotor in which a permanent magnet is embedded and a stator around which a three-phase coil is wound. An inverter, as described in [reference missing], can be used as the inverter 1004. Fig. 38 and Fig. 39 are shown, to be used.
[0109] As in Fig. As shown in Figure 41, the boost converter 1008 has a configuration in which an inductor 1011 and a smoothing capacitor 1012 are connected to an inverter 1013. The inverter 1013 is configured with a SiCMISFET 1014 and a semiconductor device as described in embodiments 1 to 6 is used.
[0110] The electronic control unit 1010 from Fig. The 40 comprises a microprocessor, a memory device, and an input / output port, and receives a signal from a sensor that detects the position of the rotor of the three-phase motor 1003, a charge / discharge value of the battery 1005, and the like. A signal is then output to control the inverter 1004, the boost converter 1008, and the relay 1009.
[0111] The inverter 1004, as an electrical power conversion device, can be used in Fig. 38 or Fig. The electrical power conversion devices shown in section 39 are used. For the three-phase motor system with the three-phase motor 1003 and the inverter 1004, the three-phase motor system can be used with the devices shown in the diagram. Fig. 38 or Fig. The electrical power conversion device shown in Figure 39 is used. Consequently, it is possible to save energy, size, weight, and space in the electric vehicle.
[0112] Although the electric motor vehicle is described, the above three-phase motor system can be applied in the same way to a hybrid vehicle that also uses a power unit, and to a fuel cell vehicle in which the battery 1005 is a fuel cell stack. The motor system can also be used for railway vehicles. A railway vehicle using the three-phase motor system is described in Fig. 42 shown. Fig. Figure 42 is a circuit diagram that shows an example of a converter and an inverter included in the railway vehicle.
[0113] As in Fig. As shown in Figure 42, electrical power is supplied to the railway vehicle from an overhead contact wire OW (e.g., 25 kV) via a pantograph PG. The voltage is reduced to 1.5 kV by a transformer 1109, and the alternating current is converted into a direct current by a converter 1107. The direct current is converted back into an alternating current by an inverter 1102 via a capacitor 1108 to drive the three-phase motor, which is a load 1101. The element configuration in the converter 1107 can be a combination of a SiCMISFET and a diode, as shown in Figure 42. Fig. 38 shown, or a single SiCMISFET, as shown in Fig. 39 is shown. In the example of Fig. Figure 42 shows an example where the configuration is a single SiCMISFET 1104. A control circuit can be omitted from the diagram. In the diagram, a symbol RT denotes a rail section, a symbol WH denotes a wheel, and a three-phase motor 1101 can input and output power to a drive shaft to which the wheel WH is connected.
[0114] In this way, a three-phase motor system in which the semiconductor device described in embodiments 1 to 6 is used for an inverter or converter is used for the railway vehicle, and therefore energy savings of the railway vehicle and miniaturization and weight reduction of underbody parts are achieved. Reference symbol list 1 semiconductor chip 2 Source wiring electrode 3 floating field boundary ring 4 protective rings 5 Gate opening section 6 SiC power MISFETs 7 Source Opening Section 8 Gate wiring electrode 101, 201, 501 Epitaxial layer 102, 202, 302, 402, 502 Body layer 103, 203, 503, 603 Source area 104, 204, 304, 404, 504 JFET range 105, 205, 305, 405, 505, 605 Current diffusion layer 106, 206, 306, 406, 506, 606 ditch 107, 207, 507 SiC substrate 108, 208, 508 Drain area 109, 509, 609 Body-layer contact area 110, 210, 310, 410, 510 gate insulation film 111, 511 Gate electrode 112, 512 Interlayer insulating film 113, 513 Source contact area (metal silicide layer) 115, 515 Metal silicide layer 116, 516 Drain wiring electrode 117, 217, 317, 417, 517 insulation film 130, 230, 330, 430, 530, 630 Potential fixing layer 140, 240, 340 End section of the depletion layer 141 SiC epitaxy substrate surface 231, 431 Relaxation layer of the electric field 432 Counter 801, 901 Last 802, 902 Inverters 803, 903 Control circuit 804, 904 SiCMISFET 805 Diode 1001 drive wheel 1002 Drive shaft 1003 Three-phase motor 1004 inverters 1005 Battery 1006 electrical power line 1007 electrical power line 1008 Upgrade plates 1009 relays 1010 electronic control unit 1011 Throttle 1012 Smoothing capacitor 1013 inverters 1014 SiCMISFET 1101 Last 1102 Inverters 1104 SiCMISFET 1107 converters 1108 Capacitor 1109 Transformer
Claims
[1] Semiconductor device comprising: a SiC substrate (107; 207; 507) of a first conductivity type; an epitaxial layer (101; 201; 501) of a first conductivity type formed on a first main surface of the SiC substrate (107; 207; 507) and having a defect concentration lower than a defect concentration of the SiC substrate (107; 207; 507); a drain region (108; 208; 508) formed on a second main surface facing the first main surface of the SiC substrate (107; 207; 507); a first and a second body layer (102; 202; 302; 402; 502) of a second conductivity type, which are formed on the epitaxial layer (101; 201; 501); a first source region (103; 203; 503; 603) of the first conductivity type, which is formed on the first body layer (102; 202; 302; 402; 502); a second source area (103; 203; 503; 603) of the first conductivity type, which is formed on the second body layer (102; 202; 302; 402; 502); a first area of the first conductivity type, which is connected to the first body layer (102; 202; 302; 402; 502) and a JFET area (104; 204; 304; 404; 504), which is the epitaxial layer (101; 201; 501) that is located between the first and second body layers (102; 202; 302; 402; 502), is in contact with and has a defect concentration that is higher than the defect concentration of the epitaxial layer (101; 201; 501); a second area of the first conductivity type, which is in contact with the JFET area (104; 204; 304; 404; 504) and the second body layer (102; 202; 302; 402; 502) and has a higher defect concentration than the epitaxial layer (101; 201; 501); a third area of the second conductivity type, which is formed on the JFET area (104; 204; 304; 404; 504); a first trench designed to extend to the first source area (103; 203; 503; 603), to the first body layer (102; 202; 302; 402; 502) and to the first area; a second trench designed to extend to the second source area (103; 203; 503; 603), to the second body layer (102; 202; 302; 402; 502) and to the second area; an insulating film (117; 217; 317; 417; 517) formed on an inner wall of the first trench and the second trench; a gate electrode (111; 511) formed on the insulating film (117; 217; 317; 417; 517) of the first and second trenches; and a fourth area of the second conductivity type, which covers the first and second areas, the JFET area (104; 204; 304; 404; 504) and the second area. [2] Semiconductor device according to claim 1, wherein the first and second body layers (102; 202; 302; 402; 502), the first and second source areas (103; 203; 503; 603) and the first and second areas in a top view exhibit striped patterns and a straight line that runs through the first trench and the second sheaf, intersecting a longitudinal direction of the striped pattern. [3] Semiconductor device according to claim 1, wherein the third region is designed to be deeper than the first and the second region. [4] Semiconductor device according to claim 1, further comprising: a fifth area of the first conductivity type, which lies directly below the third area and has a defect concentration that is higher than the defect concentration of the epitaxial layer (101; 201; 501). [5] Semiconductor device according to claim 2, wherein the third area has a stripe pattern extending in the longitudinal direction of the stripe pattern. [6] Semiconductor device comprising: a SiC substrate (107; 207; 507) of a first conductivity type; an epitaxial layer (101; 201; 501) of a first conductivity type formed on a first main surface of the SiC substrate (107; 207; 507) and having a defect concentration lower than a defect concentration of the SiC substrate (107; 207; 507); a drain region (108; 208; 508) formed on a second main surface facing the first main surface of the SiC substrate (107; 207; 507); a first and a second body layer (102; 202; 302; 402; 502) of a second conductivity type, which are formed on the epitaxial layer (101; 201; 501); a first source region (103; 203; 503; 603) of the first conductivity type, which is formed on the first body layer (102; 202; 302; 402; 502); a second source area (103; 203; 503; 603) of the first conductivity type, which is formed on the second body layer (102; 202; 302; 402; 502); a first conductivity type region that is in contact with the first body layer (102; 202; 302; 402; 502) and a JFET region (104; 204; 304; 404; 504) that is the epitaxial layer (101; 201; 501) located between the first and second body layers (102; 202; 302; 402; 502) and that has an impurity concentration higher than the impurity concentration of the epitaxial layer (101; 201; 501); a second area of the first conductivity type, which is in contact with the JFET area (104; 204; 304; 404; 504) and the second body layer (102; 202; 302; 402; 502) and has a higher defect concentration than the epitaxial layer (101; 201; 501); a third area of the second conductivity type, which is formed on the JFET area (104; 204; 304; 404; 504); a first trench designed to extend to the first source area (103; 203; 503; 603), to the first body layer (102; 202; 302; 402; 502) and to the first area; a second trench designed to extend to the second source area (103; 203; 503; 603), to the second body layer (102; 202; 302; 402; 502) and to the second area; an insulating film (117; 217; 317; 417; 517) formed on an inner wall of the first trench and the second trench; a gate electrode (111; 511) formed on the insulating film (117; 217; 317; 417; 517) of the first trench and the second trench; wherein the first and second body layers (102; 202; 302; 402; 502), the first and second source areas (103; 203; 503; 603) and the first and second areas in a top view exhibit striped patterns, a straight line that runs through the first trench and the second sheaf, intersecting a longitudinal direction of the striped pattern, and the third area is formed in an island shape in a top view in an area that is inserted between the first trench and the second trench. [7] Semiconductor device according to claim 1, further comprising: a sixth area of the second conductivity type, which is formed on the first body layer (102; 202; 302; 402; 502) and has a defect concentration that is higher than a defect concentration of the first body layer (102; 202; 302; 402; 502); a seventh region of the second conductivity type, which is formed on the second body layer (102; 202; 302; 402; 502) and has a defect concentration that is higher than a defect concentration of the second body layer (102; 202; 302; 402; 502); and a source electrode connecting the first source area (103; 203; 503; 603), the sixth area, the second source area (103; 203; 503; 603) and the seventh area. [8] Semiconductor device according to claim 7, wherein the second region is connected to the source electrode. [9] Semiconductor device according to claim 8, wherein the source electrode is in contact with the JFET region (104; 204; 304; 404; 504) in a periphery of the third region. [10] Electrical power conversion device comprising: an electrical power potential; a reference potential; a load input potential; a first switching element that is connected between the electrical power potential and the load input potential; a second switching element that is connected between the reference potential and the load input potential; and a control circuit (803; 903) that controls the first switching element and the second switching element, wherein the semiconductor device according to one of claims 1 to 9 is used as the first switching element and second switching element. [11] Electrical power conversion device according to claim 10, further comprising: a first diode connected in antiparallel to the first switching element; and a second diode, which is connected antiparallel to the second switching element. [12] Engine system comprising: an electrical power conversion device that converts direct current electrical power into alternating current electrical power; and a motor driven by the electrical power conversion device, wherein the electrical power conversion device according to claim 10 is used as an electrical power conversion device. [13] Vehicle comprising: a wheel; and a drive shaft (1002) which is connected to the wheel, wherein power can be input into and output from the drive shaft (1002) by the motor system according to claim 12.
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