Printed circuit board assembly incorporating chemical vapor deposition (CVDD) diamond wires for heat transfer

Abstract

A method of forming a plate assembly comprising: Identifying (101) a location of a hotspot (14) on a semiconductor chip (10); Attaching (102) a first chemical vapor deposition diamond (CVDD) coated wire (2) to a first circuit board (1) at a location corresponding to the location of the identified hotspot (14); Applying (103) a layer of thermal paste (4) over the first CVDD-coated wire (2); and Placing (104) the semiconductor chip (10) over the layer of thermal paste (4) such that a surface of the semiconductor chip (10) is in direct contact with the layer of thermal paste (4) and such that a portion of the first CVDD-coated wire (2) extends between the identified location of a hotspot (14) on the semiconductor chip (10) and the first circuit board (1).

Description

BACKGROUND

[0001] Semiconductor chips require effective heat transfer to prevent heat buildup, which can impair chip performance and permanently damage the chip. Historically, various mechanisms have been used to dissipate heat from chips. The most common mechanism is the use of metallic fins attached to the top of the chip via thermally conductive adhesive. This has worked well in the past for single-plate designs. However, in multi-plate designs where chips are sandwiched between two plates, there is no way to place metallic fins directly above the chip.

[0002] Diamond has the highest known thermal conductivity of any material at room temperature. Chemical vapor deposition diamond (CVDD) has been used to form CVDD sheets, which are less expensive than natural diamonds. Pastes and gels made from CVDD grains are used in a variety of different manufacturing processes due to their high thermal conductivity. The CVDD coating process was developed to enable the coating of materials with a thin layer of CVDD.

[0003] Document US 2010 / 0140790 A1 discloses an integrated circuit chip with a heat spreader comprising a CVD diamond extending along the chip carrier body and thermal vias extending through the carrier body in areas free of active devices or functional elements.

[0004] There is a need for a method and apparatus that provides sufficient heat transfer at a lower cost to prevent heat buildup within the individual die. There is also a need for a method and apparatus that can be used to remove heat from the die and that can be used in multi-die assemblies. SUMMARY

[0005] The invention is defined in the independent claims. The dependent claims define embodiments of the invention.

[0006] A method for forming a plate assembly is disclosed, including: identifying a location of a hot spot on a semiconductor chip; attaching a first CVDD-coated wire to a circuit board at a location corresponding to the location of the identified hot spot; applying a layer of thermal grease over the first CVDD-coated wire; and placing the semiconductor chip over the layer of thermal grease. A surface of the semiconductor chip is in direct contact with the layer of thermal grease, and a portion of the first CVDD-coated wire extends between the identified location of a hot spot on the semiconductor chip and the first circuit board.

[0007] A plate assembly is disclosed that includes a printed circuit board, a semiconductor chip electrically coupled to the printed circuit board, and a CVDD-coated wire. A portion of the CVDD-coated wire extends between a hot spot on the semiconductor chip and the printed circuit board. The plate assembly includes a layer of thermal grease disposed between the hot spot on the semiconductor chip and the printed circuit board. The layer of thermal grease is in direct contact with a portion of the CVDD-coated wire. The CVDD-coated wire is thermally coupled to one or more heat sinks.

[0008] Due to the high thermal conductivity of the CVDD-coated wire and thermal paste, as well as the positioning of the CVDD-coated wire and thermal paste below hot spots, heat is quickly and effectively dissipated from the chip. Furthermore, the method and apparatus of the present invention can be used in multi-plate assemblies, enabling effective heat dissipation from multi-plate assemblies. BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0009] The invention will be explained in more detail below with reference to embodiments and the drawings in which they are illustrated. It should be understood that the drawings are not drawn to scale. Fig. 1 is a block diagram showing a method of forming a plate assembly with CVDD-coated wires for heat dissipation according to an example of the invention. Fig. 2 is a diagram showing a cross-sectional view of the front side of a printed circuit board after CVDD-coated wires according to an example of the invention have been attached to the printed circuit board. Fig. 3 is a diagram showing a top view of the circuit board of Fig. 2 according to an example of the invention. Fig. 4 is a diagram showing a front cross-sectional view of the circuit board assembly of Fig. Figure 3 shows after a layer of thermal paste has been applied over a portion of each CVDD-coated wire according to an example of the invention. Fig. 5 is a diagram showing a plan view of the circuit board assembly of Fig. 4 according to an example of the invention. Fig. 6 is a diagram showing a front cross-sectional view of the circuit board assembly of Fig. 5 shows after a semiconductor chip has been placed over the layer of thermal paste according to an example of the invention. Fig. 7 is a diagram showing a plan view of the circuit board assembly of Fig. 6 according to an example of the invention. Fig. 8 is a diagram showing a front cross-sectional view of the circuit board assembly of Fig. 7 shows after leads have been attached to the chip and to the circuit board according to an example of the invention. Fig. 9A is a diagram showing a plan view of the circuit board assembly of Fig. Figure 8 shows after heat sinks have been thermally coupled to each CVDD-coated wire according to an example of the invention. Fig. 9B is a diagram showing a front view of the circuit board assembly of FIG. 9A according to an example of the invention. Fig. 10 is a diagram showing a plan view of a printed circuit board assembly in which the CVDD-coated wires cross according to an example of the invention. Fig. 11 is a diagram showing a cross-sectional view of the front side of a printed circuit board assembly including two printed circuit boards according to an example of the invention and in which leads are used to couple the semiconductor chip to the printed circuit board. Fig. 12 is a diagram showing a front cross-sectional view of a printed circuit board assembly including two printed circuit boards according to an example of the invention, in which CVDD-coated wires are attached to both printed circuit boards such that the CVDD-coated wires extend both above the semiconductor chip and below the semiconductor chip. Fig. 13 is a diagram showing a front cross-sectional view of a printed circuit board assembly in which the thermal paste is distributed such that the layer of thermal paste is a single region of thermal paste extending beneath the entire lateral surface of each of the identified hot spots, according to an example of the invention. Fig. 14 is a plan view of the structure of Fig. 13 according to an example of the invention. Fig. 15 is a diagram showing a front cross-sectional view of a printed circuit board assembly including two printed circuit boards according to an embodiment of the invention and in which CVDD-coated wires extend both above the semiconductor die and below the semiconductor die. Fig. 16 is a diagram showing a front cross-sectional view of a circuit board assembly including a ball grid array for electrically coupling the semiconductor chip to the circuit board according to an example of the invention. Fig. 17 is a diagram showing a front cross-sectional view of a printed circuit board assembly including two printed circuit boards according to an example of the invention and in which a ball grid array is used to couple the semiconductor chip to the printed circuit board. Fig. 18 is a diagram showing a front cross-sectional view of a printed circuit board assembly including two printed circuit boards according to an example of the invention and in which a ball grid array is used to couple the semiconductor chip to the printed circuit board. Fig. 19 is a block diagram illustrating a method of forming a plate assembly with CVDD-coated wires for heat dissipation, wherein the CVDD-coated wires are arranged in slots according to an example of the invention. Fig. 20 is a diagram showing a front cross-sectional view of a circuit board with slots cut into the circuit board at locations corresponding to hot spots identified according to an example of the invention. Fig. 21 is a diagram showing a top view of the circuit board of Fig. 20 according to an embodiment of the invention. Fig. 22 is a diagram showing a front cross-sectional view of the circuit board assembly of Fig. 21 shows after the CVDD-coated wires have been inserted into the slots in the circuit board according to an example of the invention. Fig. 23 is a diagram showing a plan view of the circuit board assembly of Fig. 22 according to an example of the invention. Fig. 24 is a diagram showing a front cross-sectional view of the circuit board assembly of Fig. Figure 23 shows after a layer of thermal paste has been deposited over each CVDD-coated wire according to an example of the invention. Fig. 25 is a diagram showing a plan view of the circuit board assembly of Fig. 24 shows after a semiconductor chip has been placed over the layer of thermal paste according to an example of the invention. Fig. 26 is a diagram showing a plan view of the circuit board assembly of Fig. 25 according to an example of the invention. Fig. 27 is a diagram showing a front cross-sectional view of the circuit board assembly of Fig. 26 shows after leads have been attached to the chip and to the circuit board according to an example of the invention. Fig. 28 is a diagram showing a front cross-sectional view of the circuit board assembly of Fig. 26 shows after leads have been attached to the chip and to the circuit board according to an example of the invention. Fig. 29 is a diagram showing a front cross-sectional view of a printed circuit board assembly including two printed circuit boards according to an embodiment of the invention and in which leads are used to connect the semiconductor chip to the printed circuit board. Fig. 30 is a diagram showing a front cross-sectional view of a printed circuit board assembly including two printed circuit boards according to an example of the invention and in which a ball grid array is used to connect the semiconductor chip to the printed circuit board. Fig. 31 is a diagram showing a front cross-sectional view of a circuit board assembly including three circuit boards according to an example of the invention. Fig. 32 is a diagram illustrating a method of forming a printed circuit board assembly using CVDD-coated wires for both cooling the semiconductor chip and heating the semiconductor chip according to an example of the invention. Fig. 33 is a diagram showing a top view of a circuit board assembly and illustrating an example in which a CVDD-coated wire is used to both heat the circuit board and dissipate heat from the semiconductor chip according to an example of the invention. Fig. 34 is a diagram showing a top view of a circuit board assembly and illustrating an example in which a CVDD-coated wire is used to both heat the circuit board and dissipate heat from the semiconductor chip according to an example of the invention. Fig. 35 is a diagram showing a top view of a circuit board assembly and illustrating an example in which a CVDD-coated wire is used to both heat the circuit board and dissipate heat from the semiconductor chip according to an example of the invention. DETAILED DESCRIPTION

[0010] Those of ordinary skill in the art will recognize that the following description is illustrative only and not limiting in any way. Other examples will be readily apparent to those skilled in the art.

[0011] Fig. 1 shows a method 100 for forming a plate assembly with CVDD-coated wires for dissipating heat from hotspots on a semiconductor chip. A location of a hotspot on a semiconductor chip is identified (101). The location of one or more hotspots may be determined by analyzing the thermal properties of a plurality of test semiconductor chips to identify the location of hotspots on the test semiconductor chip. Hotspots may be identified using an image of the surface of the test semiconductor chip taken with a thermal imaging camera when the test semiconductor chip is operating in nominal mode (or in a conventional test mode) to precisely identify the position of the hotspots. These locations are then accurately mapped.The term "hotspot," as used in this application, is a small area within a chip that exhibits increased heat dissipation compared to the surrounding area of the chip. In one example, areas with a temperature greater than 10 percent above the temperature of the surrounding area of the chip or greater than 10 percent above an average temperature of the surface of the chip are determined as hotspots.

[0012] The test semiconductor chip used to identify the hotspots preferably has the same structure and manufacturing as the semiconductor chip used in the plate assembly so that the position of the hotspots can be accurately determined.

[0013] A CVDD-coated wire is attached (102) to a circuit board at a location corresponding to the location of the identified hotspot. Step 102 may be performed by dispensing adhesive; placing the CVDD-coated wire in a location corresponding to the location of the identified hotspot; and curing the adhesive. In the Fig. In the example shown in FIGS. 2-3, CVDD-coated wires 2, 3 are attached to the circuit board 1 using adhesive 6. A pick-and-place device can be used to precisely position the CVDD-coated wires 2, 3. The adhesive 6 can either be dispensed onto the CVDD-coated wire 2, 3 before the CVDD-coated wire 2, 3 is placed on the circuit board 1, or it can be dispensed on the circuit board 1 (e.g., along the entire length of the area of the circuit board 1 that will lie beneath a CVDD-coated wire 2, 3 or a portion thereof). The circuit board can be a conventional copper-clad circuit board.

[0014] The CVDD-coated wire 2, 3 is first formed by placing a "seed" wire in a CVDD furnace at 900°C. The diamond chemical vapor is then deposited onto this "seed" wire over a period of time. Generally, the wire chosen is either tungsten or molybdenum (although other elements can be used), as they form carbides that allow the CVDD to bond to the wire. The CVDD is "drawn" onto the wire (approximately 0.5 µm / hour) to form a uniform coating along its length. The thickness of the diamond coating is nominally up to half the diameter of the "seed" wire.

[0015] In one example, the CVDD coated wire is formed by inserting a tungsten wire into a heated CVDD furnace to form a tungsten carbide surface, followed by chemical vapor deposition of diamond material so that the diamond bonds to the tungsten carbide surface.

[0016] The CVDD-coated wire 2, 3 maintains the thermally conductive properties of diamond. In one example, the CVDD-coated wire has a width or diameter of 25–250 µm.

[0017] A layer of thermal paste is applied over the CVDD-coated wire (103). The thermal paste may be a diamond paste. In a specific example, more than 90 percent of the thermal paste layer consists of CVDD particles less than 0.5 micrometers in size, and the remaining portion of the thermal paste is a thermally conductive material (e.g., an adhesive, gel, or grease).

[0018] In a second example, the thermal paste may be a diamond paste with a CVDD content of 70-90%, where the CVDD grains have a size of 0.5-1 µm and are supported in an organic resin and solvent.

[0019] In the Fig. 4-5, a layer of thermal paste less than 40 µm thick is applied over each CVDD-coated wire 2, 3 at the location of each identified hotspot, shown as regions of thermal paste 4, 5. In this example, when the thermal paste is diamond paste, the layer of thermal paste 4, 5 is applied only to the portions of each CVDD-coated wire 2, 3 where the wire passes through a particular hotspot location or extends within an identified hotspot location; thereby saving the relatively expensive diamond paste while providing sufficient thermal conductivity to effectively dissipate heat from the identified hotspot(s).

[0020] The semiconductor chip is placed over the layer of thermal paste (104) such that a surface of the semiconductor chip is in direct contact with the layer of thermal paste and such that a portion of the CVDD-coated wire extends between the identified location of a hot spot on the semiconductor chip and the circuit board.

[0021] In the Fig. In the example shown in Figures 6-7, a semiconductor chip 10 can be pressed against the layer of thermal paste 4, 5, so that the layer of thermal paste 4, 5 expands laterally and thus has a reduced thickness compared to the layer as applied in step 102.

[0022] In the Fig. 6-7 and as discussed above, the analysis of step 101 is performed on a test semiconductor chip having the same configuration as the semiconductor chip 10 to identify hotspots at locations on the test semiconductor chip that correspond to the locations 14-15 on the chip 10. In the following examples and discussions, the locations 14-15 are referred to as hotspots on the semiconductor chip 10. However, it should be understood that the process of identifying the location of hotspots 14-15 on a test chip (not shown) is performed prior to the assembly process and is not determined using the semiconductor chip 10 that will be used in the assembly process.

[0023] In the plate arrangement of the Fig. 6-7, a portion of each CVDD-coated wire 2, 3 extends between a hotspot on the lower surface 17 of the semiconductor chip 10 and the circuit board 1, and the layer of thermal paste 4, 5 is in direct contact with a portion of each CVDD-coated wire 2, 3 and with the lower surface 17 of the semiconductor chip 10. In particular, a portion of the CVDD-coated wire 2 extends between the hotspot 14 and the circuit board 1. The region of thermal paste 4 is in direct contact with a portion of the CVDD-coated wire 2 and the lower surface 17 of the semiconductor chip 10 and extends under the entire lateral area of the hotspot 14 between the lower surface 17 of the semiconductor chip 10 and the circuit board 1. Similarly, a portion of the CVDD-coated wire 3 extends between the hotspot 15 and the circuit board 1.The region of thermal paste 5 is in direct contact with a portion of the CVDD-coated wire 3 and the lower surface 17 of the semiconductor chip 10 and extends under the entire lateral area of the hotspot 15 between the lower surface 17 of the semiconductor chip 10 and the circuit board 1.

[0024] Optionally, the thermal paste is cured (105). In one example, the thermal paste includes CVDD diamond particles suspended in an adhesive, heat-cured, thixotropic, low-viscosity epoxy casting resin such as Delo Monopox (e.g., GE725). In this example, the curing process may include heating the printed circuit board assembly at 165 °C for 60 minutes.

[0025] The chip is electrically coupled to the circuit board (106). In an example shown in Fig. 8, leads 8 are attached to the semiconductor chip 10 and the circuit board 1 to electrically couple the semiconductor chip 10 to the circuit board 1.

[0026] Referring to step 108, one or more heat sinks are coupled (e.g., attached) to the CVDD-coated wire. In the Fig. In the example shown in Figure 9A, two heat sinks are attached to the CVDD-coated wire. Specifically, a first heat sink 21 is located on one side of the plate assembly, and a second heat sink 22 is located on the opposite side of the plate assembly, with each CVDD-coated wire 2, 3 being thermally coupled at one or more ends to a respective heat sink 21, 22.

[0027] In an example shown in Fig. 9A, one or more ends of each CVDD-coated wire 2-3 extend beyond the edge of the circuit board 1, and each heat sink 21, 22 directly contacts the portion of each CVDD-coated wire 2, 3 that extends beyond the edge of the circuit board 1 to conduct heat away from the circuit board 1. In this example, the CVDD-coated wire 2 extends beyond the semiconductor chip 10, completely through the lateral extent of the thermal paste 4 underlying the hot spot 14, and protrudes from opposite edges of the circuit board 1. The CVDD-coated wire 3 extends from an area beneath the hot spot 15 through the lateral extent of the thermal paste 5 and protrudes from one edge of the circuit board 1.

[0028] In the Fig. 9A-9B, the heat sinks 21-22 do not overlap the circuit board 1 and extend outside the edges of the circuit board 1, with part or all of the respective portion of each CVDD-coated wire 2, 3 extending beyond the edges of the circuit board 1 being in direct contact with the respective heat sink 21, 22. In particular, a portion of the CVDD-coated wire 2 near one end of the CVDD-coated wire 2 is in direct contact with the heat sink 21, and a portion of the CVDD-coated wire 2 near the other end of the CVDD-coated wire 2 is in direct contact with the heat sink 22.Similarly, a portion of the CVDD-coated wire 3 near one end of the CVDD-coated wire 3 is in direct contact with the thermal paste 5, and a portion of the CVDD-coated wire 3 near the other end of the CVDD-coated wire 3 is in direct contact with the heat sink 22.

[0029] With reference to Fig. 9B, the heat sink 22 includes an upper plate 22a and a lower plate 22b, which are secured together by screws 20. The screws 20 couple the upper plate 22a and the lower plate 22b together such that the CVDD-coated wires 2, 3 directly contact both the upper plate 22a and the lower plate 22b to thermally couple the CVDD-coated wires 2, 3 to the heat sink 22.

[0030] In the Fig. 10 shown example, in step 102 of Fig. 1 CVDD-coated wires 31-34 are attached to the circuit board 1. CVDD-coated wires 31-34 extend through regions of the thermal paste 39, each region of the thermal paste 39 lying beneath one or more hot spots on the semiconductor chip 30. Each horizontally oriented CVDD-coated wire 31, 33 crosses a corresponding vertically oriented CVDD-coated wire 32, 34 within a region of the thermal paste 39. In this example, a portion of the CVDD-coated wire 33 at or near one end of the CVDD-coated wire 33 extends between the location of a hot spot on the semiconductor chip 10 and the circuit board 1, and the other end of the CVDD-coated wire 33 is thermally coupled to a heat sink 36 (e.g., a portion of the CVDD-coated wire 33 near one end of the CVDD-coated wire 33 is in direct contact with the heat sink 36).Similarly, a portion of the CVDD-coated wire 34 at or near one end of the CVDD-coated wire 34 extends between the location of a hot spot on the semiconductor chip 10 and the circuit board 1, and a portion of the CVDD-coated wire 34, at or near the other end of the CVDD-coated wire 34, is thermally coupled to a heat sink 38.

[0031] Both ends of each CVDD-coated wire 32 are thermally coupled to a heat sink 37, 38. Specifically, a portion of the CVDD-coated wire 32 near one end of the CVDD-coated wire 32 is in direct contact with a heat sink 37, and a portion of the CVDD-coated wire 32 near the other end of the CVDD-coated wire 32 is in direct contact with a heat sink 38. Similarly, a portion of the CVDD-coated wire 31 near one end of the CVDD-coated wire 31 is in direct contact with the heat sink 35, and a portion of the CVDD-coated wire 31 near the other end of the CVDD-coated wire 31 is in direct contact with a heat sink 36.

[0032] If a network of intersecting wires is to be used (e.g. a series of intersecting wires as in Fig. 10), a spot welding process could be performed to weld the joints prior to CVDD coating. In one example, wires 32, 34 are straight, and wires 31, 33 are formed to enclose an inverted "U" shape where they intersect wires 32, 34, respectively. The joints could also be bonded or plated together. Forming and joining processes are performed prior to coating the wire with CVDD.

[0033] The methods of steps 101-106 and 108 can be applied to form multi-board assemblies. Referring to step 107, a second circuit board is now attached to the first circuit board 1 to form a multi-board assembly. Fig. 11 shows an exemplary multi-board arrangement including a second circuit board 16 coupled to the circuit board 1 via spacer structures 11 such that the semiconductor chip 10 extends between the circuit board 1 and the circuit board 16.

[0034] Some or all of steps 101-106 may be performed on each board of the multi-board assembly. In an example shown in Fig. 12, steps 102-103 are performed on the circuit board 16 before the circuit board 16 is attached to the circuit board 1 (e.g., by attaching CVDD-coated wires to the circuit board 16 in a location corresponding to the location of the identified hotspot in the same manner as in Fig. 1-10). In this example, the adhesive 6 is dispensed onto the circuit board 16 and the CVDD-coated wires 18, 19 are placed at a location corresponding to the location of the identified hotspots, and the circuit board 16 is turned over and precisely aligned with the circuit board 1 so that a portion of each CVDD-coated wire 18, 19 extends between a hotspot on the top surface of the semiconductor chip 10 and the circuit board 16. Accordingly, in the plate arrangement of Fig. 12, a portion of each CVDD-coated wire 18, 19 extends between a hotspot on the top surface of the semiconductor chip 10 and the circuit board 16, and the layer of thermal paste is in direct contact with a portion of each CVDD-coated wire 18, 19 and the top surface of the semiconductor chip 10. In particular, a portion of the CVDD-coated wire 18 extends between the hotspot 14 (not shown) and the circuit board 16. The region of thermal paste 24 is in direct contact with a portion of the CVDD-coated wire 18 and the top surface of the semiconductor chip 10 and extends over the entire lateral area of the hotspot 14 between the top surface of the semiconductor chip 10 and the circuit board 16. Similarly, a portion of the CVDD-coated wire 19 extends between the hotspot 15 (not shown) and the circuit board 16.The region of thermal paste 25 is in direct contact with a portion of the CVDD-coated wire 19 and the upper surface of the semiconductor chip 10 and extends over the entire lateral area of the hotspot 15 between the upper surface of the semiconductor chip 10 and the circuit board 16.

[0035] In the plate arrangement of Fig. 13-14, the layer of thermal paste 7 forms a single area of thermal paste extending between more than one hotspot 14, 15 and the circuit board 1. In this example, the layer of thermal paste 7 extends over a large area under the semiconductor chip 10 and lies partially or completely beneath the semiconductor chip 10. The layer of thermal paste 7 extends under the entire lateral surface of each hotspot 14, 15, between each hotspot 14, 15 on the lower surface 17 of the semiconductor chip 10 and the circuit board 1, and is in direct contact with a portion of each CVDD-coated wire 2, 3 and with the lower surface 17 of the semiconductor chip 10. In one example, the semiconductor chip 10 is pressed against the layer of thermal paste 7 such that the layer of thermal paste 7 fills all voids and excludes any air between the lower surface 17 of the semiconductor chip 10 and the circuit board 1.

[0036] Multi-plate assemblies may also include the more extensive layer of thermal paste described above with respect to Fig. 13-14. This is in Fig. 15, which shows a layer of thermal paste 27 in direct contact with a portion of each CVDD-coated wire 18, 19 and with the top surface of the semiconductor chip 10. In this example, the layer of thermal paste 27 extends between each hotspot 14, 15 (not shown) on the top surface of the semiconductor chip 10 and the circuit board 16, and further extends over the entire lateral surface of each hotspot 14, 15.

[0037] In the Fig. 16-18, the semiconductor chip 10 is in step 106 of Fig. 1 (both mechanically and electrically) to the circuit board 1 using a ball grid array, wherein each ball 12 in the ball grid array extends from a contact on the semiconductor chip 10 to a corresponding contact on the circuit board 1. It is understood that the structures and methods for forming the Fig. 16-18 can be the same as in the examples of Fig. 1-15, with the exception of the use of balls 12 to electrically couple the semiconductor chip 10 to a corresponding circuit board 1, 16.

[0038] In the examples of Fig. 17-18, adhesive 6 is applied to the circuit board 16 and CVDD-coated wires 18, 19 are placed at a location corresponding to the location of the identified hotspots of the semiconductor chip 10, and the circuit board 16 is turned over and precisely aligned with the circuit board 1 such that a portion of each CVDD-coated wire 18, 19 extends between a hotspot on the upper surface of the semiconductor chip 10 and the circuit board 16. Accordingly, in the plate arrangement of Fig. 17-18 a portion of each CVDD-coated wire 18, 19 between a hot spot on the upper surface of the semiconductor chip 10 and the circuit board 16 and the layer of thermal paste is in direct contact with a portion of each CVDD-coated wire 18, 19 and the upper surface of the semiconductor chip 10.

[0039] In the multi-plate arrangement of Fig. 17, the layer of thermal paste includes the areas 4, 5, 24, 25 of thermal paste, with the thermal paste lying both below (4, 5) and above (24, 25) each identified hotspot.

[0040] In the multi-plate arrangement of Fig. 18, the layer of thermal paste 27 lies over the semiconductor chip 10, with the thermal paste lying both under (4, 5) and over (27) each identified hotspot.

[0041] Although the previous examples show CVDD-coated wires extending beyond the edges of the circuit board 1, in alternative embodiments, one or more ends of each CVDD-coated wire extend to a position near the edge of the circuit board 1. In this embodiment, heat sinks are used that partially overlap each circuit board 1, 16.

[0042] The Fig. 19-31 illustrate a method of forming a printed circuit board assembly in which, instead of attaching CVDD-coated wires to the top of the circuit board (step 102), slots are cut in the circuit board and the CVDD-coated wires are inserted into the slots.

[0043] With reference to the method 200 of Fig. 19, as described above with respect to method 100, a location of a hotspot on a semiconductor chip is identified (101). A slot is cut (201) in the circuit board at a location corresponding to the location of the identified hotspot. The slot may be cut into the top surface 63 of the circuit board 1 using a laser or a router (e.g., a cutting device that uses a rotating blade). Fig. 20-26 illustrate slot 60 cut to have a location on circuit board 1 corresponding to the location of hotspot 14 on semiconductor chip 10, and slot 61 cut to have a location on circuit board 1 corresponding to the location of hotspot 15 on chip 10. The location of slots 60-61 can be determined by identifying where the identified hotspots are located relative to an alignment indicator on semiconductor chip 10, by pinpointing the location on circuit board 1 to which semiconductor chip 10 will be attached, by determining where the alignment indicator will be positioned on circuit board 1, and by using the position of the hotspots relative to the alignment indicator to determine where slots 60-61 need to be cut.

[0044] Adhesive is dispensed (202). With reference to Fig. 22, the adhesive 61 is dispensed into the slots 60, 61.

[0045] A CVDD-coated wire is inserted into the slot (104). Fig. In the example shown in Figures 22-23, CVDD-coated wires 2, 3 are inserted into slots 60-61. A pick-and-place device can be used to precisely position the CVDD-coated wires 2, 3 in each slot 60-61. The width of each CVDD-coated wire 2, 3 is less than the size of the corresponding slot 60, 61 into which it is inserted, so that it fits into the slot.

[0046] The adhesive 6 may be dispensed into the slots 60, 61 before the CVDD-coated wires 2, 3 are inserted into the slots 60, 61. Alternatively, adhesive 61 is dispensed onto the CVDD-coated wires 2, 3 before they are inserted into the slots 60, 61.

[0047] Optionally, the adhesive can be cured to ensure that the CVDD-coated wires 2, 3 remain in their slots 60-61 during the subsequent process steps.

[0048] The process then continues in the same way, using the same materials and structures as in the examples of Fig. 1-18. In particular, a layer of thermal paste 4, 5 is applied over the respective CVDD-coated wire 2, 3 (103), as in Fig. 24, and the semiconductor chip 10 is placed over the thermal paste 4, 5 (104), as in Fig. 25. The thermal paste 4, 5 can be applied over each CVDD-coated wire 2, 3 at the location of each identified hotspot 14, 15, as shown in Fig. 24-27, or may be larger (e.g. a lateral extension, as shown in Fig. 13-14). Optionally, the thermal paste is cured (105). Fig. 27 illustrates the use of leads 8 in step 106, and Fig. Figure 28 illustrates the use of a ball grid array comprising balls 12 to couple the semiconductor chip 10 to the circuit board 1 in step 106. Fig. Figure 29 illustrates a multi-board arrangement including leads 8 for coupling the semiconductor chip 10 to the circuit board 1 and a second circuit board 49 overlying the circuit board 1 of optional step 107. Fig. 30 illustrates a multi-plate assembly using a ball grid array to couple the semiconductor chip 10 to the circuit board 1 such that the semiconductor chip 10 extends between the circuit board 1 and the circuit board 49.

[0049] In step 108, one or more heat sinks are coupled (e.g., attached) to the CVDD-coated wire, as described above with respect to the Fig. 9A, Fig. 9B, Fig. 10 described.

[0050] The CVDD-coated wires 2, 3, 18, 19 may have a rectangular cross-sectional shape, as shown in the above FIGS. Alternatively, however, the CVDD-coated wires may also have a round or rounded cross-sectional shape. In the Fig. In the example shown in Figure 31, CVDD-coated wires 82, 92 with a round shape are shown.

[0051] In the Fig. In the example shown in Figure 31, CVDD-coated wires 82 are inserted into the slots 81 on the circuit board 84. In this example, the rounded CVDD-coated wires 82 are larger than the slots 81, so that they only partially fill the slots 81. Alternatively, however, the slots 81 could be dimensioned such that CVDD-coated wires are arranged entirely within the slots 81. In this example, the thermal paste 83 is applied before the circuit board 84 is attached to the circuit board 85 and the semiconductor chip 87. CVDD-coated wires extend both above (92) and below (2, 3) each hot spot on the semiconductor chip 88. The thermal paste 93 is in direct contact with the top surface of the semiconductor chip 88 and with the CVDD-coated wires 92. In addition, CVDD-coated wires extend both above (82) and below (2, 3) each hot spot on the semiconductor chip 87.The thermal paste 83 is in direct contact with the top surface of the semiconductor chip 87 and with the CVDD-coated wires 82. The semiconductor chip 80 is coupled to the semiconductor chip 84 by solder balls 12. The spacer structures 11 are used to attach the semiconductor chip 84 to the semiconductor chip 85 and to attach the semiconductor chip 85 to the semiconductor chip 86.

[0052] CVDD-coated wires are available in the Fig. 2-18 and 20-31 are depicted as relatively straight. Alternatively, the CVDD-coated wires 2 may also have a curved shape. If the wire needs to be shaped to the desired curvature, the shaping is performed before the wire is coated with CVDD.

[0053] Fig. Figure 32 shows a method 300 for forming a printed circuit board assembly. The chip is analyzed (101) to identify hot spots. Either the CVDD-coated wires are attached to a printed circuit board (step 102); or one or more slots are cut into the printed circuit board (201), adhesive is dispensed (202), and a CVDD-coated wire is inserted into the slot (203). Steps 103-107 are then performed in the same manner as discussed with reference to the previous figures, and may use the same materials.

[0054] A switch is coupled to at least one end of the CVDD-coated wire (301), the switch being coupled to a power source and operable to conduct a current through the CVDD-coated wire to heat the semiconductor chip 10. In the Fig. 33, the switch 71 is coupled between a power source (not shown) and one end of the CVDD-coated wire 2. The other end of the CVDD-coated wire 2 is coupled to ground. In the example shown in Fig. 33, switch 71 is coupled to a power source and couples to one end of CVDD-coated wire 2. In particular, contact 74 is coupled to ground near an edge of circuit board 1. One end of wire 76 is attached (e.g., soldered) to contact 74, and the other end of wire 76 is electrically coupled (e.g., soldered) to one end of CVDD-coated wire 2. Trace 73 couples switch 71 to contact 75 near an opposite edge of circuit board 1. Wire 77 is attached (e.g., soldered) at one end to contact 75, and the other end is electrically coupled (e.g., soldered) to the other end of CVDD-coated wire 2. Switch 71 can be coupled to the CVDD-coated wire either before or after attaching the heat sink in step 108.

[0055] It is understood that the structure of Fig. 33 is exemplary and that other mechanisms for coupling the ends of the CVDD-coated wire 2 to a power source could be used, such mechanisms including, without limitation, connectors, connector receptacles, and receptacles that receive ends of CVDD-coated wire 2.

[0056] Fig. 34 shows a network of CVDD-coated wires 41, 42 that intersect at areas of thermal paste 43. In one example, one or more switches 71 are coupled to the ends of each CVDD-coated wire 41, 42 to conduct current through each CVDD-coated wire 41, 42. The network of CVDD-coated wires 41, 42 is effective both for dissipating heat from the semiconductor chip 40 during operation and for heating the semiconductor chip 40, for example, during startup. Heat sinks 45-48 may Fig. 9B, which allows for easy coupling of the ends of the CVDD-coated wires 41, 42 to the one or more switches 71. The circuit board assembly may include multiple areas of thermal paste 43, as shown in Fig. 34, each of which is located above or below an identified hotspot (not shown) or may include a larger area of thermal paste 7 that dissipates heat from more than one hotspot 14, 15, as in Fig. 35 is illustrated.

[0057] One use of this heating capability is for "cold-start" heaters. Specifically, during startup of the plate assembly, current is passed through the CVDD-coated wires 41, 42 to heat the plates / components to their safe, optimal operating temperature range. When the semiconductor chip 40 reaches the desired temperature, or after a predetermined period of time, the heating process is stopped, and the CVDD-coated wires are used exclusively to cool the semiconductor chip 40.

[0058] In a specific example, the plate assembly is control electronics for an automotive battery pack. Due to the highly integrated nature of automotive battery pack assemblies and because the control electronics in these assemblies are located near the batteries, the methods and apparatus of the present invention are effectively used for both heating and cooling.

[0059] In addition to the other advantages discussed above, the method and apparatus of the present invention add very little weight to the board assembly compared to conventional copper plate heat sinks. Furthermore, by moving the heat sink from the circuit board 1 to adjacent locations, as shown in Fig. 34, Fig. 35, some of the physical stresses caused by acceleration on the circuit board are alleviated. Furthermore, the stiffening effect of the CVDD deposition process stiffens the multilayer board, reducing flex cracking of the circuit board assembly. This allows these board assemblies to be used in harsh environments, such as those subject to high vibration or hot environments.

Claims

[1] A method of forming a plate assembly comprising: Identifying (101) a location of a hotspot (14) on a semiconductor chip (10); Attaching (102) a first chemical vapor deposition diamond (CVDD) coated wire (2) to a first circuit board (1) at a location corresponding to the location of the identified hotspot (14); Applying (103) a layer of thermal paste (4) over the first CVDD-coated wire (2); and Placing (104) the semiconductor chip (10) over the layer of thermal paste (4) such that a surface of the semiconductor chip (10) is in direct contact with the layer of thermal paste (4) and such that a portion of the first CVDD-coated wire (2) extends between the identified location of a hotspot (14) on the semiconductor chip (10) and the first circuit board (1). [2] The method of claim 1, further comprising: Cutting (201) a first slot (60) into the first circuit board (1) at a location corresponding to the location of the identified hotspot (14), wherein attaching the first CVDD-coated wire (2) includes inserting (203) the first CVDD-coated wire (2) into the first slot (60). [3] The method of claim 1, further comprising: Cutting (201) a first slot (60) into the first circuit board (1) at a location corresponding to the location of the identified hotspot (14); and Dispensing (202) adhesive (6) into the first slot (60), and wherein attaching the first CVDD-coated wire (2) includes inserting (203) the first CVDD-coated wire (2) into the first slot (60). [4] The method of claim 2, further comprising: Cutting a second slot into the first circuit board (1) at a location corresponding to the location of the identified hotspot (14); and Inserting a second CVDD-coated wire into the second slot (61), wherein the second CVDD-coated wire crosses the first CVDD-coated wire (2), wherein the layer of thermal paste (4) is in direct contact with a portion of the second CVDD-coated wire, and wherein a portion of the second CVDD-coated wire extends between the hotspot (14) and the first circuit board (1). [5] The method of claim 1, further comprising coupling one or more heat sinks (45, 46, 47, 48) to the first CVDD-coated wire (2). [6] The method of claim 1, further comprising coupling a switch (71) to one end of the first CVDD-coated wire (2) and coupling the other end of the first CVDD-coated wire (2) to ground, wherein the switch (71) is operable to conduct a current through the first CVDD-coated wire (2) to heat the semiconductor chip (10). [7] The method of claim 1, wherein a first end of the first CVDD-coated wire (2) extends beyond an edge of the circuit board (1). [8] The method of claim 1, wherein both ends of the first CVDD-coated wire (2) extend beyond the edge of the first circuit board (1). [9] The method of claim 1, further comprising: Coupling a heat sink to the first CVDD-coated wire (2), the heat sink including an upper plate directly overlying and in contact with a portion of the first CVDD-coated wire (2) extending beyond an edge of the first circuit board (1), the heat sink including a lower plate coupled to the upper plate, the lower plate directly underlyng and in contact with the portion of the first CVDD-coated wire (2) extending beyond the edge of the first circuit board (1). [10] The method of claim 1, further comprising coupling a second circuit board (16) to the first circuit board (1) such that the semiconductor chip (10) extends between the first circuit board (1) and the second circuit board (16). [11] The method of claim 1, wherein the layer of thermal paste (4) comprises diamond paste. [12] The method of claim 1, wherein the first CVDD-coated wire (2) comprises tungsten. [13] The method of claim 1, wherein more than ninety percent of the thermal paste layer consists of CVDD particles having a size of less than 0.5 micrometers and the remaining portion of the thermal paste layer comprises a thermally conductive material. [14] Plate assembly comprising: a first circuit board (1); a semiconductor chip (10) electrically coupled to the first circuit board (1); a first chemical vapor deposition (CVDD) diamond coated wire (2), wherein a portion of the first CVDD coated wire (2) extends between a hot spot (14) on the semiconductor chip (10) and the first circuit board (1); and a layer of thermal paste (4) arranged between the hot spot (14) on the semiconductor chip (10) and the first circuit board (1), wherein the layer of thermal paste (4) is in direct contact with a portion of the first CVDD-coated wire (2). [15] The plate assembly of claim 14, wherein the first circuit board (1) includes a first slot (60), the first CVDD-coated wire (2) extending within the first slot (60). [16] The printed circuit board assembly of claim 15, further comprising: a second CVDD-coated wire extending within a second slot in the first circuit board (1), the second CVDD-coated wire crossing the first CVDD-coated wire (2), a portion of the second CVDD-coated wire (2) extending between the hotspot (14) and the first circuit board (1), wherein the layer of thermal paste (4) is in direct contact with a portion of the second CVDD-coated wire, the second CVDD-coated wire crossing the first CVDD-coated wire (2). [17] The plate assembly of claim 14, further comprising a heat sink coupled to the first CVDD-coated wire (2). [18] The plate assembly of claim 14, further comprising a switch (71) coupled to one end of the first CVDD-coated wire (2), the switch (71) operable to conduct a current through the first CVDD-coated wire (2). [19] The board assembly of claim 14, wherein both ends of the first CVDD-coated wire (2) extend beyond an edge of the first circuit board (1). [20] Plate assembly comprising: a first circuit board (1); a second circuit board (49) lying over the first circuit board (1); a semiconductor chip (10) which is electrically coupled to the first circuit board (1) and is arranged between the first (1) and the second (49) circuit board; a first chemical vapor deposition diamond (CVDD) coated wire (2) extending within a first slot (60) in the first circuit board (1), wherein a portion of the first CVDD coated wire (2) extends between a hot spot (14) on the semiconductor chip (10) and the first circuit board (1); and a layer of thermal paste (4) arranged between the hotspot (14) on the semiconductor chip (10) and the first circuit board (1), wherein the layer of thermal paste (4) is in direct contact with a portion of the first CVDD-coated wire (2); and one or more heat sinks (45, 46, 47, 48) coupled to the first CVDD-coated wire (2) and to the first circuit board (1).

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