Phase-change storage with multiple stacks of PCM materials and method for their manufacture

Abstract

Method for improved linearity of a phase change memory cell structure, PCM cell structure, wherein the method comprises: Forming a lower electrode over a substrate; Forming a heating element in direct contact with a surface of the lower electrode, wherein the width of the heating element is smaller than the lower electrode; Forming a resistive cladding, thereby creating a planar surface along an entire surface, so that the planar cladding surface extends over an entire top surface of the heating element; Building a PCM stack, comprising a plurality of PCM layers, each with a different crystallization temperature, above the lower electrode, wherein the PCM stack is in direct contact with an upper surface of the resistive cladding; and Forming an upper electrode above the PCM stack, wherein the crystallization temperature varies in an ascending order from the lower electrode to the upper electrode, and most PCM layers have four layers.

Description

BACKGROUND

[0001] The present invention relates generally to semiconductor devices and their fabrication, and more particularly to a phase change memory (PCM) cell having multiple stacks of Ge-Sb-Te (germanium-antimony-tellurium or "GST") materials with different crystallization temperatures and / or different resistivity to improve device linearity.

[0002] Phase-change memory (PCM) is one of the next-generation non-volatile memory devices expected to meet the growing demand for high-performance and low-power semiconductor storage devices. In PCM devices, data can be stored and erased by heating or cooling a phase-change layer within the device. The PCM device can also be used for analog data processing applications due to the ability of multiple states to exist within the cell. Weights can be stored in the PCM cell during neural network training or inference. However, one of the challenges associated with using PCM in artificial intelligence (AI) applications is the linearity of the PCM's state.

[0003] Several documents have already been published in this technical context: Document US 2014 / 0 117 301 A1 describes an encapsulated PCM. A phase change element wraps around an upper portion of a heating element. Document US 2009 / 0 278 107 A1 describes a PCM with two different phase change materials that have different electrical properties. Document US 2009 / 0 180 314 A1 describes a multilayer, programmable, non-volatile PCRAM memory with improved resistive resistance level accuracy. Furthermore, document EP 3 608 908 A1 also describes a memory device comprising first and second types of PCMs.Additionally, document US 2012 / 0 326 111 A1 describes a germanium-rich GST-212 PC material, and document DE 603 ​​19 424 T2 also describes an electrical component containing a phase-change material, wherein the phase-change material can change between a first phase and a second phase. Finally, document US 2010 / 0 096 609 A1 also describes a PCM component with a plurality of PCM layers; and document US 2015 / 0 243 884 A1 describes a non-volatile memory cell with reduced resistance drift.

[0004] Despite the continuous improvement of PCMs, the task of improving the properties of PCMs, especially with regard to quasi-analog data processing architectures, still remains. SUMMARY

[0005] This object is achieved by the method of patent claim 1 and the semiconductor structure of patent claim 6. Further embodiments emerge from the respective dependent claims.

[0006] In one example, a method for improved linearity of a phase-change memory (PCM) cell structure is provided. The method includes forming a bottom electrode over a substrate, building a PCM stack containing a plurality of PCM layers, each with a different crystallization temperature, over the bottom electrode, and forming a top electrode over the PCM stack. The crystallization temperature varies in an ascending order from the bottom electrode to the top electrode.

[0007] In another example, a method for improved linearity of a phase-change memory (PCM) cell structure is provided. The method includes forming a bottom electrode over a substrate, building a PCM stack containing a plurality of PCM layers, each with a different crystallization temperature, over the bottom electrode, and forming a top electrode over the PCM stack. The crystallization temperature in a middle region of the PCM stack is at a low value, and the crystallization temperature in top and bottom regions of the PCM stack is at a high value.

[0008] In yet another example, a semiconductor device for improved linearity of a phase-change memory cell (PCM cell) structure is provided. The semiconductor device includes a bottom electrode disposed over a substrate, a PCM stack including a plurality of PCM layers, each with a different crystallization temperature, disposed over the bottom electrode, and a top electrode disposed over the PCM stack. The crystallization temperature varies in a descending order within part or all of the PCM stack.

[0009] In yet another example, a semiconductor structure is provided including a bottom electrode disposed over a substrate, a PCM stack including a plurality of PCM layers each having a different crystallization temperature disposed over the bottom electrode, and a top electrode disposed over the PCM stack, wherein the crystallization temperature in a middle region of the PCM stack is at a low value and the crystallization temperature in top and bottom regions of the PCM stack is at a high value.

[0010] It should be noted that the examples are described for different subject matter. In particular, some examples are described for method-type claims, while other examples are described for device-type claims.

[0011] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The invention will provide details in the following description of preferred embodiments with reference to the following figures, in which: Fig. 1 is a sectional view of a semiconductor structure including a bottom electrode formed over a substrate, according to an embodiment of the present invention; Fig. 2 a sectional view of the semiconductor structure of Fig. 1 in which a heating element is deposited and structured according to an embodiment of the present invention; Fig. 3 a sectional view of the semiconductor structure of Fig. 2 wherein a resistive cladding is deposited, according to an embodiment of the present invention; Fig. 4 a sectional view of the semiconductor structure of Fig. 3 wherein a Ge-Sb-Te (germanium-antimony-tellurium or “GST”) stack is formed, according to an embodiment of the present invention; Fig. 5 a sectional view of the semiconductor structure of Fig. 4, in which an upper electrode is formed, according to an embodiment of the present invention; Fig. 6 is a sectional view of the semiconductor structure including a bottom electrode formed over a substrate, according to another embodiment of the present invention; Fig. 7 a sectional view of the semiconductor structure of Fig. 6, wherein a GST stack is formed over the bottom electrode, according to an embodiment of the present invention; Fig. 8 a sectional view of the semiconductor structure of Fig. 7, wherein the phase change material stack is structured, according to an embodiment of the present invention; Fig. 9 a sectional view of the semiconductor structure of Fig. 8, wherein a resistive cladding is deposited over the patterned phase change material stack, according to an embodiment of the present invention; Fig. 10 a sectional view of the semiconductor structure of Fig. 9 wherein an interlayer dielectric (ILD) is deposited and planarized, according to an embodiment of the present invention; Fig. 11 a sectional view of the semiconductor structure of Fig. 10, wherein a top electrode is formed over the patterned phase change material stack, according to an embodiment of the present invention; Fig. 12 is a block diagram of an exemplary neuromorphic and synaptronic network including a crossbar of electronic synapses interconnecting electronic neurons and axons, according to an embodiment of the present invention; and Fig. 13 illustrates a block diagram of components of a data processing system including a data processing unit and a neuromorphic chip, according to an embodiment of the present invention.

[0013] In the drawings, the same or similar reference numerals designate the same or similar elements. DETAILED DESCRIPTION

[0014] Embodiments according to the present invention provide methods and devices for constructing a phase-change memory structure or phase-change memory cell (PCM cell) with multiple stacks of Ge-Sb-Te (germanium-antimony-tellurium or "GST") materials with different crystallization temperatures and / or different resistivities to improve device linearity. A GST mushroom structure and a GST enclosed cell structure are introduced, in which the crystallization temperature varies in an ascending order or descending order, or a combination of an ascending / descending order.

[0015] Embodiments according to the present invention provide methods and devices for using multiple layers of phase-change material with different crystallization temperatures to form a single PCM device for improved linearity. No diffusion barriers or passivation layers are used between the phase-change material layers.

[0016] Embodiments according to the present invention provide methods and devices for using phase-change materials in PCM cells. For phase-change materials, such as chalcogenides, phase transitions between an amorphous state and a crystalline state can be induced by applying electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by a higher resistivity than the generally crystalline state, which can be easily detected for data display.

[0017] In the active region of the cell, phase-change materials can be switched between a first structural state in which the material exists in a generally amorphous solid phase and a second structural state in which the material exists in a generally crystalline solid phase. The term "amorphous" is used to refer to a comparatively less ordered structure, more disordered than a single crystal, that exhibits detectable characteristics such as higher electrical resistivity than the crystalline phase. The term "crystalline" is used to refer to a comparatively more ordered structure, more ordered than an amorphous structure, that exhibits detectable characteristics such as lower electrical resistivity than the amorphous phase.Other material properties influenced by switching between amorphous and crystalline phases include atomic order, free electron density, and activation energy. The material can be switched to either different solid phases or mixtures of two or more solid phases to provide a grayscale between fully amorphous and fully crystalline states.

[0018] The transition from the amorphous to the crystalline state is generally a lower-current process, requiring a current sufficient to raise the phase-change material to a level between a phase transition temperature and a melting temperature. The transition from crystalline to amorphous, referred to as "reset," is generally a higher-current process involving a short, high-current-density pulse to melt or degrade the crystalline structure, followed by rapid cooling of the phase-change material to quench the phase-change process and allow at least some of the phase-change structure to stabilize in the amorphous state.

[0019] It should be noted that the present invention is described for a given illustrative architecture; however, other architectures, structures, substrate materials, and process elements and steps / blocks may be varied within the scope of the present invention. It should be noted that, for clarity, certain features may not be shown in all figures. This should not be construed as a limitation of any particular embodiment or illustration, or of the scope of the claims.

[0020] Fig. 1 is a cross-sectional view of a semiconductor structure including a bottom electrode formed over a substrate, according to an embodiment of the present invention.

[0021] A semiconductor structure 5 includes a lower electrode 12 formed over a substrate 10. The lower electrode 12 may be formed within the substrate 10.

[0022] The substrate 10 may be crystalline, semi-crystalline, microcrystalline, or amorphous. The substrate 10 may be essentially (e.g., with the exception of impurities) a single element (e.g., silicon) or predominantly a single element (e.g., with doping), such as silicon (Si) or germanium (Ge), or the substrate 10 may contain a compound, such as GaAs, SiC, or SiGe. The substrate 10 may also comprise multiple material layers. In some embodiments, the substrate 10 includes a semiconductor material, including, but not necessarily limited to, silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), Si:C (carbon-doped silicon), silicon germanium carbide (SiGeC), carbon-doped silicon germanium (SiGe:C), III-V (e.g., GaAs, AlGaAs, InAs, InP, etc.), II-V compound semiconductors (e.g., ZnSe, ZnTe, ZnCdSe, etc.), or other similar semiconductors.Furthermore, multiple layers of semiconductor materials can be used as the semiconductor material of the substrate 10. In some embodiments, the substrate 10 contains both semiconductor materials and dielectric materials. Furthermore, the semiconductor substrate 10 can also contain an organic semiconductor or a layered semiconductor, such as Si / SiGe, a silicon-on-insulator, or a SiGe-on-insulator. Part or all of the semiconductor substrate 10 can be amorphous, polycrystalline, or single-crystalline. In addition to the above-mentioned types of semiconductor substrates, the semiconductor substrate 10 used in the present invention can also contain a hybrid-oriented (HOT) semiconductor substrate, wherein the HOT substrate has surface regions with different crystallographic orientations.

[0023] The lower electrode 12 may be formed, for example, from Ta, Ti / TiN, W, WN, TaN, polysilicon, doped polysilicon, amorphous silicon, doped amorphous silicon, or any other suitable material or any other conductive material. Alternatively, the lower electrode 12 may be any conductive material or materials, for example, Ag, Al, Cu, Ta, TaN, Ti, TiN, Al, W, or any other suitable material, and may be deposited or formed in any suitable manner.

[0024] Fig. 2 is a sectional view of the semiconductor structure of Fig. 1, in which a heating element is deposited and structured, according to an embodiment of the present invention.

[0025] In various exemplary embodiments, a heating element 14 is deposited and patterned.

[0026] The heating element 14 is arranged on one side of the dielectric layer 16. The heating element 14 includes a thin layer of a refractory material having a thickness of between about 5 nanometers (nm) and about 100 nm and having a comparatively high resistivity of between about 100 ohm-centimeters (Ω cm) and about 10,000 Ω cm, e.g., between about 500 Ω cm and about 3,000 Ω cm. Suitable refractory materials include, but are not limited to, tantalum nitride (TaN) and metals having the formula Ta x Si y N z , where x, y and z are each between zero and approximately one.

[0027] The heating element 14 may contain an electrically conductive material that is chemically inert when in contact with the materials used for the PCM stack and the top electrode. Examples of such electrically conductive but chemically inert materials include carbon, TiN, and TaN. Both titanium nitride and tantalum nitride have a low diffusion rate for metallic elements. Therefore, by forming the heating element 14 from these materials, metallic elements contained in the top electrode are prevented from diffusing into the PCM stack.

[0028] The dielectric material of layer 16 may include, but is not limited to, ultra-low-k (ULK) materials such as porous silicates, carbon-doped oxides, silicon dioxides, silicon nitrides, silicon oxynitrides, carbon-doped silicon oxide (SiCOH) and porous variants thereof, silsesquioxanes, siloxanes, or other dielectric materials having, for example, a dielectric constant in the range of about 2 to about 4. The dielectric layer 16 may have the same thickness as the heating element 14.

[0029] Fig. 3 is a sectional view of the semiconductor structure of Fig. 2, in which a resistive cladding is deposited, according to an embodiment of the present invention.

[0030] In various exemplary embodiments, a resistive cladding 18 is deposited. The resistive cladding 18 may be a metal nitride layer, such as titanium nitride (TiN). The resistive cladding 18 is used to correct resistance drift.

[0031] In another embodiment, the resistive cladding 18 can be, for example, TaN with various deposition types, such as PVD, CVD, ALD, and with various resistivity values. This material is not limited by other metal types, such as TiN, W, or amorphous carbon (aC), and dielectrics such as Al2O3, HfO2, SiN, ZrO2, etc.

[0032] Fig. 4 is a sectional view of the semiconductor structure of Fig. 3, in which a Ge-Sb-Te (germanium-antimony-tellurium or “GST”) stack is formed, according to an embodiment of the present invention.

[0033] In various exemplary embodiments, a phase-change material stack 20 is deposited. The phase-change material stack 20 may be a GST stack. The GST stack 20 may include a first layer 22, a second layer 24, a third layer 26, and a fourth layer 28.

[0034] In one example, the first layer 22 may be, for example, a GST with a low germanium (Ge) concentration (less than 20% Ge content). The second layer 24 may be, for example, a GST with a medium to low Ge concentration (between 20 and 40% Ge content). The third layer 26 may be, for example, a GST with a medium Ge concentration (between 40 and 70% Ge content). The fourth layer 28 may be, for example, a GST with a high Ge concentration (over 60% Ge content). No diffusion barriers or passivation layers are used between the layers 22, 24, 26, and 28. Thus, for better linearity, multiple layers of phase-change material, e.g., GST, with different crystallization temperatures form a single PCM unit 30.

[0035] The GST stacks 20 may have different Ge / Te concentrations to obtain a melt T gradient, where a region closer to the heater 14 requires a low melt T, and different N concentrations to obtain different R values, where the N may be implanted or co-sputtered.

[0036] Fig. 5 is a sectional view of the semiconductor structure of Fig. 4, in which an upper electrode is formed, according to an embodiment of the present invention.

[0037] In various exemplary embodiments, an ILD 34 is deposited, and a top electrode 32 is formed within the ILD 34. The GST stack 20 can be patterned to form a GST stack 30. Thus, the top electrode 32 is in direct contact with the patterned GST stack 30.

[0038] Structure 35 shows the GST stack 30 formed between the top electrode 32 and the bottom electrode 12. Structure 35 thus employs multiple GST materials with different crystallization temperatures and / or different resistivities to improve the linearity of a device. Structure 35 can be described as a mushroom structure, with a higher crystallization temperature at the top of the GST stack 30 and a lower crystallization temperature at the bottom of the GST stack 30. In other words, the crystallization temperature increases with the addition of each layer. Thus, moving from bottom to top in structure 35, the crystallization temperature increases.The crystallization temperature varies in an ascending order from the lower electrode to the upper electrode, or, alternatively, the crystallization temperature varies in a descending order from the upper electrode to the lower electrode. The different crystallization temperatures can be achieved by doping and / or varying material contents.

[0039] The upper electrode 32 may be formed, for example, from Ta, Ti / TiN, W, WN, TaN, polysilicon, doped polysilicon, amorphous silicon, doped amorphous silicon, or any other suitable material or any other conductive material. Alternatively, the upper electrode 32 may be any conductive material or materials, for example, Ag, Al, Cu, Ta, TaN, Ti, TiN, Al, W, or any other suitable material, and may be deposited or formed in any suitable manner.

[0040] The ILD 34 may include any materials known in the art, such as porous silicates, carbon-doped oxides, silicon dioxides, silicon nitrides, silicon oxynitrides, or other dielectric materials. The ILD 34 may be formed using any method known in the art, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or physical vapor deposition. The ILD may have a thickness in the range of about 25 nm to about 200 nm.

[0041] Phase-change materials can be changed from one phase state to another by applying electrical pulses. A shorter, higher-amplitude pulse tends to change the phase-change material to a generally amorphous state and is referred to as a "reset pulse." A longer, lower-amplitude pulse tends to change the phase-change material to a generally crystalline state and is referred to as a "program pulse." The energy for a shorter, higher-amplitude pulse is high enough to melt the material in the active volume and short enough to allow the material to solidify in the amorphous state.

[0042] Phase change materials can include chalcogenide-based materials and other materials. Chalcogens include the four elements oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), which form part of Group VI of the periodic table. Chalcogenides include compounds of a chalcogen with a more electropositive element or radical. Chalcogenide alloys include combinations of chalcogenides with other materials, such as transition metals. A chalcogenide alloy usually contains one or more elements from column six of the periodic table, such as germanium (Ge) and tin (Sn). Often, chalcogenide alloys contain combinations containing one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag).Phase-change memory materials can include alloys of: Ga / Sb, In / Sb, In / Se, Sb / Te, Ge / Te, Ge / Sb / Te, In / Sb / Te, Ga / Se / Te, Sn / Sb / Te, In / Sb / Ge, Ag / In / Sb / Te, Ge / Sn / Sb / Te, Ge / Sb / Se / Te, and Te / Ge / Sb / S. A wide range of alloy compositions can be functional within the Ge / Sb / Te family of alloys.

[0043] Chalcogenides and other phase-change materials are doped with impurities in some embodiments to vary the conductivity, transition temperature, melting temperature, and other properties of memory elements employing doped chalcogenides. Doping materials used for chalcogenides include nitrogen, silicon, oxygen, silicon dioxide, silicon nitride, copper, silver, gold, aluminum, aluminum oxide, tantalum, and tantalum oxide. Representative impurities used for doping include tantalum oxide, tantalum nitride, titanium, and titanium oxide.

[0044] In the present example, the phase change material stack 30 preferably includes a Ge-Sb-Te (germanium-antimony-tellurium or "GST") alloy. Alternatively, other suitable materials for the phase change material stack 30 may include Si-Sb-Te alloys, Ga-Sb-Te alloys, As-Sb-Te alloys, Ag-In-Sb-Te alloys, Ge-In-Sb-Te alloys, Ge-Sb alloys, Sb-Te alloys, Si-Sb alloys, and combinations thereof.

[0045] Fig. 6 is a cross-sectional view of the semiconductor structure including a bottom electrode formed over a substrate according to another embodiment of the present invention.

[0046] A semiconductor structure 5' includes a bottom electrode 12 formed over a substrate 10. The bottom electrode 12 may be formed within the substrate 10.

[0047] Fig. 7 is a sectional view of the semiconductor structure of Fig. 6, in which a GST stack is formed over the bottom electrode, according to an embodiment of the present invention

[0048] In various exemplary embodiments, a phase-change material stack 40 is deposited. The phase-change material stack 40 may be a GST stack. The GST stack 40 may include a first layer 42, a second layer 44, a third layer 46, a fourth layer 48, a fifth layer 50, a sixth layer 52, and a seventh layer 54.

[0049] In one example, the first layer 42 can be, for example, a GST with a high germanium (Ge) concentration (over 60% Ge content). The second layer 44 can be, for example, a GST with a medium Ge concentration (between 40 and 70% Ge content). The third layer 46 can be, for example, a GST with a medium to low Ge concentration (between 20 and 40% Ge content). The fourth layer 48 can be, for example, a GST with a low Ge concentration (less than 20% Ge content). The fifth layer 50 can be, for example, a GST with a medium to low Ge concentration (between 20 and 40% Ge content). The sixth layer 52 can be, for example, a GST with a medium Ge concentration (between 40 and 70% Ge content). The seventh layer 54 can be, for example, a GST with a high germanium (Ge) concentration (over 60% Ge content). No diffusion barriers are used between layers 42, 44, 46, 48, 50, 52, 54. Thus, for better linearity, several layers of phase change material, e.g.GST, with different crystallization temperatures a single PCM unit 40. In the structure 40, a central or middle region has the lowest crystallization temperature.

[0050] Fig. 8 is a sectional view of the semiconductor structure of Fig. 7, wherein the phase change material stack is structured, according to an embodiment of the present invention.

[0051] In various exemplary embodiments, the phase change material stack 40 is patterned to form a GST stack 40'.

[0052] Fig. 9 is a sectional view of the semiconductor structure of Fig. 8, wherein a resistive cladding is deposited over the patterned phase change material stack, according to an embodiment of the present invention.

[0053] In various exemplary embodiments, a resistive cladding 60 is deposited over the patterned phase change material stack 40'. The resistive cladding 60 is used to correct resistance drift.

[0054] The resistive coating 60 may be a metal nitride layer, such as titanium nitride (TiN).

[0055] In another embodiment, the resistive cladding 60 may be, for example, TaN with various deposition types, such as PVD, CVD, ALD, and with various resistivity values. This material is not limited by other metal types, such as TiN, W, or amorphous carbon (aC), and dielectrics such as Al2O3, HfO2, SiN, ZrO2, etc.

[0056] Fig. 10 is a sectional view of the semiconductor structure of Fig. 9, in which an interlayer dielectric (ILD) is deposited and planarized, according to an embodiment of the present invention.

[0057] In various exemplary embodiments, an ILD 62 is deposited and planarized, e.g., by chemical mechanical polishing (CMP), such that a top surface of the seventh layer 54 is exposed.

[0058] Fig. 11 is a sectional view of the semiconductor structure of Fig. 10, wherein a top electrode is formed over the patterned phase change material stack, according to an embodiment of the present invention.

[0059] In various exemplary embodiments, a top electrode 64 is formed over the patterned phase-change material stack 40'. The top electrode 64 may be formed within a dielectric layer 66. In one example, the dielectric layer 66 may be an ILD layer. The structure 70 shows the GST stack 40' formed between the top electrode 64 and the bottom electrode 12. The top and bottom electrodes 64, 12 are in direct contact with the GST stack 40'. The top electrode 64 is also in direct contact with the resistive cladding 60.

[0060] The structure 70 employs multiple GST materials with different crystallization temperatures and / or different resistivities to improve the linearity of a device. The structure 70 can be referred to as a confined-cell GST structure, in which a higher crystallization temperature is present at the top of the GST stack 30 and a lower crystallization temperature is present in the middle or center of the GST stack 30. In other words, as each layer is added, the crystallization temperature decreases to a certain value and then increases again. Thus, moving from the bottom to the middle of the structure 70, the crystallization temperature decreases to a midpoint. At the midpoint, the crystallization temperature increases as you move from the middle to the top of the structure 70 up to the top level.The crystallization temperature varies in descending order from the bottom electrode to the center and in ascending order from the center to the top electrode. The different crystallization temperatures can be achieved by doping and / or varying material contents.

[0061] In summary, the structure of the exemplary embodiments of the present invention may be a GST mushroom structure comprising GST multi-stacks with different crystallization temperatures, where the crystallization temperature is ordered from high to low from top to bottom, and where the different crystallization temperatures can be achieved by doping and / or varying material content. The method of the exemplary embodiments of the present invention includes a confined-cell GST structure comprising GST multi-stacks with different crystallization temperatures, where the crystallization temperature is ordered from high to low from top and from bottom to the middle, and where the different crystallization temperatures can be achieved by doping and / or varying material content.As a result, the exemplary embodiments of the present invention produce multiple stacks or continuous stacks of PCM thin films with different G versus set pulse properties through chemical doping of the same material and / or stepwise variation of the material composition. G varies from low to high from top to bottom. By manipulating the composition gradient and / or the thickness of the layer, improved G linearity versus the number of set pulses can be achieved. Furthermore, the same pulses are used for the entire stack.

[0062] Furthermore, the exemplary embodiments of the present invention employ PCM, which can be used in neuromorphic computing applications, as described below with reference to Fig. 12 and Fig. 13. For neuromorphic computing purposes, the linearity of conductance is useful for weight updating. Thus, the improved linearity of the mushroom and trapped-cell devices described herein may be advantageous for neuromorphic computing applications.

[0063] Fig. 12 is a block diagram of an exemplary neuromorphic and synaptronic network including a crossbar of electronic synapses interconnecting electronic neurons and axons, according to an embodiment of the present invention.

[0064] The exemplary tile-like circuit 100 includes a crossbar 112 according to an embodiment of the invention. In one example, the overall circuit may include an "ultra-dense crossbar array," which may have a pitch in the range of approximately 0.1 nm to 10 µm. The neuromorphic and synaptronic circuit 100 includes the crossbar 112 connecting a plurality of digital neurons 111, including neurons 114, 116, 118, and 120. These neurons 111 are also referred to herein as "electronic neurons." For illustrative purposes, the exemplary circuit 100 provides symmetrical connections between the two pairs of neurons (e.g., N1 and N3). However, embodiments of the invention can be used not only with such symmetrical connection of neurons, but also with asymmetrical connection of neurons (the neurons N1 and N3 do not have to be connected to the same connection).The crossbar in a tile accommodates the appropriate ratio of synapses to neurons and therefore does not have to be square.

[0065] In the exemplary circuit 100, neurons 111 are connected to crossbar 112 via dendritic tracts / wires (dendrites) 113, such as dendrites 126 and 128. Neurons 111 are also connected to crossbar 112 via axon tracts / wires (axons) 115, such as axons 134 and 136. Neurons 114 and 116 are dendritic neurons, and neurons 118 and 120 are axonal neurons connected to axons 113. In particular, neurons 114 and 116 are shown with outputs 122 and 124 connected to dendrites (e.g., bitlines) 126 and 128, respectively. Axonal neurons 118 and 120 are shown with outputs 130 and 132 connected to axons (e.g., word lines or access lines) 134 and 136, respectively.

[0066] When one of neurons 114, 116, 118, and 120 fires, it sends a pulse to its axonal and dendritic connections. Each synapse provides a contact between an axon of one neuron and a dendrite on another neuron, with the two neurons being called presynaptic and postsynaptic, respectively, with respect to the synapse.

[0067] Each connection between dendrites 126, 128 and axons 134, 136 is formed by a digital synaptic unit 131 (synapse). The connections at which the synaptic units are located may be referred to herein as "crossover junctions." In general, in one embodiment of the invention, neurons 114 and 116 will "fire" (transmit a pulse) in response to inputs they receive from axonal input connections (not shown) that exceed a threshold. Neurons 118 and 120 will "fire" (transmit a pulse) in response to inputs they receive from external input connections (not shown), usually from other neurons, that exceed a threshold. In one embodiment, when neurons 114 and 116 fire, they maintain a postsynaptic STDP (post-STDP) variable that decays. For example, in one embodiment, the decay period may be 50 ms.The post-STDP variable is used to achieve STDP by encoding the time since the corresponding neuron last fired. This STDP is used to control long-term potentiation, or "potentiation," defined in this context as increasing synaptic conductance. When neurons 118 and 120 fire, they maintain a pre-STDP (presynaptic-STDP) variable that decays in a similar manner to that of neurons 114 and 116.

[0068] Pre-STDP and post-STDP variables can, for example, decay according to exponential, linear, polynomial, or quadratic functions. In another embodiment of the invention, the variables can increase rather than decrease over time. In either case, this variable can be used to achieve STDP by encoding the time since the corresponding neuron last fired. The STDP is used to control long-term depression, or "depression," defined in this context as decreasing synaptic conductance. Note that the roles of the pre-STDP and post-STDP variables can be reversed, with the pre-STDP performing potentiation and the post-STDP performing depression.

[0069] An external two-way communication environment can supply sensory inputs and consume motor outputs. Digital neurons 111, implemented with complementary metal-oxide-semiconductor (CMOS) logic gates, receive spike inputs and integrate them. In one embodiment, neurons 111 include comparator circuits that generate spikes when the integrated input exceeds a threshold. In one embodiment, binary synapses are implemented with transposable 1-bit static random access memory (SRAM) cells, where each neuron 111 can be an excitatory or inhibitory neuron (or both). Each learning rule at each neuron axon and dendrite is reconfigurable as described below. This assumes transposable access to the crossbar memory array.Neurons that spike are selected when they send spikes to corresponding axons, where axons might be located at the nucleus or elsewhere in a larger system with numerous nuclei.

[0070] The term "electronic neuron," as used herein, refers to an architecture designed to mimic a biological neuron. An electronic neuron creates connections between processing elements that are roughly functionally equivalent to neurons of a biological brain. As such, a neuromorphic and synaptronic system including electronic neurons according to embodiments of the invention may include various electronic circuits modeled after biological neurons. Further, a neuromorphic and synaptronic system including electronic neurons according to embodiments of the invention may include various processing elements (including computer simulations) modeled after biological neurons.Although certain illustrative embodiments of the invention are described herein with electronic neurons containing electronic circuits, the present invention is not limited to electronic circuits. A neuromorphic and synaptronic system according to embodiments of the invention may be implemented as a neuromorphic and synaptronic architecture containing circuits and additionally as a computer simulation. Indeed, embodiments of the invention may take the form of a pure hardware embodiment, a pure software embodiment, or an embodiment containing both hardware and software elements.

[0071] Fig. 13 illustrates a block diagram of components of a data processing system including a data processing unit and a neuromorphic chip, according to an embodiment of the present invention.

[0072] Fig. Figure 13 illustrates a block diagram of components of a system 200 including a data processing unit 205. It should be noted that Fig. 13 provides only an illustration of one embodiment and does not impose any limitations on the environments in which various embodiments may be practiced. Numerous modifications to the illustrated environment may be made.

[0073] Computing unit 205 includes a communications network 202 that provides data transmission between computer processor(s) 204, memory 206, persistent storage 208, communications unit 210, and input / output (I / O) interface(s) 212. Communication network 202 may be implemented using any architecture designed to route data and / or control information between processors (such as microprocessors, communications and network processors, etc.), system memory, peripherals, and other hardware components within a system. For example, communication network 202 may be implemented using one or more buses.

[0074] Memory 206, cache 216, and persistent storage 208 are computer-readable storage media. In this embodiment, memory 206 includes random access memory (RAM) 214. This memory 214 may also be phase-change memory of the exemplary embodiments of the present invention. In general, memory 206 may include any suitable volatile or non-volatile computer-readable storage medium.

[0075] Some embodiments of the present invention include a deep learning program 225 executed by a neuromorphic chip 222 as a component of the computing device 205. In other embodiments, a deep learning program 225 is stored in a persistent memory 208 for execution by a neuromorphic chip 222 in conjunction with one or more of the corresponding computer processors 204 via one or more memories of the memory 206. In this embodiment, the persistent memory 208 includes a magnetic hard disk.Alternatively, or in addition to a magnetic hard disk, persistent memory 208 may include a solid-state hard disk, a semiconductor memory device, a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, or any other computer-readable storage medium capable of storing program instructions or digital information.

[0076] The medium used by persistent storage 208 may also be removable. For example, a removable hard drive may be used for persistent storage 208. Other examples include optical and magnetic disks, memory sticks, and smart cards that can be inserted into a drive for transfer to another computer-readable storage medium that is also part of persistent storage 208.

[0077] In some embodiments of the present invention, a neuromorphic chip 222 is included in the data processing unit 205 and connected to a data transmission network 202. The neuromorphic chip 222 contains electronic logic for providing layered constrained Boltzmann machines and a feed-forward neural network, including deep learning algorithm components that are trainable and perform machine learning. In other embodiments, the functions of the logic and algorithm components are performed by specialized data structures included in the data processing unit 205, which perform the deep learning functions of the layered constrained Boltzmann machines and the feed-forward neural network.

[0078] In these examples, the communication unit 210 provides communication with other computing systems or devices, including resources of a distributed computing environment. In these examples, the communication unit 210 includes one or more network interface cards. The communication unit 210 may provide communication using both wired and wireless communication connections. The deep learning program 225 may be downloaded to the persistent storage 208 by the communication unit 210.

[0079] I / O interface(s) 212 enable input and output of data with other devices connectable to data processing system 200. For example, I / O interface 212 may provide a connection to external devices 218, such as a keyboard, keypad, touchscreen, and / or other suitable input device. External devices 218 may also include portable computer-readable storage media, such as memory sticks, portable optical or magnetic disks, and memory cards.

[0080] The display 200 provides a mechanism for displaying data to a user and may be, for example, a computer monitor.

[0081] With reference to Fig.For purposes of paragraphs 1 to 11, "deposition" means any process that grows, layers, or otherwise transfers a material onto the wafer. Available processes include, but are not limited to, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD).As used herein, “deposition” may include any currently known or later developed process suitable for the material to be deposited, including, but not limited to, chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), semi-atmospheric CVD (SACVD), high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metal organic CVD (MOCVD), sputter deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitriding, spin-on deposition, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, and evaporation.

[0082] It should be noted that the present invention is described for a given illustrative architecture; however, other architectures, structures, substrate materials, and process elements and steps / blocks may be varied within the scope of the present invention.

[0083] Furthermore, it should be noted that when an element, such as a layer, region, or substrate, is referred to as being disposed "on" or "over" another element, it may be disposed directly on the other element, but there may also be intervening elements. In contrast, when an element is referred to as being disposed "directly on" or "directly over" another element, no intervening elements are present. Furthermore, it should be noted that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, no intervening elements are present.

[0084] The present embodiments may include a blueprint for an integrated circuit chip, which may be generated in a graphical computer programming language and stored in a computer storage medium (such as a disk, tape, physical hard disk, or virtual hard disk, such as in a storage access network). If the designer does not manufacture chips or the photolithographic masks used to manufacture chips, the designer may transmit the received blueprint directly or indirectly to such companies by physical means (e.g., by providing a copy of the storage medium storing the blueprint) or electronically (e.g., through the Internet). The stored blueprint is then converted into the appropriate format (e.g., GDSII) for manufacturing photolithographic masks containing multiple copies of the respective blueprint of the chip to be formed on a wafer.The photolithographic masks are used to define areas of the wafer that are to be etched or otherwise processed.

[0085] Methods as described herein can be used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., a single wafer comprising multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other higher-level carrier) or in a multi-chip package (such as a ceramic carrier having one or both of surface interconnects or buried interconnects). In either case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing units as part of (a) an intermediate product, such as a motherboard, or (b) a final product.The final product can be any product containing integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with a display, keyboard or other input device, and a central processor.

[0086] Furthermore, it should be noted that material compounds are described in terms of listed elements, e.g. SiGe. These compounds cover different proportions of the elements in the compound, e.g. SiGe covers Si x Ge 1-xwhere x is less than or equal to 1, and so on. Additionally, the compound may also contain other elements and still conform to the present embodiments. The compounds with additional elements are referred to herein as alloys. Throughout the specification, reference to "one embodiment" or "an embodiment" of the present invention, as well as other variations thereof, means that a particular element, structure, feature, and so forth described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrase "in one embodiment" or "according to an embodiment," as well as any other variations, in various places in the specification are not necessarily all referring to the same embodiment.

[0087] Please note that the use of any of the following “ / ”, “and / or”, and “at least one of”, for example, in the cases of “A / B”, “A and / or B”, and “at least one of A and B”, this phrase is intended to include selecting only the first listed option (A), or selecting only the second listed option (B), or selecting both options (A and B). As another example, in the cases of “A, B, and / or C” and “at least one of A, B, and C”, this phrase is intended to include selecting only the first listed option (A), or selecting only the second listed option (B), or selecting only the third listed option (C), or selecting only the first and second listed options (A and B), or selecting only the first and third listed options (A and C), or selecting only the second and third listed options (B and C), or selecting all three listed options (A, B, and C).As will be clear to the skilled person, this can be extended to as many elements as are listed.

[0088] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of embodiments. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms, unless the context clearly dictates otherwise. Further, it is to be understood that the terms "comprises," "having," "includes," and / or "containing," when used herein, connote the presence of specified features, integers, steps, acts, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, acts, elements, components, and / or groups thereof.

[0089] Spatial relative terms such as "beneath", "under", "lower", "above", "upper", and the like may be used herein for convenience of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the FIGS. It should be understood that the spatial relative terms are intended to include various orientations of the unit in use or operation, in addition to the orientations illustrated in the FIGS. For example, if the unit is turned over in the FIGS., elements described as being "below" or "below" other element(s) or feature(s) will then be located "above" the other elements or features. Thus, the term "below" can include an orientation of both above and below.The unit may also be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. Furthermore, it should be noted that a layer described as being "between" two layers may be the only layer between the two layers, or one or more intervening layers may be present.

[0090] It should be noted that while the terms "first," "second," etc., may be used herein to describe various elements, these elements are not intended to be limited by these terms. These terms are used only to distinguish one element from another. Thus, an element referred to below as a first element could be referred to as a second element without departing from the scope of the present concept.

Claims

[1] A method for improved linearity of a phase change memory cell structure, PCM cell structure, the method comprising: Forming a lower electrode over a substrate; Forming a heating element in direct contact with a surface of the lower electrode, wherein a width of the heating element is smaller than the lower electrode; Forming a resistive cladding, thereby forming a planar surface along an entire surface, such that the planar cladding surface extends entirely over an upper surface of the heating element; Building a PCM stack comprising a plurality of PCM layers, each having a different crystallization temperature, over the bottom electrode, the PCM stack being in direct contact with a top surface of the resistive cladding; and Forming an upper electrode over the PCM stack, wherein the crystallization temperature varies in an ascending order from the lower electrode to the upper electrode, and wherein the majority of PCM layers comprise four layers. [2] The method of claim 1, wherein each of the plurality of PCM layers comprises a Ge-Sb-Te alloy, germanium-antimony-tellurium alloy, GST alloy. [3] The method of claim 1, wherein the first layer has a germanium content, Ge content, of less than 20%, the second layer has a Ge content of between 20 and 40%, the third layer has a Ge content of between 40 and 70%, and the fourth layer has a Ge content of higher than 60%. [4] The method of claim 1, wherein the resistive cladding is used for resistance drift correction. [5] Method according to claim 1, wherein the different crystallization temperatures are achieved by doping and / or different material contents. [6] Semiconductor structure having: a lower electrode disposed above a substrate; a heating element in direct contact with a surface of the lower electrode; a resistive cladding forming a planar surface along an entire surface such that the planar cladding surface extends entirely over an upper surface of the heating element; a PCM stack comprising a plurality of PCM layers each having a different crystallization temperature disposed above the bottom electrode, the PCM stack being in direct contact with a top surface of the resistive cladding; an upper electrode arranged above the PCM stack; wherein the crystallization temperature varies in a descending order within part or all of the PCM stack, and wherein the plurality of PCM layers comprises four layers, and wherein the descending order is from the upper electrode to the lower electrode. [7] The semiconductor structure of claim 6, wherein each of the plurality of PCM layers comprises a Ge-Sb-Te alloy, germanium-antimony-tellurium alloy, GST alloy. [8] Semiconductor structure according to claim 6, wherein the different crystallization temperatures are achieved by doping and / or different material content. [9] A semiconductor structure according to claim 6, wherein a first layer of the PCM stack comprises a Germanium content, Ge content, of less than 20%, a second layer of the PCM stack has a Ge content of between 20 and 40%, a third layer of the PCM stack has a Ge content of between 40 and 70% and a fourth layer of the PCM stack has a Ge content of higher than 60%.

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