Encapsulation stack on a transistor and manufacturing process therefor

Abstract

Transistor device comprising: a substrate; a semiconductor structure on the substrate; a source contact on a source region of the semiconductor structure; a drain contact on a drain region of the semiconductor structure; and a gate contact between the source contact and the drain contact; a metallization layer comprising a non-planar surface on a surface of the semiconductor structure, wherein the metallization layer comprises a transmission line on the source contact or the drain contact; a non-planar encapsulation layer on the non-planar surface of the metallization layer, wherein the non-planar encapsulation layer comprises a non-planar encapsulation surface opposite the non-planar surface, and wherein the non-planar encapsulation layer is located on the gate contact and the transmission line;and a self-planarizing encapsulation layer on the non-planar encapsulation layer, comprising a planarized surface facing the non-planar encapsulation surface, wherein the ratio of the thickness of the non-planar encapsulation layer over the gate contact to the thickness of the self-planarizing encapsulation layer over the gate contact is between 0.20 and 0.29; or a ratio of the thickness of the non-planar encapsulation layer over the transmission line to the thickness of the self-planarizing encapsulation layer over the transmission line is between 0.28 and 0.45; or a ratio of the thickness of the non-planar encapsulation layer over an access area located between the gate contact and the source contact or the drain contact to the thickness of the self-planarizing encapsulation layer located over the access area is between 0.16 and 0.22.

Description

CLAIMING PRIORITY

[0001] This application asserts the priority of US patent application serial no. 17 / 390,020, filed on July 30, 2021, the disclosure of which is incorporated herein by reference in its entirety. AREA

[0002] The present disclosure relates to semiconductor devices and in particular to the protection of semiconductor devices from environmental influences and to related manufacturing processes. STATE OF THE ART

[0003] Materials such as silicon (Si) and gallium arsenide (GaAs) are now widely used in semiconductor devices for low-power and, in the case of Si, low-frequency applications. However, these materials may not be well suited for high-power and / or high-frequency applications, for example, due to their relatively small band gaps (1.12 eV for Si and 1.42 eV for GaAs at room temperature) and relatively low breakdown voltages.

[0004] For high-power, high-temperature, and / or high-frequency applications and devices, wide-bandgap semiconductor materials can be used, such as silicon carbide (SiC) (e.g., with a bandgap of about 3.2 eV for 4H-SiC at room temperature) and the group III nitrides (e.g., with a bandgap of about 3.36 eV for gallium nitride (GaN) at room temperature). As used herein, the term "group III nitride" refers to semiconducting compounds formed between nitrogen (N) and the elements in group III of the periodic table, usually aluminum (Al), gallium (Ga), and / or indium (In). The term encompasses binary, ternary, and quaternary compounds such as GaN, AlGaN, and AlInGaN. These compounds have empirical formulas in which one mole of nitrogen is combined with a total of one mole of the group III elements.These materials can exhibit higher electric breakdown field strengths and higher electron saturation velocities compared to GaAs and Si.

[0005] Semiconductor devices fabricated from SiC and / or group III nitrides can include power transistor devices such as field-effect transistors (FETs), including MOSFETs (metal-oxide-semiconductor field-effect transistors), DMOS transistors (doubly diffused metal-oxide-semiconductor transistors), HEMTs (high electron mobility transistors), MESFETs (metal-semiconductor field-effect transistors), LDMOS transistors (laterally diffused metal-oxide-semiconductor transistors), etc. These devices are commonly passivated with an oxide layer, such as silicon dioxide (SiO2), to protect, for example, the exposed surfaces of the device. However, the interface between the semiconductor body and the oxide layer may be insufficient to maintain high surface electron mobility.For example, the interface between SiC and SiO2 conventionally exhibits a high density of interfacial states, which can reduce surface electron mobility and introduce carrier traps, which in turn can reduce the desired performance characteristics of devices.

[0006] Accordingly, semiconductor devices, including those enclosing oxide layers, may also incorporate one or more layers of silicon nitride (SiN) to enhance the resulting electronic properties, as described, for example, in U.S. Patent No. 6,246,076. SiN can also provide an environmental barrier; without it, the structure and operation of the device may be susceptible to environmental degradation, regardless of the presence of an oxide layer. For example, semiconductor devices may operate in environments with high temperature and / or high humidity. If moisture can penetrate the semiconductor devices, corrosion may occur, which can degrade their performance.

[0007] As an environmental barrier, SiN can form a better seal over the device compared to SiO2, thus reducing or preventing contaminants such as water from reaching the device's epitaxial layers and causing degradation. Plasma-enhanced chemical vapor deposition (PECVD) can be used to form SiN as an environmental barrier for a semiconductor device, as described, for example, in US Patent No. 7,525,122. However, a PECVD SiN layer can be prone to defects, such as pinholes and pillar-like structures, which can allow moisture to penetrate the SiN layer and reach the device. SUMMARY

[0008] According to some embodiments of the present disclosure, a transistor device includes a substrate; a semiconductor structure on the substrate; a metallization layer comprising a non-planar surface on a surface of the semiconductor structure; a non-planar encapsulation layer on the non-planar surface of the metallization layer, wherein the non-planar encapsulation layer comprises a non-planar encapsulation surface opposite the non-planar surface; and a self-planarizing encapsulation layer on the non-planar encapsulation layer comprising a planarized surface opposite the non-planar encapsulation surface.

[0009] In some embodiments, the transistor device further includes a source contact on a source region of the semiconductor structure; a drain contact on a drain region of the semiconductor structure; and a gate contact between the source contact and the drain contact. The non-planar encapsulation layer is located on the gate contact, the drain contact, and the source contact.

[0010] In some embodiments, the ratio of the thickness of the non-planar encapsulation layer above the gate contact to the thickness of the self-planarizing encapsulation layer above the gate contact is between 0.20 and 0.29.

[0011] In some embodiments, the metallization layer includes a transmission line on the source contact, and the ratio of the thickness of the non-planar encapsulation layer above the transmission line to the thickness of the self-planarizing encapsulation layer above the transmission line is between 0.28 and 0.45.

[0012] In some embodiments, the semiconductor structure further comprises a source access region between the source contact and the gate contact, and the ratio of the thickness of the non-planar encapsulation layer over the source access region to the thickness of the self-planarizing encapsulation layer over the source access region is between 0.16 and 0.22.

[0013] In some embodiments, the thickness of the non-planar encapsulation layer is essentially uniform across the semiconductor structure.

[0014] In some embodiments, the non-planar encapsulation layer comprises SiO, SiN, SiON, ZrO, HfO, AlN and / or AlO.

[0015] In some embodiments, the self-planarizing encapsulation layer comprises polyimide, benzocyclobutene, glass, polyamide, polybenzoxazole and / or a photoresist.

[0016] In some embodiments, the self-planing encapsulation layer comprises a material having an uncured kinematic viscosity of 100 to 8000 centistokes.

[0017] In some embodiments, the self-planarizing encapsulation layer comprises a material that has a curing temperature of less than or equal to 250 °C.

[0018] In some embodiments, the self-planarizing encapsulation layer comprises a material that is essentially hardened.

[0019] According to some embodiments of the present disclosure, a transistor device includes a substrate; a semiconductor structure on the substrate, wherein the semiconductor structure comprises an active region; a gate contact on the active region of the semiconductor structure; a first encapsulation layer extending over the gate contact; and a second encapsulation layer on the first encapsulation layer, wherein the second encapsulation layer comprises a material having a curing temperature of less than or equal to 275 °C.

[0020] In some embodiments, the ratio of the thickness of the first encapsulation layer above the gate contact to the thickness of the second encapsulation layer above the gate contact is between 0.20 and 0.29.

[0021] In some embodiments, the semiconductor structure further comprises a source region, the transistor device further comprises a source contact on the source region and a transmission line on the source contact, and the first encapsulation layer extends over the source contact and the transmission line.

[0022] In some embodiments, the ratio of the thickness of the first encapsulation layer above the transmission line to the thickness of the second encapsulation layer above the transmission line is between 0.28 and 0.45.

[0023] In some embodiments, the semiconductor structure further comprises a source access area between the source contact and the gate contact, and the ratio of the thickness of the first encapsulation layer over the source access area to the thickness of the second encapsulation layer over the source access area is between 0.16 and 0.22.

[0024] In some embodiments, the thickness of the first encapsulation layer is essentially uniform across the semiconductor structure.

[0025] In some embodiments, an upper surface of the second encapsulation layer is essentially planar across the semiconductor structure.

[0026] In some embodiments, the first encapsulation layer comprises SiO, SiN, SiON, ZrO, HfO, AlN and / or AlO.

[0027] In some embodiments, the second encapsulation layer comprises polyimide, benzocyclobutene, glass, polyamide, polybenzoxazole and / or a photoresist.

[0028] In some embodiments, the second encapsulation layer comprises a material with a curing temperature of less than or equal to 250 °C.

[0029] According to some embodiments of the present disclosure, a transistor device includes a semiconductor structure on a substrate, the semiconductor structure comprising a source region and a drain region; a source contact on the source region; a drain contact on the drain region; a first encapsulation layer conformally extending on the drain contact, on the source contact, and on the semiconductor structure between the drain contact and the source contact; and a second encapsulation layer on the first encapsulation layer, the second encapsulation layer comprising a material having a substantially planar upper surface and extending from the source contact to the drain contact. The material is configured to transition from a kinematic viscosity of 100 to 8000 centistokes to a hardened state during a hardening process.

[0030] In some embodiments, the first encapsulation layer comprises SiO, SiN, SiON, ZrO, HfO, AlN and / or AlO.

[0031] In some embodiments, the first encapsulation layer comprises a plurality of layers.

[0032] In some embodiments, the second encapsulation layer comprises polyimide, benzocyclobutene, glass, polyamide, polybenzoxazole and / or a photoresist.

[0033] In some embodiments, the second encapsulation layer comprises a material with a curing temperature of less than or equal to 275 °C.

[0034] According to some embodiments of the present disclosure, a method for forming a transistor device includes forming a semiconductor structure on a substrate; forming a first encapsulation layer on the semiconductor structure comprising a non-planar surface opposite the semiconductor structure; forming a second encapsulation layer on the first encapsulation layer, wherein the second encapsulation layer comprises a planarized surface opposite the first encapsulation layer; and performing a hardening process on the second encapsulation layer.

[0035] In some embodiments, the second encapsulation layer comprises a material configured to transition from a kinematic viscosity of 100 to 8000 centistokes to a hardened state during the curing process.

[0036] In some embodiments, the planarized surface of the second encapsulation layer is a result of self-planarization of a material of the second encapsulation layer.

[0037] In some embodiments, the method further includes the formation of a source contact, a drain contact and a gate contact on the semiconductor structure.

[0038] Forming the first encapsulation layer includes forming the first encapsulation layer on the gate contact, the drain contact, and the source contact.

[0039] In some embodiments, the second encapsulation layer has a non-planar surface opposite the planarized surface and extends along respective profiles on the first encapsulation layer, defined by the source contact, the drain contact and / or the gate contact.

[0040] In some embodiments, the thickness of the first encapsulation layer is essentially uniform across the gate contact, the drain contact, and the source contact.

[0041] In some embodiments, the second encapsulation layer comprises SiO, SiN, SiON, ZrO, HfO, AlN and / or AlO.

[0042] In some embodiments, the second encapsulation layer comprises polyimide, benzocyclobutene, glass, polyamide, polybenzoxazole and / or a photoresist.

[0043] In some embodiments, the second encapsulation layer comprises a material with a curing temperature of less than or equal to 275 °C.

[0044] In some embodiments, the curing process is carried out on the second encapsulation layer at a temperature that is greater than a glass transition temperature of a material of the second encapsulation layer.

[0045] In some embodiments, the hardening process is carried out on the second encapsulation layer at a temperature of less than or equal to 275 °C.

[0046] In some embodiments, the formation of the second encapsulation layer on the first encapsulation layer is carried out by processes that include a spin coating process, a spray coating process, a vapor deposition process, an electroplating process, a blade coating process and / or a slot die deposition process.

[0047] Other devices, equipment, and / or methods according to some embodiments will be obvious to those skilled in the art upon review of the following drawings and the detailed description. It is intended that all such additional embodiments, in addition to any and all combinations of the foregoing embodiments described above, are included within the scope of the invention and are protected by the accompanying claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a schematic cross-sectional view of the semiconductor device or die according to some embodiments of the present disclosure. Fig. Figure 2A is a schematic top view of a HEMT device according to embodiments of the present disclosure. Fig. 2B is a schematic cross-sectional view of the HEMT device along line AA of Fig. 2A. Fig.Figures 3A to 3D are diagrams illustrating an advantageous performance of devices according to embodiments of the present disclosure. Fig. Figures 4A to 4K illustrate a method for manufacturing a semiconductor device according to embodiments of the present disclosure. Fig. 5A and Fig. Figure 5B are schematic cross-sectional views of alternative transistor device structures according to some embodiments of the present disclosure. Fig. Figures 6A to 6C are schematic cross-sectional views illustrating several exemplary ways of packing a semiconductor according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0048] Embodiments of the present inventive concepts are described in more detail below with reference to the accompanying drawings, which illustrate embodiments of the invention. However, the inventive concepts can be implemented in many different forms and should not be interpreted as being limited to the embodiments set forth herein. Rather, these embodiments are provided to ensure that this disclosure is thorough and complete and to fully convey to those skilled in the art the scope of the inventive concepts. The same reference numerals refer throughout to the same elements.

[0049] While some semiconductor devices in certain applications may be hermetically sealed within a package for protection against environmental influences, packages in other applications may not provide a hermetic seal against the operating environment. An encapsulation stack layer or structure can therefore be provided on die-level semiconductor devices to protect them from moisture and / or other operating environmental conditions. As used herein, a die or chip can refer to a small block or body of semiconducting material or other substrate on which electronic circuit elements are fabricated. A die can enclose a large number of individual "unit cell" transistor structures, which in some implementations may be electrically connected in parallel or in series.

[0050] The encapsulation layer or structure may include a conformal dielectric film. The conformal dielectric film can typically be deposited using wafer-level processing techniques such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). The conformal dielectric film may include one or more dielectrics or layers in stacked form, including, for example, SiO₂, SiN₂, SiON₂, ZrO₂, HfO₂, AlN₂, and / or AlO₂. The materials described herein with reference to the chemical formulas of the compounds (e.g., SiO₂, AlO₂) may include different stoichiometries or any combination of the constituents (e.g., SiO₂, Al₂O₃), and in some cases, amorphous or crystalline states of the materials.

[0051] For example, some RF HEMT devices can encapsulate a SiN-based PECVD dielectric layer, which can act as an environmental barrier, protecting the underlying active area from external contamination, corrosion, and / or mechanical damage. However, as mentioned above, a PECVD SiN layer can be prone to defects, such as pinholes and pillar-like structures, which can allow moisture to reach the semiconductor device. To further improve robustness against environmental conditions and / or damage during die assembly of semiconductor devices (such as RF or DC transistor devices, including RF HEMTs), one or more additional layers can be encapsulated, providing a multilayer encapsulation film or stacked structure.

[0052] Some embodiments of the present invention may arise from the realization that the use of an encapsulation stack structure comprising both a conformal first encapsulation layer and a second encapsulation layer that is self-planarizing and / or hardened can provide improved protection against environmental influences. The use of the second encapsulation layer, which is self-planarizing and / or hardened, can impart a substantially planar top surface to the stack structure, which is hardened as a result of the layer's hardening. As used herein, a substantially planar surface means a surface that varies / deviates from a theoretical plane (e.g., a planar surface) by less than 10%.As used herein, self-planarization refers to a process by which a material acquires a substantially planar top surface without the need for additional mechanical and / or chemical steps to remove portions of the top surface to achieve planarity. The combination of the top surface hardness of the stack structure and the top surface planarity of the layer can provide enhanced protection against environmental conditions such as humidity. By using materials for the second encapsulation layer that have a curing temperature within the thermal balance of the die's semiconductor devices (e.g., a maximum temperature after which the semiconductor devices may be damaged), complete and / or total curing of the second encapsulation layer without damaging the semiconductor devices can be achieved.As used herein, a curing temperature of a given material refers to a temperature that induces a change in the material's hardness such that the material achieves a hardness within 90% of the material's maximum possible hardness. For example, if the material is a polymer or includes a polymer, the material's curing temperature refers to a temperature that causes the polymer to cross-link.

[0053] Fig. Figure 1 is a schematic cross-sectional view of the semiconductor device or die 300 according to some embodiments of the present disclosure. Fig. 1. The structure is intended to be used for identification and description and is not intended to be physically to scale.

[0054] As in Fig.As shown in Figure 1, a multilayer environmental protection encapsulation film or stack 220 is provided on a semiconductor structure 390 to cover the semiconductor structure 390 for protection against moisture and / or other environmental conditions. The semiconductor structure 390 of Fig.Figure 1 is a schematic example shown as a generic semiconductor structure 390 on which the multilayer environmental protection encapsulation stack 220 is formed. The semiconductor structure 390 can be provided on a substrate 322, such as a silicon carbide (SiC) substrate or a sapphire substrate. The substrate 322 can be a semi-insulating SiC substrate. However, in embodiments of the present disclosure, any suitable substrate can be used, such as sapphire (Al₂O₃), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), silicon (Si), GaAs, LGO, zinc oxide (ZnO), LAO, indium phosphide (InP), and the like.The substrate 322 can be a SiC wafer, and the semiconductor device 300 can be formed at least partially via wafer-level processing. The wafer can then be cut or otherwise singulated to provide a die that incorporates a variety of unit-cell transistor structures. The term "semi-insulating" is used here descriptively and not in an absolute sense.

[0055] The semiconductor structure 390 can, in some embodiments, be made of a material based on SiC and / or group III nitrides. A section of the semiconductor structure 390 can define a channel region of the semiconductor device 300. The channel region can extend between a source region 215 and a drain region 205 of the semiconductor device 300. The conduction in the channel region can be controlled by a signal applied to a gate contact 310. The signals can be applied to the source region 215 via the source contact 315 and to the drain region 205 via the drain contact 305. Metal transmission lines 365 can be coupled to the source contact 315 and the drain contact 305 to provide the source and drain signals, respectively.A section of the semiconductor structure 390 from below the source contact 315 to below the gate contact 310 can be called the source access area SAR, and a section of the semiconductor structure 390 from below the drain contact 305 to below the gate contact 310 can be called the drain access area DAR.

[0056] In some embodiments, one or more passivation layers 350 can be provided on a surface of the semiconductor structure 390, and the multilayer environmental protection stack 220 can be provided on the passivation layer(s) 350 opposite the semiconductor structure 390. The passivation layer(s) 350 can be configured to reduce parasitic capacitance, reduce charge trapping, and / or otherwise improve the electronic properties of one or more layers of the semiconductor structure 390. For example, the passivation layer(s) 350 can include one or more layers of SiN deposited, for example, by CVD. More generally, the passivation layer(s) 350 can be a multilayer deposition using a process other than atomic layer deposition (ALD).

[0057] In some embodiments, a field plate 312 can be provided on the passivation layer(s) 350. In some embodiments, the field plate 312 can partially overlap the gate contact 310. The position and configuration of the field plate 312 are merely exemplary and are not intended to limit the present patent specification. In some embodiments, additional field plates 312 can be present and / or the field plate 312 can be shaped differently and / or located in different positions on the semiconductor device 300 than those described in [reference to relevant document]. Fig. Figure 1 illustrated. In some embodiments, the field plate 312 may not be present.

[0058] The multi-layer environmental protection encapsulation stack 220 can be formed on the field plate 312 (if present), the transmission lines 365, and / or the passivation layer(s) 350. The multi-layer environmental protection encapsulation stack 220 can include at least two layers: a first encapsulation layer 225 and a second encapsulation layer 230.

[0059] The first encapsulation layer 225 may be or include one or more dielectric layers conformally formed on the field plate 312 (if present), the transmission lines 365, and / or the passivation layer(s) 350. The field plate 312 (if present), the transmission lines 365, and / or the passivation layer(s) 350 may also be referred to herein as the metallization layer. The thickness Tc of the first encapsulation layer 225 may be substantially uniform across the semiconductor device 300, but the embodiments of this disclosure are not limited thereto. As used herein, the thickness Tc is substantially uniform if it varies by less than 20% across the semiconductor device 300. In some embodiments, the thickness Tc may vary by less than 10% across the semiconductor device 300.The field plate 312 (if present), the transmission lines 365 and / or the passivation layer(s) 350 may have a non-planar surface, and as a consequence, the first encapsulation layer 225 may also have a non-planar upper and lower surface due to its conformal shape.

[0060] The first encapsulation layer 225 can, for example, enclose SiO₂, SiN, SiON₂, ZrO₂, HfO₂, AlN, and / or AlO₂. In some embodiments, the first encapsulation layer 225 can enclose multiple layers. For example, the first encapsulation layer 225 can enclose a SiON₂:SiN bilayer. The first encapsulation layer 225 can be deposited using wafer-level processing methods such as CVD, PECVD, ALD, or PVD.

[0061] The second encapsulation layer 230 can be formed on the first encapsulation layer 225 such that the first encapsulation layer 225 lies between the second encapsulation layer 230 and the field plate 312 (if present), the transmission lines 365, and / or the passivation layer(s) 350. The second encapsulation layer 230 can be a curable dielectric layer formed in a viscous or liquid state, for example, by a spin coating process, a spray coating process, a vapor deposition process, an electroplating process, a blade coating process, and / or a slot die deposition process, which can initially fill surface irregularities (pinholes, columnar structures, etc.) or other non-planarities in the underlying first encapsulation layer 225.The second encapsulation layer 230 can enclose a material that allows the second encapsulation layer 230 to self-planarize. In other words, the viscosity of the material of the second encapsulation layer 230 can be such that the material settles with a substantially planar upper surface 230A. The second encapsulation layer 230 can further be fully cured to provide the substantially planar upper surface 230A relative to the first encapsulation layer 225. A lower surface 230B of the second encapsulation layer 230 can be located on and / or in contact with the non-planar surface of the first encapsulation layer 225, and as a result, the lower surface 230B of the second encapsulation layer 230 can be non-planar.

[0062] In some embodiments, the material of the second encapsulation layer 230 can be selected such that it has a curing temperature of less than or equal to 275 °C. In some embodiments, the material of the second encapsulation layer 230 can be selected such that it has a curing temperature of less than or equal to 250 °C. In some embodiments, the curing temperature of the second encapsulation layer 230 can allow the material of the second encapsulation layer 230 to be fully cured at a temperature that does not damage other elements of the semiconductor device 300.

[0063] In some embodiments, the material of the second encapsulation layer 230 can be selected to have a kinematic viscosity of 100 to 8000 centistokes (cSt). In some embodiments, the material of the second encapsulation layer 230 can be selected to have a kinematic viscosity of 1000 to 2000 cSt. In some embodiments, the viscosity of the second encapsulation layer 230 can enable the material of the second encapsulation layer 230 to fill surface irregularities (e.g., pinholes, columnar structures, etc.) or other non-planarities in the underlying first encapsulation layer 225.In some embodiments, the viscosity of the second encapsulation layer 230 can allow its upper surface 230A to self-planarize and flow in such a way as to cover the non-planar surface of the first encapsulation layer 225 (including any surface defects and voids therein). The self-planarization of the second encapsulation layer 230 can enable the formation of a planar upper surface 230A without the need for polishing or other chemical and / or mechanical steps to achieve a planar upper surface.

[0064] The second encapsulation layer 230 can, for example, enclose polyimide, benzocyclobutene (BCB), glass (e.g., borosilicate glass (BSG)), polyamide, polybenzoxazole (PBO), and / or a photoresist (e.g., SU-8). Other epoxides and / or resins can be used without deviating from the embodiments of the present disclosure.

[0065] The upper surface 230A of the second encapsulation layer 230 can be substantially planar across the width of the semiconductor device 300, despite differences in the heights of the underlying structures. For example, in some embodiments, the level of the upper surface 230A may vary by no more than 10% across the width of the semiconductor device 300. In other embodiments, the level of the upper surface 230A may vary by no more than 5% across the width of the semiconductor device 300. The second encapsulation layer 230 may have a conformal and / or non-planar lower surface 230B opposite the substantially planar upper surface 230A.The conformal and / or non-planar lower surface 230B of the second encapsulation layer 230 can extend on the first encapsulation layer 225 along respective profiles defined by the source contact 315, the drain contact 305, the gate contact 310, the metal transmission lines 365 and / or the field plate 312 (e.g. the metallization layer).

[0066] In some embodiments, the thickness of the second encapsulation layer 230 can vary across the semiconductor device 300. The second encapsulation layer 230 can have a thickness Tm across the transmission line 365, a thickness Tr across the source access area SAR and / or the drain access area DAR, and a thickness Tg across the gate contact 310. The thickness Tm can refer to the thickness of the second encapsulation layer 230 between the top surface 230A of the second encapsulation layer 230 and a top surface of the first encapsulation layer 225 on a topmost section of the transmission line 365. The thickness Tg can refer to the thickness of the second encapsulation layer 230 between the top surface 230A of the second encapsulation layer 230 and a top surface of the first encapsulation layer 225 on a topmost section of the gate contact 310.The thickness Tr can refer to a thickness of the second encapsulation layer 230 between the top surface 230A of the second encapsulation layer 230 and a top surface of the first encapsulation layer 225 on a topmost section of the semiconductor structure 390 in the source access region SAR or the drain access region DAR.

[0067] In some embodiments, the second encapsulation layer 230 can be configured to maintain a ratio of the various thicknesses Tr, Tm, and Tg of the second encapsulation layer 230 to the thickness Tc of the first encapsulation layer 225. In some embodiments, the ratios of the thicknesses Tr, Tm, and Tg of the second encapsulation layer 230 to the thickness Tc of the first encapsulation layer 225 can be maintained according to Table 1. Table 1: position Tc thickness range (µm) Second encapsulation layer 230 thickness range (µm) Ratio of first layer to second layer Over the transmission line (Tm) 1,15-1,4 3,1-4,1 0,28-0,45 Above the gate (Tg) 1,15-1,4 4,7-5,6 0,20-0,29 Above the drain / source access area (Tr) 1,15-1,4 6,2-7,2 0,16-0,22

[0068] The device with the ratios according to Table 1 provides sufficient protection across various areas of the device. The variation in the ratios results partly from the planar upper surface of the second encapsulation layer 230 and the varying surface area of ​​the first encapsulation layer 225. Consequently, although the lower surface of the second encapsulation layer 230 varies due to the varying upper surface area of ​​the first encapsulation layer 225, the upper surface 230A of the second encapsulation layer 230 remains substantially planar. Devices with ratios outside these ranges may exhibit reduced performance and / or reduced protection against moisture.

[0069] Fig.Figure 1 provides an illustration of the multilayer environmental protection encapsulation stack 220 on a semiconductor device 300, which has a number of structures, such as a gate contact 310, a source contact 315, and a drain contact 305. As those skilled in the art would understand, the multilayer environmental protection encapsulation stack 220 can be applied to a number of different semiconductor structures without deviating from the embodiments of the present disclosure.

[0070] For example, illustrate Fig. 2A and Fig. 2B an embodiment of a semiconductor device 300A implemented as a HEMT according to some embodiments of the present disclosure. Fig. Figure 2A is a schematic top view of the HEMT device 300A according to embodiments of the present disclosure. Fig. 2B is a schematic cross-sectional view of the HEMT device 300A along line AA of Fig. 2A. Fig. 2A and Fig. 2B should represent structures for identification and description and should not represent the structures to physical scale.

[0071] Referring to Fig. 2A and Fig. 2B can form a semiconductor structure 390, such as a semiconductor structure for a HEMT with a group III nitride semiconductor, on a substrate 322, such as a silicon carbide (SiC) substrate or a sapphire substrate. The substrate 322 can be a semi-insulating silicon carbide (SiC) substrate, which, for example, can be the 4H polytype of silicon carbide. Other suitable polytypes of silicon carbide can include 3C, 6H, and 15R. The substrate can be a high-purity semi-insulating substrate (HPSI) available from Cree, Inc.

[0072] In some embodiments, the silicon carbide bulk crystal of substrate 322 may have a resistivity equal to or greater than approximately 1×10 5 Ohm-cm at room temperature. Exemplary SiC substrates that may be used in some embodiments of the present disclosure are manufactured, for example, by Cree, Inc., in Durham, NC, the applicant of the present disclosure, and methods for manufacturing such substrates are described, for example, in US Patent 121.

[0073] The invention is described in U.S. Patent Nos. 34,861, 4,946,547, 5,200,022, and 6,218,680, the disclosures of which are incorporated herein by reference in their entirety. Although silicon carbide can be used as the substrate material, in embodiments of the present disclosure any suitable substrate may be used, such as sapphire (Al₂O₃), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), silicon (Si), GaAs, LGO, zinc oxide (ZnO), LAO, indium phosphide (InP), and the like. The substrate 322 can be a silicon carbide wafer, and the HEMT device 300A can be formed at least partially by processing at the wafer level, and the wafer can then be cut to provide a variety of individual high electron mobility transistors 300A.

[0074] The substrate 322 can have a lower surface 322A and an upper surface 322B. In some embodiments, the substrate 322 of the HEMT device 300A can be a thinned substrate 322. In some embodiments, the thickness of the substrate 322 (e.g., in a vertical Z-direction) can be Fig. 2B) 100 µm or less. In some embodiments, the thickness of the substrate 322 may be 75 µm or less. In some embodiments, the thickness of the substrate 322 may be 50 µm or less.

[0075] A channel layer 324 is formed on the upper surface 322B of the substrate 322 (or on the optional layers further described herein), and a barrier layer 326 is formed on an upper surface of the channel layer 324. In some embodiments, the channel layer 324 and the barrier layer 326 can each be formed by epitaxial growth. Techniques for epitaxial growth of group III nitrides have been described, for example, in U.S. Patents 5,210,051, 5,393,993, and 5,523,589, the disclosures of which are also incorporated herein by reference in their entirety. The channel layer 324 can have a band gap smaller than that of the barrier layer 326, and the channel layer 324 can also have a higher electron affinity than the barrier layer 326. The channel layer 324 and the barrier layer 326 can enclose materials based on group III nitrides.In some embodiments, the wafer thickness (e.g., the thickness of the substrate 322, the channel layer 324, and the barrier layer 326) can range from 40 µm to approximately 100 µm. In some embodiments, the wafer thickness can range from 40 µm to approximately 80 µm. In some embodiments, the wafer thickness can be approximately 75 µm.

[0076] In some embodiments, the channel layer 324 can be a group III nitride, such as Al x Ga 1-xN, where 0 ≤ x < 1, provided that the conduction band edge energy of the channel layer 324 is less than the conduction band edge energy of the barrier layer 326 at the interface between the channel and barrier layers 324, 326. In certain embodiments of the present disclosure, x = 0, indicating that the channel layer 324 is GaN. The channel layer 324 may also be other Group III nitrides, such as InGaN, AlInGaN, or the like. The channel layer 324 may be undoped (“accidentally doped”) and may be grown to a thickness greater than approximately 0.002 µm. The channel layer 324 may also be a multilayer structure, such as a superlattice or combinations of GaN, AlGaN, or the like. In some embodiments, the channel layer 324 may be subjected to pressure.

[0077] In some embodiments, the barrier layer 326 is AlN, AlInN, AlGaN, or AlInGaN, or combinations thereof. The barrier layer 326 may comprise a single layer or may be a multilayer structure. In some embodiments, the barrier layer 326 may be a thin AlN layer directly on the channel layer 324 with a single AlGaN layer or multiple layers on top of it. In certain embodiments of the present disclosure, the barrier layer 326 may be sufficiently thick and may have a sufficiently high aluminum composition (Al composition) and doping to induce a significant carrier concentration at the interface between the channel layer 324 and the barrier layer 326 through polarization effects when the barrier layer 326 is hidden beneath ohmic contact metal.The barrier layer 326 can, for example, be from about 0.1 nm to about 30 nm thick, but is not so thick as to cause cracking or significant defect formation. In some embodiments, the thickness of the barrier layer is between 13 and 18 nm. In certain embodiments, the barrier layer 326 is undoped or doped with an n-type dopant at a concentration of less than about 10. 19 cm -3 doped. In some embodiments, the barrier layer is 326 Al x Ga 1-xN, where 0 < x < 1. In certain embodiments, the aluminum concentration is about 25%. However, in other embodiments of the present disclosure, the barrier layer 326 comprises AlGaN with an aluminum concentration between about 5% and less than about 100%. In specific embodiments of the present disclosure, the aluminum concentration is more than about 10%. The channel layer 324 and / or the barrier layer 326 can be deposited, for example, by metal-organic vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride gas epitaxy (HVPE). As discussed herein, a 2DEG layer is induced in the channel layer 324 at a junction between the channel layer 324 and the barrier layer 326. The 2DEG layer acts as a highly conductive layer that enables conduction between the source and drain regions of the device, which are located below the source contact 315 and the drain contact 326, respectively.of the drain contact 305. The channel layer 324 and the junction layer 326 form the semiconductor structure 390.

[0078] While the semiconductor structure 390 is shown for illustrative purposes with the channel layer 324 and the junction 326, the semiconductor structure 390 can include additional layers / structures / elements such as one or more buffer and / or nucleation layer(s) between the channel layer 324 and the substrate 322 and / or a cover layer on the junction 326. HEMT structures that include substrates, channel layers, junctions, and other layers are described, for example, in US Patents 5,192,987, 5,296,395, 6,316,793, 6,548,333, 7,544,963, and 7,548,112.

[0079] Disclosures Nos. 7,592,211, 7,615,774, and 7,709,269 are discussed, the disclosures of which are hereby incorporated herein by reference in their entirety. For example, an AlN buffer layer can be formed on the upper surface 322B of the substrate 322 to provide a suitable crystal structure transition between the silicon carbide substrate 322 and the remainder of the HEMT device 300A.

[0080] Additionally and / or alternatively, one or more load-balancing transition layers may be provided, as described, for example, in the generally granted U.S. Patent No. 7,030,428, the disclosure of which is incorporated herein by reference as if fully set forth herein. The optional buffer / nucleation / transition layers may be deposited by MOCVD, MBE, and / or HVPE.

[0081] The source contact 315 and the drain contact 305 can be formed on an upper surface 326A of the junction 326 and can be laterally spaced apart. A gate contact 310 can be formed on the upper surface 326A of the junction 326 between the source contact 315 and the drain contact 305. The material of the gate contact 310 can be selected based on the composition of the junction 326 and can be a Schottky contact in some embodiments. Conventional materials capable of forming a Schottky contact with a gallium nitride-based semiconductor material can be used, such as nickel (Ni), platinum (Pt), and nickel silicide (NiSi). x ), copper (Cu), palladium (Pd), chromium (Cr), tungsten (W) and / or tungsten silicon nitride (WSiN).

[0082] The source contact 315 and the drain contact 305 can enclose a metal capable of forming an ohmic contact with a gallium nitride-based semiconductor material. Suitable metals include high-melting-point metals such as titanium, tungsten, titanium tungsten (TiW), silicon (Si), titanium tungsten nitride (TiWN), tungsten silicide (WSi), rhenium (Re), niobium (Nb), nickel, gold (Au), aluminum (Al), tantalum (Ta), molybdenum (Mo), and NiSi. x, titanium silicide (TiSi), titanium nitride (TiN), WSiN, Pt, and the like. In some embodiments, the source contact 315 may be an ohmic source contact 315. Thus, the source contact 315 and the drain contact 305 may contain an ohmic contact section in direct contact with the barrier layer 326. In some embodiments, the source contact 315 and / or the drain contact 305 may be formed from a plurality of layers to form an ohmic contact, as described, for example, in generally granted U.S. Patent Nos. 8,563,372 and U.S. Patent Nos.

[0083] No. 9,214,352 may be provided, the revelations of which are hereby incorporated in their entirety by reference herein.

[0084] The source contact 315 can be coupled to a reference signal, such as a ground voltage. Coupling to the reference signal can be provided by a via 325 extending from the lower surface 322A of the substrate 322 through the substrate 322 to the upper surface 326A of the junction. The via 325 can expose a lower surface of the source contact 315. A backplate metal layer 335 can be formed on the lower surface 322A of the substrate 322 and on sidewalls of the via 325. In some embodiments, the backplate metal layer 335 can directly contact the source contact 315. In other embodiments, the backplate metal layer 335 can be indirectly electrically connected to the source contact 315 via additional conductive traces. Thus, the backplate metal layer 335 and a signal coupled to it can be electrically connected to the source contact 315.

[0085] In some embodiments, the source contact 315, the drain contact 305, and the gate contact 310 can be configured as a plurality of source contacts 315, drain contacts 305, and gate contacts 310 on the substrate 322. Referring to Fig. 2A A plurality of drain contacts 305 and source contacts 315 can be arranged alternately on the substrate 322. A gate contact 310 can be arranged between adjacent drain contacts 305 and source contacts 315 to form a plurality of transistor unit cells, examples of which are shown in Fig. 2A can be designated as 300A_1 and 300A_2. Corresponding transistor unit cells 300A_1 and 300A_2 can include a source contact 315, a drain contact 305, and a gate contact 310. Fig. 2A and Fig.For the sake of simplicity, Figure 2B illustrates a subset of the source contacts 315, the drain contacts 305, and the gate contacts 310. However, it is understood that the HEMT device 300A may have additional structures, including additional source contacts 315, drain contacts 305, and gate contacts 310, which are shown in Fig. 2A and Fig. Figure 2B is not illustrated. As experts understand, a HEMT transistor can be formed by the active region between the source contact 315 and the drain contact 305 under the control of a gate contact 310 between the source contact 315 and the drain contact 305.

[0086] Referring to Fig.2B A first insulating layer 350_1 can be formed on the barrier layer 326 and a second insulating layer 350_2 can be formed on the first insulating layer 350_1. In some embodiments, the first insulating layer 350_1 and / or the second insulating layer 350_2 can be silicon nitride (Si x N y ), aluminum nitride (AlN), silicon dioxide (SiO2) and / or another suitable protective material. The thickness of the first insulating layer 350_1 can affect the gate-to-source capacitance and the gate-to-drain capacitance, which can affect the switching speed of the device 300A. Similarly, the thickness of the second insulating layer 350_2 can affect the gate-to-drain capacitance, which can affect the switching speed and the gain of the device 300A. The first and second insulating layers 350_1, 350_2 can affect the in Fig. Form 1 referenced passivation layer(s) 350.

[0087] The source contact 315 and the drain contact 305 can be formed in the first insulating layer 350_1, with sections of each being located beneath the second insulating layer 350_2. It is understood that the present invention is not limited to a specific form of the Fig. The gate contact 310 illustrated in Figure 2B is limited, and other forms of the gate contact 310, as well as other elements of the device 300A, are possible without deviating from the embodiments described herein. In some embodiments, the gate contact 310 may be located closer to the source contact 315 than to the drain contact 305. In some embodiments, the gate contact 310 may be configured as a T-shaped gate and / or gamma gate, the formation of which is exemplified in U.S. Patent No. 8,049,252, U.S. Patent No.

[0088] Disclosures No. 7,045,404 and US Patent No. 8,120,064 are discussed, the disclosures of which are hereby incorporated herein by reference in their entirety. The second insulating layer 350_2 can be formed on the first insulating layer 350_1 and on sections of the drain contact 305, the gate contact 310, and the source contact 315.

[0089] Field plates 312 can be formed on the second insulating layer 350_2. At least one section of a field plate 312 can be located on the gate contact 310. At least one section of the field plate 312 can be located on a section of the second insulating layer 350_2 that lies between the gate contact 310 and the drain contact 305. The field plate 312 can reduce the peak electric field in the HEMT device 300A, which can lead to an increased breakdown voltage and reduced charge trapping. The reduction of the electric field can also provide other advantages, such as reduced leakage currents and increased reliability. Field plates and techniques for forming field plates are discussed by way of example in U.S. Patent No. 8,120,064, the disclosure of which is hereby incorporated herein by reference in its entirety.

[0090] The transmission lines 365 can be arranged in the second insulating layer 350_2. The transmission lines 365 can provide a connection between the drain contact 305, the gate contact 310, and the source contact 315 and other parts of the HEMT device 300A. Individual transmission lines 365 can directly contact the drain contact 305 and / or the source contact 315. The transmission lines 365 can contain metal or another highly conductive material, including, for example, copper, cobalt, gold, and / or a composite metal. For easier illustration, the first and second insulating layers 350_1, 350_2, the field plates 312, and the transmission lines 365 are shown in Fig. 2A not illustrated.

[0091] The multi-layer environmental protection encapsulation stack 220 can be formed on the field plate 312, the transmission lines 365, and the first and second insulating layers 350_1, 350_2. The multi-layer environmental protection encapsulation stack 220 can include the first encapsulation layer 225, which is conformal, and the second encapsulation layer 230, which is self-planarized and / or cured. For easier illustration, the multi-layer environmental protection encapsulation stack 220 is shown in Fig. 2A not illustrated.

[0092] The properties and contents of the first encapsulation layer 225 and the second encapsulation layer 230 may be essentially similar to those of the semiconductor device 300 described herein, and therefore a duplicate description thereof is omitted.

[0093] For example, the upper surface 230A of the second encapsulation layer 230 can be substantially planar across the width of the HEMT device 300A. The thickness Tc of the first encapsulation layer 225, the thicknesses of the regions Tg, Tm, Tr of the second encapsulation layer 230, and the ratio of Tc to Tg, Tm, or Tr can be designed to match those in Table 1.

[0094] A HEMT device 300A, which incorporates the multilayer environmental protection encapsulation stack 220, can exhibit advantageous performance compared to related devices. For example, Fig. 3A to 3D diagrams illustrating the advantageous performance of devices according to embodiments of the present disclosure. Fig.In 3A to 3D, a HEMT device similar to HEMT device 300A was used, which features a multilayer environmental protection encapsulation stack 220 that includes the conformal first encapsulation layer 225 and the planar second encapsulation layer 230 (e.g., with a planar surface), in contrast to conventional HEMT devices with non-planar protective layers. Fig. 3A to 3D the first encapsulation layer 225 enclosed a SiON:SiN bilayer, and the second encapsulation layer 230 enclosed a polyimide.

[0095] Referring to Fig.Figure 3A illustrates a differential scanning calorimetry (DSC) graph showing a comparison of the performance of a device incorporating a multilayer environmental protection encapsulation stack 220, including the first encapsulation layer 225 and the planar second encapsulation layer 230 (curve 710A), versus a conventional HEMT device with non-planar protective layers (curve 712A). Differential scanning calorimetry (DSC) is a thermoanalytical technique that measures the difference in the amount of heat required to raise the temperature of a sample and a reference as a function of temperature.

[0096] In Fig.Figure 3A shows curve 710A, a device enclosing a first encapsulation layer 225, implemented as a SiON:SiN bilayer, and a second encapsulation layer 230, which encloses a polyimide. The device was cured for one hour at 250 °C. The glass transition temperature of the polyimide was 225 °C. Thus, the film was cured at a temperature above the glass transition temperature of the second encapsulation layer 230. The second encapsulation layer 230 has a curing temperature of less than 250 °C and was therefore fully cured.

[0097] In contrast, curve 712A represents an apparatus enclosing a conventional film that lacks the conformal first encapsulation layer 225 and the planar second encapsulation layer 230 as described herein. The conventional film of curve 712A has a glass transition temperature of 350 °C. The apparatus associated with curve 712A was cured at 275 °C for one hour. The curing temperature of the conventional material was such that it could not be fully cured during the one hour at 275 °C. DSC analysis was performed on both films after the one-hour curing time had elapsed.

[0098] As in Fig. Figure 3A illustrates that both films show little film transition up to the die fixing temperature of 315 °C.

[0099] Referring to Fig.Figure 3B illustrates a diagram of the die fixation film loss, showing a variance in the normalized thickness of the multilayer environmental protection encapsulation stack 220 as a function of the time spent at 315 °C, which corresponds to the processing temperatures during die fixation. Fig. 3B represents curve 710B, the same multi-layered environmental protection encapsulation stack 220 according to embodiments of the present

[0100] Revelation, which is in curve 710A of Fig. 3A illustrates the same conventional stack of foils, which is represented by curve 712A in Fig. 3A is illustrated, and curve 714B represents an additional conventional film that does not have the conformal first encapsulation layer 225 and planar / cured second encapsulation layer 230 described herein.

[0101] As in Fig.As illustrated in Figure 3B, curve 710B, representing the multilayer environmental protection encapsulation stack 220, shows less than 5% variation in normalized thickness over 30 minutes at 315°C. In contrast, curve 714B, illustrating a conventional film, shows much more variation over slightly more than 10 minutes. Curve 712B, also a conventional film, behaves similarly to the device encapsulating the multilayer environmental protection encapsulation stack 220. Thus, the multilayer environmental protection encapsulation stack 220 performs at least as well as some conventional device films and much better than others in terms of minimizing variation at relatively high temperatures.

[0102] Referring to Fig.Figure 3C illustrates a diagram of the stress-induced moisture uptake as a variance in the bending of a wafer during an undistorted high-intensity stress test (UHAST). Fig. 3C represents curve 710C, the same multilayer environmental protection encapsulation stack 220 according to embodiments of the present disclosure, which is described in Fig. 3A is illustrated by curve 710A, and curve 712C represents the same conventional foil stack that is shown in Fig. 3A is illustrated by curve 712A.

[0103] As in Fig.Figure 3C illustrates that curve 710C, representing the multilayer environmental protection encapsulation stack 220, shows a bend of less than 1 µm during more than 400 hours of UHAST testing. In contrast, curve 712C, illustrating the conventional film, shows a bend of over 2 µm in less than 100 hours. The improved performance is thought to be partly due to enhanced moisture protection provided by the planar second encapsulation layer 230 of the multilayer environmental protection encapsulation stack 220. Thus, the multilayer environmental protection encapsulation stack 220 provides enhanced protection against environmental influences compared to conventional device films.

[0104] Referring to Fig. 3D, a diagram of a Weibull analysis of reliability data for failures during stress tests (e.g., HAST tests). In Fig.3D represents curve 710D the same multilayer environmental protection encapsulation stack 220 according to embodiments of the present disclosure, which is described in Fig. 3A is illustrated by curve 710A, and curve 712D represents the same conventional stack of foils that is shown in Fig. 3A is illustrated by curve 712A.

[0105] As in Fig.Illustrated in 3D, curve 710D, which represents the multilayer environmental protection encapsulation stack 220, demonstrates improved reliability compared to conventional fixtures for at least the first 100 hours of stress testing. For example, the fixtures represented by curve 710D exhibited only one failure among 232 samples in 96 hours of HAST testing, corresponding to a lot tolerance percent defective (LTPD) of less than two. Similarly, the fixtures represented by curve 710D exhibited no failures among 223 samples in 2000 hours of temperature, humidity, and stress (THB) testing, corresponding to an LTPD of less than one. Thus, the multilayer environmental protection encapsulation stack 220 provides improved product reliability compared to conventional fixture films.

[0106] Fig.Figures 4A to 4K illustrate a method for manufacturing a semiconductor device, such as the HEMT device 300A from Fig. 2A and Fig. 2B, according to embodiments of the present disclosure. Fig. 4A to 4K are views along line BB from Fig. 2A.

[0107] Now, referring to Fig. 4A A substrate 122 is provided on which a semiconductor structure can be formed. A channel layer 324 is formed on the substrate 122, and a barrier layer 326 is formed on the channel layer 324. The substrate 122 can be a semi-insulating silicon carbide substrate (SiC substrate), which can be, for example, the 4H polytype of silicon carbide. Other suitable polytypes of silicon carbide can include the 3C, 6H, and 15R polytypes. The thickness of the substrate 122 can be 100 µm or more.

[0108] Silicon carbide exhibits a much closer crystal lattice match with the group III nitrides (which can be used in the channel layer 324 and / or the barrier layer 326) than sapphire (Al₂O₃), which can be a common substrate material for group III nitride devices. This closer lattice match can result in higher-quality group III nitride foils than those commonly available on sapphire. Silicon carbide also has relatively high thermal conductivity, and therefore the overall power output of group III nitride devices formed on silicon carbide may not be limited by thermal dissipation of the substrate to the same extent as in similar devices formed on sapphire and / or silicon. Furthermore, semi-insulating silicon carbide substrates can provide device insulation and reduced parasitic capacitance.

[0109] It is understood that, although silicon carbide can be used as a substrate, in embodiments of the present invention any suitable substrate can be used for substrate 122, such as sapphire (Al2O3), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), silicon (Si), GaAs, LGO, zinc oxide (ZnO), LAO, indium phosphide (InP) and the like.

[0110] Optional buffer, nucleation, and / or transition layers (not shown) can also be provided on substrate 122. For example, an AlN buffer layer can be provided to facilitate a suitable crystal structure transition between a silicon carbide substrate and the rest of the device. Additionally, one or more stress-balancing transition layers can be provided.

[0111] Further referring to Fig.4A A channel layer 324 is provided on the substrate 122. The channel layer 324 can be deposited on the substrate 122 using buffer layers, transition layers, and / or nucleation layers, as described above. The channel layer 324 can be subjected to pressure. Furthermore, the channel layer 324 and / or the buffer, nucleation, and / or transition layers can be deposited by MOCVD, MBE, and / or HVPE. In some embodiments of the present invention, the channel layer 324 can be a group III nitride layer.

[0112] The barrier layer 326 can be a group III nitride layer. In certain embodiments of the present invention, the barrier layer 326 can be a highly doped n-type layer. For example, the barrier layer 326 can be densified to a concentration of less than about 10 19 cm -3 be endowed.

[0113] In some embodiments of the present invention, the barrier layer 326 can have a thickness, Al composition, and / or doping sufficient to induce a significant carrier concentration at the interface between the channel layer 324 and the barrier layer 326 through polarization effects when the barrier layer 326 is hidden beneath ohmic contact metal. Furthermore, the barrier layer 326 can be thick enough to reduce or minimize electron scattering in the channel due to ionized impurities deposited at the interface between the barrier layer 326 and a subsequently formed first protective layer.

[0114] In some embodiments, the channel layer 324 and the barrier layer 326 can have different lattice constants. For example, the barrier layer 326 can be a relatively thin layer with a smaller lattice constant than the channel layer 324, so that the barrier layer 326 "stretches" at the interface between the two. Accordingly, a pseudomorphic HEMT device (pHEMT device) can be provided.

[0115] Referring to Fig. 4B A first protective layer 410 is formed on the barrier layer 326. The first protective layer 410 can be a dielectric material, such as silicon nitride (Si₂O₆). x N y), aluminum nitride (AlN), silicon dioxide (SiO2), and / or another suitable protective material. Other materials may also be used for the first protective layer 410. For example, the first protective layer 410 may also include magnesium oxide, scandium oxide, aluminum oxide, and / or aluminum oxynitride. Furthermore, the first protective layer 410 may be a single layer or may include multiple layers with uniform and / or non-uniform composition.

[0116] The first protective layer 410 can be formed over the entire surface of the barrier layer 326. For example, the first protective layer 410 can be a silicon nitride layer (SiN layer) formed by high-quality sputtering and / or plasma-enhanced chemical vapor deposition (PECVD). The first protective layer 410 can be sufficiently thick to protect the underlying barrier layer 326 during subsequent annealing of ohmic contacts.

[0117] Referring to Fig. 4C can form the first protective layer 410 (see Fig. 4B) can be structured to form source contacts 315, gate contacts 310, and drain contacts 305. For example, the first protective layer 410 can be structured to form windows that expose the barrier layer 326 for placement of the source contact 315 and the drain contacts 305. The windows can be etched using a structured mask and low-damage etching with respect to the barrier layer 326. Ohmic metal can be formed on the exposed portions of the barrier layer 326. The ohmic metal can be annealed to provide the source contacts 315 and the drain contacts 305.

[0118] The first protective layer 410 can be structured to provide the gate contacts 310. The first protective layer 410 can be etched to form windows that expose the junction 326 for placement of the gate contact 310. The gate contacts 310 can be formed within the etched windows and can extend through the first protective layer 410 to contact the exposed portion of the junction 326. Suitable gate materials may depend on the composition of the junction 326. However, in certain embodiments, conventional materials capable of forming a Schottky contact with a nitride-based semiconductor material, such as Ni, Pt, or NiSi, can be used. xCu, Pd, Cr, TaN, W and / or WSiN. A section of the gate contacts 310 can extend onto a surface of the first protective layer 410. The formation of the source contacts 315, the gate contacts 310 and the drain contacts 305 can be used to structure the first protective layer 410. Fig. 4B to form the first insulating layer 350_1.

[0119] Although the Source contact 315 in Fig. 4C is illustrated as being located on the upper surface of the barrier layer 326, it is understood that in some embodiments the source contacts 315, the gate contacts 310 and / or the drain contacts 305 may be formed within recesses in the upper surface of the barrier layer 326.

[0120] Referring to Fig.4D A second protective layer 420 can be formed on the first insulating layer 350, the source contacts 315, the gate contacts 310, and the drain contacts 305. The second protective layer 420 can be a dielectric layer. In some embodiments, the second protective layer 420 can have a different dielectric index than the first insulating layer 350.

[0121] Referring to Fig. 4E Field plates 312 can be formed on the second protective layer 420. The field plate 312 can overlap the gate contact 310 (e.g., in the Z-direction of Fig.4E) and can extend over a distance in the area between the gate and the drain (i.e., the gate-drain region). The overlap of the field plate 312 over the gate contact 310 and / or the distance over which the field plate 312 extends in the gate-drain region can be varied to achieve optimal results. In some embodiments, the field plate 312 can be electrically connected to the gate contact 310 or the source contact 315, and it is understood that field plate structures other than those illustrated in the figures can be used without deviating from the invention.

[0122] Referring to Fig.The second protective layer 420 can be structured to form the transmission lines 365. For example, the second protective layer 420 can be structured to form windows that expose the source contacts 315 and / or the drain contacts 305 for placement of the transmission lines 365. The windows can be etched using a structured mask and low-damage etching with respect to the source contacts 315 and / or the drain contacts 305. Conductive metal can be formed on the exposed sections of the source contacts 315 and / or the drain contacts 305 to form the transmission lines 365. The formation of the transmission lines 365 can be used to structure the second protective layer 420. Fig. 4E lead to form the second insulating layer 350_2.

[0123] Referring to Fig.In 4G, a conformal first encapsulation layer 225 can be formed on the field plate 312, the transmission lines 365 and / or the first and second insulating layers 350_1, 350_2. The upper surface of the first encapsulation layer 225 cannot be planar.

[0124] The first encapsulation layer 225 can be or include one or more dielectric layers. For example, the first encapsulation layer 225 can include SiO₂, SiN, SiON₂, ZrO₂, HfO₂, AlN, and / or AlO₂. In some embodiments, the first encapsulation layer 225 can include multiple layers. For example, the first encapsulation layer 225 can include a SiON₂:SiN bilayer. The thickness Tc of the first encapsulation layer 225 can be conformal and substantially uniform across the semiconductor device, but the embodiments of the present disclosure are not limited thereto. The first encapsulation layer 225 can be deposited using wafer-level processing techniques such as CVD, PECVD, ALD, or PVD.

[0125] Referring to Fig.4H An uncured layer 430 can be formed on the first encapsulation layer 225 such that the first encapsulation layer 225 lies between the uncured layer 430 and the field plate 312, the transmission lines 365 and / or the first and second insulating layers 350_1, 350_2. The uncured layer 430 can be a curable dielectric layer formed in a viscous or liquid state, for example by a spin coating, spray coating, vapor deposition, electroplating, blade coating or slot die deposition process.

[0126] The uncured layer 430 can, for example, comprise polyimide, benzocyclobutene (BCB), glass (e.g., borosilicate glass (BSG)), polyamide, polybenzoxazole (PBO), and / or a photoresist (e.g., SU-8). Other epoxides and / or resins can be used without deviating from the embodiments of this disclosure. In some embodiments, the material of the uncured layer 430 can be selected to have a kinematic viscosity of 100 to 8000 cSt. In some embodiments, the material of the uncured layer 430 can be selected to have a kinematic viscosity of 1000 to 2000 cSt.

[0127] The upper surface 430A of the uncured layer 430 cannot be planar. This means that, since the uncured layer 430 is not yet cured, the upper surface 430A of the uncured layer 430 may (at least initially) include variations, surface irregularities, and / or deviations. Due to the viscosity of the uncured layer 430, the uncured layer 430 may flow into openings and / or other deviations in the surface of the first encapsulation layer 225. Furthermore, in some embodiments, the viscosity of the uncured layer 430 may allow the upper surface 430A of the uncured layer 430 to self-planarize.

[0128] Referring to Fig.4I A curing process 480 can be carried out on the uncured layer 430. The curing process 480 can, for example, include the application of heat, but the embodiments of the present disclosure are not limited thereto. In some embodiments, the curing process 480 can be carried out at a temperature of less than 275 °C. In some embodiments, the curing process 480 can be carried out at a temperature of less than or equal to 250 °C. The material of the uncured layer 430 can be selected such that it has a curing temperature of less than 275 °C and, in some embodiments, less than 250 °C. Thus, as a result of the curing process 480, the uncured layer 430 can be substantially and / or completely cured. In some embodiments, the curing process 480 can, for example, include the application of certain wavelengths of light, such as ultraviolet light (UV light).

[0129] In some embodiments, the curing process 480 can be carried out at a temperature greater than the glass transition temperature of the uncured layer material 430. In some embodiments, the uncured layer material 430 can be selected to have a glass transition temperature of less than 250 °C (e.g., 225 °C), and the curing process 480 can be carried out for one hour at 250 °C.

[0130] In Fig. 4I illustrates the upper surface 430A of the uncured layer 430 as planar. In some embodiments, the viscosity of the uncured layer may allow the upper surface 430A of the uncured layer 430 to be planar. Fig. 4H illustrated non-planar surfaces in the Fig.4I illustrates the planar surface transitions (i.e., becomes planar itself). In some embodiments, the transition from the surface shown in Fig. 4H illustrated the transformation of a non-planar surface into a planar surface during the process. Fig. The hardening process illustrated in section 41 is carried out as follows: 480.

[0131] Referring to Fig.As a result of the hardening process 480, the unhardened layer 430 can be transformed into the planar and / or hardened second encapsulation layer 230. The upper surface 230A of the second encapsulation layer 230 can be substantially planar across the width of the device. As a result of the hardening process, the upper surface 230A of the second encapsulation layer 230 can be self-planarized. That is, the upper surface 430A of the unhardened layer 430, which includes variations, surface irregularities, and / or deviations, can be transformed into the upper surface 230A of the second encapsulation layer 230, which is substantially planar and / or hardened as a result of the hardening process. Thus, the planar upper surface 230A can be provided without the need for a planarization step.In some embodiments, the thickness Tc of the first encapsulation layer 225, the thicknesses of the regions Tg, Tm, Tr of the second encapsulation layer 230 and a ratio of the thickness Tc to Tg, Tm or Tr of the second encapsulation layer 230 can be designed to match those in Table 1.

[0132] Referring to Fig. 4K can handle substrate 122 (see Fig.4J) are thinned to form the thinned substrate 322. In some embodiments, the thickness of the substrate 322 is reduced using a grinding machine, such as a plunge or deep grinding machine. In other embodiments, the thickness of the substrate 322 is reduced by lapping, chemical or reactive ion etching, or combinations of these methods with or without grinding. In still other embodiments, etching may be used to treat the back side of the substrate 322 to reduce possible damage to the substrate 322 resulting from the thinning process. Methods for thinning a wafer are described, for example, in the generally granted U.S. Patent Nos. 7,291,529, 7,932,111, 7,259,402, and 7,259,402. Nos. 8,513,686, whose revelations are included in their entirety by reference herein.

[0133] In some embodiments of the invention, the substrate 322 is thinned to a thickness of between approximately 40 µm and approximately 100 µm. In other embodiments, the substrate 322 is thinned to a thickness of between approximately 40 µm and approximately 75 µm.

[0134] In some embodiments, the thinning of the substrate 122 is omitted, and the substrate 122 is effectively identical to the substrate 322. Although Fig. Figure 4K illustrates that the substrate 122 is thinned after the formation of the multilayer environmental protection encapsulation stack 220, which includes the first encapsulation layer 225 and the second encapsulation layer 230. However, the embodiments of the present disclosure are not limited to this. In some embodiments, the thinning of the substrate 122 can take place at other points in the processing, such as before the formation of the multilayer environmental protection encapsulation stack 220.

[0135] Referring again to Fig.2B The via 325 can be formed in the substrate 322, the channel layer 324, and the barrier layer 326. The via 325 can be formed by wet or dry etching. In some embodiments, the via 325 can be etched anisotropically, such that the sidewalls of the via 325 are inclined with respect to a top surface of the substrate 322. In some embodiments, the via 325 can expose a bottom surface of the source contact 315. In some embodiments, the source contact 315 can serve as an etch stop material during the formation of the via 325. After the formation of the via, the backplate metal layer 335 can be deposited on the bottom surface 322A of the substrate 322, the sidewalls of the via 325, and the bottom surface of the source contact 315.The reverse side metal layer 335 can include a conductive metal, such as titanium, platinum and / or gold.

[0136] Although in Fig. Since a 300A HEMT device was illustrated for 4A to 4K, it is understood that the one in relation to Fig. The multilayer environmental protection encapsulation stack 220 described in Sections 4A to 4K can be provided using other types of semiconductor devices. In other words, other types of semiconductor devices can be used, and the methods for forming the environmental protection encapsulation stack 220, including the first encapsulation layer 225 and second encapsulation layer 230 described herein (e.g., Fig. 4G to 4J) can be applied to the semiconductor device without deviating from the scope of protection of the present disclosure. Fig.Figures 5A to 5B illustrate exemplary semiconductor devices 300B and 300C that can enclose the multilayer environmental protection encapsulation stack 220 described herein. A double description of elements of Fig. 5A and Fig. Sections 5B, which have already been described, are omitted for the sake of brevity. Fig. 5A and Fig. 5B are generally views along lines AA of Fig. 2A. However, it is understood that the embodiments of the present disclosure do not include those of Fig. 2B, Fig. 5A and Fig. 5B are limited and in general the methods / structures of the present disclosure and an encapsulation stack can be applied to any semiconductor device with elements on its upper surface having upper surfaces at different heights.

[0137] Fig.Figure 5A illustrates a metal-semiconductor field-effect transistor (MESFET) device 300B, in which the area of ​​the semiconductor structure 390 between the source and drain regions 215 and 205 provides the conduction channel or channel region of the MESFET 300B. Fig. Figure 5B illustrates a metal oxide semiconductor field-effect transistor (MOSFET) device 300C, in which the semiconductor structure area 390 between the source and drain areas 215 and 205 provides the channel area of ​​the MOSFET 300C and the gate contact 310 is separated from the channel area by a gate oxide layer 110.

[0138] Each of the semiconductor devices 300B, 300C can enclose the multilayer environmental protection encapsulation stack 220, which is located on the device and protects it. Fig. 5A and Fig.5B is the multilayer environmental protection encapsulation stack 220 with a similar structure (e.g., a conformal first encapsulation layer 225 and a self-planarized and / or cured second encapsulation layer 230) as that of the in Fig. 1 and Fig. 2B illustrated semiconductor devices 300 and 300A. Semiconductor devices 300B and 300C from Fig. 5A and Fig. 5B can have similar ratios of the thicknesses of the first encapsulation layer 225 and the second encapsulation layer 230 as described herein and shown in Table 1.

[0139] Although Fig. 2A, Fig. 5A and Fig.5B While embodiments are illustrated in which the semiconductor devices each have the source, drain, and gate contacts on an upper surface of the semiconductor device, the embodiments of this disclosure are not limited thereto. Semiconductor devices that include one or more contacts (e.g., a drain contact) on a lower surface of the device may also include the multilayer environmental protection encapsulation stack 220 described herein (e.g., with a conformal first encapsulation layer 225 and a self-planarized and / or hardened second encapsulation layer 230) without deviating from the scope of this disclosure.

[0140] Fig.Figures 6A to 6C are schematic cross-sectional views illustrating several exemplary ways of packing the semiconductor device 300 according to embodiments of the present disclosure in order to provide respective packed transistor amplifiers 600A to 600C. Fig. 6A-6C show that the semiconductor device 300 of Fig. 1 is packed, it goes without saying that in the in Fig. The packages illustrated in Figures 6A-6C can be any of the semiconductor devices 300A, 300B, 300C according to embodiments of the present disclosure.

[0141] Fig. Figure 6A is a schematic side view of a packed transistor amplifier 600A. As shown in Fig.As shown in Figure 6A, the packed transistor amplifier 600A includes the semiconductor device 300, which is packed in an open-cavity package 610A. The package 610A includes metal gate leads 622A, metal drain leads 624A, a metal submount 630, side walls 640, and a cover 642.

[0142] The submount 630 can include materials configured to support the thermal management of the packed transistor amplifier 600A. For example, the submount 630 can include copper and / or molybdenum. In some embodiments, the submount 630 can consist of multiple layers and / or include vias / connections. In one exemplary embodiment, the submount 630 can be a multilayer copper / molybdenum / copper-metal flange comprising a core molybdenum layer with copper sheathing on each major surface thereof. In some embodiments, the submount 630 can include a metal heat sink that is part of a conductor frame or a metal plug. The side walls 640 and / or the cover 642 can, in some embodiments, be formed of or include an insulating material.For example, the side walls 640 and / or the cover 642 can be made of or enclose ceramic materials. In some embodiments, the side walls 640 and / or the cover 642 can, for example, be made of Al₂O₃. The cover 642 can be bonded to the side walls 640 using an epoxy adhesive. The side walls 640 can, for example, be attached to the submount 630 by brazing. The gate line 622A and the drain line 624A can be configured to extend through the side walls 640, although embodiments of the present invention are not limited to this.

[0143] The semiconductor device 300 is mounted on the upper surface of the metal submount 630 in an air-filled cavity 612, which is defined by the metal submount 630, the ceramic side walls 640, and the ceramic lid 642. The gate and drain terminals 632, 634 of the semiconductor device 300 can be located on the top of the semiconductor device 300, while a source terminal 636 can be located on the bottom of the semiconductor device 300. The source terminal 636 can be mounted to the metal submount 630, for example, using a conductive die mounting material (not shown). The metal submount 630 can provide the electrical connection to the source terminal 636 and can also serve as a heat dissipation structure, dissipating heat generated in the semiconductor device 300.The heat is primarily generated in the upper section of the semiconductor device 300, where relatively high current densities are produced, for example, in the channel regions of the unit cell transistors. This heat can be transferred through the semiconductor structure 390 to the source terminal 636 and then to the metal submount 630.

[0144] Input matching circuits 650 and / or output matching circuits 652 may also be mounted within the 610A package. The matching circuits 650 and 652 may include impedance matching and / or harmonic termination circuits. The impedance matching circuits can be used to match the impedance of the fundamental component of RF signals input to or output from the transistor amplifier 600A to the impedance at the input or output of the semiconductor device 300. The harmonic termination circuits can be used to ground harmonics of the fundamental RF signal that may be present at the input or output of the semiconductor device 300. More than one input matching circuit 650 and / or output matching circuit 652 may be provided, as shown schematically in Fig.As shown in Figure 6A, the input and output matching circuits 650 and 652 can be mounted on the metal submount 630. The gate line 622A can be connected to the input matching circuit 650 by one or more bond wires 654, and the input matching circuit 650 can be connected to the gate terminal 632 of the semiconductor device 300 by one or more additional bond wires 654. Similarly, the drain line 624A can be connected to the

[0145] Output matching circuit 652 may be connected, and the output matching circuit 652 may be connected to the drain terminal 634 of the semiconductor device 300 by one or more additional bond wires 654. The bond wires 654, which are inductive elements, may form part of the input and / or output matching circuits 650, 652.

[0146] Fig.Figure 6B is a schematic side view of a packed transistor amplifier 600B, which incorporates the semiconductor device 300 from Fig. 1 includes, which is packed in a printed circuit board-based package 610B. The packed transistor amplifier 600B is the packed transistor amplifier 600A of Fig. 6A is very similar, except that the gate and drain lines 622A, 624A of package 610A are replaced by the PCB-based lines 622B, 624B in package 610B.

[0147] Package 610B includes a submount 630, ceramic side panels 640, and a ceramic cover 642, each of which may be substantially identical to the correspondingly numbered elements of package 610A discussed above. Package 610B further includes a printed circuit board 620. Conductive traces on the printed circuit board 620 form a metal gate trace 622B and a metal drain trace 624B. The printed circuit board 620 may, for example, be attached to the submount 630 by means of a conductive adhesive. The printed circuit board 630 includes a central opening, and the semiconductor device 300 is mounted within this opening on the submount 630. Other components of the transistor amplifier 600B may be the same as the correspondingly numbered components of the transistor amplifier 600A, and therefore a further description of them is omitted.

[0148] Fig.Figure 6C is a schematic side view of another packed transistor amplifier, 600C. The transistor amplifier 600C differs from the transistor amplifier 600A in that it includes a different package, 610C. Package 610C includes a metal submount 630 (which may be similar to or identical with the similarly numbered submount 630 of package 210A) as well as the metal gate and drain leads 622C and 624C. The transistor amplifier 600C also includes a plastic overmold 660 that at least partially surrounds the semiconductor device 300, the leads 622C and 624C, and the metal submount 630. Other components of the transistor amplifier 600C may be the same as the similarly numbered components of the transistor amplifier 600A, and therefore a further description of them is omitted.

[0149] It is understood that while the terms "first," "second," etc., are used in this document to describe different elements, these elements should not be limited by these terms. These terms serve only to distinguish the individual elements from one another. For example, a first element could be referred to as a second element, and similarly, a second element could be referred to as a first element, without altering the scope of the present invention. As used herein, the term "and / or" includes all combinations of one or more of the associated listed elements.

[0150] The terminology used herein serves only to describe certain embodiments and is not intended to limit the invention. As used herein, the singular forms "a", "an", "one" and "the" are to include the plural forms unless the context clearly indicates otherwise. It is further understood that the terms "comprise", "comprehensive", "including", and / or "inclusive", as used herein, indicate the presence of specified features, integers, steps, processes, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, processes, elements, components, and / or groups thereof.

[0151] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by persons skilled in the art in the field to which this invention belongs. It is further understood that terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant field, and not in an idealized or overly formal sense, unless expressly defined herein.

[0152] It is understood that when an element, such as a layer, area, or substrate, is described as being "on" or "extending" upon another element, it may be located directly on or extending upon that other element, or there may be intermediate elements. Conversely, when an element is described as being "directly on" or extending upon another element, there are no intermediate elements. It is also understood that when an element is described as being "connected" or "coupled" to another element, it may be directly connected or coupled to that other element, or there may be intermediate elements. Conversely, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0153] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "lateral" or "vertical" may be used here to describe a relationship of one element, layer, or area to another element, layer, or area, as illustrated in the figures. It is understood that these terms are intended to encompass orientations of the device other than the one shown in the figures.

[0154] Embodiments of the invention are described herein with reference to cross-sectional drawings, which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. For clarity, the thickness of layers and areas in the drawings may be exaggerated. Furthermore, deviations from the shapes shown in the illustrations are to be expected, for example, as a result of manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be interpreted as being limited to the specific shapes of areas illustrated herein, but should include deviations in shape that result, for example, from the manufacturing process. Similarly, it is understood that dimensional deviations based on standard tolerances in manufacturing processes are to be expected.As used herein, unless otherwise stated, “approximately” and / or “essentially” includes values ​​within 10% of the nominal value.

[0155] Identical reference numerals consistently refer to the same elements. Therefore, the same or similar reference numerals can be described by reference to other drawings, even if they are neither mentioned nor described in the corresponding drawing. Furthermore, elements not designated by reference numerals can be described by reference to other drawings.

[0156] Some embodiments of the invention are described with reference to semiconductor layers and / or regions characterized by having a conductivity type such as n-type or p-type, which refers to the majority carrier concentration in the layer and / or region. Thus, N-type material has a majority equilibrium concentration of negatively charged electrons, while P-type material has a majority equilibrium concentration of positively charged holes. Certain materials may be designated with a "+" or "-" (as in N+, N-, P+, P-, N++, N--, P++, P--, or the like) to indicate a relatively larger ("+") or smaller ("-") concentration of majority carriers compared to another layer or region. However, such notation does not imply the presence of a specific concentration of majority or minority carriers in a layer or region.

[0157] The drawings and the patent specification disclose usual embodiments of the invention, and although specific terms are used, they are used only in a general and descriptive sense and not for limitation purposes, the scope of protection of the invention being set out in the following claims. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

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[0132]

Claims

[1] Transistor device comprising: a substrate; a semiconductor structure on the substrate; a metallization layer comprising a non-planar surface on a surface of the semiconductor structure; a non-planar encapsulation layer on the non-planar surface of the metallization layer, the non-planar encapsulation layer comprising a non-planar encapsulation surface opposite the non-planar surface; and a self-planarizing encapsulation layer on the non-planar encapsulation layer comprising a planarized surface opposite the non-planar encapsulation surface. [2] The transistor device of claim 1, further comprising: a source contact on a source region of the semiconductor structure; a drain contact on a drain region of the semiconductor structure; and a gate contact between the source contact and the drain contact, wherein the non-planar encapsulation layer lies on the gate contact, the drain contact and the source contact. [3] The transistor device of claim 2, wherein a ratio of a thickness of the non-planar encapsulation layer over the gate contact to a thickness of the self-planarizing encapsulation layer over the gate contact is between 0.20 and 0.

29. [4] The transistor device of claim 2, wherein the metallization layer comprises a transmission line on the source contact, and wherein a ratio of a thickness of the non-planar encapsulation layer over the transmission line to a thickness of the self-planarizing encapsulation layer over the transmission line is between 0.28 and 0.

45. [5] The transistor device of claim 2, wherein the semiconductor structure further comprises a source access region between the source contact and the gate contact, and wherein a ratio of a thickness of the non-planar encapsulation layer over the source access region to a thickness of the self-planarizing encapsulation layer over the source access region is between 0.16 and 0.

22. [6] A transistor device according to any preceding claim, wherein a thickness of the non-planar encapsulation layer is substantially uniform across the semiconductor structure. [7] A transistor device according to any preceding claim, wherein the non-planar encapsulation layer comprises SiO, SiN, SiON, ZrO, HfO, AlN and / or AlO. [8] A transistor device according to any preceding claim, wherein the self-planarizing encapsulation layer comprises polyimide, benzocyclobutene, glass, polyamide, polybenzoxazole and / or a photoresist. [9] A transistor device according to any preceding claim, wherein the self-planing encapsulation layer comprises a material having an uncured kinematic viscosity of 100 to 8000 centistokes. [10] A transistor device according to any preceding claim, wherein the self-planing encapsulation layer comprises a material having a curing temperature of less than or equal to 250°C. [11] A transistor device according to any preceding claim, wherein the self-planarizing encapsulation layer comprises a material that is substantially hardened. [12] Transistor device comprising: a substrate; a semiconductor structure on the substrate, the semiconductor structure having an active region; a gate contact on the active region of the semiconductor structure; a first encapsulation layer extending on the gate contact; and a second encapsulation layer on the first encapsulation layer, wherein the second encapsulation layer comprises a material having a curing temperature of less than or equal to 275°C. [13] The transistor device of claim 12, wherein a ratio of a thickness of the first encapsulation layer over the gate contact to a thickness of the second encapsulation layer over the gate contact is between 0.20 and 0.

29. [14] The transistor device of claim 12 or 13, wherein the semiconductor structure further comprises a source region, wherein the transistor device further comprises a source contact on the source region and a transmission line on the source contact, and wherein the first encapsulation layer extends on the source contact and the transmission line. [15] The transistor device of claim 14, wherein a ratio of a thickness of the first encapsulation layer over the transmission line to a thickness of the second encapsulation layer over the transmission line is between 0.28 and 0.

45. [16] The transistor device of claim 14, wherein the semiconductor structure further comprises a source access region between the source contact and the gate contact, and wherein a ratio of a thickness of the first encapsulation layer over the source access region to a thickness of the second encapsulation layer over the source access region is between 0.16 and 0.

22. [17] The transistor device of any of claims 12 to 16, wherein a thickness of the first encapsulation layer is substantially uniform across the semiconductor structure. [18] A transistor device according to any one of claims 12 to 17, wherein a top surface of the second encapsulation layer is substantially planar across the semiconductor structure. [19] A transistor device according to any one of claims 12 to 18, wherein the first encapsulation layer comprises SiO, SiN, SiON, ZrO, HfO, AlN and / or AlO. [20] A transistor device according to any one of claims 12 to 19, wherein the second encapsulation layer comprises polyimide, benzocyclobutene, glass, polyamide, polybenzoxazole and / or a photoresist. [21] The transistor device of any one of claims 12 to 20, wherein the second encapsulation layer comprises a material having a curing temperature of less than or equal to 250°C. [22] Transistor device comprising: a semiconductor structure on a substrate, the semiconductor structure having a source region and a drain region; a source contact on the source area; a drain contact on the drain region; a first encapsulation layer conformally deposited on the drain contact, on the source contact and on the semiconductor structure between the drain contact and the source contact; and a second encapsulation layer on the first encapsulation layer, the second encapsulation layer comprising a material having a substantially planar top surface extending from the source contact to the drain contact, the material configured to transition from a kinematic viscosity of 100 to 8000 centistokes to a cured state during a curing process. [23] The transistor device of claim 22, wherein the first encapsulation layer comprises SiO, SiN, SiON, ZrO, HfO, AlN and / or AlO. [24] A transistor device according to claim 22 or 23, wherein the first encapsulation layer comprises a plurality of layers. [25] A transistor device according to any one of claims 22 to 24, wherein the second encapsulation layer comprises polyimide, benzocyclobutene, glass, polyamide, polybenzoxazole and / or a photoresist. [26] The transistor device of any one of claims 22 to 25, wherein the second encapsulation layer comprises a material having a curing temperature of less than or equal to 275°C. [27] A method of forming a transistor device comprising: Forming a semiconductor structure on a substrate; Forming a first encapsulation layer on the semiconductor structure comprising a non-planar surface facing the semiconductor structure; Forming a second encapsulation layer on the first encapsulation layer, the second encapsulation layer comprising a planarized surface opposite the first encapsulation layer; and Performing a curing process on the second encapsulation layer. [28] The method of claim 27, wherein the second encapsulation layer comprises a material configured to transition from a kinematic viscosity of 100 to 8000 centistokes to a cured state during the curing process. [29] The method of claim 27, wherein the planarized surface of the second encapsulation layer is a result of self-planarization of a material of the second encapsulation layer. [30] The method of any one of claims 27 to 29, further comprising forming a source contact, a drain contact, and a gate contact on the semiconductor structure, wherein forming the first encapsulation layer comprises forming the first encapsulation layer on the gate contact, the drain contact, and the source contact. [31] The method of claim 30, wherein the second encapsulation layer has a non-planar surface opposite the planarized surface and extending on the first encapsulation layer along respective profiles defined by the source contact, the drain contact and / or the gate contact. [32] The method of claim 30 or 31, wherein a thickness of the first encapsulation layer is substantially uniform across the gate contact, the drain contact, and the source contact. [33] A method according to any one of claims 27 to 32, wherein the first encapsulation layer comprises SiO, SiN, SiON, ZrO, HfO, AlN and / or AlO. [34] A method according to any one of claims 27 to 33, wherein the second encapsulation layer comprises polyimide, benzocyclobutene, glass, polyamide, polybenzoxazole and / or a photoresist. [35] The method of any one of claims 27 to 34, wherein the second encapsulation layer comprises a material having a curing temperature of less than or equal to 275°C. [36] The method of any one of claims 27 to 35, wherein performing the curing process on the second encapsulation layer is at a temperature greater than a glass transition temperature of a material of the second encapsulation layer. [37] The method of any one of claims 27 to 36, wherein performing the curing process on the second encapsulation layer is at a temperature of less than or equal to 275°C. [38] The method according to any one of claims 27 to 37, wherein forming the second encapsulation layer on the first encapsulation layer is performed by processes comprising a spin-on process, a spray-on process, a vapor-deposition process, a plating process, a blade-coating process and / or a slot-die deposition process.