Stacked FET SRAM Build

Abstract

Exhibiting a semiconductor structure: a lower unit level comprising a first lower field-effect transistor, FET, (FET_1B) of a first conductivity type, a second lower FET (FET_2B) of the first conductivity type, a third lower FET (FET_3B) of the first conductivity type, and a fourth lower FET (FET_4B) of the first conductivity type, wherein the first lower FET (FET_1B) is electrically connected to the second lower FET (FET_2B), the third lower FET (FET_3B) is electrically connected to the fourth lower FET (FET_4B), the first lower FET (FET_1B) is arranged diagonally to the fourth lower FET (FET_4B), the second lower FET (FET_2B) is arranged diagonally to the third lower FET (FET_3B), and the first lower FET (FET_1B) and the fourth lower FET (FET_4B) are pass-gates. are; and an upper unit level stacked above the lower unit level, comprising a first upper FET (FET_1T) of a second conductivity type different from the first conductivity type, arranged directly above the first lower FET (FET_1B), a second upper FET (FET_2T) of the second conductivity type, arranged directly above the second lower FET (FET_2B), a third upper FET (FET_3T) of the second conductivity type, arranged directly above the third lower FET (FET_3B), and a fourth upper FET (FET_4T) of the second conductivity type, arranged directly above the fourth lower FET (FET_4B), wherein the first upper FET (FET_1T) is electrically connected to the second upper FET (FET_2T), and the third upper FET (FET_3T) is electrically connected to the fourth upper FET (FET_4T), and the first upper FET (FET_1T) is a first The dummy transistor is wired for cross-coupling (130) with the third upper FET (FET_3T),and the fourth upper FET (FET_4T) is a second dummy transistor wired for cross-coupling (130) with the second upper FET (FET_2T), and the second lower FET (FET_2B) and the second upper FET (FET_2T) are wired to provide a first inverter, and the third lower FET (FET_3B) and the third upper FET (FET_3T) are wired to provide a second inverter.

Description

BACKGROUND

[0001] The present application relates to semiconductor technology, in particular a semiconductor structure comprising a stacked field-effect transistor (FET) with a static random access memory (SRAM) configuration.

[0002] Monolithic stacking of transistors is an attractive architecture for future scaling of complementary metal-oxide semiconductors (CMOS) and potentially for ultimate scaled technology. Significant area scaling can be achieved by directly stacking one type of FET (e.g., an n-type FET) on top of another type (e.g., a p-type FET).

[0003] SRAM is a type of random-access memory (RAM) that uses latching circuits (flip-flops) to store each bit. A typical SRAM cell consists of up to six FETs. In a conventional SRAM, each bit is stored on four of the transistors, forming two cross-coupled inverters. This memory cell has two stable states used to represent 0 and 1. Two additional access transistors control access to a memory cell during read and write operations. Besides this six-transistor (6T) SRAM, other types of SRAM chips use 4, 8, 10 (4T, 8T, 10T SRAM), or more transistors per bit. Implementing a stacked architecture SRAM design is challenging.

[0004] Document US 10 297 592 B2 describes monolithic 3D integrated circuits (3D ICs) that use one or more local intermediate-plane connections tightly integrated with at least one structure of at least one transistor on at least one transistor plane within the 3D IC.

[0005] Document US 2021 / 0074350A1 describes a six-transistor SRAM memory cell. The SRAM memory cell incorporates crossed transistors in cross-coupled inverters to achieve a more compact form factor and simplify manufacturing.

[0006] Document CN 112 602 193 A describes a semiconductor device comprising multiple transistor pairs stacked on a substrate. Each of the multiple transistor pairs contains an n-type transistor and an ap-type transistor stacked on top of each other. The device also includes multiple gate electrodes arranged in a stepped configuration across the substrate. These gate electrodes are electrically connected to the gate structures of the multiple transistor pairs. The semiconductor device further includes multiple local source / drain (S / D) junctions, also arranged in a stepped configuration across the substrate. These local S / D junctions are electrically coupled to the source and drain regions of the multiple transistor pairs. SUMMARY

[0007] The present application provides a compact SRAM structure with a stacked architecture. In particular, the present application provides a 6-transistor SRAM bit cell comprising a lower unit level containing lower field-effect transistors and an upper unit level stacked above the lower unit level, containing upper field-effect transistors of a different conductivity type than the lower field-effect transistors.

[0008] In one embodiment of the present application, a semiconductor structure is provided that has a compact SRAM configuration and a stacked architecture. In one embodiment, the semiconductor structure includes a lower unit level comprising a first lower field-effect transistor (FET) of a first conductivity type, a second lower FET of the first conductivity type, a third lower FET of the first conductivity type, and a fourth lower FET of the first conductivity type, wherein the first lower FET is electrically connected to the second lower FET, the third lower FET is electrically connected to the fourth lower FET, the first lower FET is arranged diagonally to the fourth lower FET, and the second lower FET is arranged diagonally to the third lower FET, and the first lower FET and the fourth lower FET are pass gates. The semiconductor structure further comprises an upper unit level,which is stacked over the lower unit level and has a first upper FET of a second conductivity type, different from the first conductivity type, arranged directly above the first lower FET, a second upper FET of the second conductivity type arranged directly above the second lower FET, a third upper FET of the second conductivity type arranged directly above the third lower FET, and a fourth upper FET of the second conductivity type arranged directly above the fourth lower electrode, wherein the first upper FET is electrically connected to the second upper FET, and the third upper FET is electrically connected to the fourth upper FET, and the first upper FET is a first dummy transistor wired for cross-coupling with the third upper FET, and the fourth upper FET is a second dummy transistor wired for cross-coupling with the second upper FET.and the second lower FET and the second upper FET are wired to provide a first inverter, and the third lower FET and the third upper FET are wired to provide a second inverter. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a circuit diagram of a semiconductor structure according to an embodiment of the present application. Fig. 2A is a top view showing the structure of the upper unit plane of the semiconductor structure according to an embodiment of the present application. Fig. 2B is a top view showing the structure of the lower unit level of the semiconductor structure according to an embodiment of the present application; wherein this lower unit level is located below the one shown in Fig. is arranged in the upper unit plane shown in 1A. Fig. 3A is a sectional view through the in Fig. Section AA shown in 2A according to an embodiment of the present application. Fig. 3B is a sectional view through the in Fig. Section BB shown in 2A according to an embodiment of the present application. Fig. 3C is a cross-sectional view through the in Fig. Section CC shown in 2A according to an embodiment of the present application. Fig. 3D is a cross-sectional view through the in Fig. Section DD shown in 2A according to an embodiment of the present application. Fig. 4A is a sectional view through the in Fig. Section AA shown in 2A according to a further embodiment of the present application. Fig. 4B is a sectional view through the in Fig. Section BB shown in 2A according to a further embodiment of the present application. Fig. 4C is a cross-sectional view through the in Fig. Section CC shown in 2A according to a further embodiment of the present application. Fig. 4D is a cross-sectional view through the in Fig. Section DD shown in 2A according to a further embodiment of the present application. DETAILED DESCRIPTION

[0009] The present application will now be described in more detail with reference to the explanation below and the drawings accompanying it. It should be noted that the drawings accompanying the present application are provided for illustrative purposes only and are therefore not to scale. It should also be noted that identical and corresponding elements are designated by the same reference numerals.

[0010] The following description provides numerous specific details, such as particular structures, components, materials, dimensions, processing steps, and methods, to facilitate understanding of the various embodiments of the present application. However, it is clear to those skilled in the art that the various embodiments of the present application can be implemented without these specific details. In other cases, well-known structures or processing steps have not been described in detail to avoid complicating the present application.

[0011] It should be noted that when an element such as a layer, area, or substrate is described as "on" or "above" another element, it may be located directly on top of the other element, or there may be elements in between. Conversely, when an element is described as "directly on" or "directly above" another element, there are no elements in between. Furthermore, it should be noted that when an element is described as "below" or "under" another element, it may be located directly below or under the other element, or there may be elements in between. Conversely, when an element is described as "directly below" or "directly under" another element, there are no elements in between.

[0012] Stacked FETs are considered a platform for logic CMOS units beyond the 2 nm node. The present application provides a compact SRAM structure for use in stacked FET technology. In particular, the present application provides an exemplary semiconductor structure comprising a 6-transistor SRAM bit cell, having a lower unit level containing lower field-effect transistors and an upper unit level stacked above the lower unit level, containing upper field-effect transistors of a different conductivity type than the lower field-effect transistors. The exemplary semiconductor structure according to the present application includes two CMOS inverters, with the output potential of each inverter being supplied as the input to the other CMOS inverter. The pass gate (or access transistors), word line (WL), and bit line (BL) are used to read or write to the cell.These and other manifestations of the present application will now be described in more detail.

[0013] First, the focus will be on Fig. 1 Reference is made to a circuit diagram of a semiconductor structure according to an example in the present application; the semiconductor structure with this circuit diagram is shown in the remaining drawings of the present application. In particular, and as exemplified by the drawing in Fig. As shown in the circuit diagram in Figure 1, the semiconductor structure according to the present application comprises a lower unit level containing a first lower field-effect transistor (FET) of a first conductivity type (hereinafter "FET_1B"), a second lower FET of the first conductivity type (hereinafter "FET_2B"), a third lower FET of the first conductivity type (hereinafter "FET_3B"), and a fourth lower FET of the first conductivity type (hereinafter "FET_4B"). The term "FET" refers to a type of transistor that uses an electric field to control the current flow in a semiconductor material. FETs are three-terminal units: a source region, a gate, and a drain region. FETs control the current flow by applying a voltage to the gate, which in turn changes the conductivity between the source region and the drain region.

[0014] In the semiconductor structure according to the present application, and as in Fig. As shown in example 1, FET_1B is electrically connected to FET_2B at node A; node A represents a common source / drain region of FET_1B and FET_2B. In the semiconductor structure according to the present application, and as shown in Fig. As shown in Figure 1 in more detail, FET_3B is electrically connected to FET_4B at node B; node B represents a common source / drain region of FET_3B and FET_4B. In the semiconductor structure according to the present application, FET_1B is arranged diagonally to FET_4B and opposite FET_3B, and FET_2B is arranged diagonally to FET_3B and opposite FET_4B.

[0015] In examples from this application, FET_1B and FET_4B serve as pass gates (i.e., access transistors). As in Fig. As shown in Figure 1, both FET_1B and FET_4B are configured, i.e., wired, to be connected by a bit line (BL); specifically, one BL connection is located on a side of FET_1B opposite the common source / drain region (i.e., node A), while another BL connection is located on a side of FET_4B opposite the common source / drain region (i.e., node B). Furthermore, and as shown in Figure 1, Fig. As shown in Figure 1, both FET_2B and FET_3B are configured, i.e., wired, to be connected to ground (GND); specifically, one GND connection is located on a side of FET_2B opposite the common source / drain region (i.e., node A), while another GND connection is located on a side of FET_3B opposite the common source / drain region (i.e., node B). Furthermore, Figure 1 shows Fig. 1, that both FET_1B and FET_4B are configured, i.e., wired, to be connected by a word line (WL); in particular, one WL connection makes contact with a gate of FET_1B, while another WL connection makes contact with a gate of FET_4B.

[0016] The in Fig. The semiconductor structure shown in Figure 1 further comprises an upper unit level stacked above the lower unit level. The upper unit level contains a first upper FET of a second conductivity type (hereinafter referred to as "FET_1T") located directly above FET_1B, a second upper FET of the second conductivity type (hereinafter referred to as "FET_2T") located directly above FET_2B, a third upper FET of the second conductivity type (hereinafter referred to as "FET_3T") located directly above FET_3B, and a fourth upper FET of the second conductivity type (hereinafter referred to as "FET_4T") located directly above FET_4B. In particular, the various FETs of the upper unit level are stacked above the various FETs of the lower unit level. In the present application, the second conductivity type is different, i.e., of opposite conductivity, from the first conductivity type.In some embodiments, the first conductivity type can be n-type, while the second conductivity type can be p-type. In other embodiments, the first conductivity type can be p-type, while the second conductivity type can be n-type. In such an embodiment, the positions of VDD and GND can be reversed.

[0017] According to the present application, FET_1T is electrically connected to FET_2T at node C; node C represents a common source / drain region of FET_1T and FET_2T. In the semiconductor structure according to the present application, and as further described in Fig. As shown in Figure 1, FET_3T is electrically connected to FET_4T at node D; node D represents a common source / drain region of FET_3T and FET_4T. In the semiconductor structure according to the present application, FET_1T is arranged diagonally to FET_4T and opposite FET_3T, and FET_2T is arranged diagonally to FET_3T and opposite FET_4T. As shown in Fig. As shown in Figure 1, node A is wired so that it is connected to node C, and node B is wired so that it is connected to node D.

[0018] In embodiments of the present application, both FET_2T and FET_3T are configured, i.e., wired, to be connected to a power supply (VDD); in particular, a VDD connection is arranged on a side of FET_2T opposite the common source / drain region (i.e., node C), while another VDD connection is arranged on a side of FET_3T opposite the common source / drain region (i.e., node D).

[0019] According to the present application, FET_2B and FET_2T are wired to provide a first inverter, and FET_3B and FET_3T are wired to provide a second inverter. In an SRAM structure, two inverters are known to be cross-coupled in the sense that the output node of one inverter is connected to the input of the second, and vice versa. As in Fig. As shown in Figure 1, the input of the first inverter is connected to the gate of FET_4T; FET_4T serves as a dummy transistor. On the wafer, this is achieved by a common gate trace. The output of the second inverter (node ​​D) is a source / drain region of the dummy transistor FET_4T. Connecting the gate of FET_4T to node D forms the first cross-coupling segment. The input of the second inverter is connected to the gate of FET_1T; FET_1 serves as another dummy transistor. On the wafer, this is achieved by a common gate trace. The output of the first inverter (node ​​C) is a source / drain region of the dummy transistor FET_1T. Connecting the gate of FET_1T to node C forms the second cross-coupling segment, completing the cross-coupling. In particular, the cross-coupling of the first dummy transistor (i.e.,FET_1T) with FET-3T has a first contact metal that makes contact with both a gate electrode and a source / drain region of the first dummy gate region, and has the cross-coupling of the second dummy transistor (i.e. FET_4T) with FET-2T a second contact metal that makes contact with both a gate electrode and a source / drain region of the second dummy gate region.

[0020] In one embodiment, the first upper FET, the third upper FET and the third lower FET share a common gate electrode electrically, and the fourth upper FET, the second upper FET and the second lower FET share a common gate electrode electrically.

[0021] It is known that a 6T SRAM requires two pass-gate transistors for read and write functions in addition to a cross-coupled inverter pair. The gate of each pass-gate transistor is called the word line (WL). FET_1B, which has one of its source / drain regions connected to the first inverter output (node ​​A), serves as one of the pass-gate transistors. The other source / drain region serves as the bit line (BL). FET_4B, which has one of its source / drain regions connected to the second inverter output (node ​​B), serves as the other pass-gate transistor. The other source / drain region serves as the bit line (BL).

[0022] Now, the focus will shift to... Fig. 2A and Fig. Reference is made to 2B, which are the top views that illustrate the structure of each of the different unit levels of the semiconductor structure according to the present application. In particular, Fig. 2A a top view showing the structure of the upper unit level, while Fig. 2B is a top view showing the structure of the lower unit level. According to the present application, the in Fig. 2A top view shown above the in Fig. 2B shows the lower unit level stacked.

[0023] Now, attention is being paid to the in Fig. Reference is made to the lower unit plane shown in Figure 2B, which depicts two lower semiconductor channel material structures 10L and 10R that are spaced apart and aligned parallel to each other. In embodiments, the lower semiconductor channel material structures 10L and 10R can be arranged as shown in Fig. 2B shows semiconductor fins. Other types of lower semiconductor channel material structures 10L and 10R include, for example, semiconductor nanosheets or semiconductor nanowires, which are used instead of those shown in Fig. The semiconductor fins shown in Figure 2B can be used. The lower semiconductor channel material structures 10L and 10R consist of a semiconductor material exhibiting semiconductor properties. Illustrative examples of semiconductor materials that can be used according to the present application include silicon (Si), a silicon-germanium (SiGe) alloy, a silicon-germanium carbide (SiGeC) alloy, germanium (Ge), a III / V compound semiconductor, a II / VI compound semiconductor, and a multilayer stack containing at least two semiconductor materials (e.g., a multilayer stack of Si and SiGe).

[0024] Furthermore, it shows Fig. 2B the presence of two lower gate structures 12A and 12B, which are spaced apart and aligned parallel to each other. The two lower gate structures 12A and 12B are aligned perpendicular to the two lower semiconductor channel material structures 10L and 10R. As in Fig. As shown in Figure 2B, each lower gate structure spans a portion of the two lower semiconductor channel material structures 10L and 10R. Each lower gate structure 12A and 12B contains a gate dielectric material and a gate electrode, which are described in more detail below. Fig. Section 2B shows two pass-gate areas. One of the pass-gate areas contains the one shown in Fig. 1 shown FET_1B, while the other pass-gate area is shown in Fig. The other areas of the FET_4B shown in 1 contain the FET_4B shown. Fig. The setup shown in 2B includes an area containing a lower part of the first inverter, i.e., Inverter 1, and another area containing a lower part of the second inverter, i.e., Inverter 2.

[0025] In Fig. 2B also shows common source / drain areas 14L and 14R. The common source / drain area 14L is equivalent to the one in Fig. Node A shown in Figure 1, while the common source / drain area 14R is equivalent to that shown in Figure 1. Fig. The node B shown in 1 is... Furthermore, in... Fig. 2B WL contacts, BL contacts and GND contacts are shown, which are used as above for Fig. The configuration is described in section 1. Furthermore, the lower unit level contains gate-cut (CT) regions and a lower buried power rail BR1. Each gate-cut region is an area where a gate structure is cut and the buried power rail BR1 is connected to GND contacts. The buried power rails are located beneath the stacked structure and are optional.

[0026] Now, the focus will shift to... Fig. Reference is made to Figure 2A, which shows the top view of the structure according to the present application. Fig. 2A would be above the one in Fig. 2B shown in plan view, such that FET_1T is stacked directly above FET_1B, FET_4T is stacked directly above FET_4B, the Inverter 1 area shown in the upper unit plane is stacked directly above the Inverter 1 area shown in the lower unit plane, and the Inverter 2 area shown in the upper unit plane is stacked directly above the Inverter 2 area shown in the lower unit plane.

[0027] The upper unit plane contains two upper semiconductor channel material structures 11L and 11R, which are spaced apart and arranged parallel to each other. In embodiments, the upper semiconductor channel material structures 11L and 11R can be configured as shown in Fig. The semiconductor fins shown in 2A are typically, but not necessarily always, compatible with the lower semiconductor channel material structures; that is, they have the same geometry. Instead of the ones shown in Fig. Other types of upper semiconductor channel material structures 11L and 11R, including, for example, semiconductor nanosheets and semiconductor nanowires, can also be used in the semiconductor fins shown in Figure 2A. The upper semiconductor channel material structures 11L and 11R consist of one of the semiconductor materials mentioned above. In embodiments, the semiconductor material providing the upper semiconductor channel material structures 11L and 11R can have the same composition as, or a different composition than, the semiconductor material providing the lower semiconductor channel material structures 10L and 10R.

[0028] Furthermore, it shows Fig. 2A the presence of two upper gate structures 13A and 13B, which are spaced apart and aligned parallel to each other. The two upper gate structures 13A and 13B are aligned perpendicular to the two upper semiconductor channel material structures 11L and 11R. As in Fig. As shown in Figure 2A, each upper gate structure spans a portion of the two upper semiconductor channel material structures 11L and 11R. Each upper gate structure 13A and 13B contains a gate dielectric material and a gate electrode, which are described in more detail below. Fig. 2A are FET_1T and FET_4T dummy transistors, which are as shown in Fig. The components described in section 1 are wired to provide cross-coupling with FET_3T and FET_2T, respectively. The components described in section 1 are wired to provide cross-coupling with FET_3T and FET_2T, respectively. Fig. The setup shown in Figure 2A includes an area containing an upper part of the first inverter, i.e., Inverter 1, and another area containing an upper part of the second inverter, i.e., Inverter 2.

[0029] In Fig. 2A also shows common source / drain regions 15L and 15R. The common source / drain region (shared between the upper FET and the lower FET) 15L is related to the one in Fig. Node C shown in 1 is equivalent, while the common source / drain area 15R corresponds to that shown in Fig. The node D shown in section 1 is equivalent. On the wafer, the source / drain region common between the top and bottom can be implemented by forming a contact that is connected to both an upper source / drain region and the lower source / drain region directly below it. Furthermore, in Fig. 2A Cross-coupling contacts 18, WL contacts, BL contacts and VDD contacts shown, which as above for Fig. The configuration is described in section 1. The upper unit level also contains gate-cut (CT) regions and a first buried power rail BR2 and a second buried power rail BR3. Each gate-cut region denotes an area where a gate structure has been cut, and the buried power rails BR2 and BR3 are connected to VDD. The buried power rails lie below the stacked structure and are optional.

[0030] According to the present application, the output (i.e., the common source / drain region 15L) of the upper part of inverter 1 is connected to the input (i.e., gate electrode 13A) of the upper part of inverter 2. Furthermore, according to the present application, the output (i.e., the common source / drain region 15R) of the upper part of inverter 2 is connected to the input (i.e., gate electrode 13B) of the upper part of inverter 1. The in Fig. 2A with 18 marked structures provide such connections.

[0031] It is noted that the top view of the upper unit plane contains sections AA, BB, CC, and DD. Section AA passes through the upper semiconductor channel material structure 11L and the lower semiconductor channel material structure 10L; section BB passes through the upper gate structure 13B and the lower gate structure 12B; section CC passes through one side of the upper gate structure 13B and the lower gate structure 12B that does not contain a common source / drain region; and section DD passes through another side of the upper gate structure 13B and the lower gate structure 12B that contains the common source / drain regions 15L, 15R and 14L, 14R. These various sections are used to further illustrate certain appearances of the semiconductor structure according to the present application.

[0032] It will now be on Fig. 3A, Fig. 3B, Fig. 3C and Fig. 3D reference is made to the semiconductor structure according to the present application, which illustrates it in various sectional views. In particular, Fig. 3A a cross-sectional view of the semiconductor structure through the in Fig. Section AA shown in 2A is Fig. 3B a cross-sectional view of the semiconductor structure through the in Fig. Section BB shown in 2A is Fig. 3C a cross-sectional view of the semiconductor structure through the in Fig. 2A shown section CC and is Fig. 3D cross-sectional view of the semiconductor structure through the in Fig. Section DD shown in Figure 2A according to an embodiment of the present application. In this embodiment, the semiconductor channel material structures in the upper and lower unit planes are semiconductor fins.

[0033] In particular, it first shows Fig. 3A a pair of lower semiconductor fins 102F projecting upwards from a surface of a semiconductor substrate 100. The lower semiconductor fins 102F and the semiconductor substrate 100 consist of one of the semiconductor materials mentioned above for the lower semiconductor channel material structures. In some embodiments, the semiconductor material providing the lower semiconductor fins 102F may have the same composition as the semiconductor material providing the semiconductor substrate 100. In such embodiments, and as described in Fig. As shown in Figure 3A, there is no material interface between the semiconductor substrate 100 and the lower semiconductor fins 102F. In other embodiments, the semiconductor material providing the lower semiconductor fins 102F has a different composition than the semiconductor material providing the semiconductor substrate 100. In such embodiments (not shown), a material interface would exist between the semiconductor substrate 100 and the lower semiconductor fins 102F.

[0034] The in Fig. The semiconductor structure shown in Figure 3A also includes a pair of upper semiconductor fins 106F stacked above, but spaced apart from, the lower semiconductor fins 102F. The upper semiconductor fins 106F comprise one of the semiconductor materials mentioned above for the lower semiconductor channel material structures. The semiconductor material providing the upper semiconductor fins 106F may have the same composition as, or a different composition than, the semiconductor material providing the lower semiconductor fins 102F. In embodiments, the semiconductor material providing each lower semiconductor fin 102F is a semiconductor material capable of providing high channel mobility for nFET units, while the semiconductor material providing each upper semiconductor fin 106F is a semiconductor material capable of providing high channel mobility for pFET units.In other embodiments, the reverse composition configuration can be used.

[0035] In the present application, and as in Fig. As shown in Figure 3A, the upper semiconductor fins 106F are spaced apart from the lower semiconductor fins 102F by a stacked channel insulation structure 104 of the unit. The stacked channel insulation structure 104 of the unit contains a dielectric material, such as silicon dioxide, silicon nitride, silicon oxynitride, or any combination thereof. In the present application, the stacked channel insulation structure of the unit insulates FET_1B from FET_1T, FET_2B from FET_2T, FET_3B from FET_3T, and FET_4B from FET_4T.

[0036] According to the present application, lower source / drain regions 108, 108A are arranged laterally adjacent to the lower semiconductor fins 102F. Lower source / drain regions 108 are non-common source / drain regions, while lower source / drain region 108A is a common source / drain region. The lower source / drain regions 108, 108A have an epitaxial relationship (same crystal orientation) with the sidewalls of the lower semiconductor fins 102F. As used herein, a "source / drain" region can be either a source region or a drain region, depending on the subsequent wiring and the application of voltages during operation of the FET. The lower source / drain regions 108, 108A contain a semiconductor material and a dopant. The semiconductor material providing each of the source / drain regions 108, 108A may include any of the semiconductor materials mentioned above.The semiconductor material providing the lower source / drain regions 108 and 108A can have the same composition as, or a different composition than, each lower semiconductor fin 102F. The dopant present in each of the lower source / drain regions 108 and 108A can be a p-type or an n-type dopant. The term "p-type" refers to the addition of impurities to an intrinsic semiconductor that create vacancies of valence electrons. For silicon-containing semiconductor material, examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium, and indium. "n-type" refers to the addition of impurities that contribute free electrons to an intrinsic semiconductor. For silicon-containing semiconductor material, examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic, and phosphorus.In one example, each source / drain area 30 can have a dopant concentration of 4×10. 20 atoms / cm² 3 up to 3×10 21 atoms / cm² 3 exhibit. In one example, each lower source / drain region 46 consists of phosphorus-doped silicon.

[0037] According to the present application, the upper source / drain regions 114, 114A are arranged laterally adjacent to the upper semiconductor fins 106F. The upper source / drain regions 114 are non-common source / drain regions, while the upper source / drain region 114A is a common source / drain region. The upper source / drain regions 114, 114A have an epitaxial relationship (same crystal orientation) with the sidewalls of the upper semiconductor fins 106F. The semiconductor material providing the upper source / drain regions 114, 114A can comprise any of the aforementioned semiconductor materials. The semiconductor material providing the upper source / drain regions 114, 114A may have the same composition as, or a different composition than, any upper semiconductor fin 106F and / or the lower source / drain regions 108, 108A.The dopant present in each of the upper source / drain regions 114, 114A can be a p-type or an n-type dopant. The upper source / drain regions 114, 114A are of a different conductivity type than the lower source / drain regions 108, 108A. Note that there is no upper source / drain region 114 on one side wall of the upper semiconductor fin 106F in the region designated as a dummy transistor; the dummy transistor is thus a non-functional unit. In embodiments (not shown), the upper source / drain region in the region designated as a dummy transistor may be partially removed from one side wall of the upper semiconductor fin 106F.

[0038] The upper source / drain regions 114 are separated from each other by a source / drain insulation structure 110. The source / drain insulation structure 110 consists of one of the dielectric materials mentioned above for the stacked channel insulation structure 104 of the unit. The dielectric material providing the source / drain insulation structure 110 typically has a different composition than the stacked channel insulation structure 104 of the unit.

[0039] The upper source / drain region 114A and the lower source / drain region 108A are connected to each other by the S / D connector 112. The S / D connector 112 is a metal contact that touches both the upper source / drain region 114A and the lower source / drain region 108A. In this embodiment, the upper source / drain region 114A and the lower source / drain region 108A are connected to each other as an output of the inverter 1.

[0040] The in Fig. The exemplary structure shown in Figure 3A also includes an upper gate structure comprising a gate dielectric material 116, an upper gate electrode 118, and an optional upper gate cover 120, which is arranged on a top surface of the upper semiconductor fins 106F. The upper gate structure would also be present along the side walls of the upper semiconductor fins 106F. A lower gate structure, not shown in this sectional view but shown in Figure 3A, is also present. Fig. As shown in Figure 3B, the lower semiconductor fins 102F would be present along the sidewalls. The lower gate structure would include a gate dielectric material 116 and a lower gate electrode 117. Along the sidewalls of the Fig. The upper gate structure shown in 3A contains dielectric spacers 122.

[0041] In embodiments, the gate dielectric material 116 can contain silicon dioxide or a dielectric material with a higher dielectric constant than silicon dioxide (such dielectric materials can be referred to as high-k-gate dielectric materials). Illustrative examples of high-k-gate dielectric materials include metal oxides, such as hafnium dioxide (HfO₂), hafnium silicon dioxide (HfSiO₂), hafnium silicon oxynitride (HfSiO₂), lanthanum oxide (La₂O₃), lanthanum aluminum oxide (LaAlO₃), zirconium dioxide (ZrO₂), zirconium silicon dioxide (ZrSiO₄), and zirconium silicon oxynitride (ZrSiO₃). x N y ), tantalum oxide (TaO x), titanium oxide (TiO), barium strontium titanium oxide (BaO6SrTi2), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), yttrium oxide (Yb2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide (Pb(Sc,Ta)O3) and / or lead zinc niobite (Pb(Zn,Nb)O). The high-k-gate dielectric material may also contain dopants such as lanthanum (La), aluminum (Al) and / or magnesium (Mg).

[0042] In some embodiments, each of the upper gate electrode 118 and the lower gate electrode 117 consists of an electrically conductive metal-containing material, including, but not limited to, tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), zirconium (Zr), cobalt (Co), copper (Cu), aluminum (Al), lead (Pb), platinum (Pt), tin (Sn), silver (Ag) and gold (Au), tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaC). X), titanium carbide (TiC), titanium aluminum carbide, tungsten silicide (WSi2), tungsten nitride (WN), ruthenium oxide (RuO2), cobalt silicide, and nickel silicide. The electrically conductive metal-containing material that provides the upper gate electrode 118 typically has a different composition than the electrically conductive metal-containing material that provides the lower gate electrode 117.

[0043] In some embodiments, a layer of work function metal (WFM) alone or in combination with one of the aforementioned electrically conductive metal-containing materials can be used to provide the upper gate electrode 118 and the lower gate electrode 117. The WFM layer can be used to set a threshold voltage of the FET to a desired value. In some embodiments, the WFM layer can be selected to effect an n-type threshold voltage shift. “n-type threshold voltage shift,” as used herein, means a shift of the effective work function of the work function metal-containing material toward a conduction band of silicon in a silicon-containing material. In one embodiment, the work function of the n-type work function metal is in the range of 4.1 eV to 4.3 eV.Examples of such materials that can effect an n-type threshold voltage shift include, but are not limited to, titanium aluminum, titanium aluminum carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicon, and combinations thereof. In other embodiments, the WFM layer can be selected to effect a p-type threshold voltage shift. In one embodiment, the work function of the p-type work metal is in the range of 4.9 eV to 5.2 eV. As used herein, the “threshold voltage” is the lowest achievable gate voltage that will turn on a semiconductor device, such as a transistor, by making the device’s channel conductive. The term “p-type threshold stress shift”, as used herein, means a shift of the effective work function of the work function metal-containing material towards a valence band of silicon in a silicon-containing material.Examples of such materials that can cause a p-type threshold stress shift include, but are not limited to, titanium nitride and tantalum carbide, hafnium carbide and combinations thereof.

[0044] The optional upper gate cover 120 can be made of any dielectric material, such as silicon dioxide, silicon nitride, and / or silicon nitride. The dielectric spacer 122 is made of a dielectric spacer material, such as silicon dioxide, silicon nitride, and / or silicon nitride. The dielectric spacer material typically has a different composition than the dielectric material provided by the upper gate cover 120.

[0045] The in Fig. The exemplary structure shown in 3A further includes an upper interlayer dielectric (ILD) material layer 124, which is arranged laterally adjacent to the upper gate structures, wherein, as shown in Fig. 3C and Fig. As shown in the 3D drawing of the present application, a lower ILD material layer 123 may also be present. The lower ILD material layer 123 and the upper ILD material layer 124 may be ILD materials with the same or different compositions. Illustrative ILD materials that may be used include, for example, silicon dioxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), boron phosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a low-k dielectric layer obtained by chemical vapor deposition (CVD), and any combination thereof. The term "low-k," as used throughout the present application, denotes a dielectric material having a lower dielectric constant than silicon dioxide.

[0046] Furthermore, in Fig. Figure 3A shows a VDD contact 126, a BL contact 128, and a cross-coupling contact 130. The VDD contact 126, the BL contact 128, and the cross-coupling contact 130 can be made of the same or different conductive contact materials. In some embodiments, a contact cladding (not shown) may be present around the VDD contact 126, the BL contact 128, and / or the cross-coupling contact 130. The contact cladding (not shown) may include a silicide cladding, such as Ti, Ni, NiPt, etc., and a diffusion barrier material. Examples of diffusion barrier materials include, but are not limited to, Ru, TiN, TaN, WN, WC, an alloy thereof, or a stack thereof, such as Ti / TiN and Ti / WC. Illustrative examples of conductive contact materials that can be used according to the present application include, for example, W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh and an alloy thereof.

[0047] As in Fig. As shown in Figure 3A, the VDD contact 126 is designed to make contact with one of the non-common upper source / drain regions 114, the BL contact 128 is designed to make contact with the lower source / drain region 108 in a region where a dummy transistor is formed, and the cross-coupling contact 130 makes contact with the S / D connecting element 112, which is arranged above the upper source / drain regions 114A. As shown in Fig. As shown in Figure 3A, the cross-coupling contact 130 also forms contact with the upper gate structure of the dummy transistor.

[0048] Now, the focus will shift to... Fig. Reference is made to 3B, which is a sectional view of the exemplary structure along the aforementioned section BB. In addition to showing the aforementioned elements / components, the structure in Fig. The exemplary structure shown in Figure 3B comprises a shallow trench insulation region 140, a dielectric structure 142 located in a gate-cut region, and a dielectric cover 144. The shallow trench insulation region 140, the dielectric structure 142, and the dielectric cover 144 are composed of dielectric materials of different compositions, including silicon dioxide, silicon nitride, and silicon oxynitride. Figure 3B further shows Fig. 3B the presence of a WL contact 146 which makes contact with a surface of the lower gate electrode 117. The WL contact 146 has an optional contact cladding as described above and one of the conductive contact materials as described above. Furthermore, it shows Fig. 3B, that the upper gate electrode 118 forms an extension of an input of one of the inverters from the location of the inverter to the location of the dummy transistor. This facilitates the creation of cross-coupling, since a simple contact 130 now connects the input of one inverter to the output of the other. Although not shown, the upper gate electrode of FET_4T would form an extension of the input of the second inverter.

[0049] Now, the focus will shift to... Fig. Reference is made to Figure 3C, which is a sectional view of the exemplary structure along the aforementioned section CC. This drawing shows the VDD contact 126 and the BL contact 128 mentioned above.

[0050] Now, the focus will shift to... Fig. Reference is made to the 3D drawing, which is a sectional view of the exemplary structure along the aforementioned section DD. This drawing shows, as mentioned above, cross-coupling contacts 130, which are connected by the S / D connector 112 to the upper and lower common source / drain regions 114A and 108A. The S / D connector 112 has an optional contact cladding as described above and one of the conductive contact materials described above.

[0051] The in Fig. The semiconductor structure shown in Figures 3A to 3D can be fabricated using any stacked FET processing sequence employing semiconductor fins in both unit planes. Such stacked FET processing includes various deposition steps, various structuring steps, various material removal steps, and various planarization steps. To avoid complicating the semiconductor structure according to the present application, these various processing steps are not further explained herein.

[0052] Now, the focus will shift to... Fig. 4A, Fig. 4B, Fig. 4C and Fig. 4D reference is made to a further semiconductor structure according to the present application, which is represented by various sectional views. In particular, Fig. 4A a cross-sectional view of the semiconductor structure through the in Fig. Section AA shown in 2A is Fig. 4B a cross-sectional view of the semiconductor structure through the in Fig. Section BB shown in 2A is Fig. 4C a cross-sectional view of the semiconductor structure through the in Fig. 2A shown section CC and is Fig. 4D cross-sectional view of the semiconductor structure through the Fig. Section DD shown in 2A according to an embodiment of the present application. The Fig. The semiconductor structure shown in 4A to 4D is the one in Fig. The semiconductor structure shown in Figures 3A to 3D is similar, except that the lower semiconductor fin 102F and the upper semiconductor fin 106F are replaced by at least one lower semiconductor nanosheet 102NS and at least one upper semiconductor nanosheet 106NS, respectively. Fig. Figures 4A to 4D show a plurality of vertically stacked lower semiconductor nanosheets 102NS and a plurality of vertically stacked upper semiconductor nanosheets 106NS. Another difference in Fig. The semiconductor structure shown in Figures 4A to 4D contains a lower dielectric insulating layer 150 arranged beneath the majority of vertically stacked lower semiconductor nanosheets 102NS, and internal spacers 151 between the various nanosheets are present in both the majority of vertically stacked lower semiconductor nanosheets 102NS and the majority of vertically stacked upper semiconductor nanosheets 106NS. Fig. The semiconductor structure shown in 4A to 4D also contains the same elements as in Fig. 3A to 3D are shown; these identical elements are labeled with the same reference numbers. In the Fig. In embodiments 4A to 4D, a lower gate structure (116 / 117) surrounds the majority of lower semiconductor nanosheets 102NS, and the upper gate structure (116 / 118) surrounds the majority of upper semiconductor nanosheets 106NS. It is noted that the Fig. The nanosheet design shown in 4A to 4D is the same as that shown in Fig. The fin design shown in 3A to 3D is the same, with the exception of the geometry change.

[0053] The lower semiconductor nanosheets 102NS and upper semiconductor nanosheets 106NS contain one of the semiconductor materials mentioned above in the description of the semiconductor channel material structures. The semiconductor material providing the lower semiconductor nanosheets 102NS can have the same composition as, or a different composition than, the semiconductor material providing the upper semiconductor nanosheets 106NS. The lower dielectric insulating layer 150 and the internal spacers 151 consist of well-known dielectric materials.

[0054] The in Fig.The semiconductor structure shown in Figures 4A to 4D can be fabricated using any stacked FET processing sequence employing semiconductor nanosheets in both unit planes. Such stacked FET processing includes various deposition steps, various structuring steps, various material removal steps, and various planarization steps. To avoid complicating the semiconductor structure according to the present application, these various processing steps are not further explained herein.

Claims

[1] Semiconductor structure having: a lower device level including a first lower field-effect transistor, FET, (FET_1B) of a first conductivity type, a second lower FET (FET_2B) of the first conductivity type, a third lower FET (FET_3B) of the first conductivity type, and a fourth lower FET (FET_4B) of the first conductivity type, wherein the first lower FET (FET_1B) is electrically connected to the second lower FET (FET_2B), the third lower FET (FET_3B) is electrically connected to the fourth lower FET (FET_4B), the first lower FET (FET_1B) is arranged diagonally to the fourth lower FET (FET_4B), the second lower FET (FET_2B) is arranged diagonally to the third lower FET (FET_3B), the first lower FET (FET_1B) and the fourth lower FET (FET_4B) Pass gates are; and an upper device level stacked over the lower device level and including a first upper FET (FET_1T) of a second conductivity type different from the first conductivity type arranged directly above the first lower FET (FET_1B), a second upper FET (FET_2T) of the second conductivity type arranged directly above the second lower FET (FET_2B), a third upper FET (FET_3T) of the second conductivity type arranged directly above the third lower FET (FET_3B), and a fourth upper FET (FET_4T) of the second conductivity type arranged directly above the fourth lower FET (FET_4B), wherein the first upper FET (FET_1T) is electrically connected to the second upper FET (FET_2T), and the third upper FET (FET_3T) is electrically connected to the fourth upper FET (FET_4T), and the first upper FET (FET_1T) is a first Dummy transistor, which is wired for cross coupling (130) with the third upper FET (FET_3T),and the fourth upper FET (FET_4T) is a second dummy transistor wired for cross-coupling (130) to the second upper FET (FET_2T), and the second lower FET (FET_2B) and the second upper FET (FET_2T) are wired to provide a first inverter, and the third lower FET (FET_3B) and the third upper FET (FET_3T) are wired to provide a second inverter., [2] The semiconductor structure of claim 1, wherein the first upper FET (FET_1T) has a gate electrode (117, 118) forming an extension of an input of the first inverter, and the fourth upper FET (FET_4T) has another gate electrode forming an extension of an input of the second inverter. [3] The semiconductor structure of claim 1, wherein the first lower FET (FET_1B) has a gate electrode (117, 118) insulated from a gate electrode of the first upper FET (FET1_T), and the fourth lower FET (FET_4B) has a gate electrode insulated from a gate electrode of the fourth upper FET (FET_4T). [4] The semiconductor structure of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type. [5] The semiconductor structure of claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type. [6] The semiconductor structure of claim 1, wherein the first upper FET (FET_1T) arranged on one side has a source / drain region (15L) common to the second upper FET, the third upper FET (FET_3T) arranged on one side has a source / drain region (15R) common to the fourth upper FET (FET_4T), the first lower FET (FET_1B) arranged on one side has a source / drain region (14L) common to the second lower FET (FET_2B), the third lower FET (FET_3B) arranged on one side has a source / drain region (14R) common to the fourth lower FET (FET_4B). [7] The semiconductor structure of claim 6, wherein the common source / drain region (15L) of the first upper FET (FET_1T) and the second upper FET (FET_2T) is electrically connected to the common source / drain region (14L) of the first lower FET (FET_1B) and the second lower FET (FET_2B), and the common source / drain region (15R) of the third upper FET (FET_3T) and the fourth upper FET (FET_4T) is electrically connected to the common source / drain region (14R) of the third lower FET (FET_3B) and the fourth lower FET (FET_4B). [8] The semiconductor structure of claim 1, further comprising a word line electrically connected to a gate electrode (117, 118) of each of the first lower FET (FET_1B) and the fourth lower FET (FET_4B). [9] The semiconductor structure of claim 8, further comprising a bit line electrically connected to a source / drain region (30) of each of the first lower FET (FET_1B) and the fourth lower FET (FET_4B). [10] The semiconductor structure of claim 1, wherein the first lower FET (FET_1B) includes a gate electrode (117, 118) spaced from a gate electrode of the second lower FET (FET_2B) by a dielectric structure (142), and the third lower FET (FET_3B) includes a gate electrode spaced from a gate electrode of the fourth lower FET (FET_4B) by another dielectric structure (142). [11] The semiconductor structure of claim 1, wherein the first upper FET (FET_1T) and the second upper FET (FET_2T) have a common gate electrode (117, 118) and the third upper FET (FET_3T) and fourth upper FET (FET_4T) have another common gate electrode (117, 118). [12] The semiconductor structure of claim 1, wherein the second upper FET (FET_2T) and the third upper FET (FET_3T) are both wired to a current source and the second lower FET (FET_2B) and the third lower FET (FET_3B) are both grounded. [13] The semiconductor structure of claim 1, wherein each of the first lower FET (FET_1B), the second lower FET (FET_2B), the third lower FET (FET_3B), the fourth lower FET (FET_4B), the first upper FET (FET_1T), the second upper FET (FET_2T), the third upper FET (FET_3T), and the fourth upper FET (FET_4T) are disposed on a semiconductor channel material structure (10L, 10R, 11L, 11R). [14] The semiconductor structure of claim 13, wherein the semiconductor channel material structure (10L, 10R, 11L, 11R) is a semiconductor fin (102F, 106F). [15] The semiconductor structure of claim 13, wherein the semiconductor channel material structure (10L, 10R, 11L, 11R) is a semiconductor nanowire. [16] The semiconductor structure of claim 1, wherein the cross-coupling (130) of the first dummy transistor to the third upper FET (FET_3T) comprises a first contact metal that makes contact with both a gate electrode (117, 118) and a source / drain region (30) of a first dummy gate region, and the cross-coupling (130) of the second dummy transistor to the second upper FET (FET_2T) comprises a second contact metal that makes contact with both a gate electrode and a source / drain region (30) of a second dummy gate region. [17] The semiconductor structure of claim 16, wherein both the first dummy gate region and the second dummy gate region are non-functional gate structures with a removed or partially removed source / drain region (30). [18] The semiconductor structure of claim 1, wherein the first upper FET (FET_1T), the third upper FET (FET_3T) and the third lower FET (FET_3B) electrically share a common gate electrode (117, 118), and the fourth upper FET (FET_4T), the second upper FET (FET_2T) and the second lower FET (FET_2B) electrically share a common gate electrode.

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