INTEGRATED CIRCUIT DEVICE WITH ANGLED TRANSISTORS

Abstract

IC devices with angled transistors and associated assemblies and methods are disclosed herein. A transistor is described as "angled" if a longitudinal axis of an elongated semiconductor structure (e.g., a fin or nanoribbon) on which the transistor is based is at an angle other than 0 degrees or 90 degrees with respect to the edges of the front and rear faces of a support structure on / in which the transistor is located, e.g., at an angle between 10 degrees and 80 degrees with respect to at least one such edge. Angled transistors offer a promising way to increase transistor densities on the limited footprint of semiconductor chips.

Description

background

[0001] In recent decades, the scaling of features in integrated circuits (ICs) has been a driving force behind the ever-growing semiconductor industry. Scaling to ever smaller features enables increased densities of functional units on the limited usable space of semiconductor chips. For example, reducing transistor size allows for the inclusion of a larger number of memory or logic devices on a chip, which lends itself to the manufacture of products with increased capacity. However, the move to ever larger capacities also presents problems. The need to optimize the performance of each device and each contact is becoming increasingly important. Careful design of transistors can aid in such optimization. Short description of the drawings

[0002] Embodiments will be readily understood from the following detailed description when taken in conjunction with the accompanying drawings. To facilitate this description, like reference numerals indicate like structural elements. Embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings. Fig. 1 provides a perspective view of an exemplary IC device implementing a nanoribbon transistor, according to some embodiments. Fig. 2 provides a perspective view of an exemplary IC device implementing a fin-based field-effect transistor (FinFET), according to some embodiments. Fig. 3A-3B provide top views of example IC devices with non-angled elongated semiconductor structures according to some embodiments. Fig. 4A-4B provide top views of example IC devices with angled elongated semiconductor structures according to some embodiments. Fig. 5A-5Q provide schematic illustrations of cross-sectional side views of example IC devices integrating non-angled and angled transistors, according to some embodiments. Fig. 6A-6F provide top views of example IC devices with angled elongated semiconductor structures patterned according to different patterning techniques, according to some embodiments. Fig. 7A-7G provide top views of results of various processes of a loop trimming method for fabricating an IC device with angled elongated semiconductor structures according to some embodiments. Fig. 8A-8F are plan views of alternative arrangements of various components of the IC device constructed using the Fig. 7A-7G. according to some embodiments. Fig. 9A-9D provide top views of various processes of a staggered via formation method for fabricating an IC device integrating angled elongated semiconductor structures with a regular array of vias, according to some embodiments. Fig. 10 provides top views of a wafer and dies that may include one or more angled transistor IC devices, according to one of the embodiments disclosed herein. Fig. 11 is a cross-sectional side view of an IC package incorporating an IC device with angled transistors according to one of the embodiments disclosed herein. Fig. 12 is a cross-sectional side view of an IC device assembly including an IC device with angled transistors according to one of the embodiments disclosed herein. Fig. 13 is a block diagram of an exemplary computing device including an angled transistor IC device according to one of the embodiments disclosed herein. Fig. 14 is a block diagram of an exemplary processing device including an angled transistor IC device according to one of the embodiments disclosed herein. Detailed description

[0003] Angled transistor IC devices and associated assemblies and methods are disclosed herein. The devices, assemblies, and methods of this disclosure each have several novel aspects, none of which alone accounts for all of the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.

[0004] To illustrate the angled transistor IC devices proposed herein, it may be useful to first understand phenomena that may arise in such arrangements. The following basic information may be considered a basis from which the present disclosure may be adequately explained. Such information is provided for explanatory purposes only and should accordingly not be construed in any way to limit the broad scope of the present disclosure and its applications.

[0005] A field-effect transistor (FET), such as a metal-oxide-semiconductor (MOS) FET (MOSFET), is a three-terminal device that includes source, drain, and gate terminals and uses an electric field to control current flowing through the device. A FET typically includes a semiconductor channel material, a source region and a drain region provided within the channel material, and a gate stack that includes at least a gate electrode material and may optionally also include a gate insulator. The gate stack is provided over a portion of the channel material between the source region and the drain region.

[0006] Recently, FETs with non-planar architectures, such as FinFETs (sometimes called wrap-around gate transistors or tri-gate transistors) and nanoribbon / nanowire transistors (sometimes called gate-all-around (GAA) transistors), have been extensively investigated as alternatives to transistors with planar architectures.

[0007] In a FinFET, an elongated semiconductor structure (i.e., an elongated structure containing a semiconductor material), shaped as a fin, extends from a base (e.g., a semiconductor substrate or suitable support structure). A portion of a fin closest to the base may be enclosed by an insulator material. Such an insulator material, typically an oxide, is referred to as a shallow trench isolation (STI), and the portion of the fin enclosed by the STI is referred to as a subfin portion or simply a subfin. A gate stack may wrap around an upper portion of the fin (i.e., the portion farthest from the base). The portion of the fin around which the gate stack wraps is referred to as the channel or channel portion of a FinFET.A semiconductor material of the channel portion is commonly referred to as a "channel material" of the transistor. FinFETs are sometimes referred to as "tri-gate transistors" because such transistors, in use, can form conductive channels on three "sides" of the channel portion of the fin. A source region and a drain region are provided in the fin on opposite sides of the gate stack, forming a source and drain, respectively, of a FinFET.

[0008] In a nanoribbon transistor, a gate stack may be provided around a portion of an elongated semiconductor structure, referred to as a "nanoribbon," forming a gate on all sides of the nanoribbon. The "channel" or "channel portion" of a nanoribbon transistor is the portion of the nanoribbon around which the gate stack wraps. Such transistors are sometimes referred to as "GAA transistors" because, in use, such transistors can form conductive channels on all "sides" of the channel portion of the nanoribbon. A source region and a drain region are provided in the nanoribbon on each side of the gate stack, forming a source and drain, respectively, of a nanoribbon transistor. In some configurations, the term "nanoribbon" has been used to describe an elongated semiconductor structure having a substantially rectangular transverse cross-section (i.e.,a cross-section in a plane perpendicular to the longitudinal axis of the structure), although the term "nanowire" has been used to describe a similar structure but with essentially circular or square transverse cross-sections. Hereinafter, a single term "nanoribbon transistor" is used to describe all nonplanar transistors in which a gate stack wraps around essentially all sides of an elongated semiconductor structure, regardless of the shape of the transverse cross-section.Accordingly, the term “nanoribbon transistor” as used herein is used to cover transistors with elongated semiconductor structures having substantially rectangular transverse cross-sections (possibly with rounded corners), transistors with elongated semiconductor structures having substantially square transverse cross-sections (possibly with rounded corners), transistors with elongated semiconductor structures having substantially circular or elliptical / oval transverse cross-sections, and transistors with elongated semiconductor structures having any polygonal transverse cross-sections.

[0009] As the above illustrates, both FinFETs and nanoribbon transistors are formed based on elongated semiconductor structures. A longitudinal axis of such structures can be defined as a line that is the shortest line between a source region and a drain region of a FinFET or nanoribbon transistor. Typically, such a line extends substantially parallel to a support structure (e.g., a die, a chip, a substrate, a carrier substrate, or a package substrate) on which a transistor is located and is one of symmetry axes for the transistor (at least for the idealized version of the transistor, which does not reflect unintentional manufacturing variations that may affect the real geometry of the transistor). Conventionally, FinFETs and nanoribbon transistors are oriented on a support structure such that the longitudinal axes of their elongated semiconductor structures (i.e., fins and drain regions, respectively) are oriented parallel to the support structure.Nanoribbons) are parallel to the front and back surfaces of the support structure and are either perpendicular or parallel to different edges of the support structure, in particular being perpendicular or parallel to different edges of the front surface or back surface of the support structure. In contrast to such conventional implementations, embodiments of the present disclosure provide IC devices with angled transistors, where a transistor is referred to as "angled" if a longitudinal axis of the elongated semiconductor structure on which the transistor is built is at an angle other than 0 degrees or 90 degrees with respect to edges of the front or back surface of a support structure on / in which the transistor is located, e.g.at an angle between 10 degrees and 80 degrees with respect to at least one of the edges of the front or back surface of the support structure (since not one but two angles can be defined between any two intersecting lines, the angles adding up to 180, for the angled structures / transistors, angles referred to here refer to the smaller of the two angles for any given pair of two lines). Angled transistors provide a promising way to increase densities of transistors, in particular FinFETs and nanoribbon transistors, on the limited footprint of semiconductor chips, and embodiments of the present disclosure offer solutions for the layout and patterning of angled transistors as well as for the integration of angled and non-angled transistors.

[0010] In the following detailed description, various aspects of the illustrative implementations are described using terms employed by one skilled in the art to convey the substance of their work to another skilled in the art. For example, in the context of source / drain (S / D) regions, the term "region" may be used interchangeably with the terms "contact" and "terminal" of a transistor. In another example, as used herein, the term "connected" means a direct electrical or magnetic connection between the things being connected, without any intervening devices, while the term "coupled" means either a direct electrical or magnetic connection between the things being connected or an indirect connection through one or more passive or active intermediary devices.The term "circuit" means one or more passive and / or active components configured to cooperate with one another to provide a desired function. The terms "oxide," "carbide," "nitride," "sulfide," etc., when used, refer to compounds containing oxygen, carbon, nitrogen, sulfur, etc., respectively. The term "high-k dielectric" refers to a material with a higher dielectric constant (k) than silicon oxide, while the term "low-k dielectric" refers to a material with a lower k than silicon oxide. The terms "substantially," "closely," "approximately," "near," and "about" generally refer to being within + / - 20%, e.g., within + / - 5%, or within + / - 2%, of a target value based on the context of a particular value, as described herein or known in the art.Likewise, terms indicating an orientation of different elements, e.g., "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between the elements, generally refer to being within + / - 1-20% of a target value, e.g., + / - 1-10% of a target value, or + / - 1-5% of a target value, based on the context of a particular value, as described herein or known in the art.

[0011] As used herein, the terms "over," "under," "between," and "on" refer to a relative position of a material layer or component with respect to other layers or components. For example, a layer disposed over or under another layer may be in direct contact with the other layer or may have one or more intervening layers. Furthermore, a layer disposed "between" two layers may be in direct contact with the two layers or may have one or more intervening layers. In contrast, a first layer is "on" a second layer in direct contact with that second layer. Likewise, unless otherwise noted, a feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.

[0012] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The phrase "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the phrase "A / B / C" means (A), (B), and / or (C).

[0013] The description may use the terms "in one embodiment" or "in embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate discussion and are not intended to limit the application of disclosed embodiments. The accompanying drawings are not necessarily to scale. Unless otherwise specified, the use of the ordinal adjectives "first," "second," and "third," etc., indicates a more concise description.to describe a common object merely implies that reference is made to different instances of like objects, and it is not intended to imply that the objects so described must be in a given sequence, whether temporally, spatially, in order of precedence, or in any other way.

[0014] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration embodiments that may be practiced. It will be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. For convenience, corresponding elements designated in the present drawings by different reference numerals following a hyphen, e.g., edges 303-1, 303-2, 303-3, and 303-4, may be referred to collectively without the reference numerals following the hyphen, e.g., as "edges 303."To avoid cluttering the drawings, if multiple instances of certain elements are illustrated, only some of the elements may be identified with a reference symbol. Multiple drawings with the same number and different letters may be referenced without the letters, e.g., . Fig. 5A-5Q as “ Fig. 5”.

[0015] In the drawings, some schematic illustrations of example structures of various devices and assemblies described herein may be shown with precise right angles and straight lines, but it should be understood that such schematic illustrations may not reflect actual process limitations, which may cause the features to appear less than "ideal" when any of the structures described herein are examined using, for example, scanning electron microscopy (SEM) or transmission electron microscope (TEM) images. Such images of actual structures may also reveal possible processing defects, such as:not perfectly straight edges of materials, tapered vias or other openings, unintentional rounding of corners or variations in the thickness of different material layers, occasional screw, step or combinations of dislocations within the crystalline region and / or occasional dislocation defects of individual atoms or clusters of atoms. There may be other defects not listed here, but which are common in the field of device manufacturing. An inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using, for example, optical microscopy, TEM or SEM, and / or an inspection of a cross-section of a device to detect the shape and location of various device elements described herein using, for example,A physical failure analysis (PFA) would allow for the determination of the presence of IC devices with angled transistors as described here.

[0016] Various acts may be described as multiple discrete acts or acts performed in sequence in a manner that is extremely helpful in understanding the claimed subject matter. However, the order of description should not be construed to imply that these acts are necessarily order-dependent. In particular, these acts may not be performed in the order presented. Described acts may be performed in a different order than the described embodiment. Various additional acts may be performed and / or described acts may be omitted from additional embodiments.

[0017] Various angled transistor IC devices as described herein may be implemented in or associated with one or more components associated with an IC, or / or may be implemented between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those mounted on the IC or those connected to an IC. The IC may be either analog or digital and, depending on the components associated with the IC, may be used in a variety of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc.The IC can be used as part of a chipset to perform one or more associated functions in a computer.

[0018] Fig. Figure 1 provides a perspective view of an exemplary IC device 100 implementing a nanoribbon transistor 110, according to some embodiments. Nanoribbon transistor 110 is an example of an angled transistor that may be included in various IC devices and assemblies described herein.

[0019] With reference to the details of Fig. 1, the IC device 100 may include a semiconductor material, which may include one or more semiconductor materials formed as a nanoribbon 104 (i.e., an elongated semiconductor structure) extending substantially parallel to a support structure 102. The transistor 110 may be formed based on the nanoribbon 104 by having a gate stack 106 at least partially wrapped around a portion of the nanoribbon, referred to as a “channel portion,” and by having source and drain regions formed in Fig. 1 as a first S / D region 114-1 and a second S / D region 114-2, on both sides of the gate stack 106. In some embodiments, a (in Fig. 1) layer of oxide material may be provided between the support structure 102 and the gate stack 106.

[0020] The Fig. The IC device 100 shown in Figure 1, as well as IC devices shown in other drawings of the present disclosure, are intended to show relative arrangements of some of the components therein, and the IC device 100, or portions thereof, may include other components that are not illustrated (e.g., electrical contacts to the S / D regions 114 of the transistor 110, additional layers such as a spacer layer around the gate stack 106 of the transistor 110, etc.). Although this is Fig. 1, a dielectric spacer may be provided, for example, between a first S / D contact, which may be coupled to a first S / D region 114-1 of the transistor 110, and the gate stack 106, and between a second S / D contact, which may be coupled to a second S / D region 114-2 of the transistor 110, and the gate stack 106, to provide electrical isolation between the source, gate, and drain contacts (generally, “contacts” described herein may also be referred to as “electrodes”). In another example, although not specifically illustrated in Fig. 1, at least portions of transistor 110 may be surrounded by an insulating material, such as any suitable interlayer dielectric (ILD) material. In some embodiments, such an insulating material may be a high-k dielectric including elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used for this purpose may include, but are not limited to, hafnium oxide, hafnium silica, lanthanum oxide, lanthanum alumina, zirconium oxide, zirconium silica, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silica, lead scandium tantalum oxide, and lead zinc niobate.In other embodiments, the insulating material surrounding portions of transistor 110 may be a low-k dielectric material. Some examples of low-k dielectric materials include, but are not limited to, silicon dioxide, carbon-doped oxide, silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fused silica glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass.

[0021] Implementations of the present disclosure may be formed or executed on any suitable support structure 102, such as a substrate, a die, a wafer, or a chip. The support structure 102 may, for example, be the wafer 2000 of Fig. 10, which is discussed below, and can be a Die, e.g., the isolated Die 2002 from Fig. 10, discussed below, or included therein. The support structure 102 may be a semiconductor substrate comprised of semiconductor material systems including, for example, n-type or p-type material systems. In one implementation, the semiconductor substrate may be a crystalline substrate formed using bulk silicon or an SOI substructure. In other implementations, the semiconductor substrate may be formed using alternative materials that may or may not be combined with silicon, including, but not limited to, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum arsenide, indium aluminum arsenide, aluminum indium antimonide, indium gallium arsenide, gallium nitride, indium gallium nitride, aluminum indium nitride, or gallium antimonide, or other combinations of Group III-V materials (i.e.Materials from Groups III and V of the Periodic Table of Elements), Group II-VI (i.e., materials from Groups II and VI of the Periodic Table of Elements), or Group IV materials (i.e., materials from Group IV of the Periodic Table of Elements). In some embodiments, the substrate may be non-crystalline. In some embodiments, the support structure 102 may be a printed circuit board (PCB) substrate. Although a few examples of materials from which the support structure 102 may be formed are described herein, any material that can serve as a basis for constructing an IC device with angled transistors as described herein falls within the spirit and scope of the present disclosure.

[0022] The nanoribbon 104 may, for example, take the form of a nanowire or nanoribbon. In some embodiments, an area of ​​a transverse cross-section of the nanoribbon 104 (ie, an area in the xz-plane of the Fig. 1) between about 25 and 10,000 square nanometers, including all values ​​and ranges therein (e.g., between about 25 and 1,000 square nanometers or between about 25 and 500 square nanometers). The transverse cross-section of the nanoribbon 104 is a cross-section along a plane perpendicular to a longitudinal axis 120 of the nanoribbon 104, wherein the longitudinal axis 120 is, for example, along the y-axis of the Fig. 1. In some embodiments, a width of the nanoribbon 104 (i.e., a dimension that is in a plane parallel to the support structure 102 and in a direction perpendicular to the longitudinal axis 120, e.g., along the x-axis of the Fig. 1) be at least about 3 times greater than a thickness (or a “height”) of the nanoribbon 104 (i.e., a dimension measured in a plane perpendicular to the support structure 102, e.g., along the z-axis of the Fig. 1), including all values ​​and ranges therein, e.g., at least about 4 times larger or at least about 5 times larger. It should be noted that Fig. 1 illustrates the xyz coordinate system, which, for the sake of simplicity of this particular drawing, is oriented so that the longitudinal axis 120 runs along the y-axis. In other drawings, angled transistors are explained with reference to their longitudinal axes, which lie somewhere in the xy-plane but are not aligned with either the y-axis or the x-axis, because the edges of the support structure are assumed to be aligned with these axes and the transistors are angled, meaning that they are at an angle between 10 degrees and 80 degrees with respect to the y-axis and / or x-axis. Thus, if the transistor 110 is an angled transistor of any of the subsequent drawings, the longitudinal axis 120 is not aligned with the y-axis, as in Fig. 1, but at an angle between 10 degrees and 80 degrees with respect to the y-axis.

[0023] Although the Fig. 1 is shown as having a rectangular cross-section, the nanoribbon 104 may instead have a cross-section that is rounded at corners or otherwise irregularly shaped, and the gate stack 106 may conform to the shape of the nanoribbon 104. The terms "front face" and "back face" of a nanoribbon may refer to the faces of the nanoribbon 104 that are substantially parallel to the support structure 102, the term "sidewall" (or "side face") of a nanoribbon may refer to the opposing faces of the nanoribbon 104 that are substantially perpendicular to the support structure 102 and extend in a direction of the longitudinal axis 120 of the nanoribbon 104, while the term "end" of a nanoribbon may refer to the opposing faces of the nanoribbon 104 that are substantially perpendicular to the longitudinal axis 120 of the nanoribbon 104.

[0024] Nanoribbon 104 may be formed from one or more semiconductor materials, collectively referred to as a "channel material." In general, channel materials of any of the angled transistors described herein, e.g., the channel material of transistor 110, may consist of semiconductor material systems including, for example, n-type or p-type material systems. In some embodiments, the channel material may include a substantially monocrystalline semiconductor, such as silicon (Si) or germanium (Ge). In some embodiments, the channel material may include a compound semiconductor having a first sub-lattice of at least one element from Group III of the Periodic Table (e.g., Al, Ga, In) and a second sub-lattice of at least one element from Group V of the Periodic Table (e.g., P, As, Sb).In some embodiments, the channel material may include a high-mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the channel material may include a combination of semiconductor materials.

[0025] For some exemplary n-type transistor embodiments (i.e., for those embodiments where the transistor in which the channel material is included is an n-type metal-oxide-semiconductor (NMOS) transistor), the channel material may include a III-V material with a relatively high electron mobility, such as, among others, InGaAs, InP, InSb, and InAs. For some such embodiments, the channel material may be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. For some In x Ga 1-xAs-fin embodiments, an In content (x) may be between 0.6 and 0.9 and may advantageously be at least 0.7 (e.g. In 0,7 Ga 0,3 As. For some exemplary p-type transistor embodiments (i.e., for those embodiments where the transistor in which the channel material is included is a p-type metal oxide semiconductor (PMOS) transistor), the channel material may advantageously be a Group IV material with high hole mobility, such as, among others, Ge or a Ge-rich SiGe alloy. For some embodiments, the channel material may have a Ge content between 0.6 and 0.9, and may advantageously be at least 0.7.

[0026] In some embodiments, the channel material may be a high mobility oxide semiconductor material such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide.Generally, the channel material may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, n- or p-type amorphous silicon or n- or p-type polysilicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus, each of which may be possibly doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc.

[0027] As previously noted, the channel material may include IGZO. IGZO-based devices exhibit several desirable electrical and manufacturing properties. IGZO exhibits high electron mobility compared to other semiconductors, e.g., in the range of 20 to 50 times higher than amorphous silicon. Furthermore, amorphous IGZO (A-IGZO) transistors are typically characterized by high band gaps, low-temperature process compatibility, and low manufacturing costs relative to other semiconductors. IGZO can be deposited as a uniform amorphous phase while maintaining higher charge carrier mobility than oxide semiconductors, such as zinc oxide. Different formulations of IGZO include different ratios of indium oxide, gallium oxide, and zinc oxide. One particular form of IGZO has the molecular formula InGaO3(ZnO)5. Another exemplary form of IGZO has an indium:gallium:zinc ratio of 1:2:1.In various other embodiments, IGZO may have a gallium-to-indium ratio of 1:1, a gallium-to-indium ratio greater than 1 (e.g., 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, or 10:1), and / or a gallium-to-indium ratio less than 1 (e.g., 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, or 1:10). IGZO may also contain tertiary dopants, such as aluminum or nitrogen.

[0028] In some embodiments, any of the angled transistors described herein, e.g., transistor 110, may be a thin-film transistor (TFT). A TFT is a special type of FET that is fabricated by depositing active semiconductor material over a support (e.g., a support structure as previously described), which may be a non-conductive support. Some such materials can be deposited at relatively low temperatures, allowing them to be deposited within the thermal budgets imposed on back-end manufacturing to avoid damage to front-end components, such as the logic devices of an IC device in which the transistor may be included. Thus, in some embodiments, the channel material of any of the angled transistors described herein, e.g.,of transistor 110, may be a semiconductor material deposited at relatively low temperatures and may include any of the oxide semiconductor materials described above.

[0029] In other embodiments, instead of being deposited at relatively low temperatures as previously described with reference to TFTs, the channel material of any of the angled transistors described herein, e.g., transistor 110, may be grown epitaxially, which typically involves relatively high temperature processing. In such embodiments, the channel material may include any of the semiconductor materials described previously, including oxide semiconductor materials. In some such embodiments, the channel material may be grown epitaxially directly on a semiconductor layer of a support structure over which the transistor will be fabricated, in a process known as "monolithic integration." In other such embodiments, the channel material of any of the angled transistors described herein, e.g.,of transistor 110, may be grown epitaxially on a semiconductor layer of another support structure, and then the epitaxially grown layer of channel material may be transferred, in a process known as "layer transfer," to a support structure over which the transistor will be located, in which case the latter support structure may or may not include a semiconductor layer prior to the layer transfer. Layer transfer advantageously enables the formation of non-planar transistors, such as FinFETs or nanoribbon transistors, over support structures or in layers that do not include semiconductor materials (e.g., in the back end of an IC device). Layer transfer advantageously enables the formation of transistors of any architecture (e.g.,non-planar or planar transistors), without imposing the negative effects of the relatively high temperature epitaxial growth process on devices that may already be present over a support structure.

[0030] A channel material deposited at relatively low temperatures is typically a polycrystalline, polymorphic, or amorphous semiconductor, or any combination thereof. A channel material grown epitaxially is typically a very crystalline (e.g., monocrystalline or single-crystal) material. Therefore, by inspecting the grain size of the active portions of the channel material (e.g., the portions of the channel material that form channels of transistors), it can be identified whether the channel material of any of the angled transistors described herein, e.g., transistor 110, is deposited at relatively low temperatures or grown epitaxially. An average grain size of a channel material of any of the angled transistors described herein, e.g.,of transistor 110 that is between about 0.5 and 1 millimeter (in which case the material may be polycrystalline) or less than about 0.5 millimeters (in which case the material may be polymorphic or amorphous) may be indicative of the channel material that was deposited (e.g., in this case, the transistors incorporating such channel material are TFTs). On the other hand, an average grain size of a channel material of any of the angled transistors described herein, e.g., of transistor 110, that is equal to or greater than about 1 millimeter (in which case the material may be a single-crystal material) may indicate that the channel material was grown epitaxially and incorporated into the final device either by monolithic integration or by layer transfer.

[0031] In some embodiments, the channel material of any of the angled transistors described herein, e.g., transistor 110, may include a two-dimensional (2D) semiconductor material, i.e., a semiconductor material with a thickness of a few nanometers or less, wherein electrons in the material can move freely in the 2D plane, but their limited movement in the third direction is governed by quantum mechanics. In some such embodiments, such a channel material may include a single-atomic monolayer of a 2D semiconductor material, while in other such embodiments, such a channel material may include five or more atomic monolayers of a 2D semiconductor material.Examples of 2D materials that can be used to implement the channel material of any of the angled transistors described here include, but are not limited to, graphene, hexagonal boron nitride, or transition metal chalcogenides.

[0032] A gate stack 106 including a gate electrode material 108 and optionally a gate insulator 112 may wrap completely or almost completely around a portion of the nanoribbon 104, as shown in Fig. 1, wherein the channel portion of transistor 110 is the active region (channel region) of the channel material in the portion of nanoribbon 104 wrapped by gate stack 106. Gate insulator 112 is shown in the perspective drawing of Fig. 1, but is mounted in a slot 130 of Fig. 1, which provides a cross-sectional side view of a portion of the nanoribbon 104 with a gate stack 106 wrapped around it. As in Fig. 1, the gate insulator 112 may wrap around a transverse portion / cross-section of the nanoribbon 104 and the gate electrode material 108 may wrap around the gate insulator 112.

[0033] The gate electrode material 108 may include at least one p-type work function metal or one n-type work function metal, depending on whether the transistor 110 is a PMOS transistor or an NMOS transistor. A p-type work function metal may be used as the gate electrode material 108 when the transistor 110 is a PMOS transistor, and an n-type work function metal may be used as the gate electrode material 108 when the transistor 110 is an NMOS transistor. For a PMOS transistor, metals that may be used for the gate electrode material 108 may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. For an NMOS transistor, metals that can be used for the gate electrode material 108 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g.,Hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode material 108 may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a filler metal layer. Additional layers may be included besides the gate electrode material 108 for other purposes, such as to function as a diffusion barrier layer and / or an adhesion layer.

[0034] In some embodiments, the gate insulator 112 may include one or more high-k dielectrics, including any of the materials discussed herein with reference to the insulator material, that may surround portions of the transistor 110. In some embodiments, an annealing process may be performed on the gate insulator 112 during fabrication of the transistor 110 to improve the quality of the gate insulator 112. The gate insulator 112 may have a thickness that, in some embodiments, may be between about 0.5 nanometers and 3 nanometers, including all values ​​and ranges therein (e.g., between about 1 and 3 nanometers or between about 1 and 2 nanometers), although in other embodiments, the thickness of the gate insulator 112 may be greater than 3 nanometers. In some embodiments, the gate stack 106 may be surrounded by a gate spacer that, in Fig. 1 is not shown. Such a gate spacer would be configured to provide separation between the gate stack 106 and the source / drain contacts of the transistor 110 and could be made of a low-k dielectric material, some examples of which have been provided previously. A gate spacer may include pores or air gaps to further reduce its dielectric constant.

[0035] In some embodiments, the gate insulator 112 may include a hysteresis material or hysteresis array, which may collectively be referred to as a "hysteresis element." Transistors 110 in which the gate insulator 124 includes a hysteresis element may be described as "hysteresis transistors" and may be used to implement hysteresis memory. Hysteresis memory refers to a memory technology that employs hysteresis materials or arrays, where a material or array can be described as exhibiting hysteresis if it exhibits the dependence of its state on the history of the material (e.g., a previous state of the material). Ferroelectric (FE) and antiferroelectric (AFE) materials are examples of hysteresis materials.Layers of different materials arranged in a stack to demonstrate a charge trapping phenomenon are an example of a hysteresis array.

[0036] An FE or AFE material is a material that exhibits spontaneous electric polarization, i.e., a displacement of positive and negative charges from their original position, over a certain range of temperatures, where the polarization can be reversed or reoriented by the application of an electric field. In particular, an AFE material is a material that can adopt a state in which electric dipoles from the ions and electrons in the material can form a substantially ordered (e.g., substantially crystalline) arrangement, with adjacent dipoles oriented in opposite (antiparallel) directions (i.e., the dipoles of any orientation can form interpenetrating sublattices, loosely analogous to a checkerboard structure), whereas an FE material is a material that can adopt a state in which all dipoles point in the same direction.Because the displacement of charges in FE and AFE materials can be maintained for a certain time even in the absence of an electric field, such materials can be used to implement memory cells. Since the current state of the electric dipoles in FE and AFE materials depends on the previous state, such materials are hysteresis materials. Memory technologies in which logic states are stored with respect to the orientation of electric dipoles in (i.e., with respect to the polarization of) FE or AFE materials are referred to as "FE memories," with the term "ferroelectric" being used to convey the similarity of FE memories to ferromagnetic memories, even though iron (Fe) is typically not present in FE or AFE materials.

[0037] A stack of alternating layers of materials configured to exhibit charge trapping is an example of a hysteresis arrangement. Such a stack may include only two layers of materials, one of which is a charge-trapping layer (i.e., a layer of a material configured to trap charges when a voltage is applied across the material) and the other of which is a tunneling layer (i.e., a layer of a material through which charge is to be tunneled into the charge-trapping layer). The tunneling layer may include an insulator material, such as a material including silicon and oxygen (e.g., silicon oxide), or any other suitable insulator. The charge-trapping layer may include a metal or a semiconductor material configured to trap charges.Because the trapped charges can be retained in a charge-trapping array for a certain time even in the absence of an electric field, such arrays can be used to implement memory cells. Because the presence and / or quantity of trapped charges in a charge-trapping array depends on the previous state, such arrays are hysteresis arrays. A memory technology in which logic states are stored in terms of the amount of charge trapped in a hysteresis array can be referred to as "charge-trapping memory."

[0038] Hysteresis memories exhibit the potential for reasonable non-volatility, short programming time, low power consumption, long endurance, and high-speed writing. Furthermore, hysteresis memories can be manufactured using processes compatible with standard CMOS (complementary metal-oxide-semiconductor) technology. Therefore, these types of memories have emerged over the past few years as promising candidates for many growing applications.

[0039] In some embodiments, the hysteresis element of the gate insulator 112 may be provided as a layer of an FE or an AFE material. Such an FE / AFE material may include one or more materials capable of exhibiting sufficient FE / AFE behavior even at thin dimensions, such as, for example, an insulator material of which at least about 5%, e.g., at least about 7%, or at least about 10%, is in an orthorhombic phase and / or a tetragonal phase (e.g., as a material in which perhaps at most about 95-90% of the material is amorphous or in a monoclinic phase). For example, such materials may be based on hafnium and oxygen (e.g., hafnium oxides), with various dopants added to ensure a sufficient amount of an orthorhombic phase or a tetragonal phase.Some examples of such materials include materials that include hafnium, oxygen, and zirconium (e.g., hafnium zirconium oxide (HfZrO, also referred to as HZO)), materials that include hafnium, oxygen, and silicon (e.g., silicon-doped (Si-doped) hafnium oxide), materials that include hafnium, oxygen, and germanium (e.g., germanium-doped (Ge-doped) hafnium oxide), materials that include hafnium, oxygen, and aluminum (e.g., aluminum-doped (Al-doped) hafnium oxide), and materials that include hafnium, oxygen, and yttrium (e.g., yttrium-doped (Y-doped) hafnium oxide). However, in other embodiments, any other materials that exhibit FE / AFE behavior at thin dimensions may be used as the hysteresis element and are within the scope of the present disclosure.

[0040] In other embodiments, the hysteresis element of the gate insulator 112 may be provided as a stack of alternating layers of materials capable of trapping charges. In some such embodiments, the stack may be a two-layer stack, with one layer being a charge-trapping layer and the other layer being a tunneling layer. The tunneling layer may include an insulator material, such as a material including silicon and oxygen (e.g., silicon oxide), or any other suitable insulator. The charge-trapping layer may include an electrically conductive material, such as a metal or a semiconductor material. In some embodiments, the charge-trapping layer may include a substoichiometric material (i.e., a material including less than a stoichiometric amount of a reagent). The substoichiometric material may include vacancies having a concentration of at least about 10 18vacancies per cubic centimeter, e.g., with the concentration between about 10 18 Vacant spaces per cubic centimeter and about 10 22 -10 23Vacancies per cubic centimeter. As known in the art, vacancies refer to locations where atoms (e.g., oxygen or nitrogen) that should be present are missing, thereby providing a defect in a material. For example, the substoichiometric material of any of the hysteresis elements described herein may include oxygen, and the vacancies may be oxygen vacancies, or the substoichiometric material may include nitrogen, and the vacancies may be nitrogen vacancies. During operation, charges may be trapped in the vacancies of the substoichiometric material. Thus, implementing a substoichiometric material with vacancies is one way to provide a charge-trapping layer of a hysteresis device. In general, any material that has defects that can trap a charge can be used in / as a charge-trapping layer.Such defects are highly detrimental to the operation of logic devices, and therefore, intentional steps must typically be taken to prevent their presence. However, for memory devices, such defects are desirable because charge trapping can be used to represent different memory states of a memory cell.

[0041] In some embodiments of the hysteresis element provided as a stack of alternating layers of materials capable of trapping charges, the stack may be a three-layer stack in which an insulator material is provided on both sides of a charge-trapping layer. In such embodiments, a layer of insulator material on one side of the charge-trapping layer may be referred to as a "tunnel layer," while a layer of insulator material on the other side of the charge-trapping layer may be referred to as a "field layer."

[0042] In various embodiments of the hysteresis element provided as a stack of alternating layers of materials capable of trapping charges, a thickness of each layer of the stack may be between about 0.5 and 10 nanometers, including all values ​​and ranges therein, e.g., between about 0.5 and 5 nanometers. In some embodiments of a three-layer stack, a thickness of each layer of the insulator material may be about 0.5 nanometers, while a thickness of the charge-trapping layer may be between about 1 and 8 nanometers, e.g., between about 2.5 and 7.5 nanometers, e.g., about 5 nanometers. In some embodiments, a total thickness of the hysteresis element provided as a stack of alternating layers of materials capable of trapping charges (i.e., a hysteresis array) may be between about 1 and 10 nanometers, e.g., between about 2 and 8 nanometers, e.g., about 6 nanometers.

[0043] Turning to the S / D regions 114 of the transistor 110, in some embodiments, the S / D regions may be heavily doped, e.g., with dopant concentrations of about 10 21Dopants per cubic centimeter to advantageously form ohmic contacts to the respective S / D electrodes, although these regions may also have lower dopant concentrations and may form Schottky contacts in some implementations. Regardless of the exact dopant levels, the S / D regions of a transistor may be the regions with a dopant concentration that is higher than in other regions, e.g., higher than a dopant concentration in the channel portion (i.e., in a channel material extending between the first S / D region 114-1 and the second S / D region 114-2), and may therefore be referred to as "heavily doped" (HD) regions. The channel portion of the transistor 110 may include semiconductor materials with doping concentrations that are significantly lower than those of the S / D regions 114.

[0044] The S / D regions 114 of the transistor 110 can generally be formed either by an implantation / diffusion process or by an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic can be ion-implanted into the nanoribbon 104 to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the nanoribbon 104 can follow the ion implantation process. In the latter process, portions of the nanoribbon 104 can first be etched to form recesses at the locations of the future S / D regions 114. An epitaxial deposition process can then be performed to fill the recesses with a material used to fabricate the S / D regions 114.In some implementations, the S / D regions 114 may be fabricated using a silicon alloy, such as silicon germanium or silicon carbide. In some implementations, the epitaxially deposited silicon alloy may be doped in situ with dopants, such as boron, arsenic, or phosphorus. In further embodiments, the S / D regions 114 may be formed using one or more alternative semiconductor materials, such as germanium or a Group III-V material or alloy. And in further embodiments, one or more layers of metal and / or metal alloys may be used to form the S / D regions 114. In some embodiments, a distance between the first and second S / D regions 114 (i.e., a dimension measured along the longitudinal axis 120 of the nanoribbon 104) may be between about 5 and 40 nanometers, including all values ​​and ranges therein (e.g.,between about 22 and 35 nanometers or between about 20 and 30 nanometers).

[0045] In some embodiments, angled transistors described herein may be implemented in memory arrays. In some such embodiments, an angled transistor may be coupled to a storage element, thereby forming a 1T-1X memory cell of a memory array, where "1T" in the term "1T-1X memory cell" indicates that the memory cell includes one transistor (T), and where "1X" in the term "1T-1X memory cell" indicates that the memory cell includes one storage element (X). In other embodiments, an angled transistor may be coupled to multiple storage elements, or an angled transistor may be coupled to another transistor to form one or more memory cells of a memory array, all of which are within the scope of the present disclosure.In general, a storage element may be any suitable integrated circuit component that can be programmed to a target data state (e.g., corresponding to a particular charge stored in the storage element or a particular resistance state of the storage element) by applying an electric field or electrical energy (e.g., positive or negative voltage or current pulses) to the storage element for a specific duration. In various embodiments, a storage element may be a capacitor, a resistive storage element, a resistive random access memory (RRAM) device, a metal filament memory device, a phase-change memory (PCM) device, a magnetic random access memory (MRAM) device, etc.

[0046] An example of the use of transistor 110 as part of a memory cell is shown in Fig. 1, which shows that the IC device 100 may include a memory cell 160 including the transistor 110 and a storage element 166 electrically coupled to the S / D region 114-2. In various embodiments, the storage element 166 may include one of a capacitor, a magnetoresistive material, a ferroelectric material, or a resistance-changing material. In some embodiments, the storage element 166 may include two electrodes 167-1 and 167-2 separated by a storage material 169. An example of the electrodes 167 and the storage material 169 of the storage element 166 is schematically shown within the dashed outline of a slot 162 of Fig. 1, although in other embodiments, the spatial arrangement of the storage material 169 and the electrodes 167 may be different, as long as the storage material 169 is spatially located between the electrode 167-1 and the electrode 167-2 (e.g., the storage material 169 need not be a planar layer, but may be arranged in any type of three-dimensional arrangement). The storage material 169 may be any suitable material that can be placed in a target state by applying an electric field or electrical energy (e.g., positive or negative voltage or current pulses) to one or both electrodes 167 of the storage element 166 for a specific duration, thereby programming the storage element 166 to a target data state (e.g.,corresponding to a particular charge stored in the storage element 166 or corresponding to a particular resistance state of the storage element 166). Such a storage element 166 may be electrically coupled to the S / D region 114-2 by coupling the electrode 167-1 of the storage element 166 to the S / D region 114-2 (e.g., in some embodiments, the electrode 167-1 of the storage element 166 and a contact to the S / D region 114-2 may be a common contact of a suitable electrically conductive material).

[0047] For example, a dynamic random access memory (DRAM) cell may include a storage element 166 in the form of a capacitor for storing a bit value or a memory state (e.g., logic "1" or "0") of the cell, and an access transistor implemented as transistor 110 that controls access to the cell (e.g., access to write information to the cell or access to read information from the cell). Such a memory cell may be referred to as a "1T-1C memory cell," emphasizing the fact that it uses a transistor (i.e., "1T" in the term "1T-1C memory cell") and a capacitor (i.e., "1C" in the term "1T-1C memory cell"). In such embodiments, electrodes 167 may be capacitor electrodes, and storage material 169 may be a capacitor insulator.In some embodiments, the storage material 169 of such a capacitor may be a dielectric material. In other embodiments, the storage material 169 of such a capacitor may be a hysteresis element, such as previously described with reference to the embodiments in which the gate insulator 112 is a hysteresis element.

[0048] In another example, storage element 166 may be a resistive storage element (also referred to herein as a "resistive switch") that includes storage material 169, which is a resistance-changing material. That is, during operation, storage material 169 may be switched between two different non-volatile states: a high resistance state (HRS) and a low resistance state (LRS). The state of a resistive storage element may be used to represent a data bit (e.g., logic "1" for HRS and logic "0" for LRS, or vice versa). A resistive storage element may have a voltage threshold beyond which the resistive storage element is in the LRS; driving a resistive storage element into the LRS may be referred to as SET (with an associated SET threshold voltage).Similarly, a resistive storage element may have a voltage threshold beyond which the resistive storage element is in the HRS; driving a resistive storage element in the HRS may be referred to as RESET (with an associated RESET threshold voltage).

[0049] In another example, storage element 166 may be an RRAM device; in such embodiments, storage material 169 may include an oxygen exchange layer (e.g., hafnium) and an oxide layer, as known in the art.

[0050] In another example, the storage element 166 may be a metal filament memory device (e.g., a conductive bridging random access memory (CBRAM) device); in such embodiments, the memory material 169 may include a solid electrolyte, and one of the electrodes 167 of the storage element 166 may be an electrochemically active material (e.g., silver or copper), and the other of the electrodes 167 of the storage element 166 may be an inert material (e.g., an inert metal), as known in the art. A chemical barrier layer (e.g., tantalum, tantalum nitride, or tungsten) may be disposed between the electrochemically active electrode and the solid electrolyte in some such embodiments to mitigate diffusion of the electrochemically active material into the solid electrolyte.

[0051] In some embodiments, the storage element 166 may be a PCM device; in such embodiments, the storage material 169 may include a chalcogenide or other phase change memory material.

[0052] In some embodiments, storage element 166 may be an MRAM device; in such embodiments, storage material 169 may include a thin tunnel barrier material, and electrodes 167 of storage element 166 may be magnetic (e.g., ferromagnetic). As known in the art, MRAM devices may operate on the principle of tunnel magnetoresistance between two magnetic layers (e.g., the electrodes of storage element 166) separated by a tunnel junction (e.g., the storage material of storage element 166). An MRAM device may have two stable states: when the magnetic moments of the two magnetic layers are aligned parallel to each other, an MRAM device may be in the LRS, and when they are aligned antiparallel, an MRAM device may be in the HRS.

[0053] Fig. Figure 2 provides a perspective view of an exemplary IC device 200 implementing a FinFET 210, according to some embodiments. The FinFET 210 is another example of an angled transistor that may be included in various IC devices and assemblies described herein.

[0054] The Fig. The IC device 200 shown in Figure 2 is intended to show relative arrangements of some of the components therein, and the IC device 200, or portions thereof, may include other components that are not illustrated. Although this is Fig. 2, a dielectric spacer may be provided, for example, between a first S / D contact, which may be coupled to a first S / D region 214-1 of the transistor 210, and the gate stack 206, and between a second S / D contact, which may be coupled to a second S / D region 214-2 of the transistor 210, and the gate stack 206, to provide electrical isolation between the source, gate, and drain contacts. In another example, although not specifically illustrated in Fig. 2, at least portions of the transistor 210 may be surrounded by an insulator material, such as any suitable ILD material.

[0055] With reference to the details of Fig. 2, the IC device 200 may include a semiconductor material, which may include one or more semiconductor materials formed as a fin 204 extending from a support structure 202. A FinFET 210 may be formed based on the fin 204 by having a gate stack 206 at least partially wrapped around a channel portion of the fin 204 and by having source and drain regions formed in Fig. 2 as a first S / D region 214-1 and a second S / D region 214-2, on both sides of the gate stack 206. As shown in Fig. 2, the gate stack 206 includes a gate electrode material 208 and a gate insulator 212, each completely or almost completely wrapping around the channel portion of the fin 204, although in other embodiments of the IC device 200, the gate insulator 212 may be omitted. Descriptions previously provided with reference to the support structure 102, the gate stack 106, the gate electrode material 108, the gate insulator 112, and the S / D regions 114 apply to the support structure 202, the gate stack 206, the gate electrode material 208, the gate insulator 212, and the S / D regions 214, respectively, and are therefore not repeated in the interest of brevity. Fig. 2 further illustrates an STI 216 enclosing the sidewalls of a subfin portion 218 of fin 204. STI 216 may include any of the previously described insulating materials, e.g., any suitable ILD materials. The descriptions provided previously with reference to the channel material of transistor 110 apply to the semiconductor material of at least a channel portion of fin 204 (e.g., at least a portion of fin 204 wrapped around by gate stack 206) and are therefore not repeated in the interest of brevity.

[0056] A longitudinal axis 220 of the fin 204 may extend along the y-axis of the example coordinate system shown in the present drawings. The FinFET 210 may have a gate length (i.e., a distance between the first and second S / D regions 214-1, 214-2), a dimension measured along the longitudinal axis 220, which in some embodiments may be between 2 and 60 nanometers, including all values ​​and ranges therein (e.g., between 5 and 20 nanometers or between 5 and 30 nanometers). Although the fin 204 in Fig. 2 as having a rectangular cross-section in an xz-plane, the fin 204 may instead have a cross-section that is rounded or sloped at the "top" of the fin 204, and the gate stack 206 may correspond to this rounded or sloped fin 204. In use, the FinFET 210 may form conductive channels on three "sides" of the fin 204, potentially improving performance relative to single-gate transistors (which form conductive channels on one "side" of a channel material or substrate) and double-gate transistors (which form conductive channels on two "sides" of a channel material or substrate). It should be noted that, similar to Fig. 1, Fig. 2 illustrates the xyz coordinate system, which, for the sake of simplicity of this particular drawing, is oriented so that the longitudinal axis 220 runs along the y-axis. In other drawings, angled transistors are explained with reference to their longitudinal axes, which lie somewhere in the xy-plane but are not aligned with either the y-axis or the x-axis, because the edges of the support structure are assumed to be aligned with these axes and the transistors are angled, meaning that they are at an angle between 10 degrees and 80 degrees with respect to the y-axis and / or x-axis. Thus, if the FinFET 210 is an angled transistor of any of the subsequent drawings, the longitudinal axis 220 is not aligned with the y-axis, as in Fig. 2, but at an angle between 10 degrees and 80 degrees with respect to the y-axis.

[0057] An example of the use of the FinFET 210 as part of a memory cell is shown in Fig. 2, which shows that the IC device 200 may include a memory cell 260 including the FinFET 210 and a storage element 266 electrically coupled to the S / D region 214-2. In some embodiments, the storage element 266 may include two electrodes 267-1 and 267-2 separated by a storage material 269. An example of the electrodes 267 and the storage material 269 of the storage element 266 is schematically shown within the dashed outline of a slot 262 of Fig. 2, although in other embodiments, the spatial arrangement of the storage material 269 and the electrodes 267 may be different, as long as the storage material 269 is spatially located between the electrode 267-1 and the electrode 267-2 (e.g., the storage material 269 need not be a planar layer, but may be arranged in any type of three-dimensional arrangement). Descriptions previously provided with reference to the storage element 166, the electrodes 167, and the storage material 169 apply to the storage element 266, the electrodes 267, and the storage material 269, respectively, and are therefore not repeated in the interest of brevity.

[0058] Either the nanoribbon 104 or the fin 204 may be an elongated semiconductor structure upon which any of the angled transistors described herein may be built (i.e., any of the angled transistors may be implemented as, for example, the transistor 110 or the FinFET 210). Differences between non-angled elongated semiconductor structures and angled elongated semiconductor structures are described with reference to Fig. 3A-3B and Fig. 4A-4B. In particular, Fig. 3A-3B illustrate exemplary IC devices 300 with non-angled elongated semiconductor structures 304 according to some embodiments, while Fig. 4A-4B illustrate exemplary IC devices 300 with angled elongated semiconductor structures 306. A number of elements used in Fig. 3A-3B and Fig. 4A-4B and in some of the following drawings (e.g. Fig. 6A-6F) are labelled with reference numerals, are indicated in these drawings with different patterns in order not to overload the drawings with too many reference numerals, whereby a legend showing the correspondence between the reference numerals and patterns is shown to the right of Fig. 3A-3B and Fig. 4A-4B. The legend illustrates, for example, that Fig. 3A-3B and Fig. 4A-4B use various patterns to show a support structure 302, non-angled elongated semiconductor structures 304, and angled elongated semiconductor structures 306.

[0059] The IC devices 300 used in Fig. 3A-3B and Fig. 4A-4B are intended to show relative arrangements of some of the components therein, and the IC devices 300, or portions thereof, may include other components that are not illustrated. For example, although not specifically Fig. 3A-3B and Fig. 4A-4B, the IC devices 300 include transistors implemented in or based on the elongated semiconductor structures 304, 306, where transistors would include gate stacks, S / D regions, and other parts, such as previously described with reference to Fig. 1 and Fig. 2. In another example, although not explicitly stated in Fig. 3A-3B and Fig. 4A-4B, at least portions of the elongated semiconductor structures 304, 306 may be surrounded by an insulator material, such as any suitable ILD material.

[0060] As in Fig. 3A-3B and Fig. 4A-4B, the IC device 300 may include a support structure 302 that may include four edges 303, individually shown as edges 303-1, 303-2, 303-3, and 303-4. The edges 303 may be edges of either the front surface of the support structure 302 or the back surface of the support structure 302, depending on whether the non-angled elongated semiconductor structures 304 and the angled elongated semiconductor structures 306 are provided on the front surface or on the back surface of the support structure 302. The support structure 302 may be any of the support structures 102 / 202 described herein. The support structure 302 is rectangular and therefore adjacent edges 303 are at 90 degrees with respect to each other (e.g., edges 303-1 and 303-2 are adjacent to each other and at 90 degrees with respect to each other, edges 303-2 and 303-3 are adjacent to each other and at 90 degrees with respect to each other, and so on).

[0061] As in Fig. 3A-3B, a plurality of parallel non-angled elongated semiconductor structures 304 may be provided above the support structure 302. The non-angled elongated semiconductor structures 304 shown in Fig. 3A-3B are parallel because their longitudinal axes 320 are parallel to each other (in each of Fig. 3A-3B, only one such longitudinal axis 320 is shown in order not to overload the drawings.) The elongated semiconductor structures 304, which in Fig. 3A-3B are “non-angled” because their longitudinal axes 320 are at angles of 0 degrees or 90 degrees with respect to all edges 303 of the support structure 302. For example, in Fig. 3A, the longitudinal axes 320 are at an angle of 0 degrees with respect to each of the edges 303-1 and 303-3 and are at an angle of 90 degrees with respect to each of the edges 303-2 and 303-4, while in Fig. 3B, the longitudinal axes 320 are at an angle of 90 degrees with respect to each of the edges 303-1 and 303-3 and at an angle of 0 degrees with respect to each of the edges 303-2 and 303-4. One or more transistors (e.g., transistors 110 and / or FinFETs 210) may be formed along any and each of the non-angled elongated semiconductor structures 304, thereby forming non-angled transistors as described herein.

[0062] As in Fig. 4A-4B, a plurality of parallel angled elongated semiconductor structures 306 may be provided above the support structure 302. The angled elongated semiconductor structures 306 shown in Fig. 4A-4B are parallel because their longitudinal axes 320 are parallel to each other (in each of Fig. 4A-4B, only one such longitudinal axis 320 is shown in order not to overload the drawings.) The elongated semiconductor structures 306, which in Fig. 4A-4B are "angled" because their longitudinal axes 320 are at angles of neither 0 degrees nor 90 degrees with respect to any of the edges 303 of the support structure 302. In particular, in each of the Fig. 4A-4B, the longitudinal axes 320 are at an angle between approximately 10 degrees and 80 degrees with respect to each of the edges 303. One or more transistors (e.g., transistors 110 and / or FinFETs 210) may be formed along any and each of the angled elongated semiconductor structures 306, thereby forming angled transistors as described herein.

[0063] In various embodiments, both the non-angled elongated semiconductor structures 304 and the angled elongated semiconductor structures 306 may be provided over a single support structure 302, with some examples of such embodiments being shown in Fig. 5A-5Q are shown.

[0064] Fig. 5A-5Q provide schematic illustrations of cross-sectional side views of exemplary IC devices 310 integrating non-angled and angled transistors, according to some embodiments. The IC devices 310 may be examples of a combination of the IC devices 300 shown in Fig. 3A-3B, and the IC devices 300 shown in Fig. 4A-4B. For this purpose, Fig. 5A-5Q some of the same reference numerals as those in Fig. 3A-3B and Fig. 4A-4B to indicate similar or analogous elements to those described by reference to Fig. 3A-3B and Fig. 4A-4B, so that the descriptions of these for Fig. 5A-5Q are not repeated. Each of the IC devices 310 illustrates the support structure 302 as previously described, the support structure having a first surface 312-1 and a second surface 312-2 (the second surface 312-2 is opposite the first surface 312-1, where one of the surfaces 312 may be the front surface / side of the support structure 302 and the other of the surfaces 312 may be the back surface / side of the support structure 302), a layer 314 of non-angled elongated semiconductor structures (hereinafter referred to as a "non-angled layer 314") having at least one non-angled transistor 315, and a layer 316 of angled elongated semiconductor structures (hereinafter referred to as an "angled layer 316") having at least one angled transistor 317.

[0065] Fig. Figure 5A illustrates the details of the non-angled layer 314 and the angled layer 316. In particular, Fig. 5A that the non-angled layer 314 may include N non-angled elongated semiconductor structures 304, as described with reference to Fig. 3A-3B, and that at least one of the N non-angled elongated semiconductor structures 304 may include a non-angled transistor 315. Fig. 5A further illustrates that the angled layer 316 may include M angled elongated semiconductor structures 306, as described with reference to Fig. 4A-4B, and that at least one of the M angled elongated semiconductor structures 306 may include an angled transistor 317. Both N and M may be an integer equal to or greater than one.

[0066] In order not to overload the drawings, the details of the non-angled layer 314 and the angled layer 316 are shown only in Fig. 5A shown and Fig. 5B-5Q illustrate only these layers and an exemplary transistor in each of these layers. Furthermore, although Fig. 5A-5Q illustrate only one non-angled transistor 315 in the non-angled layer 314 and one angled transistor 317 in the angled layer 316. This is also only to avoid cluttering the drawings. In various other embodiments of the IC devices 310, any of the N-type non-angled elongated semiconductor structures 304 of the non-angled layer 314 may include any number of zero or more non-angled transistors 315, and any of the M-type angled elongated semiconductor structures 306 of the angled layer 316 may include any number of zero or more angled transistors 317. Any of the non-angled transistors 315 may be arranged along any of the non-angled elongated semiconductor structures 304, such as, for example,the nanoribbon transistor 110 or the FinFET 210 (possibly coupled to the storage element 166 / 266, as previously described), and any of the angled transistors 317 may be formed along any and each of the angled elongated semiconductor structures 306, such as the nanoribbon transistor 110 or the FinFET 210 (possibly coupled to the storage element 166 / 266, as previously described). Accordingly, any of the non-angled transistors 315 and the angled transistors 317 may include a source region (e.g., one of the S / D regions 114 / 214), a drain region (e.g., another of the S / D regions 114 / 214), and a channel region (e.g.,a portion of the nanoribbon 104 or the fin 204 wrapped by the gate stack 106 / 206) spatially between the source region and the drain region, as previously described, wherein for the non-angled transistor 315, the shortest line extending between the source region and the drain region (i.e., the longitudinal axis 120 / 220) is substantially parallel to at least one of the edges 303 of the support structure 302, and for the angled transistor 317, the shortest line extending between the source region and the drain region (i.e., the longitudinal axis 120 / 220) is at an angle of between 10 degrees and 80 degrees with respect to the same one of the edges 303 of the support structure 302. The edges 303 are shown in FIG. Fig. 5A-5Q not shown, but these are the edges 303 as in Fig. 3 and Fig. 4, and are the edges of either the first surface 312-1 or the second surface 312-2 of the support structure 302 shown in Fig. 5A-5Q.

[0067] Fig. 5A illustrates an embodiment in which the non-angled transistor 315 is provided over a first region of the first surface 312-1 of the support structure 302 and the angled transistor 317 is provided over a second region, which does not overlap with the first region, of the first surface 312-1 of the support structure 302 (i.e., both the non-angled transistor 315 and the angled transistor 317 are provided over the same surface 312-1 or on the same side of the support structure 302 next to each other).

[0068] In some embodiments of the IC device 310 of Fig. 5A, the support structure 302 may be a substrate made of a semiconductor material or may be a substrate having a surface including a layer of a semiconductor material, and the transistors 315 and 317 may be monolithically formed on the same surface 312 of the support structure 302 such that channel regions of these transistors include the semiconductor material of the support structure 302. In other embodiments of the IC device 310 of Fig. 5A, some of the transistors 315 and 317 may be formed monolithically on the first surface 312-1 of the support structure 302, while some others may be provided over the same surface 312-1 using the layer transfer process, as previously described. In still other embodiments of the IC device 310 of Fig. 5A, all transistors 315 and 317 may be provided over the same area 312-1 using the layer transfer process. Unless otherwise described, these variations generally apply to other embodiments of the IC device 310, as in Fig. 5B-5Q, with the modification that transistors 315 and 317 do not have to be provided side by side over the same area as in Fig. 5A, but are provided as shown in Fig. 5B-5Q shown.

[0069] Fig. 5B and Fig. 5C illustrate embodiments of the IC devices 310 in which the transistors 315 and 317 are provided on the opposite surfaces 312. For example, the non-angled transistor 315 may be provided over the first surface 312-1, while the angled transistor 317 may be provided over the second surface 312-2. For example, in some embodiments, the support structure 302 may be a substrate made of a semiconductor material or may be a substrate having a surface of the first surface 312-1 and a surface of the second surface 312-2 that includes a layer of a semiconductor material, and the non-angled and angled transistors 315, 317 may be monolithically formed on different surfaces 312 of the support structure 302 such that channel regions of these transistors include the semiconductor material. The embodiments of Fig. 5B and Fig. 5C may differ in where the projections of the transistors 315, 317 onto the support structure 302 (i.e., the footprints of the transistors 315, 317) may be located with respect to each other. In particular, Fig. 5B shows an embodiment in which a projection of the angled transistor 317 onto the support structure 302 completely overlaps with or lies within a projection of the non-angled transistor 315 onto the support structure 302, or the projection of the non-angled transistor 315 onto the support structure 302 completely overlaps with or lies within the projection of the angled transistor 317 onto the support structure 302. On the other hand, Fig. 5C illustrates an embodiment in which a projection of the angled transistor 317 onto the support structure 302 is offset with respect to a projection of the non-angled transistor 315 onto the support structure 302 (e.g., does not overlap or overlaps by less than about 75%, e.g., overlaps by less than about 25%). In some embodiments, any of the transistors 315, 317 of the IC devices 310 may be Fig. 5A-5C may be monolithically integrated onto the support structure 302, so that the channel regions of these transistors include the channel materials originating from different parts of the semiconductor material of the support structure 302.

[0070] Fig. 5D-5O illustrate embodiments of IC devices 310 in which the non-angled and angled layers 314 and 316 are provided over the same surface 312 (e.g., the first surface 312-1) of the support structure 302, stacked on top of each other, with a bonding layer 318 and / or a redistribution layer (RDL) 324 therebetween. Such embodiments may be advantageous, for example, in reducing parasitic effects and / or reducing delay in exchanging signals between the transistors and other devices of the non-angled and angled layers 314 and 316 because no support structure 302 is present between these layers.

[0071] Fig. 5D-5I, 5K-5L, and 5N-5O illustrate embodiments in which the non-angled transistor 315 is located in a first layer over the first surface 312-1 of the support structure 302, the angled transistor 317 is located in a second layer over the first surface 312-1 of the support structure 302 (i.e., the first and second layers are located over the same surface 312-1 of the support structure 302 and are closer to the first surface 312-1 of the support structure 302 than to the second surface 312-2 of the support structure 302), and the IC device further includes a bond layer 318 between the first and second layers. The IC devices 310 of Fig. 5D-5I, 5K-5L, and 5N-5O can be fabricated by forming the non-angled layer 314 with one or more non-angled transistors 315 on a first IC die, forming the angled layer 316 with one or more angled transistors 317 on a second IC die, and then bonding these two IC dies using hybrid bonding with a bond layer 318 in between. For example, the IC devices 310 of Fig. 5D-5I, 5K-5L, and 5N-5O may be manufactured using hybrid manufacturing, in which the non-angled layer 314 is first formed on a first IC die, the angled layer 316 is formed on a second IC die, and these two IC dies are then bonded together using hybrid manufacturing with a bond layer 318 therebetween. As used herein, "hybrid manufacturing" refers to manufacturing an IC device (e.g., a microelectronic package) by bonding at least two IC dies manufactured by different manufacturers using different materials or different manufacturing techniques. In some embodiments, bonding the surfaces of the first and second IC die may be performed using insulator-insulator bonding, e.g., oxide-oxide bonding, where an insulating material of the first IC die is bonded to an insulating material of the second IC die.In some embodiments, the bonding material 318 may be present between the surfaces of the first and second IC dies that are bonded to each other. To this end, the bonding material may be applied to one or both surfaces of the first and second IC dies that are to be bonded, and then the first and second IC dies are joined together, possibly while applying a suitable pressure and heating the assembly to a suitable temperature (e.g., to moderately high temperatures, e.g., between about 50 and 200 degrees Celsius) for a period of time. In some embodiments, the bonding material 318 may be an adhesive material that ensures attachment of the first and second IC dies to each other. In some embodiments, the bonding material 318 may be an etch stop material.In some embodiments, the bonding material 318 may be both an etch stop material and have suitable adhesion properties to ensure attachment of the first and second IC die to each other. In some embodiments, the bonding material 318 may include silicon, nitrogen, and carbon, where the atomic percentage of any of these materials may be at least 1%, e.g., between about 1% and 50%, indicating that these elements are intentionally added, as opposed to incidental impurities, which are typically present at a concentration of less than about 0.1%.The presence of both nitrogen and carbon at these concentrations in addition to silicon is not typically used in conventional semiconductor manufacturing processes, which typically use either nitrogen or carbon in combination with silicon, and could therefore be a characteristic feature of hybrid bonding. Using an etch stop material at the interface (i.e., the interface between the first and second IC die) that includes silicon, nitrogen, and carbon, where the atomic percentage of any of these materials may be at least 1%, e.g., SiOCN, may be advantageous in that such a material can act both as an etch stop material and have sufficient adhesion properties to bond the first and second IC die together.Additionally, an etch stop material at the interface between the first and second IC die, including silicon, nitrogen, and carbon, wherein the atomic percentage of any of these materials may be at least 1%, may be advantageous in terms of improving an etch selectivity of this material with respect to etch stop materials that may be used in different ones of the first and second IC dies. In some embodiments, no bonding material 318 may be used, but there will still be a bonding interface resulting from bonding the first and second IC dies to each other. Such a bonding interface may be formed as a seam or a thin layer in the microelectronic assembly using, for example,Selective Area Diffraction (SED) may be detectable even if the specific materials of the insulators of the first and second IC die bonded to each other may be the same, in which case the bond interface may still be detectable as a seam or a thin layer in what would otherwise appear to be a bulk insulator (e.g., bulk oxide) layer.

[0072] The embodiments from Fig. 5D-5I, 5K-5L, and 5N-5O differ in whether the non-angled transistors 315 or the angled transistors 317 are located on the bottom of the stack (i.e., closer to the support structure 302) and the bonding is a front-to-back (F2F) bond or a front-to-back (F2B) bond between the non-angled and angled layers 314 and 316.

[0073] Fig. 5D-5F and Fig. 5K-5L illustrate that the angled layer 316 and therefore the angled transistor 317 may be located on the bottom of the stack (i.e., closer to the first surface 312-1 of the support structure 302 than the non-angled layer 314 and therefore than the non-angled transistors 315).

[0074] Fig. 5D illustrates an embodiment where the bond layer 318 may be between and in contact with each of the angled layer 316 on the bottom of the bond layer 318 and the non-angled layer 314 on top of the bond layer 318.

[0075] Fig. 5E illustrates an embodiment where a metallization stack 322 may be present between (e.g., in contact with each of) the bond layer 318 and the non-angled layer 314. As is known in the art, a metallization stack refers to a collection of several levels or several layers in which electrically conductive lines are provided, where electrically conductive vias provide electrical connectivity between conductive lines of different layers. Together, electrically conductive lines and vias may be referred to as an "interconnect," where the term "interconnect" may be used to describe any element formed from an electrically conductive material to provide electrical connectivity to one or more components associated with an IC and / or between various such components.In the context of an IC die / chip, the term "interconnect" can refer to both conductive lines / wires (sometimes referred to as "lines" or "metal lines" or "trenches") and conductive vias (sometimes referred to as "vias" or "metal vias"). In general, a "conductive line" can be used to describe an electrically conductive element insulated by a dielectric material, typically comprising an interlayer low-k dielectric, provided within the plane of the IC die / chip. On the other hand, the term "conductive via" can be used to describe an electrically conductive element that interconnects two or more conductive lines of different levels of a metallization stack.For this purpose, a via may be provided substantially perpendicular to the plane of an IC die / chip or a support structure over which an IC structure is provided, and may interconnect two conductive lines in adjacent planes or two conductive lines in non-adjacent planes. Sometimes, metal lines and vias may be referred to as "conductive lines / traces" and "conductive vias," respectively, to emphasize the fact that these elements include electrically conductive materials, such as, among others, metals. Metallization stacks are typically provided in back-end-of-line (BEOL) layers of an IC die, i.e., layers farther from the die than front-end-of-line (FEOL) layers, where front-end transistors are implemented.Therefore, the presence of the metallization stack 322 between the bonding layer 318 and the non-angled layer 314 and the bonding layer 318 located between the metallization stack 322 and the angled layer 316 may indicate that the metallization stack 322 is originally (i.e., prior to bonding) a part of a first IC die including the non-angled layer 314, with the metallization stack 322 originally lying on the non-angled layer 314, with the first IC die then being bonded face down to the front surface of a second IC die including the angled layer 316. In other words, illustrated. Fig. 5E illustrates an embodiment of an F2F bond between the non-angled and angled layers 314, 316, with the angled layer 316 located on the bottom side (i.e., closer to the support structure 302).

[0076] Fig. 5F illustrates an embodiment in which the non-angled layer 314 lies between (e.g., in contact with each of) the bonding layer 318 and the metallization stack 322. The presence of the non-angled layer 314 between the bonding layer 318 and the metallization stack 322 may indicate that the metallization stack 322 is originally (i.e., prior to bonding) a part of a first IC die including the non-angled layer 314, with the metallization stack 322 lying on the non-angled layer 314, and the first IC die then being bonded backside down to the front surface of a second IC die including the angled layer 316. In other words, Fig. 5F illustrates an embodiment of an F2B bond between the angled layer 316 and the non-angled layer 314, with the angled layer 316 located on the bottom side (i.e., closer to the support structure 302). This may be accomplished as follows. Once the non-angled layer 314 is formed over the first IC die and the metallization stack 322 is formed over the non-angled layer 314, a carrier substrate may be attached to the top side of the first IC die (e.g., the carrier substrate may be attached such that the metallization stack 322 is located between the non-angled layer 314 and the carrier substrate). Such a carrier substrate may be any support structure capable of providing mechanical stability to the non-angled layer 314 and the metallization stack 322. The first IC die may then be flipped (i.e.,The carrier substrate is placed at the bottom for further processing, so that the first IC die can be thinned (e.g., gradually removed) from the backside, e.g., thinned until the non-angled layer 314 is exposed. At this point, the carrier substrate can provide mechanical stability to the assembly. Such a first IC die, with the non-angled layer 314 exposed from the back side of the first IC die, can then be bonded to the front side (e.g., to the angled layer 316) of the second IC die.

[0077] Fig. 5G-5I and Fig. 5N-5O illustrate that the non-angled layer 314 and therefore the non-angled transistor 315 may be located on the bottom of the stack (i.e., closer to the first surface 312-1 of the support structure 302 than the angled layer 316 and therefore than the angled transistors 317).

[0078] Fig. Figure 5G illustrates an embodiment in which the bonding layer 318 may be located between and in contact with each of the bottom non-angled layer 314 and the top angled layer 316 on the bonding layer 318 (i.e. Fig. 5G is similar to Fig. 5D, but with the upper and lower layers reversed with respect to the bond layer 318).

[0079] Fig. 5H illustrates an embodiment in which a metallization stack 322 may be present between (e.g., in contact with each of) the bond layer 318 and the angled layer 314. The presence of the metallization stack 322 between the bond layer 318 and the angled layer 316 and the bond layer 318 located between the metallization stack 322 and the non-angled layer 314 may indicate that the metallization stack 322 is originally (i.e., prior to bonding) a part of a second IC die including the angled layer 316, with the metallization stack 322 originally lying on the angled layer 316, with the second IC die then being bonded face down to the front surface of a first IC die including the non-angled layer 314. In other words, Fig. 5H illustrates an embodiment of an F2F bond between the non-angled and angled layers 314, 316, with the non-angled layer 314 located on the bottom side (i.e., closer to the support structure 302).

[0080] Fig. 5I illustrates an embodiment in which the angled layer 316 lies between (e.g., in contact with each of) the bonding layer 318 and the metallization stack 322. The presence of the angled layer 316 between the bonding layer 318 and the metallization stack 322 may indicate that the metallization stack 322 is originally (i.e., prior to bonding) a part of a second IC die including the angled layer 316, with the metallization stack 322 lying on the angled layer 316, and the second IC die then being bonded backside down to the front surface of a first IC die including the non-angled layer 314. In other words, Fig. 5I illustrates an embodiment of an F2B bond between the angled layer 316 and the non-angled layer 314, where the non-angled layer 314 is on the bottom side (i.e., closer to the support structure 302). This may be done as follows. Once the angled layer 316 is formed over the second IC die and the metallization stack 322 is formed over the angled layer 316, a carrier substrate may be attached to the top side of the second IC die (e.g., the carrier substrate may be attached such that the metallization stack 322 is between the angled layer 316 and the carrier substrate). Such a carrier substrate may be any support structure capable of providing mechanical stability to the angled layer 316 and the metallization stack 322. The second IC die may then be flipped (i.e.,The carrier substrate is placed at the bottom for further processing, so that the second IC die can be thinned (e.g., gradually removed) from the backside, e.g., thinned until the angled layer 316 is exposed. At this point, the carrier substrate can provide mechanical stability to the assembly. Such a second IC die, with the angled layer 316 exposed from the backside of the second IC die, can then be bonded to the front side (e.g., to the non-angled layer 314) of the first IC die.

[0081] Fig. 5J-5O illustrate embodiments in which, similar to Fig. 5D-5I, there is no support structure 302 between the non-angled and angled layers 314, 316, but an RDL 324 is present therebetween.

[0082] Fig. 5J illustrates an embodiment where the RDL 324 may be between and in contact with each of the angled layer 316 on the bottom of the RDL 324 and the non-angled layer 314 on the top of the RDL 324. The RDL 324 may be similar to the bonding layer 318 in that it may provide means for mechanically attaching the angled layer 316 and the non-angled layer 314 to each other. However, in addition to mechanical stability, as the name "RDL" suggests, it includes interconnects that provide electrical connectivity between IC components of the angled layer 316 (angled transistors 317 are a non-limiting example of such IC components) and IC components of the non-angled layer 314 (non-angled transistors 315 are a non-limiting example of such IC components). For this purpose, the RDL 324 can use any arrangement of interconnections (ieconductive vias and / or conductive lines) configured to provide such electrical connectivity. In some embodiments, the RDL 324 may be implemented using staggered via formation, as described below with reference to FIG. Fig. 9 described.

[0083] Fig. Figure 5K illustrates an embodiment of the IC device 310, similar to that in Fig. 5E, except that it further includes the RDL 324 between (e.g., in contact with each of) the angled layer 316 and the bond layer 318, such that the bond layer 318 is now between (e.g., in contact with each of) the RDL 324 and the metallization stack 322.

[0084] Fig. Figure 5L illustrates an embodiment of the IC device 310, similar to that in Fig. 5F, except that it also further includes the RDL 324 between (e.g., in contact with each of) the angled layer 316 and the bond layer 318, such that the bond layer 318 is now between (e.g., in contact with each of) the RDL 324 and the non-angled layer 314.

[0085] Fig. 5M illustrates an embodiment where the RDL 324 may be located between and in contact with each of the non-angled layer 314 on the bottom of the RDL 324 and the angled layer 316 on the top of the RDL 324.

[0086] Fig. Figure 5N illustrates an embodiment of the IC device 310, similar to that in Fig. 5H, except that it further includes the RDL 324 between (e.g., in contact with each of) the non-angled layer 314 and the bond layer 318, such that the bond layer 318 is now between (e.g., in contact with each of) the RDL 324 and the metallization stack 322.

[0087] Fig. 5O illustrates an embodiment of the IC device 310, similar to that in Fig. 5I, except that it also further includes the RDL 324 between (e.g., in contact with each of) the non-angled layer 314 and the bond layer 318, such that the bond layer 318 is now between (e.g., in contact with each of) the RDL 324 and the angled layer 316.

[0088] Fig. 5P and Fig. 5Q illustrate embodiments of the IC devices 310 in which the transistors 315 and 317 are provided on the same surface 312 of the support structure 302 (e.g., on the first surface 312-1), but some may be embedded within the others. In particular, Fig. 5P illustrates an embodiment in which the angled transistor 317 is one of a plurality of angled transistors 317 provided over the first surface 312-1 of the support structure 302, and the non-angled transistor 315 is sandwiched between the plurality of angled transistors 317. On the other hand, Fig. 5Q illustrates an embodiment in which the non-angled transistor 315 is one of a plurality of non-angled transistors 315 provided over the first surface 312-1 of the support structure 302, and the angled transistor 317 is sandwiched between the plurality of non-angled transistors 315. In some embodiments, any of the transistors 315, 317 of the IC devices 310 may be Fig. 5P and Fig. 5Q may be monolithically integrated onto the support structure 302, so that the channel regions of these transistors include the channel materials originating from different parts of the semiconductor material of the support structure 302.

[0089] Fig. 6A-6F provide top views of exemplary IC devices 324 with angled elongated semiconductor structures 306 patterned according to different patterning techniques, according to some embodiments. The angled elongated semiconductor structures 306 are Fig. 6A-6F with the same pattern as that shown in Fig. 4A-4B is used to show the same elements to indicate that descriptions with respect to the angled elongated semiconductor structures 306 of Fig. 4A-4B for Fig. 6A-6F and vice versa. The approximate outline of the support structure 302 is shown in Fig. 6A-6F with a dotted line, with the edges 303 similar to Fig. 3 and Fig. 4 are labeled, and some longitudinal axes 320 are in Fig. 6A-6F similar to Fig. 3 and Fig. 4 shown.

[0090] The Fig. 6A-6F are intended to show relative arrangements of some of the components therein, and the IC devices 300, or portions thereof, may include other components not illustrated. For example, although not specifically shown in and Fig. 6A-6F, the IC devices 324 include transistors implemented in or based on the angled elongated semiconductor structures 306, where transistors would include gate stacks, S / D regions, and other parts, such as previously described with reference to Fig. 1 and Fig. 2. In another example, although this is not Fig. 6A-6F, at least portions of the angled elongated semiconductor structures 306 may be surrounded by an insulator material, such as any suitable ILD material. The angled elongated semiconductor structures 306 shown in Fig. 6A-6F may be a part of any of the IC devices 310 described with reference to Fig. 5 (e.g., any of the transistors 317 described in Fig. 5, based on any of the Fig. 6 shown angled elongated semiconductor structures 306), although the integration of the angled elongated semiconductor structures 306 with non-angled elongated semiconductor structures 304 described with reference to Fig. 5 were declared in Fig. 6 is not shown.

[0091] In various embodiments, the angled elongated semiconductor structures 306 may be fabricated by first forming longer angled elongated semiconductor structures from suitable semiconductor materials and then cutting and / or trimming the longer structures to form various angled elongated semiconductor structures 306, as described herein. For example, each of the Fig. 6A-6F two angled elongated semiconductor structures 306 formed from a single longer angled elongated semiconductor structure, an example of which is shown within a dashed outline 323 in Fig. 6A for one of the shown pairs of angled elongated semiconductor structures 306. As in Fig. 6A, two angled elongated semiconductor structures 306 may be formed from a single longer angled elongated semiconductor structure by providing a cut 325, e.g., using a cut line 330, thereby forming a pair of angled elongated semiconductor structures 306 having a common longitudinal axis 320 (the longitudinal axis 320 is in Fig. 6A is not shown for this pair of angled elongated semiconductor structures 306, but is in Fig. 6A as a first longitudinal axis 320-1 and a second longitudinal axis 320-2 for similar other two pairs of angled elongated semiconductor structures 306). In various embodiments, such pairs of angled elongated semiconductor structures 306 may be formed by patterning using one or more intersection line structures (such as in Fig. 6A-6D), patterning using one or more cut via structures (such as in Fig. 6E) or a patterning using both one or more cut line patterns and one or more cut via patterns (such as in Fig. 6F). In general, splitting a semiconductor structure into two parts using a cut line or cut via refers to providing a line or via filled with an insulator material (e.g., any of the previously described ILD materials, or leaving an opening as a gap) to electrically isolate the two parts of the previously continuous semiconductor structure.

[0092] Turning to the details of the line structuring, Fig. 6A, a first pair of angled elongated semiconductor structures 306-1 and 306-2 sharing a single longitudinal axis 320-1, and a second pair of angled elongated semiconductor structures 306-3 and 306-4 sharing a single longitudinal axis 320-2. Other pairs of angled elongated semiconductor structures 306 are shown in Fig. 6A, but are not labeled to avoid cluttering the drawing. A longitudinal axis is to be shared between a pair of angled elongated semiconductor structures 306 by a single longitudinal axis 320 of one of the structures 306 of the pair, which would overlap with an individual longitudinal axis 320 of another of the structures 306 of the pair. As shown in Fig. 6A, the longitudinal axes 320 of different pairs are parallel to each other and each at an angle between 10 degrees and 80 degrees with respect to an edge (e.g., edge 303-1) of the support structure 302. In Fig. 6A, a first end 328-1 and a second end 328-2 may be defined for each of the angled elongated semiconductor structures 306, with two pairs of ends 328 labeled for each of the structures 306-1 and 306-2 as an example. The ends 328 may be defined such that, for each of the structures 306, the first end 328-1 is closer to the bottom of the drawing than the second end 328-2. Accordingly, for each pair of structures 306, the first end 328-1 of one of the structures 306 is opposite or facing the second end 328-2 of another of the structures 306.

[0093] Fig. Figure 6A illustrates the patterning using a single cutting line 330 because all of the first ends 328-1 of the structures 306 formed in the upper part of Fig. 6A, run along a single line 332-1 and every second of the ends 328-2 of the structures 306, which are in the lower part of Fig. 6A, run along a single line 332-2 parallel to line 332-1. Accordingly, lines 332-1 and 332-2 show boundaries (sidewalls) of the cut line 330 used to cut through the longer angled elongated semiconductor structures (such as the one shown within outline 323) to form pairs 306. As a result of the use of such line structuring, each of a projection of the first end 328-1 of the first angled structure 306-1 onto a plane parallel to the support structure 302 and a projection of the second end 328-2 of the second angled structure 306-2 is a straight line, each of a projection of the first end 328-1 of the third angled structure 306-3 and a projection of the second end 328-2 of the fourth angled structure 306-4 is a straight line, and so on.

[0094] The IC device 324, as shown in Fig. 6A illustrates a relatively simple implementation in which a single cutting line 330 is used to make the patterning cut to form all pairs of angled elongated semiconductor structures 306. Similar to Fig. 6A illustrates Fig. 6B illustrates patterning using one cutting line, but different cutting lines 330 are used to form different pairs of the angled elongated semiconductor structures 306. For example, a first cutting line 330-1 may be defined by the boundaries of lines 332-11 and 332-21, a second cutting line 330-2 may be defined by the boundaries of lines 332-12 and 332-22, and a third cutting line 330-3 may be defined by the boundaries of lines 332-13 and 332-23, as in Fig. 6B. The ends 328 and the longitudinal axes 332 are in Fig. 6B are not specifically shown in order not to clutter the drawings, but descriptions of the ends 328 and the axes 332, which are for Fig. 6A are applicable to Fig. 6B except for the differences described.

[0095] One or more intersection lines 330 defined by the boundaries of a pair of lines 332-1 and 332-2 extending in Fig. 6A and Fig. 6B, all have the same width (e.g., the distance between lines 332-1 and 332-2 is the same for different cutting lines 330, as in Fig. 6A-6B). This does not have to be the case, as shown in Fig. 6C. Similar to Fig. 6B illustrates Fig. 6C illustrates patterning using different cutting lines 330 to form different pairs of the angled elongated semiconductor structures 306, but unlike Fig. 6B, the widths of the intersection lines 330 are different. For example, a first intersection line 330-1 may be defined by the boundaries of lines 332-11 and 332-21, a second intersection line 330-2 may be defined by the boundaries of lines 332-12 and 332-22, and a third intersection line 330-3 may be defined by the boundaries of lines 332-13 and 332-23, as in Fig. Figure 6C illustrates the Fig. 6B is similar. The difference to Fig. 6B is that a distance between lines 332-11 and 332-21 differs from a distance between lines 332-12 and 332-22 and from a distance between lines 332-13 and 332-23. The ends 328 and the longitudinal axes 332 are in Fig. 6B are not specifically shown in order not to clutter the drawings, but descriptions of the ends 328 and the axes 332, which are for Fig. 6A are applicable to Fig. 6B except for the differences described.

[0096] Fig. 6A-6C illustrate embodiments in which one or more cutting lines 330 used to intersect the longer angled elongated semiconductor structures to form pairs of angled elongated semiconductor structures 306 are substantially parallel to one of the edges 303 (e.g., parallel to edges 303-1 and 303-3) of the support structure 302. However, in other embodiments, this may be different, i.e., one or more of the cutting lines 330 used to intersect any of the longer angled elongated semiconductor structures to form a pair of angled elongated semiconductor structures 306 may be at an angle that is not 0 degrees or 90 degrees with respect to any of the edges 303. An example of this is shown in Fig. 6D, which illustrates a first cut line 330-1 and a second cut line 330-2, each of which is at an angle between 0 degrees and 90 degrees with respect to the edges 303-1 and 303-3, i.e., such cut lines 330 are angled cut lines. The use of angled cut lines 330 can result in unique shapes of the ends 328 of individual angled elongated semiconductor structures 306. For example, as shown for an angled elongated semiconductor structure 306-1, its first end 328-1 is aligned with the angled cut line 330-1 and is therefore angled with respect to the edges 303 in the same manner as the cut line 330-1, but its second end 328-2 can still be parallel to the edges 303-1 and 303-3. The same is illustrated for other angled elongated semiconductor structures 306 shown in Fig. 6D are shown.

[0097] In addition to the use of cut lines 330, cut vias 340 may be used in some embodiments, such as in Fig. 6E. Three example cut vias 340-1, 340-2, and 340-3 are shown, each having a substantially elliptical top view (i.e., cross-section for the via) shape, but in other embodiments, this shape may be circular, square, rectangular, or any other polygon, possibly with rounded corners. The use of cut vias 340 may result in unique shapes of the ends 328 of individual angled elongated semiconductor structures 306. For example, as shown for an angled elongated semiconductor structure 306-1, its first end 328-1 is aligned with the cut via 330-1 and is therefore curved in the same manner as the boundary of the cut via 340-1, but its second end 328-2 may still be parallel to the edges 303-1 and 303-3. The same is illustrated for other angled elongated semiconductor structures 306 shown in Fig. 6E. It should be noted that the Fig. 6E are angled in that their axes 342-1 and 342-2, labeled for example, cut via 340-1, are not parallel or perpendicular to any of the edges 303. However, in other embodiments, the axes 342 of at least some of the cut vias 340 may be aligned with some of the edges 303 (not specifically shown in the present drawings).

[0098] Cutting lines 330 and cutting vias 340, which are Fig. 6A-6E provide some examples of how patterning may be performed to perform cuts to divide longer angled elongated semiconductor structures into pairs of angled elongated semiconductor structures 306. In various embodiments, any number of cut lines 330 and any number of cut vias 340 may be used to perform such patterning, either alone or in combination. An example of combining the use of a cut line 330 and a cut via 340 in a single IC device 324 is shown in Fig. 6F, wherein the angled elongated semiconductor structures 306-1 and 306-2 are formed by performing a cut using a cut via 340, and the angled elongated semiconductor structures 306-3 and 306-4 are formed by performing a cut using a cut line 330. The descriptions of the cut lines 330 and cut vias 340 provided above apply to the IC device 324 of Fig. 6F and are therefore not repeated in the interest of brevity.

[0099] IC devices with angled transistors disclosed herein may be fabricated using any suitable techniques. For example, Fig. 7A-7G provide top views of results of various processes of a loop trimming method for fabricating an IC device with angled elongated semiconductor structures according to some embodiments (where Fig. 8A-8F provide some alternative arrangements that can be made using the method in Fig. 7A-7G could be realized), while Fig. 9A-9D show top views of various processes of a staggered via formation method for fabricating an IC device integrating angled elongated semiconductor structures (e.g., formed according to any embodiment of the method of Fig. 7, possibly with the variations from Fig. 8) with a regularly spaced array of vias according to some embodiments.

[0100] The Fig. The IC devices shown in Figures 7-9 are intended to show relative arrangements of some of the components therein, and these IC devices, or portions thereof, may include other components not illustrated. For example, although not specifically shown in and Fig. 7-9, the IC devices shown in these drawings include transistors implemented in or based on the angled elongated semiconductor structures shown, where transistors would include gate stacks, S / D regions, and other parts, such as previously described with reference to Fig. 1 and Fig. 2. In another example, although this is not Fig. 7-9 is not specifically illustrated, at least parts of the angled elongated semiconductor structures, or parts of other Fig. 7-9, be surrounded by an insulator material, such as any suitable ILD material. The angled elongated semiconductor structures shown in Fig. 7-9 may be part of any of the IC devices 310 described with reference to Fig. 5 (e.g., any of the transistors 317 described in Fig. 5, based on any of the Fig. 7-9 shown angled elongated semiconductor structures), although the integration of the angled elongated semiconductor structures with non-angled elongated semiconductor structures described with reference to Fig. 5 were declared in Fig. 7-9 is not shown.

[0101] Although the Fig. 7 and Fig. 9 are each illustrated once and in a specific order, the operations may be performed in any suitable order and repeated as needed. For example, the operations may be performed in a different order to reflect the structure of an IC device in which an angled transistor will be included. In addition, the Fig. 7 and Fig.9 may include other processes not specifically shown in the drawings, such as various cleaning or planarization processes as are known in the art. For example, a support structure, as well as layers of various other materials subsequently deposited thereon, may, in some embodiments, be deposited before, after, or during any of the processes of the Fig. 7 and Fig. 9, e.g., to remove oxides, surface-bound organic or metallic contaminants, and surface contamination. In some embodiments, the cleaning may be performed, e.g., using chemical solutions (such as peroxide) and / or ultraviolet (UV) radiation in combination with ozone and / or oxidizing the surface (e.g., using thermal oxidation), then removing the oxide (e.g., using hydrofluoric acid (HF)). In another example, the arrangements / devices described herein may be used before, after, or during a process of the manufacturing methods described in Fig. 7 and Fig. 9, may be planarized, e.g., to remove excessive or excess material. In some embodiments, planarization may be performed using either wet or dry planarization processes, where planarization may be, e.g., chemical mechanical planarization (CMP), which is understood to be a process that uses a polishing surface, an abrasive, and a polishing slurry to remove the excess and planarize the surface.

[0102] Fig. Figure 7A illustrates an IC device 350A showing that the loop trimming process may begin with providing a support structure 302 (as a dotted rectangular contour) with edges as previously described 303 and providing angled elongated structures 352 from a backbone material 354 (in Fig. 7A only for one of the structures 352, but with the same pattern for all other structures 352 from Fig. 7A). The angled elongated structures 352 of the backbone material 354 may be provided using any suitable patterning techniques, such as, but not limited to, photolithographic or electron beam (e-beam) patterning, possibly in conjunction with a suitable etching technique, e.g., a dry etch, such as radio frequency (RF) RIE (Reactive Ion Etch) or inductively coupled plasma (ICP) RIE. In some embodiments, the etching performed in the loop trimming process may include an anisotropic etch using etchants in a form of, e.g., chemically active ionized gas (i.e., plasma) using, e.g., bromine (Br)- and chloride (Cl)-based chemistries. In some embodiments, the IC structure may be heated to elevated temperatures during the etching of the loop trimming process, e.g.,to temperatures between approximately room temperature and 200 degrees Celsius, including all values ​​and ranges therein, to promote the etching byproducts being rendered volatile enough to be removed from the surface. As described in . Fig. 7A, a first alignment line 356-1 and a second alignment line 356-2 may be defined such that first ends 358-1 of the angled elongated structures 352 of the backbone material 354 may be aligned with the first alignment line 356-1, while the second ends 358-2 of the angled elongated structures 352 of the backbone material 354 may be aligned with the second alignment line 356-2.

[0103] Fig. Figure 7B shows an IC device 350B which is substantially the same as the IC device 350A (although not all of the Fig. 7A shown reference numerals in Fig. 7B to avoid cluttering the drawing), showing that the loop trimming process may continue with the deposition of a liner 360 on the sidewalls of the angled elongated structures 352 of the backbone material 354. The liner 360 may be deposited on the sidewalls using any suitable conformal deposition technique, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or / and physical vapor deposition (PVD) processes, such as sputtering. As a result of the conformal deposition, a thickness of the liner 360 may be substantially uniform along the sidewalls of the angled elongated structures 352 of the backbone material 354.This means that new first ends 362-1 can be defined as the first ends 358-1 of the angled elongated structures 352 of the backbone material 354 with the liner 360 thereon and that new second ends 362-2 can be defined as the second ends 362-2 of the angled elongated structures 352 of the backbone material 354 with the liner 360 thereon. Similar to the first ends 358-1, the new first ends 362-1 may still be aligned, but now with a first alignment line 364-1, which is the first alignment line 356-1 shifted by a distance corresponding to the thickness of the liner 360, and the new second ends 362-2 may still be aligned, but now with a second alignment line 364-2, which is the second alignment line 356-2 shifted by a distance corresponding to the thickness of the liner 360.

[0104] Fig. Figure 7C illustrates an IC device 350C that is substantially the same as IC device 350B (although not all of the Fig. 7A-7B are shown in Fig. 7C to avoid cluttering the drawing), showing that the loop trimming process may proceed with the removal of the backbone material 354, leaving only the liner 360 previously deposited on the sidewalls of the angled elongated structures 352 of the backbone material 354. Such removal of the backbone material 354 without substantial removal of the liner 360 may be accomplished using selective etching, provided the backbone material 354 and the liner 360 exhibit sufficient etch selectivity. As is known in the art, two materials are said to exhibit "sufficient etch selectivity" if etchants used to etch one material do not substantially etch the other, thereby enabling selective etching of one material but not the other.Any suitable etching technique, either anisotropic or isotropic, can be used to remove the backbone material 354. An etch is said to be "anisotropic" if etchants preferentially remove material in one direction rather than all directions, whereas an etch is said to be "isotropic" if the etchants can remove material by etching the material in different directions. A dry etch is an example of an anisotropic etch, while a wet etch is an example of an isotropic etch.

[0105] Fig. Figure 7D illustrates an IC device 350D that is substantially the same as IC device 350C (although not all reference numerals in Fig. 7A-7C in Fig. 7D to avoid cluttering the drawing), showing that the loop trimming process may then continue with the structure of the liner 360 of the IC device 350C as an etch mask to perform an anisotropic etch (e.g., a dry etch) to remove semiconductor material of the support structure 302 not covered by the etch mask, thereby forming angled elongated semiconductor structures 366 having shapes corresponding to those of the liner 360. Subsequently, the liner 360 may be removed, having served its purpose, leaving only the angled elongated semiconductor structures 366, as shown in Fig. 7D. Such a manufacturing method may be used when the angled elongated semiconductor structures 366 serve as a basis for the formation of the angled elongated semiconductor structures 306 by monolithic integration, wherein the semiconductor material of the support structure 302 is used as a channel material of the future angled transistors, as previously described.

[0106] The substantially straight portions of the angled elongated semiconductor structures 366 of the IC device 350D can then serve as the angled elongated semiconductor structures that can be patterned to form angled transistors, as previously described. However, it is not desirable to have the loops at the first ends 362-1 and at the second ends 362-2 of the angled elongated semiconductor structures 366. Therefore, Fig. 7E, an IC device 350E which is substantially the same as the IC device 350D (although not all of the Fig. 7A-7D shown reference numbers in Fig. 7E to avoid cluttering the drawing), showing that the loop trimming process may then proceed with providing a first cut line 368-1 and a second cut line 368-2 to electrically isolate the loops of the angled elongated semiconductor structures 366 at the first ends 362-1 and at the second ends 362-2 from the straight portions of the angled elongated semiconductor structures 366 (i.e., the portions between the loops at the first ends 362-1 and at the second ends 362-2). In particular, the first cut line 368-1 may be used to electrically isolate loop portions of the first ends 362-1 from some, e.g., all, of the angled elongated semiconductor structures 366, while the second cut line 368-2 may be used to electrically isolate loop portions of the first ends 362-1 of some, e.g.,all of the angled elongated semiconductor structures 366, leaving substantially straight portions 367 of the angled elongated semiconductor structures 366 between the intersection lines 368-1 and 368-2. In . Fig. 7E, only two such substantially straight portions 367 are labeled as portions 367-1 and 367-2 for one of the loops of the angled elongated semiconductor structures 366, but multiple such portions 367 are shown (in some of the subsequent drawings, only one of the substantially straight portions 367 is labeled, portion 367-1, in order not to clutter the drawings). In some embodiments, the first cutting line 368-1 may be substantially parallel to the edges 303-2 and 303-4 and substantially perpendicular to the edges 303-1 and 303-3. Likewise, in some embodiments, the first cutting line 368-2 may be substantially parallel to the edges 303-1 and 303-3 and substantially perpendicular to the edges 303-2 and 303-4.Similar to the previously described cut lines 330, the cut lines 368 may be filled with any suitable insulator material to provide electrical isolation of the loops from the substantially straight portions 367 of the angled elongated semiconductor structures 366.

[0107] A plurality of U-shaped loop portions of semiconductor material substantially equal to the substantially straight portions 367 of the angled elongated semiconductor structures 366 at the first ends 362-1, and a plurality of U-shaped loop portions at the second ends 362-2, would be detectable in the end structures as U-shaped portions of semiconductor materials that are not electrically connected to anything, but merely remain in the end device as a result of using the loop trimming method described herein. Therefore, in some embodiments, these U-shaped portions of semiconductor materials may be enclosed on all sides by an insulator material.

[0108] As a result of the structuring of Fig. 7A-7E, if the substantially straight portions 367 of the angled elongated semiconductor structures 366 between the first ends 362-1 and the second ends 362-2 are fins extending away from the support structure 302, then the U-shaped portions would also extend away from the support structure 302 in a similar manner and to the same height. On the other hand, if the substantially straight portions 367 of the angled elongated semiconductor structures 366 between the first ends 362-1 and the second ends 362-2 are nanoribbons provided above the support structure 302, then the U-shaped portions would be in the same layer as the nanoribbons, which are also provided above the support structure 302 in a similar manner, possibly with the same insulator material between them and the support structure 302 as with the nanoribbons.

[0109] In some embodiments, in a direction of the longitudinal axes of the angled elongated semiconductor structures 366 (such as the longitudinal axes 320 described previously), a dimension of such U-shaped loop portions at either the first ends 362-1 or the second ends 362-2 would be at most 10% of the length of the substantially straight portions 367 of the angled elongated semiconductor structures 366 between the first ends 362-1 and the second ends 362-2. Projections of the U-shaped loop portions of the semiconductor material onto the support structure 302 may be curves, which would be very distinct from the analogous projections of the substantially straight portions 367 of the angled elongated semiconductor structures 366 between the first ends 362-1 and the second ends 362-2, which would be rectangles. In some embodiments, a width of any of the cutting lines 368 may be between about 3 nanometers and 1000 nanometers, e.g.between about 5 nanometers and 100 nanometers, or between about 10 nanometers and 75 nanometers.

[0110] The substantially straight portions 367 of the angled elongated semiconductor structures 366 between the first ends 362-1 and the second ends 362-2 may then be patterned according to various patterning techniques, such as with reference to Fig. 6A-6F (e.g., the substantially straight portions 367 of the angled elongated semiconductor structures 366 between the first ends 362-1 and the second ends 362-2 may be the longer angled elongated semiconductor structures used as a starting point for patterning Fig. 6A-6F for fabricating individual angled elongated semiconductor structures 306 as described herein).

[0111] In the loop trimming process described above, the backbone material 354 may include any material that is sufficiently etch-selective with respect to the liner 360, e.g., any of the insulator materials described herein. The liner 360 may be any material that can serve as an etch mask for etching the semiconductor material of the support structure 302 thereunder, i.e., the liner 360 may include any material that is sufficiently etch-selective with respect to the semiconductor material of the support structure 302, e.g., a material that includes silicon and nitrogen (e.g., silicon nitride), or any other suitable material. Further variations of the loop trimming process described above are possible and are described in Fig. 7F and Fig. 7G. In embodiments of these variations, the backbone material 354 and the liner 360 may be selected differently than previously described, depending on which variation of the loop trimming method is implemented.

[0112] Fig. Figure 7F illustrates an IC device 350F that is substantially similar to the IC device 350C as shown in Fig. 7C, except that it has been further processed to form the cut lines 368-1 and 368-2, as described with reference to Fig. 7E. Such an embodiment may be used if the liner 360 is already the semiconductor material on the basis of which angled transistors can be formed. Accordingly, in such an embodiment, the substantially straight parts 367 of the angled elongated semiconductor structures of the liner 360 between the first ends 362-1 and the second ends 362-2 may be the longer angled elongated semiconductor structures that serve as a starting point in the patterning of Fig. 6A-6F for fabricating individual angled elongated semiconductor structures 306 as described herein. In such an embodiment, the liner 360 may include any suitable semiconductor material, such as those described with reference to the channel materials of transistors 110 and 210, as long as it can be deposited as a liner. For example, the liner 360 may include any semiconductor material that can be used in a TFT, such as any of the polycrystalline, polymorphic, or amorphous semiconductors previously described. In another example from Fig. 7F, the liner 360 may include any 2D semiconductor material, such as graphene, hexagonal boron nitride, or transition metal chalcogenides previously described. Because the backbone material 354 in the embodiment of Fig. 7F, the backbone material 354 may be selected as any material that is sufficiently etch-selective with respect to the liner 360.

[0113] Fig. Figure 7G illustrates an IC device 350G that is substantially similar to the IC device 350B as shown in Fig. 7B, except that it has been further processed to form the cut lines 368-1 and 368-2, as described with reference to Fig. 7E. In other words, the IC device 350G is substantially the same as the IC device 350F shown in Fig. 7F, except that the backbone material 354 is not removed. Similar to Fig. 7F, the embodiment of Fig. 7G, if the liner 360 is already the semiconductor material on the basis of which angled transistors can be formed, as described with reference to Fig. 7F. In contrast to the version from Fig. 7F must, because the backbone material 354 during execution from Fig. 7G is not removed, the backbone material 354 is not, but may be selected as a material that is sufficiently etch-selective with respect to the liner 360, but the backbone material 354 must provide electrical insulation between individual instances of the substantially straight portions 367 of the angled elongated semiconductor structures of the liner 360 between the first ends 362-1 and the second ends 362-2. Therefore, in the embodiment of Fig. 7G the backbone material 354 may include any suitable insulator material.

[0114] Although not explicitly shown, the loop trimming method as in Fig. 7A-7G, may further include other manufacturing processes related to fabricating other components of an angled transistor. For example, the loop trimming process, as illustrated in Fig. 7A-7G, further include structuring of the angled elongated structures of the semiconductor materials (e.g., either the angled elongated semiconductor structures 366 if the version of Fig. 7E, or the semiconductor material of the lining 360, if the version from Fig. 7F or Fig. 7G is implemented), e.g. using principles developed with reference to Fig. 6A-6F. In another example, the loop trimming method as described in Fig. 7A-7G, further forming angled transistors (e.g., transistors 110 and / or transistors 210, as previously described) based on the angled elongated structures of the semiconductor materials (e.g., either the angled elongated semiconductor structures 366 if the version of Fig. 7E, or the semiconductor material of the lining 360, if the version from Fig. 7F or Fig. 7G), and integrating at least some of such angled transistors with non-angled transistors (such as described with reference to Fig. 5A-5Q).

[0115] The loop trimming method described above is not limited to the arrangements of various components of the IC devices 350 as shown in Fig. 7A-7G. Some alternative arrangements of various components of the IC device that can be made using the Fig. 7A-7G are shown in Fig. 8A-8F. Each of Fig. 8A-8F illustrates an IC device 350 corresponding to the Fig. 7E, but with some differences in arrangement. Therefore, the same or analogous reference numerals as those in Fig. 7E in Fig. 8A-8F are used to refer to similar or analog components, so only the differences of Fig. 8A-8F with reference to Fig. 7E. Accordingly, apart from the differences in the arrangement of Fig. 8A-8F all of the descriptions that apply to the loop trimming procedure from Fig. 7A-7G, to the IC devices 350 provided in Fig. 8A-8F. In particular, even if not specifically shown, any of the arrangements of Fig. 8A-8F alternatively, instead, according to the embodiments of Fig. 7F or Fig. 7G. In other words, analogous modifications can be applied to the rearrangement of the individual components of the embodiments of Fig. 7F or Fig. 7G can be applied to the arrangements made in Fig. 8A-8F such as those that involve the rearrangement of the individual components of the design from Fig. 7E, all of which embodiments fall within the scope of the present disclosure.

[0116] When executing Fig. 7E, the first alignment line 364-1 and the second alignment line 364-2 were perpendicular to each other and aligned with respective edges 303 of the support structure 302. This may not be the case in other embodiments. An example is shown in Fig. 8A, which shows that one of the alignment lines, e.g., the first alignment line 364-1, may be angled with respect to the edges 303, while the other alignment line, e.g., the second alignment line 364-2, may still be aligned (non-angled) with respect to the edges 303. Another example is shown in Fig. 8B, which shows that both alignment lines may be angled with respect to the edges 303.

[0117] Fig. 8A-8B illustrate that the first and second intersection lines 368-1, 368-2 may be parallel to the respective alignment lines 364. For example, the first intersection line 368-1 may be substantially parallel to the first alignment line 364-1, while the second intersection line 368-2 may be substantially parallel to the second alignment line 364-2. This may not be the case in other embodiments. An example is shown in Fig. 8C, which shows that one of the cutting lines, e.g., the first cutting line 368-1, may be angled (i.e., not parallel) with respect to the first alignment line 364-1, while the other cutting line, e.g., the second cutting line 368-2, may still be aligned (i.e., parallel) with respect to the corresponding alignment line, e.g., the second alignment line 364-2. Another example is shown in Fig. 8D, which shows that both of the cut lines 368 may be angled (i.e., not parallel) with respect to their respective alignment lines 364. Such embodiments, in which the cut lines 368 are not parallel to the alignment lines 364, are applicable to any embodiments of the IC devices 350, regardless of whether all of the alignment lines 364 are aligned with the edges 303 of the support structure (such as in Fig. 7E-7G) or whether some or all of the alignment lines 364 are angled with respect to the edges 303 of the support structure (as shown in Fig. 8A-8D).

[0118] Fig. 7E-7G and Fig. 8A-8D illustrate that a single cutting line 368-1 is used to separate the loops at the first ends 362-1 and another single cutting line 368-2 is used to separate the loops at the second ends 362-2. This may not be the case in other embodiments. An example is shown in Fig. 8E, which shows that multiple cutting lines 368 can be used, some for only one of the ends 362, while others extend across multiple ends 362 to perform the trimming to separate the loops at the first ends 362-1 and the second ends 362-2. The arrangement of five cutting lines 368-1 to 368-5, as shown in Fig. 8E is simply illustrative, and in other embodiments of the IC device 350, any number of cut lines 368 may be used, any of which may or may not be aligned with the edges 303 and / or aligned with the respective alignment lines 364.

[0119] Fig. 7E-7G and Fig. 8A-8E illustrate that two or more cut lines 368 are used to separate the loops at the first ends 362-1 and the second ends 362-2. This may not be the case in other embodiments. An example is shown in Fig. 8F, which shows that cut vias 370 can be used for trimming to separate the loops at the first ends 362-1 and / or at the second ends 362-2. The arrangement of two cut vias 370-1 and 370-2, as in Fig. 8F is simply illustrative, and in other embodiments of the IC device 350, any number of cut vias 370 may be used, any of which may or may not be aligned with the edges 303 and / or aligned with the respective alignment lines 364. Similar to the previously described cut vias 340, the cut vias 370 may be filled with any suitable insulator material to provide electrical isolation of the loops from the substantially straight portions 367 of the angled elongated semiconductor structures 366.

[0120] Fig. 9A-9D provide top views of various processes of a staggered via formation method for fabricating an IC device integrating angled elongated semiconductor structures with a regularly spaced array of vias, according to some embodiments.

[0121] Fig. 9A illustrates an IC device 400A showing that the staggered via formation process may begin with providing a support structure 302 (shown as a dotted rectangular contour) with edges 303 as previously described, and providing the angled elongated semiconductor structures 306 as previously described (in Fig. 9A only for one of the structures 306, but with the same pattern for all of the other structures 306 from Fig. 9A). The angled elongated semiconductor structures 306 may be provided using any suitable manufacturing techniques, such as, but not limited to, using any embodiments of the loop trimming method of Fig. 7 (possibly with variations of Fig. 8), possibly in combination with any of the provisions referred to in Fig. 6 described structuring techniques.

[0122] The angled elongated semiconductor structures 306 may serve as a basis for forming transistors thereon (i.e., angled transistors), e.g., any of the previously described transistors 110, 210. Furthermore, further IC components may be formed based on the angled elongated semiconductor structures 306, e.g., the previously described memory cells 160, 260. Various IC components (i.e., transistors, storage elements, etc.) formed based on the angled elongated semiconductor structures 306 will have terminals (e.g., the transistors will have gate terminals, drain terminals, and source terminals, the storage elements will have first and second electrode terminals, etc.).) with which electrical connections must be made to electrically connect various IC components to each other and to other components of an IC device, as needed for a particular design. Since there are countless ways in which various IC components, such as transistors and memory elements, can be implemented based on the angled elongated semiconductor structures 306 of the IC device 400A, details of these components are described in . Fig. 9A not shown and Fig. 9B continues with an illustration of an IC device 400B, showing that the method further includes providing vias 402 to connect various terminals of the IC components formed based on the angled elongated semiconductor structures 306 of Fig. 9A will be implemented.

[0123] Only one of the vias 402 is in Fig. 9B, but several such vias are shown with the same pattern. Various terminals to which one of the vias 402 is electrically coupled (e.g., in conductive contact) are shown in Fig. 9B and subsequent drawings of Fig. 9 with two-digit reference numerals, such as 11, 12, 13, 14, 15, 21, 22, and so on, where the first digit represents the row in which the terminals are arranged, and the second digit represents the column in which the terminals are arranged. The vias 402 may be provided such that an optimal overlap is obtained with the terminals of various IC components formed based on the angled elongated semiconductor structures 306. As a result, the vias 402 may not be perfectly aligned with each other in their respective rows and / or columns. For example, as in Fig. 9B, the via 402 coupled to terminal 12, the via 402 coupled to terminal 22, the via 402 coupled to terminal 32, and the via 402 coupled to terminal 42 (i.e., four vias 402 coupled to different terminals of the same column, column 2) are not aligned in the same way with respect to any single alignment line. For vias arranged in a given column, a vertical alignment line could be used; e.g., the vias of a given column would be aligned if a single vertical line can be drawn in an xy plane passing through the center of each of the vias. Alternatively, a vertical alignment line may be a line on one side of all of the vias 402 of a given column, as in Fig. 9B with a line 404. However, there is no alignment with respect to the line 404 for the vias 402 of column 2 because, as in Fig. 9B, not all vias 402 of column 2 have their right side along line 404. A careful analysis of the other vias 402 reveals that the same lack of alignment to a single vertical line also applies to the vias 402 of other columns. For the rows of IC device 400B, the vias 402 coupled to terminals of a given row are not aligned in the same manner in that the distances between various nearest adjacent pairs of vias 402 of a given row are not necessarily equal. For example, for row 1, the vias coupled to terminals 11 and 12 form a nearest adjacent pair, and the vias coupled to terminals 12 and 13 form another nearest adjacent pair, but the distance 406-1 between the vias coupled to terminals 11 and 12 is not equal to the distance 406-2 between the vias coupled to terminals 12 and 13, as in Fig. 9B. A careful analysis of the other vias 402 reveals that the same misalignment applies to the vias 402 of other nearest neighboring pairs, either in the same row 1 or in other rows.

[0124] To electrically interconnect the IC components based on the angled elongated semiconductor structures 306 of the IC device 400B, the vias 402 must be coupled to a regular array of vias that may be stacked above them. As used herein, an array of vias is described as "regular" if the vias of the array are arranged in columns and rows, with the vias aligned in both their rows and columns. Vias in a given row may be described as "aligned" if the vias of that row are aligned along a single horizontal line (in the plane of the drawings from Fig. 9) can be aligned and have the same distance between different nearest adjacent pairs of vias of that row. Vias in a given column can be described as "aligned" if the vias of that column are aligned along a single vertical line (in the plane of the drawings from Fig. 9) and have the same distance between different nearest adjacent pairs of vias of this column. Such a regular array of vias is known as vias 408 of an IC device 400C of Fig. 9C. The vias 408 are provided such that they at least partially overlap with the respective vias 402 with a one-to-one correspondence between the vias 408 and the vias 402 such that one of the vias 408 is electrically coupled to (e.g., is in conductive contact with) exactly one of the vias 402 and vice versa. For example, electrically conductive material at least partially filling the vias 402 and 408 may be in contact for each staggered pair of a via 402 and a via 408. By providing the vias 408 staggered above the vias 402, the Fig. The process illustrated in Figure 9 is called the “staggered via formation process”.

[0125] Ideally, all of the vias 408 would have the greatest overlap with the respective vias 402, since a greater overlap means lower contact resistance at the interface between a via 402 and a via 408 stacked on the via 402. However, as previously described, the vias 408 must be in a regular array, whereas the vias 402 are not in a regular array due to the nature of the angled orientation of the elongated semiconductor structures 306. Therefore, the process of arranging the vias 408 on the vias 402 may begin by selecting a terminal for which the overlap is maximized and then aligning the remaining vias 408 with respect to the via 408 of the selected terminal, since all of the vias 408 are in a regular array and therefore the location of one of them dictates the location of the others. As in Fig. 9C, such a selected terminal may be, for example, a terminal 23 which is Fig. 9C with a dashed outline around it. Maximizing the overlap between via 402 and via 408 at terminal 23 means that the location of via 408 at terminal 23 is fixed. The remaining vias 408 are then arranged with respect to via 408 at terminal 23 by ensuring that the rules of a regular array are implemented. For example, this means that for column 3, a distance between via 408 at terminal 23 and via 408 at terminal 33 is substantially equal to a distance between via 408 at terminal 23 and via 408 at terminal 13, and substantially equal to the distance between via 408 at terminal 33 and via 408 at terminal 43, and that all vias 408 of column 3 are arranged along a single vertical line (such as the one shown in Fig. 9B, but in Fig. 9C not specifically shown to avoid cluttering the drawing).

[0126] The inventors of the present disclosure have recognized that when implementing the previously described staggered via formation approach, the misalignment between a via 408 and a corresponding via 402 below the via 408 increases in all directions starting from the selected terminal for which the alignment was optimized. In other words, the misalignment increases in a radially outward direction (i.e., starting from a certain central point and increasing in all directions from that point). Such radially outward extension of the misalignment is in Fig. 9C, by observing it, that the misalignment of a pair of vias 402 and 408 at the selected terminal 23 is the minimum, increases slightly for the nearest neighboring terminals 13, 24, 33 and 22, increases slightly more for the second nearest neighboring terminals 12, 14, 34 and 32, and increases even more for the third nearest neighboring terminals 25, 43 and 21 (the third nearest neighboring terminal above terminal 23 is in Fig. 9C not shown) and increases even further for the terminals that are further away than the third nearest neighboring terminals (e.g., terminals 36 and 46 show the greatest misalignment in the example of Fig. 9C). Such radially outward extension of the misalignment between the vias 402 and the vias 408, starting from a selected terminal, contrasts sharply with misalignments that may be caused by manufacturing process limitations, as the latter are typically observed on a wafer starting on one side and increasing in a single direction (e.g., toward the other side). Therefore, the radially outward extension of the misalignment between the vias 402 and the vias 408, starting from a selected terminal within an array of terminals, is a feature indicative of, or characteristic of, the use of the staggered via formation method as described herein.

[0127] The selected terminal for which the overlap between vias 402 and 408 is maximized does not need to be substantially in the center of an array of terminals. Fig. Figure 9D illustrates an IC device 400D showing an alternative arrangement of the vias 402 and the vias 408 formed in accordance with the method described with reference to Fig. 9A-9C, but with the selected terminal being terminal 12. Even for such a terminal, a radially outward extension of the increase in misalignment between vias 402 and 408 can be observed.

[0128] In some implementations, there may be a point where the misalignment between vias 402 and 408 becomes too large and no effective contact can be made between vias 402 and 408, for example, as in the large misalignment between vias 402 and 408 of connector 47 in Fig. 9D. Therefore, the method as described with reference to Fig. 9A-9C may be repeated for another selected terminal in another portion of an array of terminals. Therefore, in some embodiments, the IC device 400 may include multiple selected terminals from which the misalignment radiates outward to some point.

[0129] It should be noted that although vias 402 and 408 in Fig. 9B-9D as having a substantially square top view shape (i.e., their transverse cross-section), this may not be the case. In other embodiments of the IC devices 400, any of the vias 402 and 408 may have other transverse cross-sections, such as rectangular transverse cross-sections (possibly with rounded corners), substantially circular or elliptical / oval transverse cross-sections, or any other polygonal transverse cross-sections (possibly with rounded corners), etc. Furthermore, the lack of orientation illustrated for the vias 402 may vary in different embodiments of the IC devices 400.For example, in some embodiments, the vias 402 coupled to terminals of a given column may not be aligned in the same way, in that the distances between different nearest neighboring pairs of the vias 402 of a given column are not necessarily equal. In another example, the vias 402 coupled to terminals of a given row may not be aligned in the same way, in that there may not be a single alignment line (e.g., a single horizontal line for the views of FIG. Fig. 9) along which the vias 402 coupled to terminals of a given row are aligned. Any combination of such exemplary misalignments may be present for the arrangements of the vias 402 of the IC devices 400.

[0130] Any of the angled transistors described here (such as those described with reference to Fig. 1, Fig. 2 and Fig. 4) as well as any of the non-angled transistors that may be integrated on the same support structure as the angled transistors (e.g., as described with reference to Fig. 5) may be used to implement any suitable components. In various embodiments, the transistors described herein may, for example, be part of one or more of the following: a central processing unit, a memory device (e.g., a high-bandwidth memory device), a memory cell, logic circuitry, input / output circuitry, a field-programmable gate array (FPGA) component, such as an FPGA transceiver or FPGA logic, power delivery circuitry, an amplifier (e.g., a III-V amplifier), Peripheral Component Interconnect Express (PCIE) circuitry, double data rate (DDR) transmission circuitry, a computing device (e.g., a wearable or handheld computing device), etc.

[0131] The angled transistor IC devices disclosed herein may be incorporated into any suitable electronic device. Fig. 10-14 illustrate various examples of devices that may include one or more of the angled transistor IC devices disclosed herein.

[0132] Fig. 10 illustrates top views of a wafer 2000 and dies 2002 that may include one or more angled transistor IC devices, according to any of the embodiments disclosed herein. In some embodiments, the dies 2002 may be included in an IC package according to any of the embodiments disclosed herein. For example, any of the dies 2002 may be included as any of the dies 2256 in a Fig. 11. The wafer 2000 may be made of semiconductor material and may include one or more dies 2002 with IC structures formed on a surface of the wafer 2000. Each of the dies 2002 may be a repeating unit of a semiconductor product including any suitable IC (e.g., ICs including one or more angled transistor IC devices as described herein). After fabrication of the semiconductor product is complete (e.g., after fabrication of any embodiment of the angled transistor IC device as described herein), the wafer 2000 may undergo a singulation process in which each of the dies 2002 is separated from the others to provide discrete "chips" of the semiconductor product. In particular, devices including one or more angled transistors as disclosed herein may vary the shape of the wafer 2000 (e.g.,The wafer 2000 may take the form of a single die 2002 (e.g., not singulated) or the die 2002 (e.g., singulated). The die 2002 may include auxiliary circuitry for carrying electrical signals to various memory cells, transistors, capacitors, as well as any other IC components. In some embodiments, the wafer 2000 or the die 2002 may implement or include a memory device (e.g., a hysteresis memory device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple devices may be combined on a single die 2002. For example, a memory array formed by multiple memory devices may be implemented on a same die 2002 as a processing device (e.g., the processing device 2402 of FIG. Fig. 11) or other logic configured to store information in the memory devices or to execute instructions stored in the memory array.

[0133] Fig. 11 is a side cross-sectional view of an exemplary IC package 2200 that may include one or more angled transistor IC devices according to any of the embodiments disclosed herein. In some embodiments, the IC package 2200 may be a system-in-package (SiP).

[0134] The package substrate 2252 may be formed from a dielectric material (e.g., a ceramic, a build-up film, an epoxy film with filler particles therein, etc.) and may have conductive paths extending through the dielectric material between the surface 2272 and the surface 2274 or between different locations on the surface 2272 and / or between different locations on the surface 2274.

[0135] The package substrate 2252 may include conductive contacts 2263 coupled to conductive paths 2262 through the package substrate 2252, thereby enabling the circuitry within the die 2256 and / or the interposer 2257 to be electrically coupled to various of the conductive contacts 2264 (or to other devices not shown included in the package substrate 2252).

[0136] The IC package 2200 may include an interposer 2257 coupled to the package substrate 2252 via conductive contacts 2261 of the interposer 2257, first-level interconnects 2265, and the conductive contacts 2263 of the package substrate 2252. The Fig. The first-level interconnects 2265 illustrated in Figure 11 are solder bumps, but any suitable first-level interconnect 2265 may be used. In some embodiments, an interposer 2257 may not be included in the IC package 2200; instead, the dies 2256 may be directly coupled to the conductive contacts 2263 on the side surface 2272 through first-level interconnects 2265.

[0137] The IC package 2200 may include one or more dies 2256 coupled to the interposer 2257 via conductive contacts 2254 of the dies 2256, first-level interconnects 2258, and conductive contacts 2260 of the interposer 2257. The conductive contacts 2260 may be coupled to conductive paths (not shown) through the interposer 2257, thereby enabling circuitry within the dies 2256 to be electrically coupled to various of the conductive contacts 2261 (or to other devices not shown included in the interposer 2257). Fig. The first-level interconnects 2258 illustrated in Figure 11 are solder bumps, but any suitable first-level interconnect 2258 may be used. As used herein, a "conductive contact" may refer to a portion of an electrically conductive material (e.g., metal) that serves as an interface between different components; conductive contacts may be recessed into, flush with, or extend away from a surface of a component and may take any suitable form (e.g., a conductive pad or a socket).

[0138] In some embodiments, an underfill material 2266 may be disposed between the package substrate 2252 and the interposer 2257 around the first-level interconnects 2265, and a potting compound 2268 may be disposed around the dies 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the potting compound 2268. Example materials that may be used for the underfill material 2266 and the potting compound 2268 are suitable epoxy potting materials. Second-level interconnects 2270 may be coupled to the conductive contacts 2264. The second-level interconnects 2270 formed in Fig. 11 are solder balls (e.g., for a ball grid array arrangement), but any suitable second-level interconnects 22770 may be used (e.g., pins in a pin grid array arrangement or contact pads in a contact pad grid array arrangement). The second-level interconnects 2270 may be used to couple the IC package 2200 to another component, such as a printed circuit board (e.g., a motherboard), an interposer, or another IC package, as is known in the art and described below with reference to Fig. 12 is discussed.

[0139] The dies 2256 may take the form of any of the embodiments of the die 2002 discussed herein (e.g., may include any of the embodiments of the angled transistor IC devices as described herein). In embodiments where the IC package 2200 includes multiple dies 2256, the IC package 2200 may be referred to as a multi-chip package (MCP). The dies 2256 may include circuitry for performing any desired functionality. For example, one or more of the dies 2256 may be logic dies (e.g., silicon-based dies), and one or more of the dies 2256 may be memory dies (e.g., high-bandwidth memory), including embedded memory dies as described herein. In some embodiments, any of the dies 2256 may include one or more angled transistor IC devices, such asAs previously discussed; in some embodiments, at least some of the dies 2256 may not include angled transistor IC devices.

[0140] The Fig. The IC package 2200 illustrated in Figure 11 may be a flip-chip package, although other package architectures may be used. For example, the IC package 2200 may be a BGA (Ball Grid Array) package, such as an eWLB (Embedded Wafer-Level Ball Grid Array) package. In another example, the IC package 2200 may be a WLCSP (WLCSP: Wafer-Level Chip Scale Package) or a panel fanout (FO) package. Although two dies 2256 in the IC package 2200 may be Fig. 11, an IC package 2200 may include any desired number of dies 2256. An IC package 2200 may include additional passive components, such as surface-mount resistors, capacitors, and inductors, disposed on the first surface 2272 or the second surface 2274 of the package substrate 2252, or on both surfaces of the interposer 2257. More generally, an IC package 2200 may include any other active or passive components known in the art.

[0141] Fig. 12 is a cross-sectional side view of an IC device assembly 2300 that may include components having one or more angled transistor IC devices, according to any of the embodiments disclosed herein. The IC device assembly 2300 includes a number of components disposed on a circuit board 2302 (which may be, for example, a motherboard). The IC device assembly 2300 includes components disposed on a first surface 2340 of the circuit board 2302 and on an opposite second surface 2342 of the circuit board 2302; generally, components may be disposed on one or both surfaces 2340 and 2342. In particular, any suitable components of the IC device assembly 2300 may include one or more angled transistor IC devices according to any of the embodiments disclosed herein; e.g.,Any of the IC packages discussed below with reference to IC device assembly 2300 may take the form of any of the IC packages previously discussed with reference to . Fig. 11 (e.g., may include one or more IC devices with angled transistors provided on a die 2256).

[0142] In some embodiments, circuit board 2302 may be a PCB that includes multiple metal layers separated by layers of dielectric material and connected by electrically conductive vias. Any one or more of the metal layers may be formed into a desired circuit pattern to carry electrical signals (optionally in conjunction with other metal layers) between components coupled to circuit board 2302. In some embodiments, circuit board 2302 may be a non-PCB substrate.

[0143] The Fig. The IC device assembly 2300 illustrated in Figure 12 includes a package-on-interposer structure 2336 coupled to the first surface 2340 of the circuit board 2302 by coupling components 2316. The coupling components 2316 may electrically and mechanically couple the package-on-interposer structure 2336 to the circuit board 2302 and may include solder balls (such as in Fig. 12), male and female parts of a socket, an adhesive, an underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0144] The package-on-interposer structure 2336 may include an IC package 2320 coupled to an interposer 2304 by coupling components 2318. The coupling components 2318 may take any form suitable for the application, such as the forms discussed above with reference to the coupling components 2316. The IC package 2320 may, for example, include a die (die 2002 of Fig. 10), an IC device, or any other suitable component. In particular, the IC package 2320 may include one or more IC devices with angled transistors as described herein. Although a single IC package 2320 in Fig. 12, multiple IC packages may be coupled to the interposer 2304; in fact, additional interposers may be coupled to the interposer 2304. The interposer 2304 may provide an intermediate substrate that bridges the circuit board 2302 and the IC package 2320. In general, the interposer 2304 may spread an interconnect to a larger pitch or reroute an interconnect to another interconnect. For example, the interposer 2304 may couple the IC package 2320 (e.g., a die) to a BGA of the coupling components 2316 for coupling the circuit board 2302. In the embodiment shown in Fig. In the embodiment illustrated in Figure 12, the IC package 2320 and the circuit board 2302 are mounted on opposite sides of the interposer 2304; in other embodiments, the IC package 2320 and the circuit board 2302 may be mounted on a same side of the interposer 2304. In some embodiments, three or more components may be interconnected via the interposer 2304.

[0145] The interposer 2304 may be formed from an epoxy resin, a glass-fiber-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 2304 may be formed from alternative rigid or flexible materials, which may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other Group III-V and Group IV materials. The interposer 2304 may include metal interconnects 2308 and vias 2310, including, among others, through-silicon vias (TSV) 2306. The interposer 2304 may further include embedded devices 2314, which may include both passive and active devices.Such devices may include, among others, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) protection devices, and memory devices. More complex devices, such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical system (MEMS) devices, may also be formed on the interposer 2304. The package-on-interposer structure 2336 may take the form of any of the package-on-interposer structures known in the art.

[0146] The IC device assembly 2300 may include an IC package 2324 coupled to the first surface 2340 of the circuit board 2302 by coupling components 2322. The coupling components 2322 may take the form of any of the embodiments discussed above with reference to the coupling components 2316, and the IC package 2324 may take the form of any of the embodiments discussed above with reference to the IC package 2320.

[0147] The Fig. The IC device assembly 2300 illustrated in Figure 12 includes a package-on-package structure 2334 coupled to the second surface 2342 of the circuit board 2302 by coupling components 2328. The package-on-package structure 2334 may include an IC package 2326 and an IC package 2332 coupled together by coupling components 2330 such that the IC package 2326 is disposed between the circuit board 2302 and the IC package 2332. The coupling components 2328 and 2330 may take the form of any embodiments of the coupling components 2316 discussed above, and the IC packages 2326 and 2332 may take the form of any embodiments of the IC package 2320 discussed above. The package-on-package structure 2334 may be configured according to any package-on-package structures known in the art.

[0148] Fig. 13 is a block diagram of an exemplary computing device 2400 that may include one or more components, including one or more angled transistor IC devices, in accordance with any of the embodiments disclosed herein. For example, any suitable components of computing device 2400 may include a die (e.g., die 2002 of Fig. 10) with one or more angled transistors as described herein. Any one or more of the components of the computing device 2400 may include an IC package 2200 made of Fig. 11 or an IC device 2300 from Fig. 12 contain or be contained therein.

[0149] A number of components are in Fig. 13 as included in the computing device 2400, however, any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in the computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components may be fabricated on a single system-on-chip (SoC) die.

[0150] Additionally, in various embodiments, the computing device 2400 may not include one or more of the Fig. 13, however, computing device 2400 may include interface circuitry for coupling to the one or more components. For example, computing device 2400 may not include a display device 2412, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which display device 2412 may be coupled. In another set of examples, computing device 2400 may not include an audio input device 2416 or audio output device 2414, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which audio input device 2416 or audio output device 2414 may be coupled.

[0151] Computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that may be stored in registers and / or memory.The processing device 2402 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device 2400 may include a memory 2404, which may itself include one or more storage devices, such as volatile memory (e.g., DRAM), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard disk. In some embodiments, the memory 2404 may include memory that shares a die with the processing device 2402.This memory can be used as cache memory and can include embedded DRAM (eDRAM) or spin-transfer torque MRAM.

[0152] In some embodiments, computing device 2400 may include a communications chip 2406 (e.g., one or more communications chips). For example, communications chip 2406 may be configured to manage wireless communications for transferring data to and from computing device 2400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated devices do not include any wires, although in some embodiments, they may not include them.

[0153] The communication chip 2406 may implement any of a number of wireless standards or protocols, including, but not limited to, Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 1402.11 family), IEEE 1402.16 standards (e.g., IEEE 1402.16-2005 Amendment), Long Term Evolution (LTE) Project along with all modifications, updates, and / or revisions (e.g., Advanced LTE Project, Ultra Mobile Broadband (UMB) Project (also referred to as "3GPP2"), etc.). IEEE 1402.16-compliant Broadband Wireless Access (BWA) networks are commonly referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformance and interoperability tests for the IEEE 1402.16 standards.The communication chip 2406 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2406 can operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2406 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and variations thereof, as well as any other wireless protocols referred to as 3G, 4G, 5G, and beyond. In other embodiments, the communication chip 2406 may operate according to other wireless protocols.Computing device 2400 may include an antenna 2408 to facilitate wireless communications and / or to receive other wireless communications (such as AM or FM radio transmissions).

[0154] In some embodiments, the communication chip 2406 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., Ethernet). As mentioned above, the communication chip 2406 may include multiple communication chips. For example, a first communication chip 2406 may be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and a second communication chip 2406 may be dedicated to longer-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2406 may be dedicated to wireless communications, and a second communication chip 2406 may be dedicated to wired communications.

[0155] Computing device 2400 may include battery / power circuitry 2410. Battery / power circuitry 2410 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of computing device 2400 to a power source separate from computing device 2400 (e.g., the AC mains supply).

[0156] Computing device 2400 may include a display device 2412 (or corresponding interface circuitry, as discussed above). Display device 2412 may include any suitable visual indicator, such as, for example, a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0157] Computing device 2400 may include an audio output device 2414 (or corresponding interface circuitry, as discussed above). Audio output device 2414 may include any device that generates an audible indicator, such as, for example, speakers, headphones, or earbuds.

[0158] Computing device 2400 may include an audio input device 2416 (or corresponding interface circuitry, as discussed above). Audio input device 2416 may include any device that generates a signal representing sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments with a musical instrument digital interface (MIDI) output).

[0159] Computing device 2400 may include another output device 2418 (or corresponding interface circuitry, as discussed above). Examples of another output device 2418 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for delivering information to other devices, or an additional storage device.

[0160] Computing device 2400 may include another input device 2420 (or corresponding interface circuitry, as discussed above). Examples of another input device 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0161] Computing device 2400 may include a GPS device 2422 (or corresponding interface circuitry, as discussed above). GPS device 2422 may be in communication with a satellite-based system and receive a location of computing device 2400, as is known in the art.

[0162] Computing device 2400 may include a security interface device 2424. Security interface device 2424 may include any device that provides security features for computing device 2400 or for any individual components therein (e.g., for processing device 2402 or for memory 2404). Examples of security features may include authorization, access to digital certificates, access to elements in key chains, etc. Examples of security interface device 2424 may include a software firewall, a hardware firewall, antivirus software, a content filtering device, or an intrusion detection device.

[0163] In some embodiments, the computing device 2400 may include a temperature detection device 2426 and a temperature control device 2428.

[0164] The temperature detection device 2426 may include any device capable of determining temperatures of the computing device 2400 or any individual components therein (e.g., temperatures of the processing device 2402 or the memory 2404). In various embodiments, the temperature detection device 2426 may be configured to determine temperatures of an object (e.g., the computing device 2400, components of the computing device 2400, devices coupled to the computing device, etc.), temperatures of an environment (e.g., a data center that includes, is controlled by, or is otherwise associated with the computing device 2400), etc. The temperature detection device 2426 may include one or more temperature sensors.Different temperature sensors of temperature detection device 2426 may have different locations within and around computing device 2400. A temperature sensor may generate data (e.g., digital data) representing detected temperatures and provide the data to another device, e.g., to temperature control device 2428, processing device 2402, memory 2404, etc. In some embodiments, a temperature sensor of temperature detection device 2426 may be turned on or off, e.g., by processing device 2402 or an external system. The temperature sensor detects temperatures when it is on and does not detect temperatures when it is off.In other embodiments, a temperature sensor of the temperature detection device 2426 may detect temperatures continuously and automatically, or detect temperatures at predefined times or at times triggered by an event associated with the computing device 2400 or any components therein.

[0165] The temperature control device 2428 may include any device configured to change (e.g., decrease) temperatures, e.g., based on one or more target temperatures and / or based on temperature measurements made by the temperature detection device 2426. A target temperature may be a preferred temperature. A target temperature may depend on an environment in which the computing device 2400 operates. In some embodiments, the target temperature may be 200 Kelvin or lower. In some embodiments, the target temperature may be 20 Kelvin or lower, or 5 Kelvin or lower. Target temperatures for different objects and different environments of the computing device 2400 may be different or associated with it.In some embodiments, the cooling provided by the temperature control device 2428 may be a multi-stage process with temperatures ranging from room temperature to 4 K or lower.

[0166] In some embodiments, the temperature control device 2428 may include one or more cooling devices. Different cooling devices may have different locations within and around the computing device 2400. A cooling device of the temperature control device 2428 may be associated with one or more temperature sensors of the temperature detection device 2426 and may be configured to operate based on temperatures detected by the temperature sensors. For example, a cooling device may be configured to determine whether a detected ambient temperature is above the target temperature, or whether the detected ambient temperature is higher than the target temperature by a predetermined value, or to determine whether any other temperature-related condition associated with the temperature of the computing device 2400 is met.In response to determining that one or more temperature-related conditions associated with the temperature of the computing device 2400 are met (e.g., in response to determining that the detected ambient temperature is above the target temperature), a cooling device may trigger its cooling mechanism and begin reducing the ambient temperature. Otherwise, the cooling device does not trigger cooling. A cooling device of the temperature control device 2428 may operate with various cooling mechanisms, such as evaporative cooling, radiative cooling, conduction cooling, convection cooling, other cooling mechanisms, or any combination thereof. A cooling device of the temperature control device 2428 may include a coolant, such as water, oil, liquid nitrogen, liquid helium, etc.In some embodiments, the temperature control device 2428 may be, for example, a dilution chiller, a helium-3 chiller, or a liquid helium chiller. In some embodiments, the temperature control device 2428 or any portion thereof (e.g., one or more of the individual chillers) may be connected in close proximity (e.g., less than about 1 meter) to the computing device 2400 or may be provided in a separate enclosure in which a dedicated heat exchanger (e.g., a compressor, a heating, ventilation, and air conditioning (HVAC) system, liquid helium, liquid nitrogen, etc.) may be located.

[0167] By maintaining target temperatures, the power consumption of the computing device 2400 (or components thereof) may be reduced, while computational efficiency may be improved. For example, when the computing device 2400 (or components thereof) operates at lower temperatures, energy dissipation (e.g., heat dissipation) may be reduced. Furthermore, energy consumed by semiconductor components (e.g., energy required to switch transistors of any of the components of the computing device 2400) may also be reduced. Various semiconductor materials may have lower resistivity and / or higher mobility at lower temperatures. In this way, the electrical current per unit supply voltage may be increased by lowering temperatures. Conversely, for the same current that would be required, the supply voltage may be lowered by lowering temperatures.Because energy is correlated with the supply voltage, the energy consumption of semiconductor components can also be lower. In some implementations, the energy savings from reducing heat dissipation and reducing the energy consumed by semiconductor components of the computing device or components thereof can outweigh (sometimes significantly outweigh) the costs associated with the energy required for cooling.

[0168] Computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cellular phone, a smartphone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, computing device 2400 may be any other electronic device that processes data.

[0169] Fig. 14 is a block diagram of an exemplary processing device 2500 that may include one or more angled transistor IC devices according to any of the embodiments disclosed herein. For example, any suitable components of the processing device 2500 may include a die (e.g., die 2002 of Fig. 10) with one or more angled transistors as described herein. Any one or more of the components of the processing device 2500 may include an IC device 2300 ( Fig. 12). Any one or more of the components of the processing device 2500 may include an IC package 2200 made of Fig. 11 or an IC device 2300 from Fig. 12. Any one or more of the components of the processing device 2500 may comprise a computing device 2400 of Fig. 13; for example, processing device 2500 may be processing device 2402 of computing device 2400.

[0170] A number of components are in Fig. 14 as included in processing device 2500, however, any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in processing device 2500 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single SoC die or coupled to a single support structure, e.g., a single carrier substrate.

[0171] In addition, in various embodiments, the processing device 2500 may not include one or more of the Fig. 14, however, processing device 2500 may include interface circuitry for coupling to the one or more components. For example, processing device 2500 may not include memory 2504, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which memory 2504 may be coupled.

[0172] Processing device 2500 may include logic circuitry 2502 (e.g., one or more circuits configured to implement logic / computation functionality). Examples of such circuits include, but are not limited to, ICs that implement input / output (I / O) functions and / or arithmetic operations and / or data pipelining, etc.

[0173] In some embodiments, logic circuitry 2502 may include one or more circuits responsible for read / write operations with respect to the data stored in memory 2504. For this purpose, logic circuitry 2502 may include one or more I / O ICs configured to control access to data stored in memory 2504.

[0174] In some embodiments, logic circuitry 2502 may include one or more high-performance computing dies configured to perform various operations with respect to data stored in memory 2504 (e.g., arithmetic and logical operations, pipelining of data from one or more memory dies of memory 2504, and possibly also data from external devices / chips). In some embodiments, logic circuitry 2502 may be configured to only control I / O access to data, but not perform any operations on the data. In some embodiments, logic circuitry 2502 may implement ICs configured to implement I / O control of data stored in memory 2504, retrieve data from memory 2504 for transport (e.g.,transport over a central bus) to devices / chips located either inside or outside the processing device 2500, etc. In some embodiments, the logic circuitry 2502 may not be configured to perform any operations on the data other than I / O and assembling for transport to the memory 2504.

[0175] Processing device 2500 may include a memory 2504, which may include one or more ICs configured to implement memory circuitry (e.g., ICs implementing memory devices and / or memory arrays and / or control logic configured to control the memory devices and arrays, etc.). In some embodiments, memory 2504 may be configured substantially as previously described with reference to memory 2404 ( Fig. 13). In some embodiments, memory 2504 may be a designated device configured to provide storage functionality for the components of processing device 2500 (i.e., locally), while memory 1604 may be configured to provide system-level storage functionality for the entire computing device 2400 (i.e., globally). In some embodiments, memory 2504 may include memory sharing a die with logic circuitry 2502.

[0176] In some embodiments, memory 2504 may comprise flat memory (sometimes referred to as "flat hierarchy memory" or "linear memory") and may therefore also be referred to as "pool memory." As known in the art, flat memory or linear memory refers to a memory addressing paradigm in which memory may appear to the program as a single contiguous address space, allowing a processor to address all available memory locations directly and linearly without resorting to memory segmentation or paging schemes. The memory implemented in memory 2504 may therefore be memory that is not divided into a hierarchical layer or levels with respect to accessing its data.

[0177] In some embodiments, memory 2504 may include hierarchical memory. In this context, hierarchical memory refers to the concept of computer architecture in which computer memory is separated into a hierarchy based on memory characteristics such as response time, complexity, capacity, performance, and control technology. Designing for high performance may require considering the limits of the memory hierarchy, i.e., the size and capabilities of each component. With hierarchical memory, each of the various memory components may be considered part of a memory hierarchy (m1, m2, ..., m n ), where each element m i is typically smaller and faster than the next higher element m i+1of the hierarchy. To limit waiting by higher levels, a lower level of a hierarchical memory structure may respond by filling a buffer and then signaling to enable the transfer. For example, in some embodiments, the hierarchical memory implemented in memory 2504 may be separated into four main storage levels: 1) internal storage (e.g., processor registers and cache), 2) main memory (e.g., the system RAM and controller cards), 3) online mass storage (e.g., secondary storage), and 4) offline mass storage (e.g., tertiary and offline storage). However, because the number of levels in the memory hierarchy and the performance capabilities at each level have increased over time and are likely to continue to increase in the future, this exemplary hierarchical division provides only a non-limiting example of how memory 2504 may be arranged.

[0178] The processing device 2500 may include a communication device 2506, which operates substantially as previously described with reference to the communication chip 2406 ( Fig. 13). In some embodiments, the communication device 2506 may be a designated device configured to provide communication functionality for the components of the processing device 2500 (i.e., locally), while the communication chip 2406 may be configured to provide system-level communication functionality for the entire computing device 2400 (i.e., globally).

[0179] Processing device 2500 may include interconnects 2508, which may include any element or device including or associated with an electrically conductive material for providing electrical connectivity to one or more components of a processing device 2500 and / or between various such components. Examples of interconnects 2508 include, but are not limited to, conductive lines / wires (sometimes referred to as "lines" or "metal lines" or "trenches") and conductive vias (sometimes referred to as "vias" or "metal vias"), metallization stacks, redistribution layers, metal-insulator-metal (MIM) structures, etc.

[0180] The processing device 2500 may include a temperature detection device 2510, which is substantially as previously described with reference to the temperature detection device 2426 of Fig. 13, but configured to determine temperatures at a more local scale, i.e., the processing device 2500 and components thereof. In some embodiments, the temperature detection device 2510 may be a designated device configured to provide temperature detection functionality for the components of the processing device 2500 (i.e., locally), while the temperature detection device 2426 may be configured to provide system-level temperature detection functionality for the entire computing device 2400 (i.e., globally).

[0181] The processing device 2500 may include a temperature control device 2512, which is substantially as previously described with reference to the temperature control device 2428 of Fig. 13, but configured to regulate temperatures at a more local scale, i.e., of the processing device 2500 and components thereof. In some embodiments, the temperature control device 2512 may be a designated device configured to provide temperature control functionality for the components of the processing device 2500 (i.e., locally), while the temperature control device 2428 may be configured to provide system-level temperature control functionality for the entire computing device 2400 (i.e., globally).

[0182] The processing device 2500 may include a battery / power circuitry 2514, which is substantially as previously described with reference to the battery / power circuitry 2410 of Fig. 13. In some embodiments, battery / power circuitry 2514 may be a designated device configured to provide battery / power functionality to the components of processing device 2500 (i.e., locally), while battery / power circuitry 2410 may be configured to provide system-level battery / power functionality for the entire computing device 2400 (i.e., globally).

[0183] The processing device 2500 may include a hardware security device 2516, which is substantially as previously described with reference to the security interface device 2424 of Fig.13. In some embodiments, hardware security device 2516 may be a physical computing device configured to protect and manage digital keys, perform encryption and decryption functions for digital signatures, authentication, and other cryptographic functions. In some embodiments, hardware security device 2516 may include one or more secure cryptoprocessor chips.

[0184] The above description of illustrated implementations of the disclosure, including what is described in the abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Unless otherwise noted, in various embodiments, features described with reference to one of the drawings may be combined with those described with reference to other drawings.

[0185] The following paragraphs provide various examples of the embodiments disclosed herein.

[0186] Example A1 provides an IC device including: a support structure (e.g., a die, a substrate, a carrier substrate, etc.); a first transistor provided over the support structure; and a second transistor provided over the support structure, wherein each of the second transistor and the first transistor includes a source region, a drain region, and a channel region spatially located between the source region and the drain region, wherein a shortest line extending between the source region and the drain region of the first transistor is substantially parallel to an edge (e.g., at least one of the edges) of the support structure, and where a shortest line extending between the source region and the drain region of the second transistor is at an angle between 10 degrees and 80 degrees with respect to the edge of the support structure. The edge of the support structure may, for example,an edge of one of the opposite front and rear surfaces of the support structure.

[0187] Example A2 provides the IC device of Example A1, wherein the support structure has a first surface and an opposite second surface.

[0188] Example A3 provides the IC device of Example A2, wherein the first transistor is provided over a first region of the first surface of the support structure and the second transistor is provided over a second region, not overlapping with the first region, of the first surface of the support structure (i.e., both transistors are provided over the same surface or on the same side of the support structure). In some embodiments, the support structure may be a substrate made of a semiconductor material or may be a substrate having a surface including a layer of a semiconductor material, and the non-angled and second transistors may be monolithically formed on the same surface of the support structure such that channel regions of these transistors include the semiconductor material.

[0189] Example A4 provides the IC device of Example A2, wherein the first transistor is provided over the first surface of the support structure and the second transistor is provided over the second surface of the support structure. In some embodiments, the support structure may be a substrate made of a semiconductor material or may be a substrate having a surface of the first surface and a surface of the second surface including a layer of a semiconductor material, and the non-angled and second transistors may be monolithically formed on different surfaces of the support structure such that channel regions of these transistors include the semiconductor material.

[0190] Example A5 provides the IC device of Example A4, wherein a projection of the second transistor onto the support structure completely overlaps with or lies within a projection of the first transistor onto the support structure, or the projection of the first transistor onto the support structure completely overlaps with or lies within the projection of the second transistor onto the support structure.

[0191] Example A6 provides the IC device of Example A4, wherein a projection of the second transistor onto the support structure is offset with respect to a projection of the first transistor onto the support structure (e.g., not overlapped or overlapped by less than about 75%).

[0192] Example A7 provides the IC device of Example A2, wherein the second transistor is one of a plurality of second transistors provided over the first surface of the support structure, and the first transistor is sandwiched between the plurality of second transistors.

[0193] Example A8 provides the IC device of Example A2, wherein the first transistor is one of a plurality of first transistors provided over the first surface of the support structure and the second transistor is sandwiched between the plurality of first transistors.

[0194] Example A9 provides the IC device of any one of Examples A1-A8, wherein the support structure is a substrate including a semiconductor material, the channel region of the first transistor includes a first portion of the semiconductor material, and the channel region of the second transistor includes a second portion of the semiconductor material.

[0195] Example A10 provides the IC device of Example A1, wherein the support structure has a first surface and an opposite second surface, the first transistor is in a first layer over the first surface of the support structure, the second transistor is in a second layer over the first surface of the support structure (i.e., the first and second layers are over the same surface of the support structure and are closer to that first surface of the support structure than to the other second surface of the support structure), and the IC device further includes a bonding layer between the first layer and the second layer.

[0196] Example A11 provides the IC device of Example A10, wherein the bonding layer includes a bonding material including an etch stop material including silicon, nitrogen, and carbon, wherein an atomic percentage of each of silicon, nitrogen, and carbon within the etch stop material is at least about 1%, e.g., at least about 5%, e.g., between about 1% and 50%, indicating that these elements are intentionally added, as opposed to accidental impurities, which are typically present at concentrations below 0.1%.

[0197] Example A12 provides the IC device of any one of Examples A10-A11, wherein the second layer is closer to the first surface of the support structure than the first layer.

[0198] Example A13 provides the IC device of Example A12, further including a metallization stack, wherein the metallization stack is between the bonding layer and the first layer, and the bonding layer is between the metallization stack and the second layer (i.e., the metallization stack is a portion of a first IC die including the first layer and the metallization stack on the first layer, wherein the first IC die is then bonded face down to the front side of a second IC die including the second layer).

[0199] Example A14 provides the IC device of Example A13, further comprising a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, the redistribution layer being between the second layer and the bond layer, and the bond layer being between the redistribution layer and the metallization stack.

[0200] Example A15 provides the IC device of Example A12, further including a metallization stack, wherein the first layer is between the bond layer and the metallization stack (ie, the metallization stack is a portion of a first IC die including the first layer and the metallization stack on the first layer, wherein the first IC die is then bonded backside down to the front side of a second IC die including the second layer).

[0201] Example A16 provides the IC device of Example A15, further comprising a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, the redistribution layer being between the second layer and the bond layer, and the bond layer being between the redistribution layer and the first layer.

[0202] Example A17 provides the IC device of any one of Examples A10-A11, wherein the first layer is closer to the first surface of the support structure than the second layer.

[0203] Example A18 provides the IC device of Example A17, further including a metallization stack, wherein the metallization stack is between the bond layer and the second layer, and the bond layer is between the metallization stack and the first second layer (i.e., the metallization stack is a portion of a second IC die including the second layer and the metallization stack on the second layer, the second IC die then being bonded face down to the front side of a first IC die including the first layer).

[0204] Example A19 provides the IC device of Example A18, further comprising a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, the redistribution layer being between the first layer and the bond layer, and the bond layer being between the redistribution layer and the metallization stack.

[0205] Example A20 provides the IC device of Example A17, further including a metallization stack, wherein the second layer is between the bond layer and the metallization stack (ie, the metallization stack is a portion of a second IC die including the second layer and the metallization layer on the second layer, wherein the second IC die is then bonded backside down to the front side of a first IC die including the first layer).

[0206] Example A21 provides the IC device of Example A20, further comprising a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, the redistribution layer being between the first layer and the bond layer, and the bond layer being between the redistribution layer and the second layer.

[0207] Example B1 provides an IC device including: a support structure (e.g., a die, a substrate, a carrier substrate, etc.); and a plurality of angled structures (e.g., angled elongated semiconductor structures 306) provided over the support structure, wherein the plurality of angled structures includes at least a first angled structure (e.g., 306-1) and a second angled structure (e.g., 306-2), each of the angled structures including a first end (e.g., 328-1), a second end (e.g., 328-2) opposite the first end, and a longitudinal axis (e.g., 320) extending between the first end and the second end, wherein the longitudinal axis of each of the angled structures is at an angle between 10 degrees and 80 degrees with respect to an edge of the support structure (the edge of the support structure may, for example,an edge of one of the two opposite surfaces of the support structure), and wherein the longitudinal axis of the first angled structure and the longitudinal axis of the second angled structure are a common longitudinal axis.

[0208] Example B2 provides the IC device of Example B1, wherein the first end of the first angled structure is opposite the second end of the second angled structure (i.e., the first end of the first angled structure is closer to the second end of the second angled structure than the second end of the first angled structure, and the second end of the second angled structure is closer to the first end of the first angled structure than the first end of the second angled structure), and each projection of the first end of the first angled structure onto a plane parallel to the support structure and a projection of the second end of the second angled structure onto the plane is a straight line.

[0209] Example B3 provides the IC device of Example B2, wherein the straight line of projection of the first end of the first angled structure onto the plane is parallel to the straight line of projection of the second end of the second angled structure onto the plane.

[0210] Example B4 provides the IC device of any one of Examples B2-B3, wherein at least one (e.g., all) of the straight lines of projection of the first end of the first angled structure onto the plane and the straight line of projection of the second end of the second angled structure onto the plane are substantially parallel to the edge of the support structure.

[0211] Example B5 provides the IC device of any one of Examples B2-B3, wherein at least one of the straight lines of projection of the first end of the first angled structure onto the plane and the straight line of projection of the second end of the second angled structure onto the plane is at an angle between 10 degrees and 80 degrees with respect to the edge of the support structure.

[0212] Example B6 provides the IC device of Example B5, wherein at least one projection of the second end of the first angled structure onto the plane and one projection of the first end of the second angled structure onto the plane are substantially parallel to the edge of the support structure.

[0213] Example B7 provides the IC device of any one of Examples B1-B6, wherein the common longitudinal axis is a first common longitudinal axis, the plurality of angled structures further includes a third angled structure (e.g., 306-3) and a fourth angled structure (e.g., 306-4), the longitudinal axis of the third angled structure and the longitudinal axis of the fourth angled structure is a common second longitudinal axis, and the first common longitudinal axis (e.g., 320-1) and the second common longitudinal axis (e.g., 320-2) are substantially parallel and at a distance from each other (i.e., they do not overlap or coincide).

[0214] Example B8 provides the IC device of Example B7, wherein the first end of the first angled structure is opposite the second end of the second angled structure (ie, the first end of the first angled structure is closer to the second end of the second angled structure than the second end of the first angled structure, and the second end of the second angled structure is closer to the first end of the first angled structure than the first end of the second angled structure), wherein the first end of the third angled structure is opposite the second end of the fourth angled structure (iethe first end of the third angled structure is closer to the second end of the fourth angled structure than the second end of the third angled structure, and the second end of the fourth angled structure is closer to the first end of the third angled structure than the first end of the fourth angled structure), and wherein each of a projection of the first end of the first angled structure onto a plane parallel to the support structure, a projection of the second end of the second angled structure onto the plane, a projection of the first end of the third angled structure onto the plane, and a projection of the second end of the fourth angled structure onto the plane is a straight line.

[0215] Example B9 provides the IC device of Example B8, wherein the straight line of projection of the first end of the first angled structure onto the plane is parallel to the straight line of projection of the second end of the second angled structure onto the plane, and the straight line of projection of the first end of the third angled structure onto the plane is parallel to the straight line of projection of the second end of the fourth angled structure onto the plane.

[0216] Example B10 provides the IC device of any one of Examples B8-B9, wherein at least one (e.g., all) of the straight lines of projection of the first end of the first angled structure onto the plane and the straight line of projection of the second end of the second angled structure onto the plane are substantially parallel to the edge of the support structure, and at least one (e.g., all) of the straight lines of projection of the first end of the third angled structure onto the plane and the straight line of projection of the second end of the fourth angled structure onto the plane are substantially parallel to the edge of the support structure.

[0217] Example B11 provides the IC device of any one of Examples B8-B10, wherein the straight line of projection of the first end of the first angled structure onto the plane and the straight line of projection of the first end of the third angled structure onto the plane are perpendicular to the support structure in different planes.

[0218] Example B12 provides the IC device of Example B11, wherein the straight line of projection of the second end of the second angled structure onto the plane and the straight line of projection of the second end of the fourth angled structure onto the plane are perpendicular to the support structure in different planes.

[0219] Example B13 provides the IC device of any one of Examples B8-B12, wherein a distance between the straight line of projection of the first end of the first angled structure onto the plane and the straight line of projection of the second end of the second angled structure onto the plane is different from a distance between the straight line of projection of the first end of the third angled structure onto the plane and the straight line of projection of the second end of the fourth angled structure onto the plane.

[0220] Example B14 provides the IC device of any one of Examples B8-B10, wherein the straight line of projection of the first end of the first angled structure onto the plane and the straight line of projection of the first end of the third angled structure onto the plane are in a single first plane perpendicular to the support structure, and the straight line of projection of the second end of the second angled structure onto the plane and the straight line of projection of the second end of the fourth angled structure onto the plane are in a single second plane perpendicular to the support structure.

[0221] Example B15 provides the IC device of any one of examples B8-B10 or B14, wherein a distance between the straight line of projection of the first end of the first angled structure onto the plane and the straight line of projection of the second end of the second angled structure onto the plane is equal to a distance between the straight line of projection of the first end of the third angled structure onto the plane and the straight line of projection of the second end of the fourth angled structure onto the plane.

[0222] Example B16 provides the IC device of Example B1, wherein the first end of the first angled structure is opposite the second end of the second angled structure (i.e., the first end of the first angled structure is closer to the second end of the second angled structure than the second end of the first angled structure, and the second end of the second angled structure is closer to the first end of the first angled structure than the first end of the second angled structure), and wherein each of a projection of the first end of the first angled structure onto a plane parallel to the support structure and a projection of the second end of the second angled structure onto the plane is a curved line.

[0223] Example B17 provides the IC device of Example B16, wherein the curved line of projection of the first end of the first angled structure onto the plane and the curved line of projection of the second end of the second angled structure onto the plane are parts of an ellipse or an oval.

[0224] Example B18 provides the IC device of any one of Examples B1-B17, wherein the angled structures include a semiconductor material.

[0225] Example B19 provides the IC device of any one of Examples B1-B18, wherein one or more of the angled structures are fins of one or more semiconductor materials, the fins extending from a base (where the base may be part of the support structure or may be located between the support structure and the fins).

[0226] Example B20 provides the IC device of any one of Examples B1-B19, wherein one or more of the angled structures are nanoribbons of one or more semiconductor materials.

[0227] Example B21 provides the IC device of any one of Examples B1-B20, further including a first transistor above the support structure, the transistor including a source region, a drain region, and a channel region spatially between the source region and the drain region, wherein a shortest line extending between the source and drain regions of the transistor is the common longitudinal axis, and wherein the channel region of the transistor includes a semiconductor material of the first angled structure (i.e., the transistor is formed based on the first angled structure).

[0228] Example B22 provides the IC device of Example B21, further including a storage element coupled to the transistor.

[0229] Example B23 provides the IC device of Example B22, wherein the storage element is coupled to the source region or the drain region of the transistor.

[0230] Example B24 provides the IC device of any one of Examples B22-B23, wherein the storage element is one of a capacitor, a magnetoresistive material, a ferroelectric material, or a resistance-changing material.

[0231] Example B25 provides the IC device of any one of Examples B21-B24, wherein the transistor is a first transistor, the IC device further includes a second transistor provided above the support structure, and a shortest line extending between a source region of the second transistor and a drain region of the second transistor is substantially parallel to the edge of the support structure.

[0232] Example B26 provides the IC device of Example B25, wherein the support structure has a first surface and an opposite second surface.

[0233] Example B27 provides the IC device of Example B26, wherein the first transistor is provided over a first region of the first surface of the support structure and the second transistor is provided over a second region, not overlapping with the first region, of the first surface of the support structure (i.e., both the non-angled and second transistors are provided over the same surface or on the same side of the support structure). In some embodiments, the support structure may be a substrate made of a semiconductor material or may be a substrate having a surface including a layer of a semiconductor material, and the non-angled and second transistors may be monolithically formed on the same surface of the support structure such that channel regions of these transistors include the semiconductor material.

[0234] Example B28 provides the IC device of Example B26, wherein the first transistor is provided over the first surface of the support structure and the second transistor is provided over the second surface of the support structure. In some embodiments, the support structure may be a substrate made of a semiconductor material or may be a substrate having a surface of the first surface and a surface of the second surface including a layer of a semiconductor material, and the non-angled and second transistors may be monolithically formed on different surfaces of the support structure such that channel regions of these transistors include the semiconductor material.

[0235] Example B29 provides the IC device of Example B28, wherein a projection of the second transistor onto the support structure completely overlaps with or lies within a projection of the first transistor onto the support structure, or the projection of the first transistor onto the support structure completely overlaps with or lies within the projection of the second transistor onto the support structure.

[0236] Example B30 provides the IC device of Example B28, wherein a projection of the second transistor onto the support structure is offset with respect to a projection of the first transistor onto the support structure (e.g., not overlapped or overlapped by less than about 75%).

[0237] Example B31 provides the IC device of Example B26, wherein the second transistor is one of a plurality of second transistors provided over the first surface of the support structure, and the first transistor is sandwiched between the plurality of second transistors.

[0238] Example B32 provides the IC device of Example B26, wherein the first transistor is one of a plurality of first transistors provided over the first surface of the support structure and the second transistor is sandwiched between the plurality of first transistors.

[0239] Example B33 provides the IC device of any one of Examples B25-B32, wherein the support structure is a substrate including a semiconductor material, the channel region of the first transistor includes a first portion of the semiconductor material, and the channel region of the second transistor includes a second portion of the semiconductor material.

[0240] Example B34 provides the IC device of Example B25, wherein the support structure has a first surface and an opposite second surface, the first transistor is in a first layer over the first surface of the support structure, the second transistor is in a second layer over the first surface of the support structure (i.e., the first and second layers are over the same surface of the support structure and are closer to that first surface of the support structure than to the other second surface of the support structure), and the IC device further includes a bonding layer between the first layer and the second layer.

[0241] Example B35 provides the IC device of Example B34, wherein the bonding layer includes a bonding material including an etch stop material including silicon, nitrogen, and carbon, wherein an atomic percentage of each of silicon, nitrogen, and carbon within the etch stop material is at least about 1%, e.g., at least about 5%, e.g., between about 1% and 50%, indicating that these elements are intentionally added, as opposed to accidental impurities, which are typically present at concentrations below 0.1%.

[0242] Example B36 provides the IC device of any one of Examples B34-B35, wherein the second layer is closer to the first surface of the support structure than the first layer.

[0243] Example B37 provides the IC device of Example B36, further including a metallization stack, wherein the metallization stack is between the bonding layer and the first layer, and the bonding layer is between the metallization stack and the second layer (i.e., the metallization stack is a portion of a first IC die including the first layer and the metallization layer on the first layer, wherein the first IC die is then bonded face down to the front side of a second IC die including the second layer).

[0244] Example B38 provides the IC device of Example B37, further comprising a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, the redistribution layer being between the second layer and the bond layer, and the bond layer being between the redistribution layer and the metallization stack.

[0245] Example B39 provides the IC device of Example B36, further including a metallization stack, wherein the first layer is between the bond layer and the metallization stack (ie, the metallization stack is a portion of a first IC die including the first layer and the metallization layer on the first layer, wherein the first IC die is then bonded backside down to the front side of a second IC die including the second layer).

[0246] Example B40 provides the IC device of Example B39, further comprising a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, the redistribution layer being between the second layer and the bond layer, and the bond layer being between the redistribution layer and the first layer.

[0247] Example B41 provides the IC device of any one of Examples B34-B35, wherein the first layer is closer to the first surface of the support structure than the second layer.

[0248] Example B42 provides the IC device of Example B41, further including a metallization stack, wherein the metallization stack is between the bond layer and the second layer, and the bond layer is between the metallization stack and the first second layer (i.e., the metallization stack is a portion of a second IC die including the second layer and the metallization layer on the second layer, the second IC die then being bonded face down to the front side of a first IC die including the first layer).

[0249] Example B43 provides the IC device of Example B42, further comprising a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, the redistribution layer being between the first layer and the bond layer, and the bond layer being between the redistribution layer and the metallization stack.

[0250] Example B44 provides the IC device of Example B41, further including a metallization stack, wherein the second layer is between the bond layer and the metallization stack (ie, the metallization stack is a portion of a second IC die including the second layer and the metallization layer on the second layer, the second IC die then being bonded backside down to the front side of a first IC die including the first layer).

[0251] Example B45 provides the IC device of Example B44, further comprising a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, the redistribution layer being between the first layer and the bond layer, and the bond layer being between the redistribution layer and the second layer.

[0252] Example C1 provides an IC device including: a support structure (e.g., a die, a substrate, a carrier substrate, etc.); an elongated structure (e.g., a fin or a nanoribbon) made of a semiconductor material provided over the support structure; and another structure made of the semiconductor material (i.e., the same material as the elongated structure) proximate the elongated structure, wherein a projection of the elongated structure on the support structure is substantially a rectangle, and a projection of the further structure on the support structure is a curve.

[0253] Example C2 provides the IC device according to Example C1, wherein the projection of the further structure on the support structure has a U-shape.

[0254] Example C3 provides the IC device of any one of Examples C1-C2, wherein the rectangle has a first dimension in a first direction and a second dimension in a second direction, the first direction is perpendicular to the second direction, the first dimension is greater than the second dimension, and the curve has a portion extending along the first direction.

[0255] Example C4 provides the IC device of Example C3, wherein a line along the first direction in the rectangle overlaps with a line along the first direction in the portion of the curve.

[0256] Example C5 provides the IC device of any one of Examples C3-C4, wherein the first direction is at an angle between 10 degrees and 80 degrees with respect to an edge of the support structure (e.g., the edge of the support structure may be an edge of one of the two opposing surfaces of the support structure).

[0257] Example C6 provides the IC device of any one of Examples C3-C5, wherein a dimension of the portion of the curve extending along the first direction is less than 10% of the first dimension of the rectangle.

[0258] Example C7 provides the IC device of any one of Examples C1-C6, wherein a distance between the elongated structure and the further structure is between about 3 nanometers and 1000 nanometers, e.g., between about 5 nanometers and 100 nanometers or between about 10 nanometers and 75 nanometers.

[0259] Example C8 provides the IC device of any one of Examples C1-C7, wherein the elongated structure is a fin extending away from the support structure and the further structure is a curved structure extending away from the support structure.

[0260] Example C9 provides the IC device of Example C8, wherein a height of the fin is substantially equal to a height of the curved structure.

[0261] Example C10 provides the IC device of any one of Examples C1-C7, wherein the elongated structure is a nanoribbon extending parallel to the support structure and the further structure is a curved structure extending parallel to the support structure.

[0262] Example C11 provides the IC device of Example C10, further including an insulator material between the nanoribbon and the support structure and between the curved structure and the support structure.

[0263] Example C12 provides the IC device of any one of Examples C1-C11, wherein a distance from the support structure to a surface of the elongated structure farthest from the support structure is substantially equal to a distance from the support structure to a surface of the further structure farthest from the support structure.

[0264] Example C13 provides the IC device of any one of Examples C1-C12, further including an insulator material between the elongated structure and the further structure.

[0265] Example C14 provides the IC device of any one of Examples C1-C13, wherein the further structure is not electrically connected to any other elements or components of the IC device.

[0266] Example C15 provides the IC device of any one of Examples C1-C14, wherein the further structure is enclosed on all sides by an insulator material (i.e., the further structure is not electrically connected to anything in the IC device).

[0267] Example D1 provides an IC device including: a support structure (e.g., a die, a substrate, a carrier substrate, etc.); a plurality of angled structures (e.g., angled elongated semiconductor structures 306) provided over the support structure, wherein a single angled structure of the plurality of angled structures includes a semiconductor material and is an elongated structure with a longitudinal axis substantially parallel to the support structure and at an angle between 10 degrees and 80 degrees with respect to an edge of the support structure (the edge of the support structure may, for example, be an edge of one of the two opposite surfaces of the support structure); a plurality of IC components based on the plurality of angled structures, wherein the plurality of IC components have a plurality of terminals;and an array of stacked via pairs including: a first stacked via pair, a second stacked via pair, and a third stacked via pair, wherein each stacked via pair of the array includes: a first via electrically coupled to a different one of the terminals, and a second via stacked above and electrically coupled to the first via, wherein an overlap between the first via and the second via for the first stacked via pair is greater than the overlap for the second stacked via pair and the overlap for the third stacked via pair, and wherein the second stacked via pair and the third stacked via pair are on opposite sides of the first stacked via pair.;

[0268] Example D2 provides the IC device of Example D1, wherein the overlap for the first stacked via pair is the largest of all stacked via pairs of the array.

[0269] Example D3 provides the IC device of any one of Examples D1-D2, wherein the overlap decreases radially outward starting from the first stacked via pair.

[0270] Example D4 provides the IC device of any one of Examples D1-D3, wherein the overlap for the first stacked via pair is greater than the overlap of each stacked via pair that is a nearest neighbor of the first stacked via pair.

[0271] Example D5 provides the IC device of Example D4, wherein the overlap for at least one stacked via pair that is the nearest neighbor of the first stacked via pair is greater than the overlap for at least one stacked via pair that is a second nearest neighbor of the first stacked via pair.

[0272] Example D6 provides the IC device of any one of Examples D1-D5, wherein the overlap for at least two stacked via pairs that are nearest neighbors of the first stacked via pair is greater than the overlap for at least two stacked via pairs that are second nearest neighbors of the first stacked via pair.

[0273] Example D7 provides the IC device of any one of Examples D1-D6, wherein for the respective stacked via pair, the first via is between the one of the terminals and the second via.

[0274] Example D8 provides the IC device of any one of Examples D1-D7, the second vias of the array of stacked via pairs are arranged in rows and columns, for each of the rows, distances between different pairs of the nearest adjacent second vias of the row are substantially equal, and for each of the columns, distances between different pairs of the nearest adjacent second vias of the column are substantially equal.

[0275] Example D9 provides the IC device of Example D8, wherein for each of the rows, second vias of the row are aligned along a single line, and for each of the columns, second vias of the column are aligned along a single line.

[0276] Example D10 provides the IC device of any one of Examples D1-D9, further including: a plurality of non-angled structures (e.g., non-angled elongated semiconductor structures 304) provided over the array of stacked vias, wherein a single non-angled structure of the plurality of non-angled structures includes a semiconductor material and is an elongated structure having a longitudinal axis that is substantially parallel to the support structure and parallel or perpendicular with respect to an edge of the support structure (the same edge as in Example 1); and a plurality of further IC components based on the plurality of non-angled structures, wherein the plurality of further IC components have a plurality of further terminals, wherein another of the second vias of the array of stacked via pairs is electrically coupled to one of the plurality of further terminals.

[0277] Example E1 provides the IC device of any one of the preceding examples A, B, C, or D, wherein the IC device includes or is a part of a central processing unit.

[0278] Example E2 provides the IC device of any of the preceding examples A, B, C, or D, wherein the IC device includes or is a part of a memory device, e.g., a high bandwidth memory device.

[0279] Example E3 provides the IC device of any one of the preceding examples A, B, C, or D, wherein the IC device further includes a plurality of memory cells, each of the memory cells including a storage element.

[0280] Example E4 provides the IC device of Example E3, wherein the storage element is one of a capacitor, a magnetoresistive material, a ferroelectric material, or a resistance-changing material.

[0281] Example E5 provides the IC device of any of the preceding examples A, B, C, or D, wherein the IC device includes or is a part of a logic circuit.

[0282] Example E6 provides the IC device of any of the preceding examples A, B, C, or D, wherein the IC device includes or is a part of input / output circuitry.

[0283] Example E7 provides the IC device of any of the preceding examples A, B, C, or D, wherein the IC device includes or is a part of an FPGA transceiver.

[0284] Example E8 provides the IC device of any of the preceding examples A, B, C, or D, wherein the IC device includes or is a part of FPGA logic.

[0285] Example E9 provides the IC device of any of the preceding examples A, B, C, or D, wherein the IC device includes or is a part of power delivery circuitry.

[0286] Example E10 provides the IC device of any one of the preceding examples A, B, C, or D, wherein the IC device includes or is a part of a III-V amplifier.

[0287] Example E11 provides the IC device of any one of the preceding examples A, B, C, or D, wherein the IC device includes or is a part of PCIE circuitry or DDR transfer circuitry.

[0288] Example E12 provides an IC package including an IC device according to any one of the preceding examples A, B, C, D, or E; and another IC component coupled to the IC die.

[0289] Example E13 provides the IC package of Example E12, wherein the further IC component includes one of a package substrate, an interposer, or another IC die.

[0290] Example E14 provides a computing device including a carrier substrate and an IC device coupled to the carrier substrate, wherein the IC device is an IC device according to any one of the preceding examples A, B, C, D, or E, or the IC device is included in the IC package according to any one of examples E12-E13.

[0291] Example E15 provides the computing device of Example E14, wherein the computing device is a wearable or handheld computing device.

[0292] Example E16 provides the computing device of examples E14 or E15, wherein the computing device further includes one or more communication chips and an antenna.

[0293] Example E17 provides the computing device of any one of Examples E14-E16, wherein the carrier substrate is a motherboard.

[0294] Example E18 provides a method of manufacturing an IC device, the method including providing the IC device according to any one of the preceding examples.

Claims

[1] Integrated circuit (IC) device comprising: a support structure; a plurality of angled structures above the support substrate, wherein a single angled structure of the plurality of angled structures includes a semiconductor material and includes a longitudinal axis that is substantially parallel to the support structure and at an angle between 10 degrees and 80 degrees with respect to an edge of the support structure; a plurality of IC components based on the plurality of angled structures, wherein the plurality of IC components have a plurality of terminals; and an array of stacked via pairs comprising a first stacked via pair, a second stacked via pair, and a third stacked via pair, each stacked via pair including: a first via electrically coupled to another of the terminals, and a second via stacked above and electrically coupled to the first via, wherein an overlap between the first via and the second via for the first stacked via pair is greater than the overlap for the second stacked via pair and the overlap for the third stacked via pair, and wherein the second stacked via pair and the third stacked via pair are located on opposite sides of the first stacked via pair. [2] The IC device of claim 1, wherein the overlap for the first stacked via pair is the largest of all stacked via pairs of the array. [3] The IC device of claim 1, wherein the overlap decreases radially outward starting from the first stacked via pair. [4] The IC device of claim 1, wherein the overlap for the first stacked via pair is greater than the overlap of each stacked via pair that is a nearest neighbor of the first stacked via pair. [5] The IC device of claim 4, wherein the overlap for at least one stacked via pair that is the nearest neighbor of the first stacked via pair is greater than the overlap for at least one stacked via pair that is a second nearest neighbor of the first stacked via pair. [6] The IC device of any of claims 1-5, wherein the overlap for at least two stacked via pairs that are nearest neighbors of the first stacked via pair is greater than the overlap for at least two stacked via pairs that are second nearest neighbors of the first stacked via pair. [7] The IC device of any of claims 1-5, wherein for the respective stacked via pair, the first via is located between the one of the terminals and the second via. [8] IC device according to any one of claims 1-5, wherein: the second vias of the array of stacked via pairs are arranged in rows and columns, for each of the rows, distances between different pairs of the nearest adjacent second vias of the row are substantially equal, and for each of the columns, distances between different pairs of the nearest adjacent second vias of the column are substantially equal. [9] The IC device according to claim 8, wherein: for each of the rows, second vias of the row are aligned along a single line, and For each of the columns, second vias of the column are aligned along a single line. [10] The IC device according to any one of claims 1-5, further comprising: a plurality of non-angled structures over the array of stacked vias, wherein a single non-angled structure of the plurality of non-angled structures includes a semiconductor material and is an elongated structure having a longitudinal axis that is substantially parallel to the support structure and parallel or perpendicular with respect to an edge of the support structure; and a plurality of further IC components based on the plurality of non-angled structures, wherein the plurality of further IC components have a plurality of further terminals, wherein another of the second vias of the array of stacked via pairs is electrically coupled to one of a plurality of the further terminals. [11] Integrated circuit (IC) device comprising: a substrate; and a first angled structure and a second angled structure above the substrate, where: each of the first angled structures and the second angled structure includes a first end, a second end opposite the first end, and a longitudinal axis extending between the first end and the second end, the longitudinal axis of both the first angled structure and the second angled structure is at an angle of between 10 degrees and 80 degrees with respect to an edge of the substrate, and the longitudinal axis of the first angled structure and the longitudinal axis of the second angled structure are a common longitudinal axis. [12] The IC device according to claim 11, wherein: the first end of the first angled structure is opposite the second end of the second angled structure, and each of a projection of the first end of the first angled structure onto a plane parallel to the substrate and a projection of the second end of the second angled structure onto the plane is a straight line. [13] The IC device of claim 12, wherein the straight line of projection of the first end of the first angled structure onto the plane is parallel to the straight line of projection of the second end of the second angled structure onto the plane. [14] The IC device of claim 12, wherein at least one of the straight lines of projection of the first end of the first angled structure onto the plane and the straight line of projection of the second end of the second angled structure onto the plane is at an angle of between 10 degrees and 80 degrees with respect to the edge of the substrate. [15] The IC device of claim 11, wherein: the first end of the first angled structure is opposite the second end of the second angled structure, and each of a projection of the first end of the first angled structure onto a plane parallel to the substrate and a projection of the second end of the second angled structure onto the plane is a curved line. [16] The IC device of claim 15, wherein the curved line of projection of the first end of the first angled structure onto the plane and the curved line of projection of the second end of the second angled structure onto the plane are parts of an ellipse or an oval. [17] The IC device of any of claims 11-16, wherein the first angled structure and the second angled structure are fins or nanoribbons of one or more semiconductor materials. [18] The IC device of any of claims 11-16, further comprising a transistor over the substrate, wherein: the transistor includes a source region, a drain region and a channel region between the source region and the drain region, a line between the source and drain regions of the transistor is the common longitudinal axis, and the channel region of the transistor contains a semiconductor material of the first angled structure. [19] Integrated circuit (IC) device comprising: a support structure; an elongated structure of a semiconductor material over the support structure; and another structure made of the semiconductor material, where: a distance between the elongated structure and the further structure is between about 3 nanometers and 1000 nanometers, a projection of the elongated structure on the support structure is substantially a rectangle, and a projection of the further structure onto the support structure is a curve. [20] The IC device of claim 19, wherein: the rectangle has a first dimension in a first direction and a second dimension in a second direction, the first direction being perpendicular to the second direction, the first dimension is larger than the second dimension, the curve has a part extending along the first direction, and a dimension of the part of the curve in the first direction is less than 10% of the first dimension.

Images