Driver device

Abstract

The task is to provide a technique capable of optimizing the turn-on speed. A driver device comprises a gate driver circuit voltage supply capable of varying an output voltage; a voltage supply with a fixed voltage lower than the output voltage; a control unit that modifies the output voltage of the gate driver circuit voltage supply based on information regarding a load current of the semiconductor switching element; and a delay circuit which, when the gate driver signal is turned on, performs a control operation to supply the fixed voltage to a gate of the semiconductor switching element for a predefined period, and subsequently performs a control operation to supply the output voltage to the gate.

Description

Technical area

[0001] The present disclosure relates to a driving device. State of the art

[0002] Various techniques have been proposed for a driving device that drives a semiconductor switching element, such as a voltage-controlled type semiconductor switching element. For example, Patent Documents 1 and 2 propose a technique for increasing and decreasing the voltage applied to a gate of a voltage-controlled type semiconductor switching element based on the load current in order to reduce the steady-state loss of the voltage-controlled type semiconductor switching element. State of the art documentsPatent documents Patent Document 1: Japanese Patent No. 4333802 Patent Document 2: Japanese Patent Application Laid-Open No. 2004-96830 SummaryProblem to be solved by the invention

[0003] In general, when the load current of the semiconductor switching element is zero or low, the turn-on speed of the semiconductor switching element increases. Furthermore, when the voltage applied to the gate of the semiconductor switching element at the time of turn-on increases sharply, the turn-on speed of the semiconductor switching element increases.

[0004] However, since the techniques of Patent Documents 1 and 2 simply increase the voltage applied to the gate, it is possible that the voltage applied to the gate may increase sharply when the AC load current immediately becomes zero or low. In this case, there is a problem that the turn-on speed of the semiconductor switching element becomes excessive, and the surge voltage and radiation noise become large.

[0005] Therefore, the present disclosure has been made in view of the above problems, and an object thereof is to provide a technique capable of optimizing the power-on speed. Means to solve the problem

[0006] A driving device according to the present disclosure is a driving device that drives a semiconductor switching element based on the on and off of a gate driving signal. The driving device includes: a gate driving circuit power supply capable of varying an output voltage; a power supply having a fixed voltage lower than the output voltage; a control unit that varies the output voltage of the gate driving circuit power supply based on associated information related to a load current of the semiconductor switching element; and a delay circuit that performs control to supply the fixed voltage to the gate of the semiconductor switching element for a predefined period of time and then performs control to supply the output voltage to the gate when the gate driving signal is turned on. Effects of the invention

[0007] According to the present disclosure, when a gate drive signal is turned on, control is performed to supply a fixed voltage to a gate of a semiconductor switching element for a predefined period of time, and then control is performed to supply an output voltage to the gate. According to such a configuration, the turn-on speed can be optimized.

[0008] Objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying figures. Short description of the characters Fig. 1 is a circuit diagram illustrating a configuration of a driving device according to a first embodiment. Fig. 2 is a circuit diagram illustrating a configuration of the driving device according to the first embodiment. Fig. 3 is a diagram illustrating a change pattern of a power supply output voltage according to the first embodiment. Fig. 4 is a diagram illustrating an operation of the driving device according to the first embodiment. Fig. 5 is a circuit diagram illustrating a configuration of a driving device according to a modification. Fig. 6 is a circuit diagram illustrating a configuration of a driving device according to a second embodiment. Fig. 7 is a diagram illustrating an operation of the driving device according to the second embodiment. Fig. 8 is a circuit diagram illustrating a configuration of a driving device according to a third embodiment. Fig. 9 is a diagram illustrating an operation of the driving device according to the third embodiment. Fig. 10 is a diagram illustrating an operation of the driving device according to the third embodiment. Description of the embodiments<Erste Ausführungsform>

[0009] Fig. 1 is a circuit diagram illustrating a configuration of a driving device according to a first embodiment. The driving device of Fig. 1 comprises a gate driver circuit voltage supply E1, a PWM controller 1, which is a control unit, a gate driver circuit 2, and a resistor RG.

[0010] The driver device of Fig. 1 is connected to a gate of a semiconductor switching element Q1, which is a semiconductor switching element of a voltage-controlled type. The driver device of Fig. 1 controls the semiconductor switching element Q1 based on an on and off of the gate drive signal.

[0011] The semiconductor switching element Q1 according to the first embodiment is used in an inverter circuit as shown in Fig. 2 illustrates the inverter circuit. In the inverter circuit of Fig. 2, freewheeling diodes D1 to D6 are connected in parallel with semiconductor switching elements Q1 to Q6, respectively. Furthermore, semiconductor switching elements Q2, Q4, and Q6 as the upper arms and semiconductor switching elements Q1, Q3, and Q5 as the lower arms are connected in series, respectively, and the three sets of upper and lower arms and a power supply E2 are connected in parallel. Fig. 1 is an illustration of Fig. 2 is omitted for simplicity, and the semiconductor switching element Q1 is connected to the voltage supply E2 via a load unit 9.

[0012] In the following, the semiconductor switching element Q1 is described as a metal oxide semiconductor field effect transistor (MOSFET), but as described later, it is not limited to the MOSFET.

[0013] Next, components of the driving device according to the first embodiment will be described in detail.

[0014] The gate driver circuit power supply E1 is designed to be capable of varying an output voltage, which is an output voltage from the gate driver circuit power supply E1. Hereinafter, the output voltage of the gate driver circuit power supply E1 may be referred to as a power supply output voltage.

[0015] The PWM controller 1 outputs a gate drive signal having a rectangular waveform to the gate drive circuit 2. The PWM controller 1 controls the load current of the semiconductor switching element Q1 by varying the duty cycle of the on-period and the off-period of the gate drive signal, and controls the output of the gate drive circuit 2. The load current of the semiconductor switching element Q1 is, for example, a current flowing through the source-drain of the semiconductor switching element Q1, which is connected between the load unit 9 or the like.

[0016] The PWM controller 1 also outputs a voltage control signal to the gate drive circuit power supply E1. The PWM controller 1 performs control to change the power supply output voltage of the gate drive circuit power supply E1 by changing the voltage control signal based on the related information related to the load current of the semiconductor switching element Q1. In the first embodiment, the related information related to the load current is a change pattern of the power supply output voltage, which is determined in advance with respect to the effective value of the load current, and this change pattern is stored in the PWM controller 1 in advance.

[0017] Fig. Figure 3 is a diagram illustrating an example of a change pattern of the power supply output voltage. A thin solid line indicates an instantaneous value of the load current, a thin dashed line indicates an effective value of the load current, and a thick solid line indicates a change pattern of the power supply output voltage. The instantaneous value of the load current corresponds to the waveform of the gate drive signal and changes in accordance with the on and off of the gate drive signal. An alternating current, which is indicated by an instantaneous value of the load, flows through a load connected to the output (U, V, W) of Fig. 2 is connected.

[0018] The PWM controller 1 controls the power supply output voltage of the gate drive circuit power supply E1 such that the power supply output voltage of the gate drive circuit power supply E1 increases when the effective value of the load current is large and that the power supply output voltage of the gate drive circuit power supply E1 decreases when the effective value of the load current is small. The PWM controller 1 can control the power supply output voltage of the gate drive circuit power supply E1 as shown in Fig. 3 illustrates a stepwise increase or decrease, or it may be proportional to the effective value of the load current. For example, the PWM controller 1 can change the power supply output voltage of the gate drive circuit power supply E1 based on the number of times the gate drive signal is turned on and off and a predefined change pattern.

[0019] The resistance RG in Fig. 1 is connected between the gate of the semiconductor switching element Q1 and the gate driver circuit 2.

[0020] The gate driver circuit 2 of Fig. 1 comprises a power supply E3, a first switch S1, a second switch S2, a third switch S3, an inverter circuit INV, which is a NOT circuit, and a delay circuit DLC.

[0021] The power supply E3 has a fixed voltage that is lower than the power supply output voltage of the gate driver circuit power supply E1.

[0022] One end of the first switch S1 is connected to the power supply E3, the other end of the first switch S1 is connected to the resistor RG, and an on and off of the first switch S1 is controlled by the delay circuit DLC.

[0023] One end of the second switch S2 is connected to the gate drive circuit power supply E1, the other end of the second switch S2 is connected to the resistor RG, and an on and off of the second switch S2 is controlled by the delay circuit DLC.

[0024] One end of the third switch S3 is connected to the reference voltage GND, the other end of the third switch S3 is connected to the resistor RG, and an on and off of the third switch S3 is controlled by a gate drive signal which is inverted by the inverter circuit INV.

[0025] When the gate drive signal is turned on, the delay circuit DLC executes control to turn on the first switch S1 and turn off the second switch S2, so that the fixed voltage of the power supply E3 is supplied to the gate of the semiconductor switching element Q1 for a predefined period of time. After the fixed voltage of the power supply E3 is supplied to the gate for a predefined period of time, the delay circuit executes control to turn off the first switch S1 and turn off the second switch S2, so that the power supply output voltage of the gate drive circuit power supply E1 is supplied to the gate of the semiconductor switching element Q1.

[0026] The delay circuit DLC performs control to turn off the first switch S1 and the second switch S2 when the gate drive signal is turned off. In this case, the third switch S3 is turned on by the gate drive signal inverted by the inverter circuit INV, and the reference voltage GND is supplied to the gate of the semiconductor switching element Q1. That is, in the first embodiment, the first switch S1, the second switch S2, and the third switch S3 are exclusively turned on. <betrieb>

[0027] Fig. 4 is a diagram illustrating an operation of the driving device according to the first embodiment. Hereinafter, to distinguish it from the power supply output voltage of the gate driving circuit power supply E1, the output voltage of the gate driving circuit 2 may be referred to as a circuit output voltage. Fig. 4 illustrates a gate drive signal, an on and off of the first switch S1, an on and off of the second switch S2, a circuit output voltage, and a gate voltage of the semiconductor switching element Q1.

[0028] When the gate drive signal is switched from off to on at time T0, the first switch S1 is turned on. As a result, the circuit output voltage becomes the voltage of the power supply E3, and the gate voltage increases. A period from time T1 to time T2 is a Miller period, and during the Miller period, the gate voltage becomes constant at a voltage lower than the voltage of the power supply E3. When the Miller period ends at time T2, the gate voltage increases to approach the fixed voltage of the power supply E3.

[0029] At a time T3, the gate voltage becomes approximately a fixed voltage of the power supply E3. In the example of Fig. 4, at this time, the first switch S1 is turned off and the second switch S2 is turned on under the control of the delay circuit DLC. As a result, the circuit output voltage becomes the supply voltage output voltage of the gate drive circuit power supply E1, and the gate voltage increases even after time T3.

[0030] In the example of Fig. 4, the time at which the first switches S1 and S2 are switched is the same as the time at which the gate voltage becomes approximately the fixed voltage of the power supply E3, but the present invention is not limited to this. For example, the time at which the first switches S1 and S2 are switched may be before or after the time at which the gate voltage becomes approximately the fixed voltage of the power supply E3, or it may be within the Miller period.

[0031] As described above, after time T3 in Fig. 4 the power supply output voltage becomes low when the load current is small, and the power supply output voltage becomes high when the load current is high, and this is reflected in the circuit output voltage and gate voltage.

[0032] Although not illustrated, when the gate drive signal is switched from on to off, the first switch S1 and the second switch S2 are turned off, and the third switch S3 is turned on. As a result, the circuit output voltage becomes the reference voltage GND, the gate voltage drops, and the semiconductor switching element Q1 is turned off. <Zusammenfassung der ersten Ausführungsform>

[0033] According to the driving device of the first embodiment, the PWM controller 1 changes the power supply output voltage of the gate drive circuit power supply E1 based on the associated information related to the load current of the semiconductor switching element Q1. As a result, as shown in the Fig. 3 and Fig. As illustrated in Figure 4, since the gate voltage applied to the semiconductor switching element Q1 increases as the load current increases, the voltage of the semiconductor switching element Q1 when it is turned on can be reduced, and the steady loss of the semiconductor switching element Q1 can be reduced. Furthermore, the ratio of the time period under the state where the load current is maximum to the entire operation time becomes small, and the average voltage applied to the gate of the semiconductor switching element Q1 and the gate drive circuit 2 becomes lower than the maximum voltage of the power supply output voltage of the gate drive circuit power supply E1. Therefore, it can be expected that errors of the gate of the semiconductor switching element Q1 and the gate drive circuit 2 will be reduced.

[0034] Here, when the load current of the semiconductor switching element is zero or small, the turn-on speed of the semiconductor switching element generally increases. Furthermore, when the voltage applied to the gate of the semiconductor switching element at the time of turn-on increases sharply, the turn-on speed of the semiconductor switching element increases. Therefore, if the gate voltage is raised to a single level in accordance with an increase in the effective value of the load current in order to reduce a steady loss of the semiconductor switching element Q1, the voltage applied to the gate may increase sharply when the instantaneous value of the AC load current is zero or small. In this case, there is a problem that the turn-on speed of the semiconductor switching element Q1 becomes excessive, and the surge voltage and radiation noise become large.

[0035] In contrast, in the first embodiment, the gate voltage initially applied when the semiconductor switching element Q1 is turned on is set to the fixed voltage of the power supply E3. Therefore, an increase in the gate voltage of the semiconductor switching element is smooth. As a result, an increase in the turn-on speed due to an increase in the power supply output voltage of the gate drive circuit power supply E1 can be suppressed, so that an increase in the surge voltage and radiation noise can be suppressed.

[0036] In the first embodiment, the PWM controller 1 changes the power supply output voltage of the gate drive circuit power supply E1 based on a predefined change pattern. Thus, even if the load current waveform is a sine wave or the like, the power supply output voltage of the gate drive circuit power supply E1 can be appropriately changed. Note that even if the load current waveform is a sine wave or the like, there are cases where it is not necessary to appropriately change the power supply output voltage of the gate drive circuit power supply E1, and the design value of the load current of the semiconductor switching element Q1 is detected.In such a case, the PWM controller 1 may measure the duty value of the load current of the semiconductor switching element Q1, and change the power supply output voltage of the gate drive circuit power supply E1 based on the duty value instead of based on a predefined change pattern. <modifikation>

[0037] The semiconductor switching element Q1 can be, for example, an insulated-gate bipolar transistor (IGBT), a reverse-conducting IGBT (RC-IGBT), or the like. The material of the semiconductor switching element Q1 can be ordinary silicon (Si), or it can be a wide-band-gap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), or diamond. When the material of the semiconductor switching element Q1 is a wide-band-gap semiconductor, stable operation at high temperatures and high voltages is possible, and a high switching speed can be achieved.

[0038] Although the gate driver circuit 2 of Fig. 1 includes the inverter circuit INV, it is possible that the gate driver circuit 2 does not include the inverter circuit INV. For example, in a case where the first switch S1, the second switch S2, and the third switch S3 are each formed of an NPN transistor, an NPN transistor, and a PNPN transistor, as in a complementary transistor of Fig. 5, the inverter circuit INV is not necessary. In addition, the configuration of the gate driver circuit 2 is not limited to the configuration in Fig. 1 as long as the circuit output voltage in Fig. 4 can be obtained.

[0039] It should be noted that the present modification can be suitably applied to a second and subsequent embodiments described below. <Zweite Ausführungsform>

[0040] Fig. 6 is a cross-sectional view illustrating a configuration of a driving device according to a second embodiment. Hereinafter, among the components of the second embodiment, identical or similar components to those described above are denoted by identical or similar reference numerals, and different components will be mainly described.

[0041] The configuration of the driver device of Fig. 6 is similar to the configuration of the driver device of Fig. 1, in which the PWM controller 1 is replaced by a control unit 3, and the load unit 9 is replaced by an inductive load L1 and a freewheeling diode D1. The drain of the semiconductor switching element Q1 is connected to the voltage supply E2 via the inductive load L1 and the freewheeling diode D1, which are connected in parallel.

[0042] A gate drive signal used as a sample and hold (S / H) instruction and a load current detection signal indicating a sampled load current of the semiconductor switching element Q1 are input to the control unit 3 of Fig. 6 is input. The control unit 3 changes the power supply output voltage of the gate drive circuit power supply E1 based on the load current of the semiconductor switching element Q1, which is sampled when the gate drive signal is turned off.

[0043] In other words, the control unit 3 performs control to vary the power supply output voltage of the gate drive circuit power supply E1 by varying the voltage control signal based on the related information regarding the load current of the semiconductor switching element Q1. The related information mentioned here is a load current sampled when the gate drive signal is turned off.

[0044] The other configurations of the second embodiment are similar to those of the first embodiment. For example, when the gate drive signal is turned on, the delay circuit DLC performs control to supply a fixed voltage of the power supply E3 to the gate of the semiconductor switching element Q1 for a predefined period of time, and then performs control to supply a power supply output voltage of the gate drive circuit power supply E1 to the gate. <betrieb>

[0045] Fig. Fig. 7 is a diagram illustrating the operation of the control unit 3, which changes the power supply output voltage of the gate drive circuit power supply E1 under the processes of the drive device according to the second embodiment. In the process of the drive device according to the second embodiment, the process related to the circuit output voltage of the gate drive circuit 2 is similar to the process related to the circuit output voltage described with reference to Fig. 4 in the first embodiment. The following mainly describes the operation of the control unit 3, which changes the power supply output voltage of the gate drive circuit power supply E1.

[0046] When the semiconductor switching element Q1 is turned off, a load current flows back to the freewheeling diode D1, as shown by a dashed line in Fig. 7, due to the inductive load L1 in Fig. 6.

[0047] The control unit 3 samples the load current of the semiconductor switching element Q1 at times t1, t3, t5,... at which the semiconductor switching element Q1 is turned off. Subsequently, the control unit 3 changes the power supply output voltage of the gate drive circuit power supply E1 based on the sampled load current during the off periods t1 to t2, t3 to t4,... of the semiconductor switching element Q1, and then maintains the power supply output voltage until the next times t3, t5,... For example, the control unit 3 increases the power supply output voltage when the sampled load current is greater than the previous sample, and decreases the power supply output voltage when the sampled load current is smaller than the previous sample.The control unit 3 may increase or decrease the power supply output voltage of the gate drive circuit power supply E1 stepwise, or it may be proportional to the effective value of the load current. <Zusammenfassung der zweiten Ausführungsform>

[0048] According to the driving device of the second embodiment, the control unit 3 changes the power supply output voltage of the gate drive circuit power supply E1 based on the associated information related to the load current of the semiconductor switching element Q1. As a result, similar to the first embodiment, the steady loss of the semiconductor switching element Q1 can be reduced, and the error of the gate of the semiconductor switching element Q1 and the gate drive circuit 2 can be reduced. In the second embodiment, similar to the first embodiment, the gate voltage initially applied when the semiconductor switching element Q1 is turned on is set to the fixed voltage of the power supply E3, so that an increase in surge voltage and radiation noise can be suppressed similarly to the first embodiment.

[0049] In the conventional technique such as Patent Document 2, since the power supply output voltage of the gate drive circuit power supply E1 is changed while the semiconductor switching element Q1 is on, it is necessary to shorten the change so that the influence during the change does not reach the semiconductor switching element Q1.

[0050] In contrast, in the second embodiment, the control unit 3 changes the power supply output voltage of the gate drive circuit power supply E1 based on the load current of the semiconductor switching element Q1, which is sampled when the gate drive signal is turned off. According to such a configuration, since the power supply output voltage of the gate drive circuit power supply E1 can be changed during the period in which the semiconductor switching element Q1 is turned off, it is possible to suppress the influence of the change in the power supply output voltage on affecting the semiconductor switching element Q1. Furthermore, the change in the instantaneous value of the load current can be reflected to some extent in the change in the power supply output voltage of the gate drive circuit power supply E1. <Dritte Ausführungsform>

[0051] Fig. 8 is a circuit diagram illustrating a configuration of a driving device according to a third embodiment. Hereinafter, among the components according to the third embodiment, identical or similar components to those described above are denoted by identical or similar reference numerals, and different components will be mainly described.

[0052] The driver device in Fig. 8 comprises a gate driver circuit voltage supply E1, a control unit 4, a gate driver circuit 5, a first resistor RG1, and a second resistor RG2.

[0053] The driver device of Fig. 8 is connected to the gate of semiconductor switching element Q1 and controls semiconductor switching element Q1 based on the on / off switching of a gate drive signal. The drain of semiconductor switching element Q1 is connected to power supply E2 via inductive load L1 and freewheeling diode D1, which are connected in parallel.

[0054] Next, components of the driving device according to the third embodiment will be described in detail.

[0055] The gate drive circuit power supply E1 is designed to be capable of changing a power supply output voltage output from the gate drive circuit power supply E1.

[0056] Similar to the control unit 3 according to the second embodiment, the control unit 4 changes the power supply output voltage of the gate drive circuit power supply E1 based on the load current of the semiconductor switching element Q1, which is sampled when the gate drive signal is turned off. The control unit 4 of Fig. 8 can output the on-resistance switching signal to an AND circuit U1 of the gate driver circuit 5 described later.

[0057] The first resistor RG1 and the second resistor RG2 are connected between the gate of the semiconductor switching element Q1 and the gate driver circuit 5.

[0058] The gate driver circuit 5 of Fig. 8 comprises a first switch S1, a second switch S2, a third switch S3, an inverter circuit INV, which is a NOT circuit, and an AND circuit U1.

[0059] One end of the first switch S1 is connected to the gate drive circuit power supply E1, the other end of the first switch S1 is connected to the first resistor RG1, and the on / off of the first switch S1 is controlled by a gate drive signal. Consequently, the first resistor RG1 may be connected between the gate drive circuit power supply E1 and the gate of the semiconductor switching element Q1.

[0060] One end of the second switch S2 is connected to the gate drive circuit power supply E1, the other end of the second switch S2 is connected to the second resistor RG2, and the on / off of the second switch S2 is controlled by an output signal and the AND circuit U1. Consequently, the second resistor RG2 can be connected in parallel with the first resistor RG1 between the gate drive circuit power supply E1 and the gate of the semiconductor switching element Q1.

[0061] One end of the third switch S3 is connected to the reference voltage GND, the other end of the third switch S3 is connected to the resistor RG, and an on and off of the third switch S3 is controlled by a gate drive signal which is inverted by the inverter circuit INV.

[0062] The AND circuit U1 performs an AND operation based on the on-resistance switching signal from the control unit 4 and the gate drive signal, and outputs the result as an output signal of the AND circuit U1. That is, the AND circuit U1 outputs an "on" only when the on-resistance switching signal is on and the gate drive signal is on.

[0063] Hereinafter, a resistor connected to the gate of the semiconductor switching element Q1 at the time of turn-on is referred to as a turn-on gate resistor. The control unit 4 according to the third embodiment selectively performs high resistance control using the high turn-on gate resistor and low resistance control using the low turn-on gate resistor based on the load current. The operation of the control unit 4 will be described in detail later. <betrieb>

[0064] In the operation of the driving device according to the third embodiment, the operation for changing the power supply output voltage of the gate driving circuit power supply E1 is similar to the operation described with reference to Fig. 7 in the second embodiment.

[0065] In the third preferred embodiment, when the load current of the semiconductor switching element Q1 is sampled, the control unit 4 outputs when the gate drive signal is equal to or less than a threshold value TH1 in Fig. 9, an on-resistance switching signal indicating an off is output and the gate drive signal is on, the first switch S1 is turned on, and the second switch S2 and the third switch S3 are turned off. Therefore, the power supply output voltage of the gate drive circuit power supply E1 is supplied to the gate of the semiconductor switching element Q1 via the first resistor RG1. Therefore, as shown in Fig. 9 illustrates, the turn-on gate resistance when the load current is equal to or less than the threshold TH1, the first resistor RG1.

[0066] On the other hand, when the load current of the semiconductor switching element Q1, which is sampled when the gate drive signal is on, exceeds the threshold value TH1 in Fig. 9, the control unit 4 outputs an on-resistance switching signal indicating on. When the on-resistance switching signal indicating on is output and the gate drive signal is on, the first switch S1 and the second switch S2 are turned on, and the third switch S3 is turned off. Therefore, the power supply output voltage of the gate drive circuit power supply E1 is supplied to the gate of the semiconductor switching element Q1 via the first resistor RG1 and the second resistor RG2. As shown in Fig. As shown in Figure 9, when the load current exceeds the threshold TH1, the turn-on gate resistance is a parallel combined resistance (RG1 × RG2 / (RG1 + RG2)) of the first resistor RG1 and the second resistor RG2.

[0067] As described above, when the load current of the semiconductor switching element Q1, which is sampled when the gate drive signal is on, is equal to or less than the threshold TH1, high-resistance control is performed in which the turn-on gate resistance becomes the first resistor RG1. On the other hand, when the load current of the semiconductor switching element Q1, which is sampled when the gate drive signal is on, exceeds the threshold TH1, low-resistance control is performed in which the turn-on gate resistance is a parallel combination of the first resistor RG1 and the second resistor RG2.

[0068] When the load current of the semiconductor switching element Q1, which is sampled when the gate drive signal is on, is equal to or less than a threshold value TH2 which is greater than the threshold value TH1 in Fig. 9, the control unit 4 keeps the power supply output voltage of the gate drive circuit power supply E1 constant. On the other hand, when the load current of the semiconductor switching element Q1, which is sampled when the gate drive signal is on, exceeds the threshold value TH2 in Fig. 9, the control unit 4 increases the power supply output voltage of the gate drive circuit power supply E1 as the load current increases.

[0069] Fig. 10 is a diagram illustrating an operation of the driving device according to the third embodiment, and is specifically a diagram illustrating the transition of the gate voltage of the semiconductor switching element Q1 by the operation of the driving device. The dotted line indicates the circuit output voltage of the gate driving circuit 2 during high-resistance control in which the turn-on gate resistance increases, and the solid line indicates the circuit output voltage of the gate driving circuit 2 during low-resistance control in which the turn-on gate resistance decreases. When the load current of the semiconductor switching element Q1 is small, high-resistance control is performed, and the increase in the gate voltage of the semiconductor switching element becomes smooth, and the switching speed decreases.On the other hand, when the load current of the semiconductor switching element Q1 is large, the control is carried out with low resistance and the switching speed increases. <Zusammenfassung der dritten Ausführungsform>

[0070] According to the driving device of the third embodiment, the control unit 4 changes the power supply output voltage of the gate drive circuit power supply E1 based on the load current of the semiconductor switching element Q1, which is sampled when the gate drive signal is turned off. As a result, similar to the first and second embodiments, the steady loss of the semiconductor switching element Q1 can be reduced, and a gate error of the semiconductor switching element Q1 and the gate drive circuit 2 can be reduced.

[0071] Furthermore, since the power supply output voltage of the gate drive circuit power supply E1 is changed during the period in which the semiconductor switching element Q1 is off, as in the second embodiment, it is possible to suppress the influence of the change in the power supply output voltage on the semiconductor switching element Q1. Furthermore, the change in the instantaneous value of the load current can be reflected to some extent in the change in the power supply output voltage of the gate drive circuit power supply E1.

[0072] In the third embodiment, when the load current of the semiconductor switching element Q1 is equal to or lower than the threshold TH1, the turn-on gate resistance increases. Since the switching speed at the time of turn-on is reduced, surge voltage and radiation noise can be suppressed. On the other hand, when the load current of the semiconductor switching element Q1 exceeds the threshold TH1, the turn-on gate resistance decreases. Since the switching speed at the time of turn-on is increased, the switching loss during the turn-on period can be reduced.

[0073] If a configuration is implemented to reduce the turn-on speed when the load current is increased, a signal obtained by inverting the on-resistance switching signal can be used instead of the on-resistance switching signal. With such a configuration, the turn-on speed can be reduced because the on-gate resistance increases.

[0074] It should be noted that the embodiments and modifications can be freely combined, and the embodiments and modifications can be appropriately modified or omitted.

[0075] The above description is illustrative and not restrictive in all aspects. It is understood that numerous non-illustrated modifications may be adopted. List of reference symbols 1 PWM control 3, 4 Control unit DLC delay circuit E1 Gate driver circuit voltage supply E3 Power supply Q1 semiconductor switching element RG1 first resistance RG2 second resistor QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 4333802

[0002] < / betrieb> < / betrieb> < / modifikation> < / betrieb>

Claims

[1] A driving device that drives a semiconductor switching element based on an on and off of a gate driving signal, the driving device comprising: • a gate driver circuit voltage supply configured to vary an output voltage; • a power supply having a fixed voltage lower than the output voltage; • a control unit that changes the output voltage of the gate drive circuit power supply based on associated information relating to a load current of the semiconductor switching element; and • a delay circuit which, when the gate drive signal is turned on, executes control to supply the fixed voltage to a gate of the semiconductor switching element for a predefined period, and then executes control to supply the output voltage to the gate. [2] The driving device according to claim 1, wherein the related information is a change pattern of the output voltage determined in advance with respect to an effective value of the load current. [3] The driving device according to claim 1, wherein the associated information is the load current sampled when the gate driving signal is turned off. [4] A driving device that drives a semiconductor switching element based on an on and off of a gate driving signal, the driving device comprising: • a gate driver circuit voltage supply configured to vary an output voltage; • a control unit that changes the output voltage of the gate drive circuit power supply based on a load current of the semiconductor switching element, the load current being sampled when the gate drive signal is turned off; • a first resistor connectable between the gate driver circuit voltage supply and a gate of the semiconductor switching element; and • a second resistor which can be connected in parallel to the first resistor between the gate driver circuit voltage supply and the gate of the semiconductor switching element, wherein • the control unit selectively executes control for providing the output voltage of the gate drive circuit power supply to the gate via the first resistor and control for providing the output voltage of the gate drive circuit power supply to the gate via the first resistor and the second resistor based on the load current.

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