SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD

Abstract

In one embodiment, the semiconductor device (1) comprises a semiconductor body (2), a gate electrode (33) and a first electrode (31), wherein - the semiconductor body (2) comprises a first region (21) which is a source region or an emitter region, and a well region (22), the first region (21) is of a first conductivity type and the well region (22) is of a different, second conductivity type, - the well region (22) is separated from the gate electrode (33) by a gate insulator layer (4), - the first region (21) is electrically contacted by means of the first electrode (31), which is a source electrode or an emitter electrode, - at least one current limiting region (5) is located in the first region (21), and - the at least one current limiting region (5) consists of at least one electrically insulating material.

Description

[0001] A semiconductor device is provided. Furthermore, a method for manufacturing such a semiconductor device is provided.

[0002] The documents US 2017 / 0243970 A1, US 2017 / 0229535 A1 and US 2015 / 0108564 A1 relate to semiconductor devices.

[0003] One problem to be solved is to provide a semiconductor device that has an improved trade-off between conduction losses and a short circuit withstand time (SCWT).

[0004] This object is achieved, inter alia, by a semiconductor device and a method according to the independent patent claims. Exemplary developments are the subject matter of the dependent claims.

[0005] For example, the semiconductor device described herein comprises one or more current confinement regions made of an electrically insulating material and located in a source region or an emitter region. A source resistance value, R S , increased. This increase in R S should be done in such a way that the device performance during normal operation is not significantly impaired, but the short-circuit behavior is improved.

[0006] According to at least one embodiment, the semiconductor device comprises a semiconductor body, a gate electrode, and a first electrode. For example, the semiconductor body consists of a wide bandgap semiconductor material such as SiC, Ga 2 O 3or GaN. Alternatively, the semiconductor body can also be made of silicon, or Si for short. The electrodes can be made of at least one metal or of a highly doped and / or ohmically conductive semiconductor material, such as poly-Si.

[0007] According to at least one embodiment, the semiconductor body comprises a first region. For example, the first region is a source region or an emitter region.

[0008] According to at least one embodiment, the semiconductor body comprises a well region. The well region is located adjacent to the first region. This means that the first region may touch the well region and may thus be in direct physical contact with it. A channel region is part of the well region and may have the same doping concentration. During operation, electrons in the channel region flow from the source region to a drift region along a gate insulator layer. During operation of the semiconductor device, the channel region may be that part of the well region that is adjacent to the gate insulator layer.

[0009] According to at least one embodiment, the first region is of a first conductivity type and the well region is of a different second conductivity type. For example, the first conductivity type is n-type and the second conductivity type is p-type, or vice versa. Hereinafter, the first conductivity type is referred to as n-type; thus, if the first conductivity type is p-type instead, the doping ratios described below must be reversed.

[0010] According to at least one embodiment, the well region is adjacent to the gate electrode and separated from the gate electrode by the gate insulator layer. The gate insulator layer may be located directly between the gate electrode and the well region.

[0011] According to at least one embodiment, the first region is electrically contacted by means of the first electrode, which is, for example, a source electrode or an emitter electrode. Therefore, the first electrode can contact the semiconductor body at least at the first region. For example, the well is also electrically contacted by means of the first electrode or otherwise by a separate electrode.

[0012] According to at least one embodiment, one or more current limiting regions are located in the first region. The at least one current limiting region can correspond to a recess in the at least one associated first region. That is, the at least one current limiting region can correspond to at least one recess formed in the at least one associated first region.

[0013] Thus, the at least one current-limiting region consists of at least one electrically insulating material. For example, a difference in a specific electrical conductivity of a material of the first region and the at least one electrically insulating material of the current-limiting region is at least a factor of 10 2 or at least a factor of 10 3 or at least a factor of 10 4 , so that the current-limiting region does not conduct a significant amount of current compared to the first region. For example, the at least one electrically insulating material is a solid material, for example, at least at temperatures between 250 K and 400 K.

[0014] For example, the at least one electrically insulating material may be a metal oxide, a semiconductor oxide, a metal nitride, or a semiconductor nitride. For example, the at least one current confinement region may include one or more of the following materials: SiO 2 , Si 3 N 4 , Al 2 O 3 , Y 2 O 3 , ZrO 2 , HfO 2 , La 2 O 3 , Ta 2 O 5 , TiO 2 . The same materials can be used for the gate insulator layer, which can also be called gate oxide.

[0015] In at least one embodiment, the semiconductor device comprises a semiconductor body, a gate electrode and a first electrode, wherein - the semiconductor body comprises a first region and a well region located adjacent to the first region, the first region being of a first conductivity type and the well region being of a different, second conductivity type, - the well region is located next to the gate electrode and is separated from the gate electrode by a gate insulator layer, - the first region is electrically contacted by means of the first electrode, - there is at least one current limitation area in the first area, and - at least one current limiting region consists of at least one electrically insulating material.

[0016] For example, this application describes a metal-insulator-semiconductor field-effect transistor (MISFET) or a metal-oxide-semiconductor field-effect transistor (MOSFET) based, for example, on silicon carbide (SiC) material. To improve the trade-off between conduction losses and short-circuit resistance time, at least one recess is etched in the source or emitter region and filled with the electrically insulating material.

[0017] SiC MOSFETs are currently available from several manufacturers. Offered in either planar or trench cell designs, SiC MOSFETs provide competitive static losses, fast dynamic performance, and sufficient reliability. In terms of fault handling capability, SiC MOSFETs still lag behind the typical industry standard values ​​of approximately 10 µs demonstrated by their Si counterparts. This is typically associated with the strong trade-off between conduction losses and short-circuit resistance time (SCWT). One approach to an optimal trade-off between the SCWT and a device on-state resistance (R) DS,ON , is to use a slightly increased source resistance value, R S , to use.

[0018] Accordingly, for example, a SiC MOSFET is described here in which a part of the source region is etched away and filled with the electrically insulating material, such as SiO 2, is filled. By removing a part of the implanted n + of the source region, the total source area is reduced, whereby the source resistance R S is increased.

[0019] Therefore, with the proposed at least one current confinement region, the total source area is reduced and the channel-to-contact path of the carriers is increased. Both effects lead to an increased value of the source resistance R S . An increase in the value of R S When a short circuit occurs, SC for short, the saturation current I is reduced SAT A depth of the etched region d and its length L could be properly designed to achieve the desired effect on the SC current, while its influence during conduction under nominal conditions, i.e., on the total resistance between source and drain in the on-state, also known as R DS,ON remains negligible.

[0020] According to a further embodiment, the semiconductor device is a power device. This means, for example, that the semiconductor device is configured for a maximum current through the well region of at least 10 A or at least 50 A. Optionally, the maximum current is at most 500 A or at most 1.5 kA. Alternatively or additionally, the semiconductor device is configured for a maximum voltage of at least 0.6 kV or at least 1.2 kV between source and drain or between emitter and collector. Optionally, the maximum voltage can be at most 6.5 kV.

[0021] According to at least one embodiment, both the gate electrode and the first electrode overlap with the first region, as seen in a top view of the semiconductor body. Here and below, "top view" may refer to a view perpendicular to a top side of the semiconductor body on which the first electrode is applied and at which the first region is located.

[0022] According to at least one embodiment, the at least one current confinement region, as seen in a plan view of the semiconductor body, is remote from the gate electrode and / or from the first electrode. For example, the at least one current confinement region, as seen in a plan view, is remote from the gate electrode and from the first electrode.

[0023] According to at least one embodiment, the at least one current limiting region is positioned mirror-symmetrically, for example, in the associated first region within the manufacturing tolerances. This means that, viewed in a plan view of the semiconductor body, the first region, together with the at least one current limiting region, has a mirror-symmetric axis of symmetry, for example with regard to the shape of the first region and the at least one current limiting region. This mirror-symmetric axis of symmetry can, viewed in a plan view, run parallel to the gate electrode and / or the first electrode and / or be arranged between the gate electrode and the first electrode. Otherwise, non-mirror-symmetric arrangements of the at least one current limiting region in the associated first region, viewed in a plan view, are also possible.

[0024] According to at least one embodiment, the first region, viewed in a plan view of the semiconductor body, extends completely between the at least one current confinement region and the first electrode, as well as between the at least one current confinement region and the gate electrode. In other words, a portion of the first region is located between the at least one current confinement region and the respective electrode, for example, at the top side of the semiconductor body and viewed in a plan view of the semiconductor body.

[0025] Alternatively, the at least one current confinement region may be partially covered by the first electrode and / or by the gate electrode, or the at least one current confinement region may touch the first electrode and / or the gate electrode in view of the semiconductor body.

[0026] According to at least one embodiment, the at least one current confinement region is located between the first electrode and the gate electrode. For example, the entire at least one current confinement region is placed between the electrodes.

[0027] According to at least one embodiment, as viewed in the cross-section of the semiconductor body, the first region extends entirely around the at least one current confinement region in the direction of the well region. This may mean that the first region is embedded in the well region and / or that the at least one current confinement region is embedded in the first region. For example, as viewed in cross-section, a part of the first region is present entirely around the at least one current confinement region, such that no straight connecting line exists within the semiconductor body from the at least one current confinement region to the well region without traversing the first region.

[0028] The term “cross-section of the semiconductor body” may refer to a cross-section through the first region, through the current confinement region or through at least one of the current confinement regions and through the gate electrode, for example in a direction perpendicular to the top side of the semiconductor body and / or perpendicular to a direction of the main extension of the gate electrode.

[0029] According to at least one embodiment, a volume of the at least one current-limiting region is at least 5%, or at least 10%, or at least 20%, or at least 40%, or at least 60% of a total volume of the at least one current-limiting region together with the first region. Alternatively or additionally, this percentage is at most 95%, or at most 85%, or at most 75%. For example, this percentage is between 40% and 85% inclusive.

[0030] For example, due to the at least one current confinement region, an electrical resistance through the first region between the first electrode and the channel region is increased by a factor of at least 1.1 or by a factor of at least 1.5 or by a factor of at least 2 or by a factor of at least 5. Alternatively or additionally, this factor is at most 100 or at most 25 or at most 15 or at most 10 or at most 5. For example, this factor is between 2 and 10 inclusive. The electrical resistance through the first region may relate to a normal operating current for which the semiconductor device is designed in an on-state. These factors relate to a comparison with a device that does not have at least one current confinement region in the first region within the manufacturing tolerances, but is otherwise structurally identical.

[0031] By means of the at least one current confinement region, a cross section for the current flow within the first region from the first electrode to the well region next to the gate insulator layer, that is to say to the channel region through the at least one current confinement region is reduced by a factor of at least 1.1 or by a factor of at least 1.5 or by a factor of at least 2 or by a factor of at least 5. Alternatively or additionally, this factor is at most 100 or at most 15 or at most 10 or at most 5 or at most 2. For example, this factor is between 2 and 10 inclusive.

[0032] According to at least one embodiment, the at least one current-limiting region is at least one recess in the first region. This means that the at least one electrically insulating material is located in at least one recess of the first region. A one-to-one assignment can exist between these recesses and the current-limiting regions and / or the at least one electrically insulating material if more than one recess and more than one current-limiting region are present. The at least one electrically insulating material can completely fill the assigned recess. It is possible for more than one electrically insulating material to be present per recess.

[0033] According to at least one embodiment, the at least one electrically insulating material terminates in alignment with the first region. Thus, the top surface may be planar across the first region and the at least one current confinement region.

[0034] In other words, the first region and the electrically insulating material form a flat surface and end in alignment with each other.

[0035] According to at least one embodiment, the semiconductor body further comprises a drift region. The drift region is of the first conductivity type and has, for example, a lower maximum doping concentration compared to the first region and the well region.

[0036] According to at least one embodiment, the semiconductor body further comprises a second region. For example, the second region is a drain region or a collector region. In the case of a drain region, the second region is also of the first conductivity type, but, for example, with a maximum doping concentration that is higher than in the drift region. In the case of a collector region, the second region is of the second conductivity type.

[0037] According to at least one embodiment, the drift region is located between the well region and the second region. Accordingly, the first region is separated from the second region by the well region.

[0038] According to at least one embodiment, the semiconductor device further comprises a second electrode, which is, for example, a collector electrode or a drain electrode. The second electrode can be located on a side of the second region facing away from the drift region and / or the first region.

[0039] According to at least one embodiment, the gate electrode and the first electrode each extend along a straight line, as seen in a plan view of the semiconductor body. If a plurality of the first electrodes and / or the gate electrodes are present, there may be a plurality of straight lines along which the first electrodes and / or the gate electrodes extend.

[0040] According to at least one embodiment, the first region extends parallel to the gate electrode and / or the first electrode. Therefore, the semiconductor device may be of a stripe design comprising a plurality of straight stripes of the gate electrodes and / or the first electrodes.

[0041] According to at least one embodiment, the gate electrode and / or the first electrode, viewed in a plan view of the semiconductor body, each comprise a plurality of subsections. For example, the subsections correspond to cell units. The cell units can be arranged, for example, in a regular two-dimensional grid. The semiconductor body can extend continuously over all cell units and comprise a correspondingly arranged plurality of the first regions. Therefore, the semiconductor device can be of a cell design comprising a plurality of cells, each having a first electrode, a corresponding gate electrode, and a corresponding first region with the at least one current confinement region.

[0042] According to at least one embodiment, the semiconductor device has a planar design. That is, the gate insulation layer and the gate electrode are applied to a planar portion of the top surface of the semiconductor body. The first region and the at least one current confinement region may be located on the top surface.

[0043] According to at least one embodiment, the semiconductor device has a trench design. Thus, the gate insulation layer and the gate electrode are partially or completely arranged in a trench in the semiconductor body. For example, a depth of the trench exceeds a depth of the well region, starting from the top side of the semiconductor body. In this case, too, the first region and the at least one current confinement region can be located at the top side.

[0044] According to at least one embodiment, the current limiting region is present in the first region. In the case of multiple first regions, a one-to-one mapping can be made between the first regions and the current limiting region.

[0045] Otherwise, there are multiple current confinement regions in the first region. In the case of multiple first regions, multiple current confinement regions may be present per first region. The current confinement regions of each of the first regions, or of the precisely one first region, are spaced apart from one another as seen in a plan view of the semiconductor body.

[0046] When viewed from above on the semiconductor body, the current limiting region or each of the current limiting regions can be completely surrounded by the respectively associated first region.

[0047] According to at least one embodiment, the current-limiting regions are arranged along one strip or along multiple strips. Additionally, the current-limiting regions, viewed in plan view, are optionally arranged along one row or along multiple rows, wherein the strips and rows may be oriented perpendicular to one another. In the case of multiple first regions, this may apply to each of the first regions, wherein each of the first regions is associated with multiple current-limiting regions.

[0048] According to at least one embodiment, the current confinement regions, viewed in a top view of the semiconductor body, are shaped as at least one of the following: triangle, square, rectangle, hexagon, or circle. Viewed in a top view, all current confinement regions may have the same shape and / or the same surface area. Otherwise, differently shaped and / or dimensioned current confinement regions may also be combined with one another per first region.

[0049] Additionally, a method for manufacturing the semiconductor device is provided. By means of the method, a semiconductor device is manufactured as specified in connection with at least one of the above-mentioned embodiments. Thus, features disclosed for the semiconductor device are also disclosed for the method, and vice versa.

[0050] In at least one embodiment, the manufacturing method is for manufacturing a semiconductor device. The method comprises, for example, in the order given: - Providing the semiconductor body, - forming the first region and the well region in the semiconductor body, - etching at least one recess into the first region and filling the at least one recess with the at least one electrically insulating material, so that the at least one current limiting region is produced, - Applying the gate insulator layer to the semiconductor body, and - Applying the gate electrode and the first electrode to the semiconductor.

[0051] According to at least one embodiment, the at least one recess is etched into the semiconductor body, and then at least a portion of a doping of the first region is applied through the at least one recess into the semiconductor body. This means that by forming the at least one recess, at least one deeper region of the semiconductor body is exposed, and this at least one deeper region is then provided with a dopant for the first region. Thus, a relatively deep doping can be achieved, for example, with moderate ion energies during ion implantation or with moderate time and / or temperature during diffusion doping.

[0052] According to at least one embodiment, at least a portion of the doping for the first region is applied between the etching of the at least one recess and the application of the at least one electrically insulating material into the at least one recess. Accordingly, the step of forming the at least one current confinement region can be divided into substeps that are not necessarily consecutive steps.

[0053] According to at least one embodiment, the method further comprises forming at least one plug region in the semiconductor body. The at least one plug region is of the second conductivity type and has a maximum doping concentration that is higher than a maximum doping concentration of the well region. The at least one plug region serves to electrically contact the well region, for example, by means of the first electrode.

[0054] According to at least one embodiment, the first region extends deeper into the semiconductor body than the at least one plug region.

[0055] According to at least one embodiment, the creation of the first region comprises two different doping steps, so that, viewed in cross-section, a doping profile of the first region is step-like. This means that the first region can widen toward the top side.

[0056] A semiconductor device and a method described herein are explained in more detail below using exemplary embodiments with reference to the drawings. In the individual figures, identical elements are designated by the same reference numerals. However, the relationships between the elements are not shown to scale; rather, individual elements may be exaggerated to facilitate understanding.

[0057] The figures show: Fig. 1 is a schematic perspective sectional view of an embodiment of a semiconductor device described herein, Fig. 2 to 4 are schematic sectional views of embodiments of semiconductor devices described here, Fig. 5 and Fig. 6 schematic perspective sectional views of embodiments of semiconductor devices described here, Fig. 7 is a schematic sectional view of an embodiment of a semiconductor device described herein, Fig. 8 to 11 are schematic diagrams of electrical characteristics of simulations of semiconductor devices described here in comparison with corresponding semiconductor devices that do not have the at least one current limiting region, Fig. 12 is a schematic block diagram of an embodiment of a method for manufacturing semiconductor devices described herein, and Fig. 13 and Fig. 14 schematic plan views of embodiments of semiconductor devices described herein.

[0058] Fig. 1 illustrates an embodiment of a semiconductor device 1. The semiconductor device 1 comprises a semiconductor body 2, which is made of SiC, for example. The semiconductor body 2 includes a first region 21, a well region 22, and a drift region 23. A plug region 25 is provided for electrically contacting the well region 22.

[0059] Furthermore, the semiconductor device 1 comprises a gate electrode 33, which is separated from the semiconductor body 2 by a gate insulator layer 4. Furthermore, a first electrode 31 is present, which electrically contacts the first region 21 and the plug region 25. The gate insulator layer 4 and the first electrode 31 are located on a top side 20 of the semiconductor body 2. The top side 20 is planar. The gate electrode 33 and the first electrode 31 can each extend along a straight line along a direction perpendicular to the Fig. 1 illustrated cross-section.

[0060] For example, the first region 21 and the drift region 23 are n-doped, and the well region 22 and the plug region 25 are p-doped. If the semiconductor device 1 is an insulated-gate bipolar transistor (IGBT) or a reverse-conducting insulated-gate bipolar transistor (RC-IGBT), the first region 21 is an emitter region and the first electrode 31 is an emitter electrode. If the semiconductor device 1 is a junction field-effect transistor (JFET), a metal-insulator-semiconductor field-effect transistor (MISFET), or a metal-oxide-semiconductor field-effect transistor (MOSFET), the first region 21 is a source region and the first electrode 31 is a source electrode.

[0061] In the first region 21 there is a current limiting region 5. The current limiting region 5 consists of an electrically insulating material, for example SiO 2. The current limiting region 5 runs along a straight line parallel to the gate electrode 33 and the first electrode 31. The current limiting region 5, like the first region 21, is located directly on the top side 20.

[0062] A depth of the first region 21 into the semiconductor body 2 exceeds a depth of the current confinement region 5 into the semiconductor body 2, starting from the top side 20. In the direction of the well region 22, in which the first region 21 is embedded, the first region 21, viewed in cross section, is located around the current confinement region 5.

[0063] Optionally, the at least one current confinement region 5 is arranged mirror-symmetrically in the first region 21, both in plan view and in cross-section. For example, viewed in plan view of the top side 20, the current confinement region 5 is arranged symmetrically in the first region 21 and between the electrodes 31, 33. Therefore, there may be a mirror symmetry line M with respect to the current confinement region 5 and the first region 21.

[0064] Thus, Fig. 1 shows the basic concept of the proposed semiconductor device 1, in which a recess is etched into the first region 21. The etched and filled recess can have different shapes and depths and can be arranged along the direction perpendicular to the cross section of Fig. 1 be even or uneven, see also Fig. 2 to 7 below.

[0065] With the proposed at least one current confinement region 5, the total source area or emitter area is reduced, and the channel-to-contact path of the carriers is increased. Both effects lead to an increased value of the source resistance R S or corresponding to an emitter resistance. An increase in the value of R S will lead to a reduction of the saturation current I SAT during a short-circuit condition. A depth d of the current confinement region 5 and its length L parallel to the top surface 20 and along the cross section of Fig. 1 could be properly designed to achieve the desired effect on the short-circuit current, while limiting its influence during conduction under nominal conditions, for example, on the total R DS,ON , remains negligible.

[0066] The semiconductor device 1 of Fig. 1 is of planar design. In contrast, the semiconductor device 1 is of Fig. 2 of a trench design. Thus, the gate electrode 33 and the gate insulator layer 4 are at least partially located in a trench in the semiconductor body 2. Accordingly, the top side 20, in contrast to what is shown in Fig. 1, it is not planar because it is penetrated by the trench. For example, the gate electrode 33, starting from the top side 20, extends deeper into the semiconductor body 2 than the well region 22.

[0067] Furthermore, in Fig. 2 shows that there are several first regions 21 and thus current limiting regions 5, which are arranged symmetrically with respect to the gate electrode 33. Several of the Fig. 2 illustrated units may be present side by side, so that several strips of the gate electrode 33 and the first electrode 31, which are perpendicular to the projection plane of Fig. 2 may be present.

[0068] This symmetrical arrangement of Fig. 2, see also Fig. 13, and / or the trench design of Fig. 2 can of course also be applied analogously to all other embodiments.

[0069] The current limitation areas 5, one per first area 21, of Fig. 2 have the same design as in Fig. 1, namely a cuboid-shaped depression. According to Fig. 2, the trough has sharp edges and corners; according to Fig. 1, the recess has rounded edges and corners. Both designs are possible in all embodiments depending on the manufacturing process of the at least one current confinement region 5.

[0070] In addition, Fig. 2 that there is a second electrode 32 and the semiconductor body 2 comprises a second region 24. For example, the second region 24 is a substrate on which the other regions 23, 22, 21, 25 are formed by growth and / or doping, such as ion implantation. In the case of an IGBT or RC-IGBT, the second electrode 32 is a collector electrode, and the second region is a collector region that is of the same doping type as the well region. In the case of a MOSFET or MISFET, the second electrode 32 is a drain electrode, and the second region is a drain region that is of the same doping type as the first region. The same applies to all other embodiments of the semiconductor device 1. For example, in Fig. 1 the second region 24 and the second electrode 32 analogous to Fig. 2 directly on a side of the drift area 23 facing away from the top side 20.

[0071] Furthermore, the plug area 25 extends according to Fig. 2, starting from the top side 20, deeper into the semiconductor body 2 than the first region 21. Otherwise, see Fig. 1, the plug region 25 may have the same depth as the first region 21 or may also be shallower or deeper than the first region 21. Both possibilities can apply to all embodiments.

[0072] As in Fig. 1 is also in Fig. 2 the at least one current confinement region 5 per first region 21 is removed from the first electrode 31, from the gate electrode 33 and from the gate insulator layer 4.

[0073] For example, maximum doping concentrations of the first region 21, the second region 24 and the at least one plug region 25 are at least 1 × 10 18 cm -3 or at least 5 × 10 18 cm -3 or at least 1 × 10 19 cm -3 and / or a maximum of 5 × 10 20 cm-3 or at most 2 × 10 20 cm -3 or at most 1 × 10 20 cm -3 . Furthermore, a maximum doping concentration of the well region 22 and thus of a channel region next to the gate insulator layer 4 can be at least 5 × 10 16 cm -3 or at least 1 × 10 17 cm -3 and / or a maximum of 5 × 10 19 cm -3 or at most 5 × 10 18 cm -3 Depending on the voltage class of the semiconductor device 1, a maximum doping concentration of the drift region 23 can be at least 1 × 10 11 cm -3 or at least 1 × 10 12 cm -3 or at least 1 × 10 13 cm 3 and / or at most 1 × 10 17 cm -3 or at most 5 × 10 16 cm -3 or at most 1 × 10 16 cm -3For example, the thickness of the gate insulator layer 4 is between 10 nm and 250 nm or between 80 nm and 150 nm. These parameters can also apply individually or jointly to all other embodiments.

[0074] Otherwise, this may Fig. 1 What has been said also applies to Fig. 2 apply and vice versa.

[0075] In the Fig. 3 and Fig. 4 there are, as in Fig. 1, one current limiting region 5 per first region 21. The current limiting region 5 can be arranged mirror-symmetrically in the first region 25, wherein the mirror symmetry axis runs perpendicular to the upper side 20.

[0076] In contrast to the Fig. 1 Shown extends according to the Fig. 3 and Fig. 4, the current confinement region 5 extends beyond the gate insulator layer 4 and the gate electrode 33. Such an arrangement is also possible in all other embodiments. Otherwise, in contrast to the Fig. 3 and Fig. 4, the current confinement region 5 may not be positioned mirror-symmetrically in the first region 21, so that the current confinement region 5 ends away from the gate insulator layer 4 and thus cannot extend beyond the gate electrode 33. This is also possible in all other embodiments.

[0077] According to Fig. 3, the current confinement region 5 is formed as a shallow depression in the first region 21, which is also formed as a depression. The depth d of the current confinement region 5 is, for example, between 10% and 90% or between 40% and 80% of a depth D of the first region 21. The first region 21 and the plug region 25 can, for example, have the same depth within manufacturing tolerances. For example, the depth D of the first region 21 is at least 0.1 µm and / or at most 2 µm.

[0078] According to Fig. 4, the current confinement region 5 is formed as a deep depression in the first region 21, which is formed as two depressions one above the other, wherein the depression next to the top side 20 has a greater extension parallel to the projection plane of Fig. 4. In this case too, the maximum depth d of the current confinement region 5 can be between 10% and 90% or between 40% and 80% of the total depth D of the entire first region 21 formed from the two wells. Due to the design with two stacked wells, the first region 21 can extend deeper into the semiconductor body 2 than the plug region 25. It is possible, for example, within manufacturing tolerances, for the plug region 25 to have the same depth as the well of the first region 21 adjacent to the top side 20. For example, the depth D of the first region 21 is at least 0.2 µm and / or at most 4 µm.

[0079] For example, first the well next to the top side 20 is formed by appropriate doping, and then the recess for the current confinement region 5 is formed, and then the doping for the well remote from the top side 20 is provided by the recess before the electrically insulating material is applied. Therefore, the well of Fig. 4, seen in cross-section, has a stepped design. Otherwise, a deep trough with a rectangular shape with rounded corners, as in Fig. 3, also in the configuration of Fig. 4 possible.

[0080] Both designs with a flat or a deep first area 21, as in the Fig. 3 and Fig. 4 are also possible in all other embodiments.

[0081] For example, the length L of the current limiting region 5 is between 10% and 90% or between 40% and 80% or between 50% and 70% of a width B of the first region 21. This is also possible in all other embodiments.

[0082] Otherwise, this can be for the Fig. 1 and Fig. 2 What has been said also applies to the Fig. 3 and Fig. 4 apply and vice versa.

[0083] According to the Fig. 5 to 7, there are several current limiting areas 5 per first area 21. As for the parameters d, D, B, L, as stated above for the case of a single current limiting area 5 per first area 21, the same applies to the case for several current limiting areas 5 per first area 21, where L corresponds to a total width of all respective current limiting areas 5, compare for example Fig. 6. Due to the multiple current limiting regions 5, there are more design parameters to achieve an optimized first region.

[0084] In case of only one current confinement region 5 in the direction perpendicular to the gate electrode 33 and / or the first electrode 31, see Fig. 5, the total width L is the same as a width W of a single, island-like current confinement area 5, as in Fig. 4 is illustrated.

[0085] According to Fig. However, a strip of subsequent current-limiting regions 5 is provided, extending parallel to the electrodes 31, 33. Viewed in plan view, the current-limiting regions 5 are rectangular or square, optionally with rounded corners, each with a width W and a longitudinal extension V. For example, V is between 0.5 L and 100 L, or between 0.5 L and 10 L, or between 0.7 L and 5 L.

[0086] For example, a distance Zs between adjacent current limiting areas 5 along the strip is between 10% and 75% or between 10% and 40% of the width W and / or the longitudinal extent V. The individual current limiting areas 5 in the strip can be equidistant or, as shown in Fig. Figure 5, arranged at different distances from each other. These aspects can also apply to all other embodiments, individually or jointly.

[0087] Unlike shown, the current limiting areas 5, when viewed in plan view, do not have to have a square shape, but can, when viewed in plan view, also have a rectangular, hexagonal, regular or irregular polygonal or circular shape. The same applies to all other embodiments.

[0088] According to the Fig. 5 to 7, all current-limiting regions 5 per first region 21 have the same shape. This is not absolutely necessary. This means that differently shaped current-limiting regions 5 can be combined within a first region 21.

[0089] There may be N strips of current confinement regions 5 between the electrodes 31, 33, where N is a natural number greater than or equal to two. For example, N is at most ten or at most four. According to the example of Fig. 6, N is two. For example, 0.1 B / N ≤ W ≤ 0.99 B / N or 0.4 B / N ≤ W ≤ 0.95 B / N or 0.7 B / N ≤ W ≤ 0.90 B / N. Alternatively or additionally, a distance Zt between adjacent current confinement regions 5 in a transverse direction perpendicular to the strips is, for example, between 10% and 75% or between 10% and 40% of the linear extent V. Alternatively or additionally, for example, 0.1 B / N ≤ V ≤ 100 B / N or 0.4 B / N ≤ V ≤ 10 B / N or 0.7 B / N ≤ V ≤ 5 B / N. The current limiting regions 5 can be arranged equidistantly parallel and perpendicular to the electrodes 31, 33.

[0090] As in Fig. As shown in Figure 6, all N strips have the same number of current confinement regions 5, so that there are K current confinement regions 5 adjacent to each other in a direction parallel to the strips. Consequently, a regular array of N × K current confinement regions 5 is formed, and all current confinement regions 5 are identically shaped.

[0091] However, this is not required. This means that current-limiting regions 5 of different shapes and sizes can be combined with one another, and there can be different numbers K of current-limiting regions 5 per strip and / or different numbers N of current-limiting regions 5 in the direction parallel to the width L. For example, current-limiting regions 5 of different widths W are present, so that parallel to the direction along the width L, there can be rows with a single wide current-limiting region 5, which, for example, alternate with rows with several narrower current-limiting regions 5.

[0092] In Fig. 7 illustrates that N is equal to three. Optionally, the stripe furthest from the first electrode 31 extends beyond the gate insulator layer 4. Unlike in Fig. 7, however, as seen in the top view of the top side 20, for example, all stripes may be removed from the gate electrode 33.

[0093] Each of the stripes of Fig. 7 can, as in Fig. 5 and Fig. 6, consist of several current limitation areas 5, or it is, as in Fig. 1 to 4, only a single current-limiting region 5 is present per strip. The same applies to all other embodiments.

[0094] The current limitation areas 5 of the Fig. 5 to 7 are of flat design, see for example Fig. 3 above. It is also possible that all or some of the current confinement regions 5 per first region 21 have the deep design, as in connection with Fig. 4 is shown.

[0095] Otherwise, this can be for the Fig. 1 to 4 also applies to the Fig. 5 to 7 apply and vice versa.

[0096] The Fig. 8 to 11 show a simulated isothermal output J D vs. V DS at a gate-source voltage V GS = 15 V and at a temperature of 300 K, and the electrothermal short-circuit waveforms at a drain-source voltage V DS = 600 V and at V GS,Swing = -5 V / +15V for a semiconductor device 1, E1 of Fig. 1 compared to a corresponding reference MOSFET design 9 without any current limiting region, see Fig. 8 and Fig. 9. In the Fig. 10 and Fig. 11 shows corresponding data for two semiconductor devices 1, E2, E3 with a deep current confinement region 5, as in Fig. 4. In the device E1, the Fig. 1, the quotient d / D of the depth d of the current limiting region 5 and the depth D of the first region 21 is 0.65. The devices E2 and E3, the Fig. 4, have quotients d / D of 1.40 and 2.00 respectively, where D refers to the depth of the first area 21 of Fig. 1. The quotient L / B of the length L of the current limiting region 5 and the width B of the first region 21 is 0.5.

[0097] It should be noted that the achieved reduction of a maximum saturation current I SAT,Peak during the short circuit is greater than the increase in resistance in the on state, R DS,ON . Since the energy to which the device is exposed during the short circuit is directly related to the maximum value of I SAT related, the semiconductor devices 1 described here improve the short-circuit resistance time without significantly affecting the conduction losses.

[0098] In Fig. 12 illustrates a method for manufacturing the semiconductor devices 1. In a method step S1, the semiconductor body 2 is provided. For example, the semiconductor body 2 provides the drift region 23. Then, in a method step S2, the first region 21 and the well region 22 are formed in the semiconductor body 2 and the plug region 25.

[0099] Next, in step S3, at least one recess is etched into the first region 21, and the at least one recess is filled with the at least one electrically insulating material, so that the at least one current confinement region 5 per first region 21 is created.

[0100] Then, in step S4, the gate insulator layer 4 is applied, followed by step S5 in which the gate electrode 33 and the first electrode 31 are applied to the semiconductor body 2 and optionally also the second electrode 32.

[0101] The process steps do not necessarily have to be performed in the specified order. Furthermore, it is possible that the process steps can be intermixed; for example, some of the electrodes 31, 32, 33 can be applied before etching, and some of the electrodes 31, 32, 33 can be applied after etching.

[0102] In Fig. Figure 13 shows an example of the semiconductor device 1 in a top view. It can be seen that the strip of the gate electrode 33 is located, for example, symmetrically between two strips of one half of the first electrode 31 and thus between two strips of the first region 21 with the current confinement region 5. The structure in Fig. 13 corresponds to a cell unit that can be multiplied so that several of the cell units can be arranged next to each other.

[0103] This stripe design can also be applied analogously to the designs of the Fig. 1 and 3 to 7 are applied; in Fig. 2 this type of symmetrical design is already shown.

[0104] Otherwise, this can be for the Fig. 1 to 12 also applies to the Fig. 13 apply and vice versa.

[0105] Furthermore, see Fig. 14, the semiconductor device 1, viewed in plan view, can also be of a cell design, so that a rectangular or square cell unit can be created. For example, the first electrode 31 is located in the center of the cell unit, surrounded by the gate electrode 33 in a frame-like manner. Such cell units can be arranged two-dimensionally, so that the semiconductor device 1 can comprise a large number of such cell units.

[0106] Otherwise, this may Fig. 13 What has been said also applies to Fig. 14 apply and vice versa.

[0107] Unless otherwise stated, the components shown in the figures follow one another directly above the other in the order shown, by way of example. Components that do not touch in the figures are spaced apart by way of example. If lines are drawn parallel to each other, the corresponding surfaces may be aligned parallel to each other. Likewise, unless otherwise stated, the relative positions of the drawn components are correctly represented in the figures.

[0108] The invention described here is not limited by the description based on the exemplary embodiments. Rather, the invention encompasses any novel feature as well as any combination of features, including, in particular, any combination of features in the patent claims, even if this feature or combination itself is not explicitly stated in the patent claims or exemplary embodiments. List of reference symbols 1 semiconductor device 2 semiconductor bodies 20 Top of the semiconductor body 21 first area (source area or emitter area) 22 Bath area 23 Drift area 24 second area (drain area or collector area) 25 Plug area 31 first electrode (source electrode or emitter electrode) 32 second electrode (drain electrode or collector electrode) 33 Gate electrode 4 Gate insulator layer 5 Current limitation area 9 Comparative example of a semiconductor device B Width of the first area d Depth of the current confinement area D Depth of the first area E1 first example of the semiconductor device E2 first example of the semiconductor device E3 first example of the semiconductor device L Length of the current limitation area M mirror symmetry line S Process step T time in µs J D Current density in the drain region in A / cm 2 V DS Voltage between the drain electrode and the source electrode in V V Longitudinal extension of the current limitation areas W Width of an island-like current limitation area ZS Distance between current limiting areas along a strip ZT Distance between current limitation areas in transverse direction QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 2017 / 0243970 A1

[0002] US 2017 / 0229535 A1

[0002] US 2015 / 0108564 A1

[0002]

Claims

[1] Semiconductor device (1) comprising a semiconductor body (2), a gate electrode (33) and a first electrode (31), wherein - the semiconductor body (2) comprises a first region (21) which is a source region or an emitter region, and a well region (22) which is located adjacent to the first region (21), the first region (21) is of a first conductivity type and the well region (22) is of a different, second conductivity type, - the well region (22) is located next to the gate electrode (33) and is separated from the gate electrode (33) by a gate insulator layer (4), - the first region (21) is electrically contacted by means of the first electrode (31), which is a source electrode or an emitter electrode, - at least one current limiting region (5) is located in the first region (21), and - the at least one current limiting region (5) consists of at least one electrically insulating material. [2] Semiconductor device (1) according to the preceding claim, wherein, as seen in the plan view of the semiconductor body (2), the gate electrode (33) and the first electrode (31) overlap with the first region (21) and the at least one current limiting region (5) is remote from the gate electrode (33) and from the first electrode (31). [3] Semiconductor device (1) according to one of the preceding claims, wherein, as seen in the plan view of the semiconductor body (2), the first region (21) extends completely between the at least one current limiting region (5) and the first electrode (31) and between the at least one current limiting region (5) and the gate electrode (33), the at least one current limiting region (5) is located between the first electrode (31) and the gate electrode (33). [4] Semiconductor device (1) according to one of the preceding claims, wherein, viewed in the cross section of the semiconductor body (2) through the first region (21) and through the gate electrode (33), the first region (21) extends completely around the at least one current confinement region (5) in the direction of the well region (22), so that the first region (21) is embedded in the well region (22) and so that the at least one current confinement region (5) is embedded in the first region (21). [5] Semiconductor device (1) according to one of the preceding claims, wherein a volume of the at least one current confinement region (5) is at least 10% and at most 95% of a total volume of the at least one current confinement region (5) together with the first region (21). [6] Semiconductor device (1) according to one of the preceding claims, wherein the at least one current limiting region (5) consists of a metal oxide or a semiconductor oxide, wherein the at least one current limiting region (5) is at least one recess in the first region (21) and the at least one electrically insulating material fills the at least one recess, and wherein the at least one electrically insulating material ends in alignment with the first region (21). [7] Semiconductor device (1) according to one of the preceding claims, wherein the semiconductor body (2) further comprises a drift region (23) which is of the first conductivity type and also comprises a second region (24) which is a drain region or a collector region, wherein the drift region is located between the well region (22) and the second region (24), wherein the semiconductor device (1) further comprises a second electrode (32) which is a collector electrode or a drain electrode, the second electrode (32) is located on a side of the second region (24) facing away from the drift region (23), and wherein the semiconductor body (2) consists of SiC. [8] Semiconductor device (1) according to one of the preceding claims, wherein, as seen in the plan view of the semiconductor body (2), the gate electrode (33) and the first electrode (31) each extend along a straight line, the first region (21) extends parallel to the gate electrode (33) and the first electrode (31), or wherein, as seen in plan view of the semiconductor body (2), the gate electrode (33) and the first electrode (31) each comprise a plurality of subsections arranged along at least one arrangement line, the first region (21) extending between adjacent subsections of the gate electrode (33) and the first electrode (31). [9] Semiconductor device (1) according to one of the preceding claims, which is of planar design such that the gate insulation layer (4) and the gate electrode (33) are applied to a planar portion of a top side (20) of the semiconductor body (2), wherein the first region (21) is located at the top side (20). [10] Semiconductor device (1) according to one of claims 1 to 8, which is of trench-shaped design, so that the gate insulation layer (4) and the gate electrode (33) are at least partially arranged in a trench in the semiconductor body (2), a depth of the trench exceeds a depth of the well region (22), the first region (21) is located at the top side (20) starting from a top side (20) of the semiconductor body (2). [11] Semiconductor device (1) according to one of the preceding claims, wherein the exactly one current limiting region (5) is present in the first region (21). [12] Semiconductor device (1) according to one of claims 1 to 10, wherein a plurality of the current limiting regions (5) are present in the first region (21), the current limiting regions (5) being spaced apart from one another as seen in the plan view of the semiconductor body (2). [13] Semiconductor device (1) according to the preceding claim, wherein the current limiting regions (5) are arranged along one strip or along several strips. [14] Semiconductor device (1) according to one of the two preceding claims, comprising: wherein, as seen in plan view of the semiconductor body (2), the current confinement regions (5) are shaped as at least one of the following: triangle, square, rectangle, hexagon, circle. [15] A manufacturing method for a semiconductor device (1) according to any one of the preceding claims, the method comprising: - providing the semiconductor body (2), - forming the first region (21) and the well region (22) in the semiconductor body (2), - etching at least one recess into the first region (21) and filling the at least one recess with the at least one electrically insulating material, so that the at least one current limiting region (5) is produced, - applying the gate insulator layer (4) to the semiconductor body (2), and - Applying the gate electrode (33) and the first electrode (31) to the semiconductor body (2). [16] Method according to the preceding claim, wherein the at least one recess is etched into the semiconductor body (2) and then at least a part of a doping of the first region (21) is applied through the recess into the semiconductor body (2) and then the at least one electrically insulating material is filled into the at least one recess. [17] Method according to one of the two preceding claims, further comprising forming at least one plug region (25) in the semiconductor body (2), wherein the at least one plug region (25) is of the second conductivity type and has a maximum doping concentration that is higher than a maximum doping concentration of the well region (22), wherein the at least one plug region (25) is provided for electrically contacting the well region (22), wherein the first region (21) extends deeper into the semiconductor body (2) than the at least one plug region (25). [18] Method according to one of the two preceding claims, wherein the production of the first region (21) includes two different doping steps, so that, seen in cross section, a doping profile of the first region (21) is step-like.

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