Semiconductor component and manufacturing process

Abstract

In one embodiment, the semiconductor device (1) comprises a semiconductor body (2), a gate electrode (33) and a first electrode (31), wherein - the semiconductor body (2) has a first region (21) which is a source region or an emitter region and has a well region (22) which is arranged next to the first region (21), wherein the first region (21) has a first conductivity type and the well region (22) has a second conductivity type, - the trough area (22) is separated from the gate electrode (33) by a gate insulation layer (4), - the first area (21) is electrically contacted by means of the first electrode (31), - in the first area (21) at least one current limiting area (5) is present, and - that at least one current limiting area (5) is a sub-area of ​​the first area (21) with reduced electrical conductivity.

Description

[0001] A semiconductor device is provided. A method for manufacturing such a semiconductor device is also provided.

[0002] The documents US 2017 / 0243970 A1, US 2017 / 0229535 A1 and US 2015 / 0108564 A1 concern semiconductor devices.

[0003] A problem to be solved is to provide a semiconductor device that has an improved trade-off between conduction losses and short circuit withstand time (SCWT).

[0004] This problem is solved, inter alia, by a semiconductor device and a method as defined in the independent patent claims. Examples of further developments form the subject matter of the dependent claims.

[0005] For example, the semiconductor device described here comprises one or a plurality of current confinement regions that are subregions of a source region or emitter region, wherein the subregions are irradiated such that more crystal lattice defects are present in the subregions than in remaining regions of the source region or emitter region, and therefore the at least one current confinement region has a reduced electrical conductivity compared to remaining regions of the source region or emitter region. By means of the at least one current confinement region, a source resistance value R s increased. This R s -Increase does not significantly affect the component performance in normal operation, but improves short-circuit behavior.

[0006] According to at least one embodiment, the semiconductor component comprises a semiconductor body, a gate electrode, and a first electrode. For example, the semiconductor body is made of a wide-bandgap semiconductor material, such as SiC, Ga2O3, or GaN. However, the semiconductor body can alternatively be made of silicon, or Si for short. The electrodes can be made of at least one metal or also of a heavily doped and / or ohmically conductive semiconductor material, such as polySi.

[0007] According to at least one embodiment, the semiconductor body has a first region. For example, the first region is a source region or an emitter region.

[0008] According to at least one embodiment, the semiconductor body comprises a well region. The well region is arranged adjacent to the first region. This means that the first region may touch the well region and may thus be in direct physical contact therewith. A channel region represents a portion of the well region and may have the same doping concentration. During operation, electrons in the channel region flow from the source region to a drift region along a gate insulation layer. During operation of the semiconductor device, the channel region may be that portion of the well region that is adjacent to the gate insulation layer.

[0009] According to at least one embodiment, the first region has a first conductivity type, and the well region has a different, second conductivity type. For example, the first conductivity type is n-type and the second conductivity type is p-type, or vice versa. Hereinafter, the first conductivity type is referred to as n-type; therefore, if the first conductivity type is p-type instead, the doping relationships described below must be reversed.

[0010] According to at least one embodiment, the well region is adjacent to the gate electrode and separated from the gate electrode by the gate insulation layer. The gate insulation layer may be located directly between the gate electrode and the well region.

[0011] According to at least one embodiment, the first region is electrically contacted by means of the first electrode, which is, for example, a source electrode or an emitter electrode. Therefore, the first electrode can contact the semiconductor body at least at the first region. For example, the well is also electrically contacted by means of the first electrode, or otherwise by a separate electrode.

[0012] According to at least one embodiment, a current confinement region is present in the first region or a plurality of current confinement regions are present therein. The at least one current confinement region represents a subregion of the first region with a reduced electrical conductivity. For example, the first region and the at least one current confinement region are made of the same base material, such as SiC. However, more defects in a crystal lattice are present in the at least one current confinement region than in other regions of the first region, so that the electrical conductivity in the at least one current confinement region is intentionally lower than in the other regions of the first region.

[0013] In at least one embodiment, the semiconductor component comprises a semiconductor body, a gate electrode and a first electrode, wherein - the semiconductor body has a first region and a well region arranged adjacent to the first region, wherein the first region has a first conductivity type and the well region has a different, second conductivity type, - the well region is adjacent to the gate electrode and is separated from the gate electrode by a gate insulation layer, - the first area is electrically contacted by means of the first electrode, - there is at least one current limitation area in the first area, and - the at least one current limiting region is a sub-region of the first region with a reduced electrical conductivity.

[0014] Therefore, this application describes, for example, a metal-insulator-semiconductor field-effect transistor (MISFET), a metal-oxide-semiconductor field-effect transistor (MOSFET), or a junction field-effect transistor (JFET), for example based on silicon carbide (SiC). At least a portion of the source region or the emitter region is damaged by irradiation to reduce its electrical conductivity, thereby improving the tradeoff between conduction losses and short-circuit withstand time.

[0015] SiC MOSFETs are currently available from several suppliers. SiC MOSFETs, available in either planar or trench cell designs, offer competitive static losses, fast dynamic performance, and reasonable reliability. In terms of fault handling capability, SiC MOSFETs continue to lag behind the typical industry standard values ​​of approximately 10 µs exhibited by their Si counterparts. This is typically associated with the sharp trade-off between conduction losses and short-circuit withstand time (SCWT). One approach to achieving an optimal trade-off between the SCWT and the device's on-state resistance R DS,on consists in using a slightly increased source resistance value Rs.

[0016] Accordingly, for example, a SiC MOSFET is described here, where part of the source region is subjected to an irradiation process. If the appropriate mask, such as a SiO2 mask or an Al mask, is used, irradiation with electrons, protons, or neutrons in the n + -Source to form defects that reduce mobility and therefore the source resistance R s increase; for example, the resistivity in the at least one current limiting region can be changed such that it is in the range of 10 -2 up to 10 7 Ωcm.

[0017] In the proposed at least one current-limiting region, the current therefore flows in a path that has a higher resistance and / or is more limited. This effect leads to an increased value of the source resistance R s . An increase in R s -value leads to a reduction of the saturation current I SATupon occurrence of a short circuit, SC for short. The depth d of the irradiated area and its length L could be suitably designed to achieve the desired effect on the SC current, while at the same time minimizing its influence during conduction under nominal conditions, i.e., on the total resistance between source and drain in the on-state, also known as R DS,on referred to, is considered negligible.

[0018] According to at least one embodiment, the semiconductor component is a power component. This means, for example, that the semiconductor component is designed for a maximum current through the well region of at least 10 A or at least 50 A. Optionally, the maximum current is at most 500 A or at most 1.5 kA. Alternatively or additionally, the semiconductor component is designed for a maximum voltage of at least 0.6 kV or at least 1.2 kV between source and drain or between emitter and collector. As an option, the maximum voltage can be at most 6.5 kV.

[0019] According to at least one embodiment, when viewed in a top view of the semiconductor body, the gate electrode and the first electrode overlap the first region. Here and below, 'top view' may refer to a view perpendicular to an upper side of the semiconductor body to which the first electrode is applied and on which the first region is arranged.

[0020] According to at least one embodiment, when viewed in a top view of the semiconductor body, the at least one current confinement region is remote from the gate electrode and / or the first electrode. For example, when viewed in a top view, the at least one current confinement region is remote from the gate electrode as well as from the first electrode.

[0021] According to at least one embodiment, the at least one current confinement region is arranged in the associated first region, for example, in a mirror-symmetric manner within the manufacturing tolerances. This means that, when viewed in a plan view of the semiconductor body, the first region, together with the at least one current confinement region, has a mirror-symmetric axis of symmetry, for example with regard to the shape of the first region and the at least one current confinement region. When viewed in a plan view, the mirror-symmetric axis of symmetry can run parallel to the gate electrode and / or the first gate electrode and / or it can be arranged between the gate electrode and the first electrode. Otherwise, when viewed in a plan view, non-mirror-symmetric arrangements of the at least one current confinement region in the associated first region are also possible.

[0022] According to at least one embodiment, when viewed in a plan view of the semiconductor body, the first region extends completely between the at least one current confinement region and the first electrode, as well as between the at least one current confinement region and the gate electrode. In other words, a part of the first region is present between the at least one current confinement region and the respective electrode, for example, on the upper side of the semiconductor body, and when viewed in a plan view of the semiconductor body.

[0023] As an alternative, the at least one current confinement region may be partially covered with the gate electrode when viewing a view of the semiconductor body, or the at least one current confinement region may touch the gate electrode.

[0024] According to at least one embodiment, the at least one current confinement region is arranged between the first electrode and the gate electrode. For example, the entirety of the at least one current confinement region is arranged between the electrodes.

[0025] According to at least one embodiment, when viewed in a cross-section of the semiconductor body, the first region extends around the at least one current confinement region in directions toward the well region. This may mean that the first region is embedded in the well region and / or that the at least one current confinement region is embedded in the first region. For example, in this case, when viewed in a cross-section, part of the first region is present around the at least one current confinement region, such that no straight connecting line exists within the semiconductor body from the at least one current confinement region to the well region without traversing the first region.

[0026] The term 'cross-section of the semiconductor body' may, for example, refer to a cross-section through the first region, through the current confinement region or through at least one of the current confinement regions, and through the gate electrode in a direction perpendicular to the upper side of the semiconductor body and / or perpendicular to a direction of a main extension of the gate electrode.

[0027] According to at least one embodiment, when viewed in a cross-section of the semiconductor body, the at least one current confinement region is completely embedded in the first region. For example, when viewed in a cross-section of the semiconductor body, the first region is located around the at least one current confinement region.

[0028] According to at least one embodiment, for example, when viewed in a cross-section of the semiconductor body, the at least one current confinement region extends completely through the first region. Therefore, the at least one current confinement region may be as deep as or deeper than the first region. In other words, the at least one current confinement region penetrates the first region in the direction perpendicular to the upper side of the semiconductor body. The at least one current confinement region may start directly at the upper side or may otherwise start at a distance from the upper side within the first region.

[0029] According to at least one embodiment, a volume of the at least one current-limiting region is at least 5%, or at least 10%, or at least 20%, or at least 40%, or at least 60% of a total volume of the associated first region. Alternatively or additionally, the percentage is at most 95%, or at most 85%, or at most 75%. For example, the percentage is between 40% and 85%, inclusive.

[0030] For example, due to the at least one current confinement region, an electrical resistance through the first region between the first electrode and the channel region is increased by a factor of at least 1.1, or by a factor of at least 1.5, or by a factor of at least 2, or by a factor of at least 5. Alternatively or additionally, the factor is at most 100, or it is at most 25, or it is at most 15, or it is at most 10, or it is at most 5. For example, the factor is between 2 and 10, inclusive. The electrical resistance through the first region may relate to a normal operation current for which the semiconductor device is designed in an on-state. These factors relate to a comparison with a device that does not have the at least one current confinement region in the first region, but otherwise has an identical design within manufacturing tolerances.

[0031] According to at least one embodiment, an electrical conductivity of the at least one current-limiting region is at least 0.1%, or at least 1%, or at least 5% of an electrical conductivity of remaining regions of the first region. Alternatively or additionally, the value is at most 95%, or at most 80%, or at most 20%, or at most 10%.

[0032] According to at least one embodiment, a crystal lattice in the at least one current confinement region has more defects than the remaining regions of the first region by at least a factor of two, or by at least a factor of five, or by at least a factor of ten. Alternatively or additionally, the factor is at most 10 3or it is at most 100 or is at most 10. Therefore, a higher defect density is present in the at least one current confinement region than in the remaining regions of the first region, which is achieved by irradiating the at least one current confinement region.

[0033] For example, by means of the at least one current confinement region, an effective cross-section for the current flow within the first region from the first electrode to the well region adjacent to the gate insulation layer, that is to say to the channel region, through the at least one current confinement region is reduced by a factor of at least 1.5 or by a factor of at least 2 or by a factor of at least 5. Alternatively or additionally, the factor is at most 100 or is at most 15 or is at most 10 or is at most 5 or is at most 2. For example, the factor is between 2 and 10, inclusive.

[0034] The effective cross-section A eff for the current flow may be a minimum of a local electrical resistance r, which is integrated over an area A of a cross-section through the first region perpendicular to a main direction of the current flow, Aeff=min∫r dA.

[0035] According to at least one embodiment, the at least one current confinement region ends aligned with the first region. Thus, the upper side may be planar across the first region and the at least one current confinement region, and both the at least one current confinement region and the remaining regions of the first region end in the upper side. In other words, the first region and the current confinement region form a flat surface and end aligned with each other.

[0036] According to at least one embodiment, the semiconductor body further comprises a drift region. The drift region has the first conductivity type and, for example, has a lower maximum doping concentration compared to the first region and the well region.

[0037] According to at least one embodiment, the semiconductor body further comprises a second region. For example, the second region is a drain region or a collector region. In the case of a drain region, the second region also has the first conductivity type, but, for example, with a maximum doping concentration that is higher than in the drift region. In the case of a collector region, the second region has the second conductivity type.

[0038] According to at least one embodiment, the drift region is arranged between the well region and the second region. Accordingly, the first region is separated from the second region by the well region.

[0039] According to at least one embodiment, the semiconductor device further comprises a second electrode, which is, for example, a collector electrode or a drain electrode. The second electrode can be arranged on a side of the second region remote from the drift region and / or remote from the first region.

[0040] According to at least one embodiment, when viewed in a plan view of the semiconductor body, the gate electrode and the first electrode each extend along a straight line. If a plurality of first electrodes and / or gate electrodes are present, a plurality of straight lines may be present along which the first electrodes and / or the gate electrodes extend.

[0041] According to at least one embodiment, the first region extends parallel to the gate electrode and / or the first gate electrode. Therefore, the semiconductor component may have a strip-shaped design comprising a plurality of straight strips of the gate electrodes and / or the first electrodes.

[0042] According to at least one embodiment, when viewed in a plan view of the semiconductor body, the gate electrode and / or the first electrode each comprise a plurality of subsections. For example, the subsections correspond to unit cells. The unit cells may, for example, be arranged in a regular two-dimensional grid. The semiconductor body may extend continuously across all the unit cells and comprise a correspondingly arranged plurality of the first regions. Therefore, the semiconductor device may have a cellular design comprising a plurality of cells, each of which comprises a first electrode, a corresponding gate electrode, and a corresponding first region with the at least one current confinement region.

[0043] According to at least one embodiment, the semiconductor device has a planar design. This means that the gate insulation layer and the gate electrode are applied to a planar portion of the upper side of the semiconductor body. The first region and the at least one current confinement region can be arranged on the upper side.

[0044] According to at least one embodiment, the semiconductor device has a trench design. Thus, the gate insulation layer and the gate electrode are partially or completely arranged in a trench in the semiconductor body. For example, a depth of the trench exceeds a depth of the well region, starting from the upper side of the semiconductor body. In this case, too, the first region and the at least one current confinement region can be arranged on the upper side.

[0045] According to at least one embodiment, the current limiting region is present in the first region. In the case of a plurality of first regions, a one-to-one mapping can exist between the first regions and the current limiting region.

[0046] Otherwise, a plurality of current confinement regions are present in the first region. In the case of a plurality of first regions, a plurality of current confinement regions may be present per first region. The current confinement regions of each of the first regions, or of the precisely one first region, are spaced apart from one another when viewed in a plan view of the semiconductor body.

[0047] When viewed in a plan view of the semiconductor body, the current confinement region or each of the current confinement regions may be completely surrounded by the respectively associated first region.

[0048] According to at least one embodiment, the current-limiting regions are arranged along a strip or along a plurality of strips. Furthermore, as an option, the current-limiting regions, when viewed in plan view, are arranged along a row or along a plurality of rows, wherein the strips and rows may be oriented perpendicular to one another. In the case of a plurality of first regions, this may apply to each of the first regions, wherein each of the first regions is associated with a plurality of the current-limiting regions.

[0049] According to at least one embodiment, when viewed in a plan view of the semiconductor body, the current confinement regions have at least one of the following shapes: triangle, square, rectangle, hexagon, circle. When viewed in a plan view, all of the current confinement regions can have the same shape and / or the same surface area. Otherwise, differently shaped and / or dimensioned current confinement regions can also be combined with one another per first region.

[0050] A method for manufacturing the semiconductor component is also provided. Using the method, a semiconductor component is manufactured as specified in connection with at least one of the aforementioned embodiments. Features of the semiconductor component are therefore also disclosed for the method, and vice versa.

[0051] In at least one embodiment, the manufacturing method is for manufacturing a semiconductor device, the method comprising, for example, in the order given: - Providing the semiconductor body, - forming the first region and the well region in the semiconductor body, - Applying a mask layer to the semiconductor body, - irradiating at least one portion of the first region defined by the mask layer with at least one of X-rays, electrons, protons, neutrons or ions, so that the at least one current confinement region is created in the irradiated at least one portion, and - Applying the gate insulation layer as well as the gate electrode and the first electrode to the semiconductor body.

[0052] A dose for irradiating the at least one section can be used as a design parameter to tune the resistance of the at least one current confinement region and thus of the first region and achieve the desired effect. For example, in the case of electron irradiation, the dose could be in the range between 10 10 cm -2 and 10 17 cm -2 and / or up to 10% of a maximum doping concentration of the first region. For example, in the case of proton irradiation, the dose can be between 10 8 cm -2 and 10 14 cm -2 be.

[0053] The shape of the at least one current confinement region, when viewed from a top view, is defined by the mask layer, while the depth of the at least one current confinement region depends on the mask layer thickness and the energy used for irradiation, for example, a minimum of 116 keV for electrons or a minimum of 200 keV for protons and neutrons. It is possible for only one type of irradiation, for example, only electron irradiation, to be present, or different types of irradiation can be combined.

[0054] According to at least one embodiment, the method further comprises forming at least one plug region in the semiconductor body. The at least one plug region has the second conductivity type and has a maximum doping concentration that is higher than a maximum doping concentration of the well region. The at least one plug region serves to electrically contact the well region, for example, using the first electrode.

[0055] According to at least one embodiment, the first region extends deeper into the semiconductor body than the at least one plug region.

[0056] According to at least one embodiment, the creation of the first region comprises two different doping steps, so that, when viewed in cross-section, a doping profile of the first region is stepped. This means that the first region can become wider toward the upper side.

[0057] A semiconductor device and method described herein are explained in more detail below using exemplary embodiments with reference to the drawings. Elements that are the same in the individual figures are indicated by the same reference numerals. However, the relationships between the elements are not drawn to scale; rather, individual elements may be exaggerated for clarity.

[0058] They show: Fig. 1 a schematic perspective cross-sectional view of an embodiment of a semiconductor device described here, Fig. 2 to 4 are schematic cross-sectional views of embodiments of semiconductor devices described here, Fig. 5 and Fig. 6 schematic perspective cross-sectional views of embodiments of semiconductor devices described here, Fig. 7 to 9 are schematic cross-sectional views of embodiments of semiconductor devices described here, Fig. 10 and Fig. 11 schematic diagrams of electrical characteristics of simulations of an embodiment of a semiconductor device described here in comparison with a corresponding semiconductor device which is free of the at least one current limiting region, Fig. 12 is a schematic block diagram of an embodiment of a method for manufacturing semiconductor devices described herein, Fig. 13 a schematic cross-sectional view of a method step of an embodiment of a method described here, and Fig. 14 and Fig. 15 schematic plan views of embodiments of semiconductor components described here.

[0059] Fig. Figure 1 illustrates an embodiment of a semiconductor component 1. The semiconductor component 1 comprises a semiconductor body 2, which is made of SiC, for example. A first region 21, a well region 22, and a drift region 23 are present in the semiconductor body 2. A plug region 25 for electrically contacting the well region 22 is also present therein.

[0060] In addition, the semiconductor component 1 has a gate electrode 33, which is separated from the semiconductor body 2 by a gate insulation layer 4. Furthermore, a first electrode 31 is present therein, which electrically contacts the first region 21 and the plug region 25. The gate insulation layer 4 and the first electrode 31 are arranged on an upper side 20 of the semiconductor body 2. The upper side 20 is designed to be planar. The gate electrode 33 and the first electrode 31 can each extend along a straight line in a direction perpendicular to the Fig. 1. The gate insulation layer 4 may be made of a metal oxide, a semiconductor oxide, a metal nitride, and / or a semiconductor nitride. For example, the gate insulation layer 4 comprises one or a plurality of the following materials: SiO2, Si3N4, Al2O3, Y2O3, ZrO2, HfO2, La2O3, Ta2O5, TiO2.

[0061] For example, the first region 21 and the drift region 23 are n-doped, and the well region 22 and the plug region 25 are p-doped. If the semiconductor device 1 is an insulated-gate bipolar transistor (IGBT) or a reverse-conducting insulated-gate bipolar transistor (RC-IGBT), then the first region 21 is an emitter region, and the first electrode 31 is an emitter electrode. If the semiconductor device 1 is a junction field-effect transistor (JFET), a metal-insulator-semiconductor field-effect transistor (MISFET), or a metal-oxide-semiconductor field-effect transistor (MOSFET), then the first region 21 is a source region, and the first electrode 31 is a source electrode.

[0062] A current confinement region 5 is present in the first region 21. The current confinement region 5 is made of the same material as the rest of the first region, for example, SiC. However, due to irradiation of the part of the first region 21 that forms the current confinement region 5, the electrical conductivity in the current confinement region 5 is reduced compared to the rest of the first region 21.

[0063] Therefore, Fig. 1 shows the basic concept of the proposed semiconductor device 1. A region, i.e., the at least one current confinement region 5, is irradiated after source activation. Its width is defined by a mask design, while the depth of this region 5 depends on a mask thickness and the energy used for irradiation. During irradiation, for example, several point defects are formed. These defects can form electrically active levels in the band gap, such as the junction. For details on the EH1, Z1 / 2, EH3, EH4, EH5, and EH6 / 7 levels, see Alfieri et al., “Annealing behavior between room temperature and 2000 °C of deep level defects in electron-irradiated n-type 4H silicon carbide,” Journal of Applied Physics 98, 043518 (2005), doi: 10.1063 / 1.2009816, and Alfieri et al., “Isothermal Annealing Study of the EH1 and EH3 Levels in n-type 4H-SiC,” J. Phys.: Condens. Matter 32, 4657'3 (2020), doi: 10.1088 / 1361-648X / abaeaf. These levels trap charge carriers and reduce mobility.The lower mobility increases the value of the source resistance R. s .

[0064] The current confinement region 5 runs along a straight line parallel to the gate electrode 33 and the first electrode 31. The current confinement region 5 is arranged directly on the upper side 20, like the first region 21. A depth of the first region 21 into the semiconductor body 2 exceeds a depth of the current confinement region 5 into the semiconductor body 2, starting from the upper side 20. In the direction of the well region 22, in which the first region 21 is embedded, the first region 21 is located around the current confinement region 5, when viewed in cross section.

[0065] For example, the at least one current confinement region 5 is arranged mirror-symmetrically in the first region 21 when viewed in a top view as well as in a cross-section. For example, when viewed in a top view of the upper side 20, the current confinement region 5 is arranged symmetrically in the first region 21 and between the electrodes 31, 33. Therefore, a mirror symmetry line M may be present with respect to the current confinement region 5 and the first region 21.

[0066] The at least one current confinement region 5 may have different shapes and depths and may be arranged along the direction perpendicular to the cross section of Fig. 1 be uniform or non-uniform, see also Fig. 2 to 9 below.

[0067] In the proposed at least one current-limiting region 5, the current flows in a path that has a higher resistance and / or is more limited. This effect leads to an increased value of the source resistance R s or corresponding to an emitter resistance. An increase in R s -value leads to a reduction of the saturation current I SAT during a short-circuit condition. A depth d of the current confinement region 5 and its length L parallel to the upper side 20 and along the cross section of Fig. 1 could be suitably designed to achieve the desired effect on the short-circuit current, while minimizing its effect during conduction under rated conditions, for example, on the total R DS,on , is kept negligible.

[0068] For example, an effective channel-to-contact path length Leff of the charge carriers is a minimum of a local resistance r along all possible routes S with incremental elements s within the first region 21, including the at least one current confinement region 5, Leff=min ∫s□rds.

[0069] The semiconductor device 1 of Fig. 1 has a planar design. In contrast, the semiconductor device 1 of Fig. 2 has a trench design. Therefore, the gate electrode 33 and the gate insulation layer 4 are at least partially arranged in a trench in the semiconductor body 2. Accordingly, the upper side 20 is not designed to be planar, since, in contrast to the case of Fig. 1 is penetrated by the trench. The gate electrode 33 extends deeper into the semiconductor body 2 than, for example, the well region 22, starting from the upper side 20.

[0070] In addition, Fig. 2 that a plurality of first regions 21, and therefore current limiting regions 5, are arranged, for example, symmetrically with respect to the gate electrode 33. A plurality of the regions shown in Fig. 2 may be arranged side by side along a direction parallel to the upper side 20, so that a plurality of strips of the gate electrode 33 and the first electrode 31, which are perpendicular to the plane of the drawing of Fig. 2 and run parallel to each other.

[0071] This symmetrical arrangement of Fig. 2, see also Fig. 14, and / or the trench design of Fig. 2 can also be applied analogously to all other embodiments.

[0072] The current limitation areas 5, one per first area 21, of Fig. 2 have the same design as in Fig. 1, that is, a cuboid-shaped depression. According to Fig. 2, the recess has sharp edges and corners; according to Fig. 1, the recess has rounded edges and corners. Both designs are possible in all embodiments, depending on the manufacturing process of the at least one current confinement region 5.

[0073] Furthermore, it is in Fig. 2 shows that a second electrode 32 is present, and the semiconductor body 2 has a second region 24. For example, the second region 24 is a substrate on which the other regions 23, 22, 21, 25 are formed by growth and / or doping, such as ion implantation. In the case of an IGBT or RC-IGBT, the second electrode 32 is a collector electrode, and the second region is a collector region having the same doping type as the well region. In the case of a MOSFET or MISFET, the second electrode 32 is a drain electrode, and the second region is a drain region having the same doping type as the first region. The same applies to all other embodiments of the semiconductor device 1.

[0074] In addition, according to Fig. 2 the plug region 25 extends deeper into the semiconductor body 2, starting from the upper side 20, than the first region 21. Otherwise, the plug region 25, see Fig. 1, may have the same depth as the first region 21, or it may also be shallower or deeper than the first region 21. Both possibilities can be used in all embodiments.

[0075] As in Fig. 1 is also in Fig. 2 the at least one current confinement region 5 per first region 21 is removed from the first electrode 31, from the gate electrode 33 and from the gate insulation layer 4.

[0076] For example, maximum doping concentrations of the first region 21, the second region 24 and the at least one plug region 25 are at least 1 × 10 18 cm -3 or be at least 5 × 10 18 cm -3 or at least 1 × 10 19 cm -3 and / or a maximum of 5 × 10 20 cm -3 or at most 2 × 10 20 cm -3 or at most 1 × 10 20 cm -3. In addition, a maximum doping concentration of the well region 22 and therefore of a channel region adjacent to the gate insulation layer 4 may be at least 5 × 10 16 cm -3 or at least 1 × 10 17 cm -3 and / or a maximum of 5 × 10 19 cm -3 or at most 5 × 10 18 cm -3 Depending on the voltage class of the semiconductor component 1, a maximum doping concentration of the drift region 23 can be at least 1 × 10 11 cm -3 or at least 1 × 10 12 cm -3 or at least 1 × 10 13 cm -3 and / or at most 1 × 10 17 cm -3 or at most 5 × 10 16 cm -3 or at most 1 × 10 16 cm -3For example, the thickness of the gate insulation layer 4 is between 10 nm and 250 nm or between 80 nm and 150 nm. These parameters may also apply individually or in their entirety to all other embodiments.

[0077] Otherwise, the same as for Fig. 1, also for Fig. 2 apply, and vice versa.

[0078] In Fig. 3 and Fig. 4 is, as in Fig. 1, one current limiting region 5 is present per first region 21. The current limiting region 5 can be arranged mirror-symmetrically in the first region 25, with the mirror symmetry axis running perpendicular to the upper side 20.

[0079] In contrast to the representation in Fig. 1 extends according to Fig. 3 and Fig. 4, the current confinement region 5 extends beyond the gate insulation layer 4 and the gate electrode 33. Such an arrangement is also possible in all other embodiments. Otherwise, in contrast to the illustration in Fig. 3 and Fig. 4, the current confinement region 5 may not be arranged mirror-symmetrically in the first region 21, so that the current confinement region 5 ends far from the gate insulation layer 4 and therefore may not extend beyond the gate electrode 33. This is also possible in all other embodiments.

[0080] According to Fig. 3, the current confinement region 5 is formed as a shallow depression in the first region 21, which is also formed as a depression. The depth d of the current confinement region 5 is, for example, between 10% and 90% or between 40% and 80% of a depth D of the first region 21. The first region 21 and the plug region 25 can, for example, have the same depth, within manufacturing tolerances. For example, the depth D of the first region 21 is at least 0.1 µm and / or it is at most 2 µm.

[0081] According to Fig. 4, the current limiting region 5 is formed as a deep depression in the first region 21, which is formed as two depressions one above the other, wherein the depression next to the upper side 20 has a larger extension parallel to the plane of the drawing of Fig. 4. In this case, the depth d of the current confinement region 5 may also be, for example, between 10% and 90% or between 40% and 80% of the depth D of the entire first region 21. Due to the design with two stacked recesses, the first region 21 may extend deeper into the semiconductor body 2 than the plug region 25. It is possible, within manufacturing tolerances, for the plug region 25 to have the same depth as, for example, the recess of the first region 21 adjacent to the upper side 20. For example, the depth D of the first region 21 is at least 2 µm and / or it is at most 4 µm.

[0082] For example, first, the recess adjacent to the upper side 20 is formed by appropriate doping, and then the doping is provided for the recess remote from the upper side 20, for example, using a different energy in an ion implantation step. Therefore, the recess of Fig. 4 when viewed in cross-section has a stepped design. Otherwise, for example, a deep recess with the rectangular shape with rounded corners, as in Fig. 3, equally in the design of Fig. 4 possible.

[0083] Both designs with a flat or a deep first area 21, as in Fig. 3 and Fig. 4 are also possible in all other embodiments.

[0084] For example, the length L of the current limiting region 5 is between 10% and 90% or between 40% and 80% or between 50% and 70% of a width B of the first region 21. This is also possible in all other embodiments.

[0085] Otherwise, the same as for Fig. 1 and Fig. 2, also for Fig. 3 and Fig. 4 apply, and vice versa.

[0086] According to Fig. 5 to 7, several current limiting regions 5 are present per first region 21. With regard to the parameters d, D, B, L, as stated above for the case of a single current limiting region 5 per first region 21, the same applies to the case of several current limiting regions 5 per first region 21, where L corresponds to a total width of all respective current limiting regions 5, compare for example Fig. 6. Due to the plurality of current limiting regions 5, more design parameters are available to achieve an optimized first region.

[0087] In the case of a current confinement region 5 in the direction perpendicular to the gate electrode 33 and / or the first electrode 31, see Fig. 5, the total width L is equal to a width W of a single island-like current limiting area 5, as in Fig. 4 shown.

[0088] However, according to Fig. 5, a strip of current confinement regions 5 is present, extending parallel to the electrodes 31, 33. When viewed in plan view, the current confinement regions 5 have a rectangular or square shape, optionally with rounded corners, each having a width W and a length V. For example, V is between 0.5 L and 100 L, or it is between 0.5 L and 10 L, or it is between 0.7 L and 5 L.

[0089] For example, a distance Zs between adjacent current limiting regions 5 along the strip is between 10% and 75% or between 10% and 40% of the width W and / or the length V. The individual current limiting regions 5 in the strip can be arranged in an equidistant manner or, deviating from the representation in Fig. 5, be arranged at different distances from one another. These aspects can also apply individually or in their entirety to all other embodiments.

[0090] Contrary to what is shown, the current confinement regions 5 do not have to have a square shape when viewed from above, but can also have a rectangular, hexagonal, regular or irregular polygonal, or circular shape when viewed from above. The same applies to all other embodiments.

[0091] According to Fig. 5 to 7, all the current-limiting regions 5 per first region 21 have the same shape. This is not absolutely necessary. This means that differently shaped current-limiting regions 5 can be combined within a first region 21.

[0092] There may be N strips of current confinement regions 5 between the electrodes 31, 33, where N is a natural number greater than or equal to two. For example, N is at most ten or it is at most four. According to the example of Fig. 6, N is two. For example, 0.1 B / N ≤ W ≤ 0.99 B / N or 0.4 B / N ≤ W ≤ 0.95 B / N or 0.7 B / N ≤ W ≤ 0.90 B / N. Alternatively or additionally, a distance Zt between adjacent current confinement regions 5 in a transverse direction perpendicular to the strips is, for example, between 10% and 75% or between 10% and 40% of the linear extent V. Alternatively or additionally, for example, 0.1 B / N ≤ V ≤ 100 B / N or 0.4 B / N ≤ V ≤ 10 B / N or 0.7 B / N ≤ V ≤ 5 B / N. The current limiting regions 5 can be arranged in an equidistant manner parallel and perpendicular to the electrodes 31, 33.

[0093] As in Fig. As shown in Figure 6, all N strips have the same number of current confinement regions 5, so that in each case, K current confinement regions 5 are present next to each other in a direction parallel to the strips. As a result, a regular array of N x K current confinement regions 5 is formed, and all the current confinement regions 5 have the same shape.

[0094] However, this is not necessary. That is, current-limiting regions 5 of different shapes and sizes can be combined with each other, and different numbers K of current-limiting regions 5 per strip and / or different numbers N of current-limiting regions 5 can be present in the direction parallel to the width L. For example, current-limiting regions 5 of different widths W are present, so that, for example, rows having a single wide current-limiting region 5 can be present parallel to the direction along the width L, alternating with rows having a plurality of narrower current-limiting regions 5.

[0095] In Fig. 7 shows that N is three. As an option, the stripe furthest from the first electrode 31 extends beyond the gate insulation layer 4. However, in contrast to the illustration in Fig. 7, when viewed in a plan view of the upper side 20, for example, all stripes may be removed from the gate electrode 33.

[0096] Each of the strips of Fig. 7 may be composed of several current limiting areas 5, as in Fig. 5 and Fig. 6, or there is only a single current limiting area 5 per strip, as in Fig. 1 to 4. The same applies to all other embodiments.

[0097] The current limitation areas 5 of Fig. 5 to 7, for example, have a flat design, compare for example Fig. 3 above. It is also possible that all or some of the current confinement regions 5 per first region 21 have the deep design, as in the context of Fig. 4 shown.

[0098] Otherwise, the same as for Fig. 1 to 4, also for Fig. 5 to 7 apply, and vice versa.

[0099] In semiconductor device 1 of Fig. 8, the current confinement region 5 extends completely through the first region 21 from the upper side 20 to the well region 22. Neglecting possible small currents around the current confinement region 5 through the part of the well region 22 on a side of the current confinement region 5 remote from the upper side 20, the entire current must therefore flow from the first electrode 31 to the channel region of the well region 22 adjacent to the gate insulation layer 4 through the current confinement region 5 with a lower electrical conductivity.

[0100] By the length parallel to the plane of Fig. 8 and the electrical conductivity of the current limiting region 5 allows the resistance of the first region 21 to be adjusted particularly precisely.

[0101] Otherwise, the same as for Fig. 1 to 7, also for Fig. 8 apply, and vice versa.

[0102] In semiconductor device 1 of Fig. 9, the current confinement region 5 is completely embedded in the remainder of the first region 21. This means that the first region 21 is located around the current confinement region 5. Accordingly, it is possible for the current confinement region 5 to extend beyond the gate electrode 33. Contrary to what is illustrated, the current confinement region 5 may not extend below the gate electrode 33.

[0103] For example, a layer thickness of the first region 21 around the current confinement region 5 has a thickness of at least 5% or of at least 10% and / or of at most 30% or of at most 45% of a total thickness of the first region 21 together with the embedded current confinement region 5.

[0104] The design of Fig. 9 is also possible with a plurality of current limitation areas 5 per first area 21, compare for example Fig. 5 to 7, or with a deep current limiting area 5, compare for example Fig. 4.

[0105] Otherwise, the same as for Fig. 1 to 8, also for Fig. 9 apply, and vice versa.

[0106] Fig. 10 and Fig. 11 show a simulated isothermal output J D vs. V DS at a gate-source voltage V GS = 15 V and a temperature of 300 K, and the electrothermal short-circuit waveforms at a drain-source voltage V DS = 600 V and at V GS, Swing = -5 V / +15 V for the semiconductor device 1 of Fig. 8, compared with a corresponding reference MOSFET design 9 without a current limiting region. In the semiconductor device 1, the Fig. 8, the quotient d / D of the depth d of the current limiting region 5 and the depth D of the first region 21 is 1. The quotient L / B of the length L of the current limiting region 5 and the width B of the first region 21 is 0.5.

[0107] It should be noted that the achieved reduction of a maximum saturation current I SAT,peak during a short circuit is greater than the increase in resistance in the on state R DS,on . Since the energy to which the component is exposed during a short circuit is directly related to the maximum value of I SAT The semiconductor component 1 described here improves the short-circuit withstand time without significantly affecting the conduction losses.

[0108] In Fig. 12 illustrates a method for manufacturing semiconductor components 1. In a method step S1, the semiconductor body 2 is provided. For example, the semiconductor body 2 provides the drift region 23. Then, in a method step S2, the first region 21 and the well region 22 in the semiconductor body 2, as well as the plug region 25, are formed.

[0109] Next, in step S3, at least one mask layer is provided on the upper side 20 of the semiconductor body 2. Furthermore, see step S4, at least one portion of the first region 21 defined by the mask layer is irradiated with at least one of X-rays, electrons, protons, neutrons, or ions, so that the at least one current confinement region 5 is created in the at least one irradiated portion. Then, in step S5, the gate insulation layer 4, the gate electrode 33, and the first electrode 31, and optionally also the second electrode 32, are applied to the semiconductor body 2.

[0110] In a further step, not shown, the mask layer can be partially or completely removed and the semiconductor device 1 can be completed.

[0111] The process steps S1 to S5 do not necessarily have to be carried out in the order mentioned.

[0112] In Fig. 13, process step S5 is shown in more detail. As in Fig. 13, the electrodes were optionally not yet applied in this step S5. It is also possible that the gate insulation layer 4 is applied directly after the irradiation step, which is shown in Fig. 13 is symbolized by the fact that the gate insulation layer 4 is represented by a dashed line.

[0113] Therefore, according to Fig. 13, the mask layer 6, which is made of silicon dioxide, for example, is applied to the upper side 20 and is patterned to represent the at least one current confinement region 5. In the area of ​​the at least one current confinement region 5, the radiation R can reach the first region 21 through the mask layer 6. In other parts of the semiconductor body 2, it is possible that the radiation R may not reach the semiconductor body 2.

[0114] In contrast to the representation in Fig. 13, it is also possible that the upper side 20 is completely free of the mask layer 6 in the region of the at least one current limitation region 5.

[0115] For example, the radiation R is composed of electrons, protons, or neutrons with energies above approximately 0.1 MeV. Such radiation can damage the crystal lattice of the material of the first region 21, resulting in an increased number of point defects. In addition to creating an increased defect density, it may alternatively or additionally be possible, for example, to neutralize the doping of the first region 21 by counter-doping, so that the radiation R can also be composed of ions.

[0116] In Fig. Figure 14 shows an example of the semiconductor device 1 in a plan view. It can be seen that the strip of the gate electrode 33 is arranged, for example, in a symmetrical manner between two strips of one half of the first electrode 31, and therefore between two strips of the first region 21 comprising the current confinement region 5. The structure in Fig. 14 corresponds to a unit cell that can be multiplied so that a plurality of the unit cells can be arranged next to each other.

[0117] This stripe design can also be applied analogously to the designs of Fig. 1 and 3 to 9 are applied; in Fig. This type of symmetrical design is already shown in Figure 2.

[0118] Otherwise, the same as for Fig. 1 to 13, also for Fig. 14 apply, and vice versa.

[0119] Furthermore, the semiconductor device 1 can also have a cellular design when viewed from a top view, so that a rectangular or square unit cell can be formed. For example, the first electrode 31 is located in the center of the unit cell, which is surrounded by the gate electrode 33 in a frame-like manner.

[0120] Such unit cells can be arranged two-dimensionally, so that the semiconductor device 1 can have a large number of such unit cells.

[0121] Otherwise, the same as for Fig. 14, also for Fig. 15 apply, and vice versa.

[0122] Unless otherwise stated, the components shown in the figures follow one another directly above the other in the order shown. Components that are not in contact in the figures are spaced apart from one another for illustrative purposes. If lines are drawn parallel to each other, the corresponding surfaces may be aligned parallel to each other. Likewise, unless otherwise stated, the positions of the drawn components relative to each other are correctly represented in the figures.

[0123] The invention described here is not limited by the description based on the exemplary embodiments. Rather, the invention encompasses any novel feature and also any combination of features, in particular encompassing any combination of features in the patent claims, even if this feature or combination itself is not explicitly specified in the patent claims or exemplary embodiments. List of reference symbols 1 semiconductor component 2 semiconductor bodies 20 upper side of the semiconductor body 21 first area (source area or emitter area) 22 Bath area 23 Drift area 24 second area (drain area or collector area) 25 plug area 31 first electrode (source electrode or emitter electrode) 32 second electrode (drain electrode or collector electrode) gate electrode 4 Gate insulation layer 5 Current limitation area 6 mask layer 33 9 Comparative example of a semiconductor component B Width of the first area d Depth of the current confinement area D Depth of the first area E1 first example of the semiconductor device E2 first example of the semiconductor device E3 first example of the semiconductor device L Length of the current limitation area M mirror symmetry line R radiation S.. Process step T time in µs J D Current density in the drain region in A / cm 2 V DS Voltage between the drain electrode and the source electrode in V V Length of the current limitation areas W Width of an island-like current limitation area Zs Distance between current limiting areas along a strip Zt Distance between current limiting areas in a transverse direction QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 2017 / 0243970 A1

[0002] US 2017 / 0229535 A1

[0002] US 2015 / 0108564 A1

[0002] Cited non-patent literature

[0000] Alfieri et al., “Annealing behavior between room temperature and 2000 °C of deep level defects in electron-irradiated n-type 4H silicon carbide”, Journal of Applied Physics 98, 043518 (2005), doi: 10.1063 / 1.2009816

[0063] Alfieri et al., „Isothermal Annealing Study of the EH1 and EH3 Levels in n-type 4H-SiC“, J.Phys.: Condens. Matter 32, 4657'3 (2020), doi: 10.1088 / 1361-648X

[0063]

Claims

[1] Semiconductor component (1) comprising a semiconductor body (2), a gate electrode (33) and a first electrode (31), wherein - the semiconductor body (2) has a first region (21), which is a source region or an emitter region, and a well region (22) arranged next to the first region (21), wherein the first region (21) has a first conductivity type and the well region (22) has a different, second conductivity type, - the well region (22) is adjacent to the gate electrode (33) and is separated from the gate electrode (33) by a gate insulation layer (4), - the first region (21) is electrically contacted by means of the first electrode (31), which is a source electrode or an emitter electrode, - at least one current limiting region (5) is present in the first region (21), and - the at least one current limiting region (5) is a sub-region of the first region (21) with a reduced electrical conductivity. [2] Semiconductor component (1) according to the preceding claim, wherein, when viewed in a plan view of the semiconductor body (2), the gate electrode (33) and the first electrode (31) overlap the first region (21), and the at least one current limiting region (5) is remote from the gate electrode (33) and from the first electrode (31). [3] Semiconductor component (1) according to one of the preceding claims, wherein, when viewed in a plan view of the semiconductor body (2), the first region (21) extends completely between the at least one current limiting region (5) and the first electrode (31) and between the at least one current limiting region (5) and the gate electrode (33), wherein the at least one current limiting region (5) is arranged between the first electrode (31) and the gate electrode (33). [4] Semiconductor component (1) according to one of the preceding claims, wherein, when viewed in a cross section of the semiconductor body (2) through the first region (21) and through the gate electrode (33), the first region (21) extends around the at least one current confinement region (5) in directions towards the well region (22), so that the first region (21) is embedded in the well region (22) and so that the at least one current confinement region (5) is embedded in the first region (21). [5] Semiconductor component (1) according to the preceding claim, wherein the at least one current limiting region (5) is completely embedded in the first region (21) such that, when viewed in a cross section of the semiconductor body (2), the first region (21) is located around the at least one current limiting region (5). [6] Semiconductor component (1) according to one of claims 1 to 3, wherein the at least one current limiting region (5) extends completely through the first region (21), so that the at least one current limiting region (5) is as deep as or deeper than the first region (21). [7] Semiconductor component (1) according to one of the preceding claims, wherein a volume of the at least one current limiting region (5) is at least 10% and at most 95% of a total volume of the first region (21). [8] Semiconductor component (1) according to one of the preceding claims, wherein an electrical conductivity of the at least one current limiting region (5) is between 5% and 90% of an electrical conductivity of remaining regions of the first region (21), wherein a crystal lattice in the at least one current confinement region (5) has at least a factor of two more defects than the remaining regions of the first region (21). [9] Semiconductor component (1) according to one of the preceding claims, wherein the semiconductor body (2) further comprises a drift region (23) having the first conductivity type and also a second region (24) which is a drain region or a collector region, wherein the drift region is arranged between the well region (22) and the second region (24), wherein the semiconductor component (1) further comprises a second electrode (32) which is a collector electrode or a drain electrode, wherein the second electrode (32) is arranged on a side of the second region (24) which is remote from the drift region (23), and wherein the semiconductor body (2) is made of SiC. [10] Semiconductor component (1) according to one of the preceding claims, wherein, when viewed in a plan view of the semiconductor body (2), the gate electrode (33) and the first electrode (31) each extend along a straight line, the first region (21) extends parallel to the gate electrode (33) and the first electrode (31), or wherein, when viewed in a plan view of the semiconductor body (2), the gate electrode (33) and the first electrode (31) each have a plurality of subsections arranged along at least one arrangement line, the first region (21) extending between adjacent subsections of the gate electrode (33) and the first electrode (31). [11] Semiconductor device (1) according to one of the preceding claims, having a planar design such that the gate insulation layer (41) and the gate electrode (33) are applied to a planar portion of an upper side (20) of the semiconductor body (2), wherein the first region (21) is arranged on the upper side (20). [12] Semiconductor component (1) according to one of claims 1 to 10, comprising a trench design such that the gate insulation layer (41) and the gate electrode (33) are at least partially arranged in a trench in the semiconductor body (2), wherein a depth of the trench exceeds a depth of the well region (22), starting from an upper side (20) of the semiconductor body (2), wherein the first region (21) is arranged on the upper side (20). [13] Semiconductor component (1) according to one of the preceding claims, wherein exactly one current limiting region (5) is present in the first region (21). [14] Semiconductor component (1) according to one of claims 1 to 10, wherein a plurality of the current limiting regions (5) are present in the first region (21), wherein the current limiting regions (5) are spaced apart from one another when viewed in a plan view of the semiconductor body (2). [15] A manufacturing method for a semiconductor device (1) according to any one of the preceding claims, the method comprising: - providing the semiconductor body (2), - forming the first region (21) and the well region (22) in the semiconductor body (2), - applying a mask layer (6) to the semiconductor body (2), - irradiating at least one portion of the first region (21) defined by the mask layer (6) with at least one of X-rays, electrons, protons, neutrons or ions, so that the at least one current confinement region (5) is created in the at least one irradiated portion, and - Applying the gate insulation layer (41) as well as the gate electrode (33) and the first electrode (31) to the semiconductor body (2).

Images