Semiconductor device and power conversion device

Abstract

A semiconductor device includes a gate voltage control circuit that applies a turn-on bias and a turn-off bias to a gate terminal of a power semiconductor element according to a first driver signal; and a turn-off bias control circuit that adjusts a turn-off bias voltage level according to the first driver signal and a second driver signal and controls a period of time of application of the adjusted turn-off bias.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device and, more particularly, to driving a power semiconductor element. STATE OF THE ART

[0002] One of the problems related to the reliability of a power semiconductor device is gate misconnection. When a gate misconnection occurs, the high-voltage power supply on the upper arm and the low-voltage power supply on the lower arm of a phase of a power inverter experiencing the misconnection are short-circuited. As a result, a high short-circuit current flows between the power supplies, which can increase the electrical loss of the power inverter and, in the worst case, lead to thermal runaway.

[0003] As a countermeasure against gate misconnection, an approach of applying a negative bias voltage between the gate and source of a power semiconductor element is widely known. Gate misconnection is caused by a displacement current generated by the turn-on operation of the power semiconductor element on the opposite arm. Since the displacement current is proportional to the voltage change rate of the power conversion element on the opposite arm, the displacement current increases as the switching speed increases, and as a result, misconnection of the switching-side element is likely to occur.However, if a negative bias is applied at a time when false turn-on occurs, it is possible to prevent a short circuit from occurring in the elements of the upper and lower arms without exceeding the gate threshold voltage, and the larger the negative bias, the greater the effect of preventing false turn-on.

[0004] In contrast, when a negative bias is applied between the gate and source during the OFF operation of a conventional power semiconductor device, the gate is driven with a constant application of the negative bias. If the negative bias is applied for a long period of time, the gate oxide film of the power semiconductor device is subjected to stress. A report on a silicon nitride-based metal-oxide-semiconductor field-effect transistor (SiC-MOSFET) reported that high stress on the gate oxide film can cause characteristic degradation or failure of a power semiconductor device. As a result, the overall reliability of the power inverter is reduced. LIST OF CITIONSPATENT LITERATURE

[0005] PTL 1: Japanese Patent Application Laid-Open No. 2013-219874 NON-PATENT LITERATURE

[0006] NPL 1: Andreas Marz et al., Comparison of SiC MOSFET gate-drive concepts to suppress parasitic turn -on in low inductance power modules, EPE, 2017. KURZDARSTELLUNG DER ERFINDUNGTECHNISCHES PROBLEM

[0007] In PTL 1, two voltages are applied to the gate terminal of the power semiconductor device: a first voltage and a second voltage lower than the first voltage. The turn-off operation of the power semiconductor device is performed at the first voltage, but the first voltage is generally not greater than the negative bias voltage applied to the gate terminal. In other words, the switching loss of the power semiconductor device increases compared to the case where the second voltage is used.In contrast, increasing the first voltage improves switching loss by accelerating the turn-on process. However, a negative bias voltage (e.g., the second voltage) greater than the first voltage must be continuously applied to the gate until the end of the turn-on process of the power semiconductor element on the opposite arm, including a dead time after the turn-off process. Therefore, this leads to the above-mentioned problem of stress on the gate oxide film, thereby reducing the overall reliability of the power converter.

[0008] In NPL 1, a negative bias voltage is applied to the gate terminal of a self-timer element for a period from the start of the turn-off operation of the power semiconductor element to the end of the turn-on operation of the power semiconductor element on the opposite arm. In other words, the negative bias voltage is continuously applied to the gate terminal of the self-timer element during the dead period and the switching period. Therefore, in a system or the like where the dead time is set to a long value, there is a concern that the effect of reducing the stress on the gate oxide film may be insufficient.

[0009] An object of the present disclosure is to provide a semiconductor device and a power conversion apparatus capable of improving the reliability of a power semiconductor element. SOLUTION TO THE PROBLEM

[0010] A semiconductor device according to an embodiment includes: a gate voltage control circuit that applies a turn-on bias voltage and a turn-off bias voltage to a gate terminal of a power semiconductor element according to a first drive signal; and a turn-off bias control circuit that adjusts a voltage level of the turn-off bias voltage according to the first drive signal and a second drive signal and controls a period of application of the adjusted turn-off bias voltage.

[0011] A power conversion device according to an embodiment includes: a first power semiconductor element; a second power semiconductor element provided on an opposite arm and connected in series with the first power semiconductor element; a first gate drive circuit provided for the first power semiconductor element and configured to drive the first power semiconductor element according to a first drive signal; and a second gate drive circuit provided for the second power semiconductor element and configured to drive the second power semiconductor element according to a second drive signal.The gate drive circuits each include: a gate voltage control circuit that applies a turn-on bias voltage and a turn-off bias voltage to a gate terminal of a corresponding power semiconductor element according to a corresponding drive signal; and a turn-off bias control circuit that adjusts a voltage level of a turn-off bias voltage according to the first and second drive signals and controls a period of application of the adjusted turn-off bias voltage. ADVANTAGEOUS EFFECTS OF THE INVENTION

[0012] According to the semiconductor device and the power conversion apparatus of the present disclosure, it is possible to improve the reliability of a power semiconductor element. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram illustrating a gate drive circuit 100 of a power semiconductor device according to a first embodiment; Fig. 2 is a diagram illustrating a concrete configuration of a first control circuit 21 and a second control circuit 31 according to the first embodiment; Fig. 3 is a diagram illustrating a timing chart when the gate drive circuit 100 according to the first embodiment controls the gate of a power semiconductor element 10; Fig. 4 is a diagram illustrating a gate drive circuit 101 according to a second embodiment; Fig. 5 is a diagram illustrating a timing chart when the gate drive circuit 101 according to the second embodiment controls the gate of a power semiconductor element; Fig. 6 is a block diagram illustrating a gate drive circuit 100# of a power semiconductor device according to a third embodiment; Fig. 7 is a diagram illustrating a concrete configuration of a first control circuit 21# and a second control circuit 31# according to the third embodiment; Fig. 8 is a diagram illustrating a waveform of a gate voltage Vgs of a SiC MOSFET to which the gate drive circuit 100 of the present disclosure is applied; Fig. 9 is a diagram illustrating a timing chart when a gate drive circuit 101 according to a fifth embodiment controls the gate of the power semiconductor element; Fig. 10 is a block diagram illustrating a driver integrated circuit 102 according to a sixth embodiment; and Fig. 11 is a block diagram illustrating a configuration of a power conversion system according to a seventh embodiment. DESCRIPTION OF EMBODIMENTSFirst embodiment.

[0013] A gate drive circuit of a power semiconductor device which is an example of the present disclosure will be described below.

[0014] Fig. 1 is a block diagram illustrating a gate driver circuit 100 according to a first embodiment.

[0015] With reference to Fig. 1, the gate driver circuit 100 controls the gate of a power semiconductor element 10 connected between high-voltage DC power supplies according to the input of an external drive signal IN1 and an external drive signal IN2. Specifically, the gate driver circuit 100 controls an on / off operation, i.e., a switching operation, of the power semiconductor element 10.

[0016] The power semiconductor element 10 corresponds to a switching element of a main circuit in an inverter circuit of a power conversion device. For example, the power semiconductor element 10 is an element of a 2-in-1 half-bridge circuit, a 4-in-1 full-bridge circuit, or a 6-in-1 three-phase inverter. In these circuit configurations, since the output voltage of the inverter is generated according to PWM control, a high voltage of several hundred volts or more is applied between the drain and source of the element during the OFF operation. Furthermore, a high current flows through the element during the ON operation according to the system of the power conversion device. In these operating states, the gate voltage for turning the power semiconductor element 10 on or off is controlled according to the external drive signal IN1.

[0017] The gate driver circuit 100 includes a gate voltage control circuit 20 and a turn-off bias control circuit 30.

[0018] The gate voltage control circuit 20 controls a turn-on bias voltage and a turn-off bias voltage of the gate of the power semiconductor element 10.

[0019] The gate voltage control circuit 20 includes a first control circuit 21 and a first switching circuit 22.

[0020] The first control circuit 21 controls a gate control signal so that a desired switching operation of the power semiconductor element 10 is performed according to the input external drive signal IN1. Specifically, the gate control signal is set to "1" during a period in which the power semiconductor element 10 should be turned on, and the gate control signal is set to "0" during a period in which the power semiconductor element 10 should be turned off. These binary voltage signals can be obtained by generating a pulse wave using a communication signal source, such as a 5V system or a 3.3V system, in a logic circuit.

[0021] The first circuit 22 is arranged between the gate of the power semiconductor element 10 and the first control circuit 21. The high side of the first circuit 22 is connected to a positive voltage source Vdd, and the low side thereof is connected to a second circuit 32.

[0022] The first circuit 22 includes an NPN transistor 22A, a PNP transistor 22B and a resistance element 22C.

[0023] The NPN transistor 22A and the PNP transistor 22B are connected in series.

[0024] The NPN transistor 22A is connected to the source Vdd of positive voltage and is connected to an output node.

[0025] The PNP transistor 22B is connected to the output node and an output node of the second circuit 32.

[0026] The gate of the NPN transistor 22A and the gate of the PNP transistor 22B are connected to the first control circuit 21 via the resistance element 22C.

[0027] The first switching circuit 22 can switch the current path according to a gate control signal output from the first control circuit 21. As a result, the current path through which the gate current flows in the power semiconductor element 10 is changed, corresponding to switching between gate charging and gate discharging. Therefore, the first switching circuit 22 switches a gate voltage to be applied to the gate of the power semiconductor element 10 to control the on / off operation of the power semiconductor element 10.

[0028] The turn-off bias control circuit 30 controls the voltage level of a turn-off bias applied to the gate during the OFF operation of the power semiconductor element 10 according to the external drive signal IN1 and the external drive signal IN2. Specifically, the turn-off bias control circuit 30 always sets the voltage level below 0 V during the OFF operation of the power semiconductor element 10, because if the voltage level is a positive value, it may exceed the gate threshold voltage of the power semiconductor element 10.

[0029] In addition, the number of voltage levels of the turn-off bias to be switched is, for example, two.

[0030] In the present embodiment, the external drive signal IN1 and the external drive signal IN2 are used to switch the two voltage levels of the turn-off voltage. The external drive signal IN1 is equal to the input signal to the first control circuit 21. The external drive signal IN2 is required to provide the gate drive circuit 100 with timing information of a gate misturn (also referred to as a self-turn-on phenomenon) of the power semiconductor element 10, which will be described later. The external drive signal IN2 is provided as a means different from the external drive signal IN1.

[0031] The turn-off bias control circuit 30 includes a second control circuit 31 and a second switching circuit 32.

[0032] The second control circuit 31 outputs a turn-off bias control signal capable of arbitrarily adjusting a voltage level of a turn-off bias applied to the gate of the power semiconductor element 10 and an application period of the turn-off bias based on the input of the external drive signal IN1 and the external drive signal IN2. A specific scheme will be described below.

[0033] The second circuit 32 is connected to the second control circuit 31, the first circuit 22 and the source electrode of the power semiconductor element 10.

[0034] The high side of the second circuit 32 is connected to a source electrode of the power semiconductor element 10 and the low side thereof is connected to a negative voltage source Vneg.

[0035] The second circuit 32 includes an NPN transistor 32A, a PNP transistor 32B and a resistance element 32C.

[0036] The NPN transistor 32A and the PNP transistor 32B are connected in series.

[0037] The NPN transistor 32A is connected to the source electrode of the power semiconductor element 10 and is connected to an output node. The output node is connected to the first switching circuit 22.

[0038] The PNP transistor 32B is connected to the output node and the negative voltage source Vneg.

[0039] The gate of the NPN transistor 32A and the gate of the PNP transistor 32B are connected to the second control circuit 31 via the resistance element 32C.

[0040] The second switching circuit 32 switches the gate turn-off voltage level according to a turn-off voltage control signal generated by the second control circuit 31. Specifically, the second switching circuit switches a reference potential Vs based on the source potential of the power semiconductor element 10 and switches the negative voltage source Vneg. In other words, the voltage level of a turn-off bias voltage to be applied to the gate of the power semiconductor element 10 is switched by switching the source potential of the power semiconductor element 10.

[0041] Hereinafter, the state in which the reference potential Vs is connected may be referred to as a “shallow turn-off bias”, and the state in which the negative voltage source Vneg is connected may be referred to as a “deep turn-off bias”, if appropriate.

[0042] However, the shallow turn-off bias voltage and the deep turn-off bias voltage applied to the gate of the power semiconductor element 10 are based on the OFF operation of the power semiconductor element 10. Therefore, the shallow turn-off bias voltage and the deep turn-off bias voltage to be applied to the gate of the power semiconductor element 10 are not uniquely determined by the operation of the second switching circuit 32, but are switched by the first switching circuit 22 only during the OFF operation of the power semiconductor element 10. In other words, the voltage level of the turn-off bias voltage applied to the gate of the power semiconductor element 10 is controlled based on the state of the gate voltage control circuit 20 and the turn-off bias control circuit 30.

[0043] The first control circuit 21 or the second control circuit 31 may include a passive element such as a resistor, a capacitor, or a diode, and an RC filter as components not shown in the figure. The first control circuit or the second control circuit may include a Schmitt trigger element configured to tune a transmission signal. The first control circuit 21 includes a delay line (which may be implemented by a delay IC or a buffer circuit) that delays the transmission signal by a certain period of time, and the second control circuit 31 includes a logical operation circuit that performs a logical operation such as a logical OR or a logical AND on the transmission signal.

[0044] Furthermore, the first switching circuit 22 and the second switching circuit 32 have a totem-pole circuit structure in which switching elements are arranged on the upper and lower arms as components not shown in the figure and can perform two-stage control on outputs according to an input gate control signal. Specifically, the circuit may be configured as a push-pull circuit, with the high-side element being an NPN transistor and the low-side element being a PNP transistor, as described above, or may have any other configuration.

[0045] Fig. 2 is a diagram illustrating a concrete configuration of the first control circuit 21 and the second control circuit 31 according to the first embodiment.

[0046] With reference to Fig. 2, the first control circuit 21 includes a control unit 21A and a delay circuit 21B.

[0047] The control unit 21A receives the external drive signal IN1 as an input signal and generates a tuned signal. For example, the control unit 21A may be implemented by a capacitor for holding a voltage, a diode element for preventing reverse conduction, and a Schmitt trigger element for tuning the transmission signal.

[0048] Delay circuit 21B receives an output signal from control unit 21A, delays the output signal by a specified period of time, and generates a delay signal. For example, delay circuit 21B may be a delay line that delays the transmission signal by a specified period of time, and the delay line may be formed from a logic IC or a buffer element.

[0049] By forming the first control circuit 21 in this way, the gate control signal input to the Fig. 1 is delayed by a certain period of time based on the external drive signal IN1. The operation of the first switching circuit 22 can also be delayed by the same period of time in response to the delay amount of the gate control signal. Therefore, the switching operation of the power semiconductor element 10 is also delayed by the same period of time. Furthermore, the gate delay amount of the power semiconductor element 10 can be variably set by providing a plurality of terminals for each of the logic IC and the buffer element constituting the delay line, by setting different delay amounts for the logic IC and the buffer element, or by using a jumper pin to switch the connection point of the circuit.

[0050] The second control circuit 31 includes delay circuits 31A and 31B, inverters IV0 and IV1, AND circuits AD0 and AD1, and a NOR circuit NR.

[0051] The AND circuit AD0 receives the external drive signal IN1 via the delay circuit 31A and the external drive signal IN1 via the inverter IV0 and outputs an AND logic operation result to the NOR circuit NR.

[0052] The AND circuit AD1 receives the external drive signal IN2 via the delay circuit 31B and the inverter IV1 and the external drive signal IN2 directly, and outputs an AND logic operation result to the NOR circuit NR.

[0053] The NOR circuit NR receives inputs from the AND circuits AD0 and AD1 and outputs a NOR logic operation result.

[0054] Delay circuits 31A and 31B are configured to generate a delay signal. For example, the delay circuit may be an RC filter, which is a general delay time adjustment circuit, or may include a Schmitt trigger element for tuning a transmission signal. The delay amount of delay circuit 31A may be different from the delay amount of delay circuit 31B.

[0055] The NOR circuit NR normally outputs an off-bias control signal (“1”).

[0056] As a result, the NPN transistor 32A of the second switching circuit 32 is turned on.

[0057] On the other hand, when the external drive signal IN1 changes from "1" to "0," the AND circuit AD0 outputs a monostable pulse signal proportional to the delay amount of the delay circuit 31A. In response, the NOR circuit NR turns on the PNP transistor 32B of the second switching circuit 32 during the period of the monostable pulse signal.

[0058] When the external drive signal IN2 changes from "0" to "1," the AND circuit AD1 outputs a monostable pulse signal proportional to the delay amount of the delay circuit 31B. In response, the NOR circuit NR turns on the PNP transistor 32B of the second switching circuit 32 during the period of the monostable pulse signal.

[0059] The second control circuit 31 is a logic operation circuit that receives two signals of the external drive signals IN1 and IN2, performs a logical operation, such as a logical OR or a logical AND, on the two signals, and generates a single off-bias control signal from the two output signals. For example, the second control circuit may be formed from a discrete IC element in which only one element is integrated, or may be formed from a 2-in-1 logic IC with two logic functions. The second control circuit may include at least one AND element and at least one OR element as a logical operation.

[0060] Due to the provision of the delay circuits 31A and 31B, it is possible to generate a turn-off bias control signal according to the external drive signal IN1 and the external drive signal IN2, and it is possible to adjust the timing of the turn-off bias control signal.

[0061] Specifically, it is possible to determine a timing and period of applying the deep turn-off bias voltage Vneg to the gate of the power semiconductor element 10 in response to the delay amount of the delay circuits 31A and 31B. The resistor or capacitor in the RC filter of each of the delay circuits 31A and 31B may be a variable resistor or a variable capacitor. With such a configuration, it is possible to variably adjust a timing and period of applying the deep turn-off bias voltage Vneg to the power semiconductor element 10.

[0062] According to the first embodiment, since the control unit 21A and the delay circuit 21B are provided in the first control circuit 21 included in the gate voltage control circuit 20, and the delay circuits 31A and 31B are provided in the second control circuit 31 included in the turn-off bias control circuit 30, it is possible to generate an appropriate turn-off bias level control signal, and it is possible to determine the timing and period of applying the deep turn-off bias voltage Vneg to the power semiconductor element 10. As a result, the reliability of the power semiconductor element 10 is improved.

[0063] Next, a concrete operation of the gate drive circuit 100 according to the first embodiment will be described.

[0064] Fig. 3 is a diagram illustrating a timing chart when the gate drive circuit 100 according to the first embodiment controls the gate of the power semiconductor element 10.

[0065] With reference to Fig. 3 illustrates operational differences between the gate drive circuit 100 according to the first embodiment and the comparative example. The horizontal axis represents time, and the vertical axis represents an external drive signal IN1, an external drive signal IN2, and a gate voltage Vgs of the power semiconductor element 10.

[0066] At time t0, the external drive signal IN1 changes from "1" to "0," and in response, the gate drive circuit 100 begins to discharge the gate of the power semiconductor element 10. In other words, the power semiconductor device 10 is turned off. As the charges of the gate, which is charged during the ON operation, are discharged, the gate voltage Vgs of the power semiconductor element begins to drop.

[0067] First, the gate voltage Vgs drops sharply from a turn-off bias voltage Vdd. Then, while a drain-source voltage Vds (not shown) of the power semiconductor element 10 begins to rise, the gate voltage Vgs is maintained at a certain constant voltage value. This period is called the mirror period and lasts until the parasitic gate-drain capacitance, which depends on the drain-source voltage Vds, no longer changes (generally, the mirror period in the SiC MOSFET is very short). After the end of the mirror period, the gate voltage Vgs begins to drop again and reaches the deep turn-off bias voltage Vneg, thereby ending the turn-off operation. Thus, there are major differences between the gate drive circuit according to the first embodiment and the comparative example (the configuration described in PTL 1).

[0068] The most significant difference is the presence or absence of the deep turn-off bias Vneg.

[0069] Since the gate drive circuit 100 according to the first embodiment is provided with a function of applying the deep turn-off bias voltage Vneg to the gate, the turn-off speed of the power semiconductor element 10 is faster than that of the comparative example not provided with the function of applying the deep turn-off bias voltage. In the interval from time t0 to the start of the mirror period and from the end of the mirror period to the end of the turn-off operation, the absolute value of a change rate dVgs / dt of the gate voltage Vgs is larger in the configuration according to the first embodiment than in the configuration of the comparative example.

[0070] This effect enables a reduction in the turn-off loss of the power semiconductor device 10, which has the advantages of suppressing heat generation of the power conversion device and reducing the size of the heat sink.

[0071] In contrast, in the configuration according to the comparative example, since the turn-off operation is performed by the flat turn-off bias voltage Vs, there are concerns that the reduction in the turn-off loss of the power semiconductor element 10 is insufficient. Furthermore, there are differences in the behavior of the gate voltage Vgs after the end of the turn-off operation.

[0072] Since the configuration according to the first embodiment has the deep turn-off bias voltage Vneg, the gate voltage Vgs drops from the shallow turn-off bias voltage Vs to the deep turn-off bias voltage Vneg.

[0073] In the gate drive circuit 100 according to the first embodiment, the turn-off operation of the power semiconductor element 10 is completed at the time t1 at which the gate voltage Vgs reaches the deep turn-off bias voltage Vneg.

[0074] According to the configuration of the gate drive circuit 100 according to the first embodiment, since the deep turn-off bias voltage Vneg is applied to the gate of the power semiconductor element 10 from time t1, which may cause characteristic deterioration or failure due to the stress on the gate oxide film as described above, the period from time t1 to time t2 at which the deep turn-off bias voltage Vneg starts to return to the shallow turn-off bias voltage Vs is sufficiently shorter than a dead period Td (both the upper arm and the lower arm are off) set in the inverter circuit of the power conversion device. In other words, the actual stress on the gate oxide film is very small. Therefore, high reliability of the power semiconductor element 10 can be ensured.

[0075] In the present embodiment, the deep turn-off bias voltage Vneg is applied to the gate of the power semiconductor element 10 during the period from time t0 to time t2. This period is defined as a first period. Next, the operations after time t2 will be described.

[0076] During the dead period Td, the gate voltage Vgs of the power semiconductor element 10 is set to the flat turn-off bias voltage Vs, and the external drive signal IN1 and the external drive signal IN2 are both set to “0”.

[0077] In the present embodiment, the external drive signal IN2 has a function of notifying the timing of a misturn on of the gate of the power semiconductor element 10, in other words, the turn-on timing of the opposite arm element.

[0078] Thus, the external drive signal IN2 changes from "0" to "1" at the end of the dead period Td.

[0079] The gate driver circuit 100 determines, based on the change in the external drive signal IN2, that it is time to turn on the opposite arm element of the power semiconductor element 10 and changes the gate voltage Vgs of the power semiconductor element 10 from the shallow turn-off bias voltage Vs to the deep turn-off bias voltage Vneg. Then, the opposite arm element is turned on, thereby raising the gate voltage Vgs of the power semiconductor element 10 from the deep turn-off bias voltage Vneg. Since the deep turn-off bias voltage Vneg is set higher than the raised voltage value of the gate voltage Vgs, the gate voltage Vgs does not exceed 0 V. In other words, there is a sufficient margin for the gate threshold voltage of the power semiconductor element 10.

[0080] The period from time t3 to time ton, at which the opposite arm element of the power semiconductor device 10 actually begins the turn-on process, coincides with the delay amount of the gate control signal to the opposite arm element. Since it takes some time for the deep turn-off bias voltage Vneg to be applied to the gate voltage Vgs of the power semiconductor device 10, a delay of the gate control signal to the opposite arm element is introduced. This makes it possible to reliably prevent the gate of the power semiconductor device 10 from being turned on incorrectly.

[0081] At time t4, after the turn-on operation of the opposite arm element of the power semiconductor element 10 is completed, the gate voltage Vgs of the power semiconductor element 10 begins to return from the deep turn-off bias voltage Vneg to the shallow turn-off bias voltage Vs. In other words, the stress on the gate oxide film of the power semiconductor element 10 is very small. In other words, during the period from time t3 to time t4, the deep turn-off bias voltage Vneg is applied to the gate of the power semiconductor element 10. In the present embodiment, the period from the end of the dead period Td until the shallow turn-off bias voltage is applied to the gate of the power semiconductor element 10 is defined as a second period. In other words, the period from time t3 to time t4 is included in the second period.

[0082] The gate drive circuit 100 according to the first embodiment can reduce switching loss by applying a deep turn-off bias to the power semiconductor device 10, and can improve the reliability of the power semiconductor device 10 by limiting the application time of the deep turn-off bias to a limited interval within the first period and the second period. As a result, the lifetime of the power semiconductor device can be extended, making the power conversion system economical. Second embodiment.

[0083] In a second embodiment, the operation of a gate driver circuit 101 is described, which includes a gate resistance control circuit 40 arranged between the power semiconductor element 10 and the first switching circuit 22.

[0084] Fig. 4 is a diagram illustrating the gate drive circuit 101 according to the second embodiment.

[0085] With reference to Fig. 4, the gate drive circuit 101 differs from the gate drive circuit 100 according to the first embodiment in that the gate resistance control circuit 40 is arranged between the power semiconductor element 10 and the first switching circuit 22. Since the other configurations are the same, their detailed description will not be repeated.

[0086] The gate resistance control circuit 40 includes a gate resistance 41 and a bypass switching element 42 connected in parallel to both ends of the gate resistance 41.

[0087] The gate resistor 41 adjusts a switching speed, in particular a turn-on speed and a turn-off speed, of the power semiconductor element 10.

[0088] When the resistance of the gate resistor 41 is large, the surge voltage of the drain-source voltage Vds and the electromagnetic noise at the time of switching can be reduced, but the switching loss increases. Conversely, when the resistance of the gate resistor 41 is small, the relationship between the surge voltage of the drain-source voltage Vds, the electromagnetic noise, and the switching loss is opposite to that of the case where the resistance is large.

[0089] The bypass switching element 42 performs a turn-on operation and a turn-off operation in response to an ON / OFF command of the gate control signal. The bypass switching element 42 is connected in parallel with the gate resistor 41. After the bypass switching element 42 is turned on, a gate current flows through the bypass switching element 42, and after the bypass switching element is turned off, the gate current flows through the gate resistor 41.

[0090] The timing at which the bypass switching element 42 according to the second embodiment is turned on to bypass the gate resistor 41 corresponds to the timing at which the turn-off bias level of the gate is switched between the deep turn-off bias voltage Vneg and the shallow turn-off bias voltage Vs.

[0091] Specifically, the bypass switching element 42 is maintained in the OFF state during the first period until the turn-off operation of the power semiconductor element 10 is completed, and the bypass switching element 42 is turned on after the turn-off operation of the power semiconductor element 10 is completed and the turn-off bias voltage is switched from the deep turn-off bias voltage Vneg to the shallow turn-off bias voltage Vs.

[0092] For example, the bypass switching element 42 is turned on during the period from time Tb1 to time Tb2.

[0093] Also, the timing at which the bypass switching element 42 according to the second embodiment is turned off and switched to the path via the gate resistor 41 is a period from the time at which the dead period Td ends to a time prepared for the turn-on operation of the opposite arm element, in other words, a period from a time at which the shallow turn-off bias voltage Vs is switched to the deep turn-off bias voltage Vneg to the start of the turn-on operation of the opposite arm element.

[0094] Specifically, during the second period, the bypass switching element 42 is maintained in the ON state until the shallow turn-off bias voltage Vs is switched to the deep turn-off bias voltage Vneg, and the bypass switching element 42 is turned off before the turn-on operation of the opposite arm element.

[0095] For example, the bypass switching element 42 is turned on during the period from time T3 to time Tb3.

[0096] By operating the bypass switching element 42 as described above, the bypass path without the gate resistor 41 is used only to switch the deep turn-off bias voltage Vneg and the shallow turn-off bias voltage Vs to be applied to the gate of the power semiconductor element 10.

[0097] As mentioned above, in the first embodiment, the second switching circuit 32 operates in conjunction with the first switching circuit 22. In other words, the switching speed of the deep turn-off bias voltage Vneg and the shallow turn-off bias voltage Vs depends on the conduction constant of the discharge path of the power semiconductor element 10. In short, when the resistance of the gate resistor 41 is large, the switching speed of the deep turn-off bias voltage Vneg and the shallow turn-off bias voltage Vs becomes correspondingly slow. In the second embodiment, the bypass path without the gate resistor 41 makes it possible to increase the switching speed of the deep turn-off bias voltage Vneg and the shallow turn-off bias voltage Vs. In other words, it is possible to appropriately control the level and timing of the turn-off bias voltage applied to the gate of the power semiconductor element 10.

[0098] Furthermore, the gate resistor 41 is effective against gate misconnection. This is because when the gate resistance 41 is low (for example, 0 Ω), oscillation may occur due to a floating inductance component of the gate wiring of the power semiconductor element 10, which may lead to gate misconnection. Furthermore, susceptibility to electromagnetic noise may trigger gate misconnection. To counteract these phenomena, when gate misconnection occurs, in other words, when the opposite arm element is turned on, the bypass switching element 42 is turned off to establish a path through the gate resistor 41.

[0099] Next, a concrete operation of the gate drive circuit 101 according to the second embodiment will be described.

[0100] Fig. 5 is a diagram illustrating a timing chart when the gate drive circuit 101 according to the second embodiment controls the gate of the power semiconductor element.

[0101] With reference to Fig. 5, since the basic operation of the gate driving circuit 101 according to the second embodiment is the same as the basic operation of the gate driving circuit 100 according to the first embodiment, its detailed description will not be repeated.

[0102] At time t0, the power semiconductor device 10 is turned on. As illustrated in the figure, the gate voltage of the power semiconductor device 10 is lowered to the deep turn-off bias voltage Vneg, and the deep turn-off bias voltage Vneg is established at time t1. Thereafter, at time t2, the turn-off bias voltage is switched from the deep turn-off bias voltage Vneg to the shallow turn-off bias voltage Vs to shorten the application time of the deep turn-off bias voltage Vneg.

[0103] The difference from the gate drive circuit 100 according to the first embodiment is that the bypass switching element 42 is turned on at time tb1 in an interval between time t1 and time t2 included in the first period. By adding the operation at time tb1 in the present embodiment, the gate voltage of the power semiconductor element 10 changes at time t2. Specifically, the speed switching from the deep turn-off bias Vneg to the shallow turn-off bias Vs is increased, and it is possible to quickly return to the shallow turn-off bias Vs, as illustrated in the figure. Since the turn-off bias Vs quickly returns to the shallow turn-off bias Vs, the application time of the deep turn-off bias Vneg can be reliably shortened compared to that in the first embodiment.It should be noted that at time tb2 the bridging switching element 42 is turned off.

[0104] After the dead period Td has elapsed, the external drive signal IN2, which indicates the turn-on timing of the opposite arm element, changes from "0" to "1." In other words, the dead period Td ends at time t3.

[0105] At time t3, the gate voltage of the power semiconductor element 10 is again switched from the flat turn-off bias voltage Vs to the negative bias voltage Vneg.

[0106] At time t3, the bypass switching element 42 is turned on. Thus, the gate resistor 41 is bypassed, and as a result, the speed of switching from the shallow turn-off bias voltage Vs to the deep turn-off bias voltage Vneg becomes faster than that in the first embodiment, and as illustrated in the figure, it is possible to quickly apply the deep turn-off bias voltage Vneg to the gate of the power semiconductor element 10.

[0107] Then, the bypass switching element 42 is turned off at time tb3.

[0108] Subsequently, at time ton, the opposite arm element is turned on, and a gate misturn of the power semiconductor element 10 occurs. In the present embodiment, the bypass switching element 42 is turned off at time tb3 within an interval between time t3 and time ton included in the second period.

[0109] As described above, by adding the operation of the gate resistance control circuit 40 according to the second embodiment at time tb3, it is possible to prevent the gate misconnection of the power semiconductor element 10 from being caused by the floating inductance and electromagnetic noise. Specifically, by turning off the bypass switching element 42 to switch to the gate resistance 41, it is possible to achieve a gate misconnection tolerance equivalent to that of the first embodiment, as illustrated in the figure.

[0110] In the dead period Td after time tb2, in other words, in the off-bias period of the power semiconductor element 10, the gate resistance control circuit 40 turns off the bypass switching element 42 to connect the gate resistance 41. As described above, by keeping the gate resistance 41 connected even during the off operation of the power semiconductor element 10, it is possible to dampen the gate oscillation caused by external factors. As a result, the gate misconnection of the power semiconductor element 10 can be prevented.

[0111] The ON-operation period (tb1-tb2, t3-tb3) of the bypass switching element 42 can be adjusted by the components described in the first embodiment. Specifically, it can be implemented by combining the RC filter that delays the period from time t0 to time t1 and the logic operation circuit described in the first embodiment that generates a monostable pulse using the external drive signal IN1 and the external drive signal IN2. Furthermore, the ON-operation period (bypass period) of the bypass switching element 42 can also be arbitrarily adjusted, and the ON-operation and OFF-operation can also be switched via a plurality of locations.

[0112] The gate resistor 41 can be formed by a circuit element such as a general-purpose resistor or a chip resistor, as long as it has a conduction constant or a power capacitance according to the switching operation condition of the power semiconductor element 10. The number of circuit elements constituting the gate resistor 41 can be single or multiple, and the circuit configuration can be series or parallel. The bypass switching element 42 can be a low-cost discrete circuit element as long as it can cope with the gate capacitance of the power semiconductor element 10. The bypass switching element 42 desirably has a higher high-speed response.The trade-off relationship states that the higher the gate threshold voltage, the lower the risk of malfunction, but the lower the high-speed response; conversely, the lower the gate threshold voltage, the higher the high-speed response, but the higher the risk of malfunction.

[0113] The gate drive circuit 101 according to the second embodiment includes a gate resistance control circuit 40 arranged between the power semiconductor element 10 and the first switching circuit 22, which makes it possible to further shorten the period of the deep turn-off bias voltage Vneg applied to the gate of the power semiconductor element 10. Furthermore, by accelerating the switching from the shallow turn-off bias voltage Vs to the deep turn-off bias voltage Vneg, it is possible to further improve the reliability of the power semiconductor element 10.

[0114] Therefore, it is possible to further extend the lifetime of the power semiconductor element 10, making the power conversion system economical. Third embodiment.

[0115] In a third embodiment, a circuit having a different configuration from that of the first embodiment is described.

[0116] Fig. 6 is a block diagram illustrating a gate drive circuit 100# of the power semiconductor device according to the third embodiment.

[0117] With reference to Fig. 6, the gate drive circuit 100# differs from the gate drive circuit 100 in that the gate voltage control circuit 20 is replaced by a gate voltage control circuit 20# and the turn-off bias control circuit 30 is replaced by a turn-off bias control circuit 30#.

[0118] Since the other configurations are the same as those of the gate driving circuit 100 according to the first embodiment, the detailed description thereof will not be repeated.

[0119] The gate voltage control circuit 20# differs from the gate voltage control circuit 20 in that the first control circuit 21 is replaced by a first control circuit 21# and the first switching circuit 22 is replaced by a first switching circuit 22#.

[0120] The turn-off bias circuit 30# differs from the turn-off bias circuit 30 in that the second control circuit 31 is replaced by a second control circuit 31# and the second switching circuit 32 is replaced by a second switching circuit 32#.

[0121] The first circuit 22# includes a PMOSFET 22P on the high side and an NMOSFET 22N on the low side.

[0122] The PMOSFET 22P and the NMOSFET 22N are connected in series.

[0123] The PMOSFET 22P is connected to the positive voltage source Vdd and is connected to an output node.

[0124] The NMOSFET 22N is connected to the output node and an output node of the second circuit 32.

[0125] The second circuit 32# includes a PMOSFET 32P on the high side and an NMOSFET 32N on the low side.

[0126] The PMOSFET 32P and the NMOSFET 32N are connected in series.

[0127] The PMOSFET 32P is connected to the source electrode of the power semiconductor element 10 and is connected to the output node. The output node is connected to the first switching circuit 22#.

[0128] The NMOSFET 32N is connected to the output node and the negative voltage source Vneg. The circuit according to the third embodiment is particularly effective in a power conversion device to which, for example, a wide bandgap semiconductor is applied and which is used for a high-frequency drive application.

[0129] A CMOS circuit constituted by the PMOSFET 22P and the NMOSFET 22N and the PMOSFET 32P and the NMOSFET 32N according to the third embodiment will be described.

[0130] Since both the upper and lower arm elements are MOSFETs, power consumption is lower than when these elements are formed by bipolar transistors. Furthermore, as the switching frequency of the power inverter increases, the number of switching cycles of the gate driver circuit also increases accordingly. In other words, this is very useful for the high-frequency driver applications described above.

[0131] The output conduction of the 22P PMOSFET and the 22N NMOSFET fluctuates between the power supply voltage Vdd applied to the high side of the 22P PMOSFET and the potential applied to the low side (the shallow turn-off bias voltage Vs or the deep turn-off bias voltage Vneg). Furthermore, constant drive capability can be achieved regardless of the difference between the input voltage from the power supply voltage and the output voltage of the output line. With such a drive output, it is possible to implement the 100# gate drive circuit with high drive capability and high stability.

[0132] In contrast, in a general push-pull circuit, the output voltage fluctuation range is narrowed by the gate threshold voltage of the transistor elements on the upper and lower arms. In other words, if the output voltage is outside the fluctuation range, the output of the push-pull circuit will be floating, indicating unstable operation.

[0133] In the gate drive circuit 100# according to the third embodiment, the circuit is implemented using a CMOS circuit, and it is possible to achieve high drive capability and high stability. These effects are expected to improve the characteristics of the power semiconductor device 10 and prevent oscillations caused by gate potential fluctuations.

[0134] Although the advantages of CMOS circuitry have been described above, CMOS circuitry can also have disadvantages. At the time of switching between the upper and lower arm elements, a through current may flow between the high-side power supply voltage and the low-side reference potential. This through current may increase the power consumption of gate driver circuit 100. This increase in power consumption makes CMOS circuitry unsuitable for high-frequency drive operation, which contradicts the advantages described above.

[0135] Therefore, a dead period can be created between the upper and lower arms of the PMOSFET 22P and NMOSFET 22N, and the PMOSFET 32P and NMOSFET 32N. By providing an appropriate dead period, it is possible to reduce the through current flowing into the CMOS circuit. For example, the signals applied to the gates of the PMOSFET 22P and NMOSFET 22N, and the PMOSFET 32P and NMOSFET 32N can be controlled independently.

[0136] Fig. Fig. 7 is a diagram illustrating a concrete configuration of a first control circuit 21# and a second control circuit 31# according to the third embodiment. Since the basic element configuration and the like are the same as those of the first control circuit 21 and the second control circuit 31 shown in Fig. 2, their description is not repeated.

[0137] With reference to Fig. 7, the first control circuit 21# includes a control unit 21A# and a delay circuit 21B#.

[0138] The second control circuit 31# includes delay circuits 31A# and 31B#, an inverter IV, an AND circuit AD and an OR circuit OR.

[0139] The AND circuit AD receives the external drive signal IN2 via the delay circuit 31B# and the inverter IV, or receives the external drive signal IN2 without any elements or additional circuits, and outputs an AND logic operation result to the OR circuit OR.

[0140] The OR circuit receives the external drive signal IN1 via the delay circuit 31A# or receives an input from the AND circuit AD and outputs a result of an OR logic operation.

[0141] Delay circuits 31A# and 31B# are configured to generate a delay signal. For example, the delay circuit may be an RC filter, which is a general delay time adjustment circuit, or may include a Schmitt trigger element for tuning a transmission signal. The delay amount of delay circuit 31A# may be different from the delay amount of delay circuit 31B#.

[0142] The OR circuit OR outputs a turn-off bias control signal ("1") when the power semiconductor element 10 is in a steady ON state without switching operation, and outputs a turn-off bias control signal ("0") when the power semiconductor element is in a steady OFF state without switching operation.

[0143] As a result, the PMOSFET 32P of the second circuit 32# repeats the ON operation and the OFF operation with a constant cycle.

[0144] In contrast, the output of the turn-off bias control signal changes in a complex manner during the transition period of the switching operation. When the external drive signal IN1 changes from "1" to "0," the OR circuit OR maintains the output of "1" for a period proportional to the delay amount of the delay circuit 31A#. In response, the OR circuit OR turns on the NMOSFET 32N of the second switching circuit 32# in response to the period during which the output is maintained at "1."

[0145] When the external drive signal IN2 changes from "0" to "1," the AND circuit AD outputs a monostable pulse signal proportional to the delay amount of the delay circuit 31B#. Accordingly, the OR circuit OR turns on the NMOSFET 32N of the second switching circuit 32# in response to the monostable pulse signal.

[0146] According to the present embodiment, the PMOSFET 22P and the NMOSFET 22N are provided in the first control circuit 21 included in the gate voltage control circuit 20, and the PMOSFET 32P and the NMOSFET 32N are provided in the second control circuit 31 included in the turn-off bias control circuit 30. As a result, it is possible to suppress gate oscillation or the like in high-frequency applications while maintaining high characteristics of the power semiconductor element 10.

[0147] Furthermore, the configuration of the gate resistance control circuit 40 according to the second embodiment can be applied. Fourth embodiment.

[0148] In a fourth embodiment, the voltage level control of the turn-off bias voltage applied to the gate of the power semiconductor element 10 is described.

[0149] Fig. 8 is a diagram illustrating a waveform of the gate voltage Vgs of the SiC MOSFET to which the gate drive circuit 100 of the present disclosure is applied.

[0150] Fig. Figure 8 illustrates a case where the period of application of the deep turn-off bias is adjusted.

[0151] In the present embodiment, the gate turn-on bias voltage is set to +20 V, the shallow turn-off bias voltage Vs is set to 0 V, and the deep turn-off bias voltage Vneg is set to -5 V. The driving conditions were the same except for the period of the deep turn-off bias voltage Vneg.

[0152] The LA waveform represents a case where the application period of the off-bias voltage is shorter than that of the LB waveform. In other words, the two waveforms have different periods of the deep off-bias voltage Vneg.

[0153] The period of the deep turn-off bias voltage Vneg is adjusted by adjusting the time constant of the RC filter constituting the delay circuit included in the turn-off bias control circuit 30.

[0154] Specifically, the delay amount of the delay circuit is adjusted by adjusting the capacitance of the capacitor, thereby adjusting the period during which the turn-off bias voltage is applied.

[0155] In particular, in the case where two types of capacitance of 470 pF and 680 pF are provided as the capacitance of the capacitor in the delay circuit, the period of the deep turn-off bias voltage Vneg can be set to a shorter period by setting the capacitance of the capacitor to "470 pF." Thus, it is possible to further reduce the stress on the gate oxide film.

[0156] For example, if the capacitor is a variable capacitor, it is possible to adjust the turn-off bias period Vneg to an optimal period by adjusting the capacitance of the capacitor to an optimal capacitance. Fifth embodiment.

[0157] In a fifth embodiment, another aspect will be described regarding the operation of the gate driver circuit 100 including the gate resistance control circuit 40 according to the second embodiment.

[0158] Fig. 9 is a diagram illustrating a timing chart when a gate drive circuit 101 according to the fifth embodiment controls the gate of the power semiconductor element.

[0159] With reference to Fig. 9, the basic operation of the gate driving circuit 101 according to the fifth embodiment is the same as that of the gate driving circuit 100 according to the second embodiment, and therefore, its detailed description will not be repeated.

[0160] Compared to the time course diagram from Fig. 5, the bridging switching element 42, which is shown in the drawing with reference to Fig. 3, is turned on during an interval between time tb4 and time tb5 within the period between time ton and time t4.

[0161] Through this process, as in Fig. 9 illustrates, the gate voltage Vgs of the power semiconductor element 10 is quickly switched from the deep turn-off bias voltage Vneg to the shallow turn-off bias voltage Vs. As a result, the period of application of the deep turn-off bias voltage Vneg to the gate of the power semiconductor element 10 is reliably shortened.

[0162] The time tb4 at which the bypass switching element 42 is turned on is set to be between the time at which the turn-on operation of the opposite arm element of the power semiconductor element 10 is completed and the time t4. With this setting, it is possible to suppress oscillation of the gate of the power semiconductor element 10 during the turn-on period of the opposite arm element and avoid the risk of causing false turn-on. Furthermore, it is also possible to achieve the effect of shortening the period of applying the deep turn-off bias voltage Vneg to the power semiconductor element 10.

[0163] The present embodiment can be realized by providing additional elements to the configuration of Fig. 4. The additional element is provided with a function for controlling the gate resistance control circuit 40 to decrease the value of the gate resistance 41 and to determine the time tb3 at which the bypass switching element 42 is turned on.

[0164] In particular, time information of the time ton at which the opposite arm element of the power semiconductor element 10 is turned on is used to determine the time tb4.

[0165] For example, the timing information at time ton can be detected by providing an overvoltage detection circuit or a voltage change rate dVds / dt detection circuit between the drain and source electrodes of the power semiconductor element 10. Alternatively, a gate current detection circuit can be connected in series with and adjacent to the gate resistance control circuit 40. By synchronizing the detection information of these detection circuits with the signal of the second control circuit 31 included in the turn-off bias control circuit 30, it is possible to adjust the timing tb3 to an appropriate time.

[0166] Alternatively, the second control circuit 31 included in the turn-off bias control circuit 30 may be provided with a state timer with preset times. For example, the time tb4 may be set by measuring the time it takes to turn on the opposite arm element of the power semiconductor element 10 in a pre-conducted experiment.

[0167] In the fifth embodiment, the timing at which the bypass switching element 42 included in the gate resistance control circuit 40 is turned on is added to the configuration according to the second embodiment. As a result, the period for applying the deep turn-off bias voltage Vneg to the gate of the power semiconductor element 10 can be more appropriately shortened. Sixth embodiment.

[0168] In a sixth embodiment, the configuration of a driver integrated circuit 102 is described.

[0169] Fig. 10 is a block diagram illustrating the driver integrated circuit 102 according to the sixth embodiment.

[0170] With reference to Fig. 10, the integrated driver circuit 102 according to the sixth embodiment differs from the gate driver circuit 100 in that it is an integrated circuit integrated into two driver circuits of a gate driver circuit 100P and a gate driver circuit 100N.

[0171] The integrated driver circuit means that, for example, the upper arm and the lower arm are integrated and the power semiconductor elements are connected in series, and can be applied to a half-bridge circuit, which is often seen in a power module in which the power semiconductor elements are installed in a 2-in-1 structure, as in Fig. 10 illustrates.

[0172] The power semiconductor element 10P and the power semiconductor element 10N connected in series with each other, that is, the power semiconductor elements in the upper and lower arms, are driven by a single driver circuit, that is, the driver integrated circuit 102.

[0173] The input signals are the external driver signal IN1 and the external driver signal IN2.

[0174] As described in the first embodiment, the external drive signal may be a logic pulse signal as long as the external drive signal IN is set to "1" during a period in which a corresponding power semiconductor element should be turned on and the external drive signal IN is set to "0" during a period in which a corresponding power semiconductor element should be turned off.

[0175] In the present embodiment, the external drive signal IN1 controls the gate of the upper-arm power semiconductor element 10P and is input to the gate voltage control circuit 20P. The external drive signal IN2 controls the gate of the lower-arm power semiconductor element 10N and is input to the gate voltage control circuit 20N.

[0176] As described in the first embodiment, the external drive signal IN2 for notifying the turn-on timing of the lower arm power semiconductor element 10N, which is one of the opposing arm elements, is input to the turn-off bias control circuit 30P. The external drive signal IN1 for notifying the turn-on timing of the upper arm power semiconductor element 10P, which is the other of the opposing arm elements, is input to the turn-off bias control circuit 30N.

[0177] With such a configuration, the integrated driver circuit performs the same operation as the gate driver circuit 100 described in the first embodiment.

[0178] Gate driver circuit 100P and gate driver circuit 100N included in driver integrated circuit 102 have substantially the same circuit configuration, but when there are variations in element characteristics between the power semiconductor elements 10P and 10N of the upper and lower arms, turn-off bias control circuits 30P and 30N can perform fine adjustment internally. For example, by adjusting the timing of the deep turn-off bias voltage Vneg and the shallow turn-off bias voltage Vs with respect to turn-off bias control circuit 30P and turn-off bias control circuit 30N, more suitable operation of the power semiconductor elements can be achieved.

[0179] In the sixth embodiment, the external drive signal IN1 and the external drive signal IN2 are isolated by an insulating element having sufficient dielectric strength, for example, an insulating element such as a photocoupler or an insulating transformer inside the gate voltage control circuit 20P and the gate voltage control circuit 20N and inside the turn-off bias control circuit 30P and the turn-off bias control circuit 30N. The insulating element may be an isolator IC having a plurality of inputs and a plurality of outputs, and with such a configuration, the isolation process of the gate voltage control circuit 20P and the turn-off bias control circuit 30P can be shared.

[0180] A positive voltage source Vdd_P to be supplied to the gate driver circuit 100P must be an isolated power source, and the potential of the positive voltage source Vdd_P is a floating potential with respect to the ground potential. Each of the deep turn-off bias voltage Vneg_P and the shallow turn-off bias voltage Vs_P included in the gate driver circuit 100P is also a floating potential with respect to the ground potential. Since the positive voltage source Vdd_P is a floating power supply, for example, a three-terminal regulator can generate any potential, a suitable deep turn-off bias voltage Vneg_P, and a suitable shallow turn-off bias voltage Vs_P.

[0181] With such a configuration, the power semiconductor element 10P, which corresponds to the upper arm element in the half-bridge circuit, can be electrically and safely driven by the gate drive circuit 100P included in the drive integrated circuit 102.

[0182] In the present embodiment, the configuration of a half-bridge circuit was described, but the method according to the fifth embodiment can also be applied, for example, to a power module for a three-phase inverter in which the power semiconductor elements are installed in a 6-in-1 configuration.

[0183] The configuration according to the sixth embodiment includes an integrated driver circuit 102, which integrates the upper arm driver circuit and the lower arm driver circuit to drive the upper and lower arm elements in the half-bridge circuit of the power conversion device. As a result, the upper arm power semiconductor element 10P and the lower arm power semiconductor element 10N can be driven with a simple circuit configuration, without requiring additional addition or complicated processing of external drive signals. Seventh embodiment.

[0184] In a seventh embodiment, the power conversion device according to the above-described embodiment is applied to a power conversion system. Although the present disclosure is not limited to a specific power conversion system, the present disclosure in the seventh embodiment relates to a power conversion system to which a three-phase inverter is applied.

[0185] Fig. 11 is a block diagram illustrating a configuration example of a power conversion system according to the seventh embodiment.

[0186] With reference to Fig.11, the power conversion system according to the seventh embodiment includes a power supply 1000, a power conversion device 1001, and a load 1004. The power supply 1000 is a DC power supply that supplies DC power to the power conversion device 1001. The power supply 1000 can be constituted by various types of power supplies and can be constituted, for example, by a DC system, a solar cell, a storage battery, a rectifier circuit, or an AC / DC converter connected to an AC system. Furthermore, the power supply 1000 can be constituted by a DC / DC converter that converts DC power output from a DC system into a specific power.

[0187] The power conversion device 1001 is a three-phase inverter connected between the power supply 1000 and the load 1004, and is configured to convert DC power supplied from the power supply 1000 into AC power and supply the AC power to the load 1004. The power conversion device 1001 includes a main conversion circuit 1002 that converts DC power into AC power and outputs the AC power, and a control circuit 1003 that outputs a control signal for controlling the main conversion circuit 1002 to the main conversion circuit 1002.

[0188] The load 1004 is a three-phase electric motor driven by the AC power supplied from the power conversion device 1001. The load 1004 is not limited to a specific application and can be any electric motor mounted on various electrical devices, and can be used, for example, as an electric motor for a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an air conditioner.

[0189] The power conversion device 1001 is described in more detail below. The main conversion circuit 1002 includes a power semiconductor element and a freewheeling diode (not shown), converts DC power supplied from the power supply 1000 into AC power by switching the power semiconductor element, and supplies the AC power to the load 1004.

[0190] Although the main conversion circuit 1002 can have various specific circuit configurations, the main conversion circuit 1002 according to the embodiment is a two-stage three-phase full-bridge circuit and may be formed by six power semiconductor elements and six freewheeling diodes connected in parallel in the reverse direction. Two of the six power semiconductor elements are connected in series to form upper and lower arms, and each upper arm or each lower arm forms a phase (U-phase, V-phase, W-phase) of the full-bridge circuit. The output terminals of the upper and lower arms, in other words, the three output terminals of the main conversion circuit 1002, are connected to the load 1004.

[0191] The gate driving circuit described in the first to sixth embodiments and configured to drive each power semiconductor element can be applied to the main conversion circuit 1002.

[0192] The gate drive circuit generates a gate control signal that drives the power semiconductor element of the main conversion circuit 1002 and supplies the gate control signal to the control electrode of the power semiconductor element of the main conversion circuit 1002. Specifically, the control circuit 1003 outputs an external drive signal for turning on the power semiconductor element and an external drive signal for turning off the power semiconductor element to the control electrode of each power semiconductor element. When the switching element is maintained in the ON state, the external drive signal is a voltage signal (ON signal) equal to or higher than the threshold voltage of the power semiconductor element, and when the switching element is maintained in the OFF state, the external drive signal is a voltage signal (OFF signal) equal to or lower than the threshold voltage of the power semiconductor element.

[0193] The control circuit 1003 controls the power semiconductor element of the main conversion circuit 1002 so that the desired power is supplied to the load 1004. Specifically, the control circuit calculates a time (ON time) during which each power semiconductor element of the main conversion circuit 1002 should be turned on, based on the power to be supplied to the load 1004. For example, the main conversion circuit 1002 can be controlled by a PWM controller that modulates the ON time of the power semiconductor element according to the voltage to be output. Then, a control command (external drive signal) is output to a gate drive circuit included in the main conversion circuit 1002 so that, at each time, an ON signal is output to the power semiconductor element that should be turned on, or an OFF signal is output to the power semiconductor element that should be turned off.

[0194] In the power conversion device according to the present embodiment, since the above-described gate drive circuit constituting the main conversion circuit 1002 is employed, it is possible to improve the reliability.

[0195] In the present embodiment, the present disclosure is applied to a two-stage three-phase inverter, but the present disclosure is not limited thereto, and it can be applied to various types of power conversion devices. In the present embodiment, a two-stage power conversion device is used, but a three-stage or multi-stage power conversion device may be used, and the present disclosure can be applied to a single-phase inverter that supplies electric power to a single-phase load. The present disclosure can be applied to a DC / DC converter or an AC / DC converter that supplies electric power to a DC load, or the like.

[0196] Moreover, the power conversion device to which the present disclosure is applied is not limited to the case where the load is an electric motor, and can be used as a power supply device of an electric discharge machine, a laser cutting machine, an induction heating cooker, or a non-contact power supply system, and can also be used as a power enhancer of a solar power generation system, a power storage system, or the like.

[0197] It is understood that the embodiments disclosed herein are illustrative and not restrictive in all respects. Furthermore, it is understood that it is not difficult to combine a variety of embodiments in a suitable manner, and it is desirable to utilize the power conversion device efficiently and economically by further enhancing the effects of each embodiment.

[0198] The scope of the present invention is defined by the content of the claims rather than by the description of the above embodiments and is intended to include any modifications that are within the scope of the claims and the meaning equivalent to their content. LIST OF REFERENCE SYMBOLS

[0199] 10, 10N, 10P: power semiconductor element; 20, 20N, 20P: gate voltage control circuit; 21: first control circuit; 22: first switching circuit; 30, 30N, 30P: turn-off bias control circuit; 31: second control circuit; 32: second switching circuit; 40: gate resistance control circuit; 41: gate resistance; 42: bypass switching element; 100, 100N, 100P, 101: gate driver circuit; 102: driver integrated circuit; 1000: power supply; 1001: power conversion device; 1002: main conversion circuit; 1003: control circuit; 1004: load. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2013-219874

[0005] Cited non-patent literature

[0000] Andreas Marz et al., Comparison of SiC MOSFET gate-drive concepts to suppress parasitic turn-on in low inductance power modules, EPE, 2017

[0006]

Claims

[1] A semiconductor device comprising: a gate voltage control circuit that applies a turn-on bias voltage and a turn-off bias voltage to a gate terminal of a power semiconductor element according to a first drive signal; and a turn-off bias control circuit that adjusts a voltage level of the turn-off bias according to the first drive signal and a second drive signal and controls a period of application of the adjusted turn-off bias. [2] The semiconductor device according to claim 1, wherein the turn-off bias control circuit adjusts the voltage level of the turn-off bias in a first period in which the turn-off bias is applied according to the first drive signal and adjusts the voltage level of the turn-off bias in a second period in which the turn-off bias is applied according to the second drive signal. [3] A semiconductor device according to claim 2, wherein the second drive signal is a control signal for applying a turn-on bias voltage and a turn-off bias voltage to a gate terminal of a power semiconductor element provided on an opposite arm connected in series with the power semiconductor element, and the second period includes a period for completing a turn-on operation of the power semiconductor element provided on the opposite arm after a dead period. [4] The semiconductor device according to any one of claims 1 to 3, wherein the turn-off bias control circuit sets a first turn-off bias voltage to a second turn-off bias voltage lower than the first turn-off bias voltage according to the first and second drive signals. [5] A semiconductor device according to any one of claims 1 to 4, further comprising: a gate resistance control circuit provided between the power semiconductor device and the gate voltage control circuit and configured to control a gate resistance of the power semiconductor device. [6] The semiconductor device according to claim 5, wherein the gate resistance control circuit controls the gate resistance when adjusting the voltage level of the turn-off bias voltage. [7] The semiconductor device according to claim 6, wherein the gate resistance control circuit increases the gate resistance before the voltage level of the turn-off bias is changed, and decreases the gate resistance when the voltage level of the turn-off bias is adjusted. [8] The semiconductor device according to any one of claims 5 to 7, wherein the gate resistance control circuit includes a resistance element provided between the power semiconductor element and the gate voltage control circuit, and a bypass circuit that bypasses the resistance element. [9] A semiconductor device according to any one of claims 1 to 8, wherein the turn-off bias control circuit includes: a first delay circuit that delays the first drive signal; a second delay circuit that delays the second drive signal; a logic circuit that generates a switching signal based on a combination of a delay signal from the first delay circuit and a delay signal from the second delay circuit; and a circuit that adjusts the voltage level of a turn-off bias voltage based on the switching signal. [10] Power conversion device comprising: a first power semiconductor element; a second power semiconductor element provided on an opposite arm and connected in series with the first power semiconductor element; a first gate driver circuit provided for the first power semiconductor element and configured to drive the first power semiconductor element according to a first driver signal; and a second gate driver circuit provided for the second power semiconductor element and configured to drive the second power semiconductor element according to a second driver signal, the gate driver circuits each include: a gate voltage control circuit that applies a turn-on bias voltage and a turn-off bias voltage to a gate terminal of a corresponding power semiconductor element according to a corresponding drive signal; and a turn-off bias control circuit that adjusts a voltage level of a turn-off bias according to the first and second drive signals and controls a period of application of the adjusted turn-off bias.

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