PIXEL CIRCUIT, CONTROL METHOD AND DISPLAY DEVICE

Abstract

A pixel circuit, a driving method, and a display device are provided. The pixel circuit includes a light-emitting element, a driver circuit, a first energy storage circuit, a first control circuit, and a data write circuit. The first control circuit is configured to control the connection between the first node and the second node under the control of a first light emission control signal. A first terminal of the first energy storage circuit is electrically connected to the second node, and a second terminal of the first energy storage circuit is electrically connected to the second terminal of the driver circuit. The first energy storage circuit is configured to store electrical energy. The data write circuit is configured to write a data voltage to the second node under the control of a first strobe signal.After the source follower threshold voltage compensation is used, the voltage difference between the two terminals of the energy storage circuit does not change under the condition that one terminal of the first energy storage circuit is floating, the threshold voltage compensation is realized.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of display technology, in particular to a pixel circuit, a driving method and a display device. BACKGROUND

[0002] In the prior art, the pixel circuit with internal threshold voltage compensation can fully compensate for the characteristic deviation of the threshold voltage of the driver transistor, but the number of capacitors is large, which is not conducive to the realization of a narrow frame. SUMMARY

[0003] In a first aspect, the present disclosure provides, in some embodiments, a pixel circuit comprising a light-emitting element, a driver circuit, a first energy storage circuit, a first control circuit, and a data write circuit; wherein a control terminal of the driver circuit is electrically connected to a first node, a first terminal of the driver circuit is electrically connected to a power supply voltage terminal, and a second terminal of the driver circuit is electrically connected to the light-emitting element; the driver circuit is configured to drive the light-emitting element under the control of a potential of the control terminal of the driver circuit;a control terminal of the first control circuit is electrically connected to a first light emission control line, a first terminal of the first control circuit is electrically connected to the first node, and a second terminal of the first control circuit is electrically connected to a second node; the first control circuit is configured to control the connection between the first node and the second node under the control of a first light emission control signal provided by the first light emission control line; a first terminal of the first energy storage circuit is electrically connected to the second node, and a second terminal of the first energy storage circuit is electrically connected to the second terminal of the driver circuit; the first energy storage circuit is configured to store electrical energy;the data write circuit is electrically connected to a first sensing terminal, the second node, and a data line, and is configured to write a data voltage provided by the data line to the second node under the control of a first sensing signal provided by the first sensing terminal;

[0004] Optionally, the pixel circuit further comprises a first reference voltage writing circuit; wherein the first reference voltage writing circuit is electrically connected to a second reset terminal and the first node, and the first reference voltage writing circuit is also electrically connected to a reference voltage terminal or the power supply voltage terminal and is configured to write a reference voltage provided by the reference voltage terminal or a power supply voltage provided by the power supply voltage terminal to the first node under the control of a second reset signal provided by the second reset terminal.

[0005] Optionally, the pixel circuit further comprises a second reference voltage write circuit; wherein the second reference voltage write circuit is electrically connected to a first reset terminal, the reference voltage terminal, and the first node, respectively, and is configured to write the reference voltage to the first node under the control of the first reset signal provided by the first reset terminal.

[0006] Optionally, the pixel circuit further comprises a first light emission control circuit; wherein the first light emission control circuit is electrically connected to the second light emission control line, the power supply voltage terminal, and the first terminal of the driver circuit, and is configured to control the connection between the power supply voltage terminal and the first terminal of the driver circuit under the control of the second light emission control signal provided by the second light emission control line.

[0007] Optionally, the pixel circuit further comprises a second light emission control circuit; wherein the second light emission control circuit is electrically connected to the second light emission control line, the second terminal of the driver circuit, and a first terminal of the light-emitting element, and is configured to control the connection between the second terminal of the driver circuit and the first terminal of the light-emitting element under the control of the second light emission control signal provided by the second light emission control line.

[0008] Optionally, the pixel circuit further comprises a first initialization circuit; wherein the first initialization circuit is electrically connected to a first reset terminal, a first reset voltage terminal, and the second terminal of the driver circuit, and is configured to write a first reset voltage provided by the first reset voltage terminal to the second terminal of the driver circuit under the control of a first reset signal provided by the first reset terminal; wherein the first reset voltage terminal comprises an initial voltage terminal, a first voltage terminal, a reference voltage terminal, or the power supply voltage terminal.

[0009] Optionally, the driver circuit comprises a driver transistor, the first control circuit comprises a first transistor, and the first energy storage circuit comprises a first capacitor; a gate electrode of the first transistor is electrically connected to the first light emission control line, a first electrode of the first transistor is electrically connected to the first node, and a second electrode of the first transistor is electrically connected to the second node; a gate electrode of the driver transistor is electrically connected to the first node, a first electrode of the driver transistor is electrically connected to the power supply voltage terminal, and a second electrode of the driver transistor is electrically connected to the light-emitting element;a first terminal of the first capacitor is electrically connected to the second node, and a second terminal of the first capacitor is electrically connected to a second electrode of the driver transistor;

[0010] Optionally, the first reference voltage writing circuit comprises a second transistor; a gate electrode of the second transistor is electrically connected to the second reset terminal, a first electrode of the second transistor is electrically connected to the reference voltage terminal, and a second electrode of the second transistor is electrically connected to the first node; or the gate electrode of the second transistor is electrically connected to the second reset terminal, the first electrode of the second transistor is electrically connected to the power supply voltage terminal, and the second electrode of the second transistor is electrically connected to the first node.

[0011] Optionally, the second reference voltage writing circuit comprises a third transistor; a gate electrode of the third transistor is electrically connected to the first reset terminal, a first electrode of the third transistor is electrically connected to the reference voltage terminal, and a second electrode of the third transistor is electrically connected to the first node.

[0012] Optionally, the first light emission control circuit comprises a fourth transistor; a gate electrode of the fourth transistor is electrically connected to the second light emission control line, a first electrode of the fourth transistor is electrically connected to the power supply voltage terminal, and a second electrode of the fourth transistor is electrically connected to the first terminal of the driver circuit; the second light emission control circuit comprises a fifth transistor; a gate electrode of the fifth transistor is electrically connected to the second light emission control line, a first electrode of the fifth transistor is electrically connected to the second terminal of the driver circuit, a second electrode of the fifth transistor is electrically connected to the first terminal of the light emitting element.

[0013] Optionally, the first initialization circuit comprises a sixth transistor; a gate electrode of the sixth transistor is electrically connected to the first reset terminal, a first electrode of the sixth transistor is electrically connected to the initial voltage terminal, the first voltage terminal, the reference voltage terminal, or the power supply voltage terminal, and a second electrode of the sixth transistor is electrically connected to the second terminal of the driver circuit.

[0014] Optionally, the pixel circuit further comprises a second energy storage circuit and a second initialization circuit; wherein a second terminal of the first energy storage circuit is electrically connected to the second terminal of the driver circuit via the second energy storage circuit; a first terminal of the second energy storage circuit is electrically connected to a third node, a second terminal of the second energy storage circuit is electrically connected to the second terminal of the driver circuit, and the second energy storage circuit is configured to store electrical energy;the second initialization circuit is electrically connected to a sensing terminal, the second terminal of the driver circuit, and the second reset voltage terminal, and is configured to control the connection between the second terminal of the driver circuit and the second reset voltage terminal under the control of a sensing signal provided by the sensing terminal; the second reset voltage terminal comprises an initial voltage terminal, a first voltage terminal, or a third node; the sensing terminal comprises a first sensing terminal or a second sensing terminal;

[0015] Optionally, the pixel circuit further comprises a second energy storage circuit, a first reference voltage write circuit, a data write circuit, and a first initialization circuit; wherein the second node is electrically connected to the first node via the second energy storage circuit; the first reference voltage write circuit is electrically connected to each of the reset terminal, the reference voltage terminal, and the first node and is configured to write the reference voltage provided by the reference voltage terminal to the first node under the control of the reset signal provided by the reset terminal;The data write circuit is electrically connected to the first sensing terminal, the second node, and the data line, and is configured to write the data voltage provided by the data line to the second node under the control of the first sensing signal provided by the first sensing terminal; The first initialization circuit is electrically connected to the reset terminal, the initial voltage terminal, and the second terminal of the driver circuit, and is configured to write the initial voltage provided by the initial voltage terminal to the second terminal of the driver circuit under the control of the reset signal provided by the reset terminal.

[0016] In a second aspect, an embodiment of the present disclosure provides a pixel circuit comprising a light-emitting element, a driver circuit, a power storage unit, a first control circuit, a data write circuit, and a second initialization circuit; wherein a control terminal of the driver circuit is electrically connected to a first node, a first terminal of the driver circuit is electrically connected to a power supply voltage terminal, and a second terminal of the driver circuit is electrically connected to the light-emitting element; the driver circuit is configured to drive the light-emitting element under the control of a potential of the control terminal of the driver circuit;a control terminal of the first control circuit is electrically connected to a first light emission control line, a first terminal of the first control circuit is electrically connected to the first node, and a second terminal of the first control circuit is electrically connected to a second node; the first control circuit is configured to control the connection between the first node and the second node under the control of a first light emission control signal provided by the first light emission control line; the data write circuit is electrically connected to a first sensing terminal, the second node, and a data line, and is configured to write a data voltage provided by the data line to the second node under the control of a first sensing signal provided by the first sensing terminal;the second initialization circuit is electrically connected to a sensing terminal, the second terminal of the driver circuit, and a second reset voltage terminal, and is configured to control the connection between the second terminal of the driver circuit and the second reset voltage terminal under the control of a sensing signal provided by the sensing terminal; the energy storage unit comprises a first energy storage circuit, a second energy storage circuit, and a second write-in circuit; a first terminal of the first energy storage circuit is electrically connected to the second node, a second terminal of the first energy storage circuit is electrically connected to the third node, and the first energy storage circuit is configured to store electrical energy;A first terminal of the second energy storage circuit is electrically connected to the third node, a second terminal of the second energy storage circuit is electrically connected to the second terminal of the driver circuit, and the second energy storage circuit is configured to store electrical energy; the second write circuit is electrically connected to a reset terminal and the third node and is configured to control a potential of the third node under the control of a reset signal provided by the reset terminal.

[0017] Optionally, the pixel circuit further comprises the second reset voltage terminal comprising an initial voltage terminal, a first voltage terminal, or a third node; the sensing terminal comprising a first sensing terminal or a second sensing terminal.

[0018] Optionally, the pixel circuit further comprises a first write-in circuit; wherein the first write-in circuit is electrically connected to the reset terminal, a write-in voltage terminal, and a write-in node, and is configured to write a write-in voltage provided by the write-in voltage terminal into the write-in node under the control of the reset signal provided by the reset terminal; wherein the write-in node comprises the first node or the third node, and the write-in voltage terminal comprises a reference voltage terminal or the power supply voltage terminal.

[0019] Optionally, the second write circuit is further electrically connected to a first reset voltage terminal and configured to write a first reset voltage provided by the first reset voltage terminal to the third node under the control of the reset signal provided by the reset terminal; the first reset voltage terminal includes the initial voltage terminal, the first voltage terminal, the reference voltage terminal, or the power supply voltage terminal.

[0020] Optionally, the second write circuit is further electrically connected to the control terminal of the driver circuit and configured to control the connection between the control terminal of the driver circuit and the third node under the control of the reset signal.

[0021] Optionally, the pixel circuit further comprises a first light emission control circuit; wherein the first light emission control circuit is electrically connected to a second light emission control line, the power supply voltage terminal, and the first terminal of the driver circuit, and is configured to control the connection between the power supply voltage terminal and the first terminal of the driver circuit under the control of a second light emission control signal provided by the second light emission control line.

[0022] Optionally, the first energy storage circuit comprises a first capacitor; the second energy storage circuit comprises a second capacitor, and the second initialization circuit comprises a seventh transistor; a gate electrode of the seventh transistor is electrically connected to a first sense terminal or a second sense terminal, a first electrode of the seventh transistor is electrically connected to a second reset voltage terminal, and a second electrode of the seventh transistor is electrically connected to the second terminal of the driver circuit; a first electrode of the seventh transistor is electrically connected to a second reset voltage terminal, and a second electrode of the seventh transistor is electrically connected to the second terminal of the driver circuit;a first terminal of the first capacitor is electrically connected to the second node, and a second terminal of the first capacitor is electrically connected to the third node; a first terminal of the second capacitor is electrically connected to the third node, and a second terminal of the second capacitor is electrically connected to the second terminal of the driver circuit;

[0023] Optionally, the first write-in circuit comprises an eighth transistor; a gate electrode of the eighth transistor is electrically connected to the reset terminal, a first electrode of the eighth transistor is electrically connected to the reference voltage terminal, and a second electrode of the eighth transistor is electrically connected to the control terminal of the driver circuit.

[0024] Optionally, the second write circuit comprises a ninth transistor; a gate electrode of the ninth transistor is electrically connected to the reset terminal, a first electrode of the ninth transistor is electrically connected to the first reset voltage terminal, and a second electrode of the ninth transistor is electrically connected to the third node.

[0025] Optionally, the second write circuit comprises a ninth transistor; a gate electrode of the ninth transistor is electrically connected to the reset terminal, a first electrode of the ninth transistor is electrically connected to the third node, and a second electrode of the ninth transistor is connected to the control circuit of the driver circuit.

[0026] Optionally, the first light emission control circuit comprises a fourth transistor; a gate electrode of the fourth transistor is electrically connected to the second light emission control line, a first electrode of the fourth transistor is electrically connected to the power supply voltage terminal, and a second electrode of the fourth transistor is electrically connected to the first terminal of the driver circuit.

[0027] Optionally, the data write circuit comprises a tenth transistor; a gate electrode of the tenth transistor is electrically connected to the first scanning terminal, a first electrode of the tenth transistor is electrically connected to the second node, and a second electrode of the tenth transistor is electrically connected to the data line; the first control circuit comprises a first transistor; a gate electrode of the first transistor is electrically connected to the first light emission control line, a first electrode of the first transistor is electrically connected to the first node, and a second electrode of the first transistor is electrically connected to the second node.

[0028] In a third aspect, an embodiment of the present disclosure provides a driving method applied to the pixel circuit, the driving method comprising: driving the light-emitting element by the driving circuit under the control of the potential of the control terminal of the driving circuit; controlling the connection between the first node and the second node by the first control circuit under the control of the first light-emission control signal provided through the first light-emission control line; storing electric power by the first power storage circuit; writing the data voltage provided through the data line to the second node by the data writing circuit under the control of the first sensing signal provided through the first sensing terminal.

[0029] Optionally, the pixel circuit further comprises a first initialization circuit; the display period includes a first phase and a second phase which are sequentially set, and the driving method further comprises: in the first phase, the first initialization circuit writes the first reset voltage to the second terminal of the driver circuit; in the second phase, the first initialization circuit writes the first reset voltage to the second terminal of the driver circuit; the data write circuit writes the data voltage provided from the data line to the second node under the control of the first strobe signal.

[0030] In a fourth aspect, an embodiment of the present disclosure provides a driving method applied to the pixel circuit, the driving method comprising: driving the light-emitting element by the driving circuit under the control of the potential of the control terminal of the driving circuit; controlling the connection between the first node and the second node by the first control circuit under the control of the first light-emitting control signal provided by the first light-emitting control line; storing electric energy by the first energy storage circuit; storing electric energy by the second energy storage circuit; writing the data voltage provided by the data line to the second node by the data writing circuit under the control of the first scanning signal provided by the first scanning terminal;Controlling the connection between the second terminal of the driver circuit and the second reset voltage terminal by the second initialization circuit under the control of the scan signal provided by the scan terminal; Controlling the potential of the third node by the second write circuit under the control of the reset signal provided by the reset terminal;

[0031] Optionally, the pixel circuit further comprises a first write-in circuit; the display period includes a first phase and a second phase which are sequentially set; the driving method includes: in the first phase, the first write-in circuit writes the write-in voltage to the control terminal of the driver circuit, the second initialization circuit controls to connect the second terminal of the driver circuit and the second reset voltage terminal, the second write-in circuit writes the first reset voltage to the third node, and the data write-in circuit writes the data voltage provided from the data line to the second node; in the second phase, the first write-in circuit writes the write-in voltage to the control terminal of the driver circuit, and the second write-in circuit writes the first reset voltage to the third node.

[0032] Optionally, the pixel circuit further comprises a first write-in circuit; the display period includes a first phase and a second phase which are sequentially set; the driving method comprises: in the first phase, the first write-in circuit writes the write-in voltage into the control terminal of the driver circuit or the third node, and the second initialization circuit controls to connect the second terminal of the driver circuit and the second reset voltage terminal, the second write-in circuit controls to connect the control terminal of the driver circuit and the third node, and the data write-in circuit writes the data voltage provided by the data line into the second node;In the second phase, the first write circuit writes the write voltage to the control terminal of the driver circuit or the third node, and the second write circuit controls to connect the control terminal of the driver circuit and the third node.;

[0033] In a fifth aspect, an embodiment of the present disclosure provides a display device comprising the pixel circuit. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 8 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 9 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 10 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 11 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 12 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 13 is a working time diagram of the Fig. 12 shown pixel circuit; Fig. 14 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 15 is a working time diagram of the Fig. 14 shown pixel circuit; Fig. 16 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 17 is a working time diagram of the Fig. 16 shown pixel circuit; Fig. 18 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 19 is a working time diagram of the Fig. 18 shown pixel circuit; Fig. 20 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 21 is a working time diagram of the Fig. 20 pixel circuit shown; Fig. 22 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 23 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 24 is a working time diagram of the Fig. 23 shown pixel circuit; Fig. 25 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 26 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 27 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 28 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 29 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 30 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 31 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 32 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 33 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 34 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 35 is a working time diagram of the Fig. 34 pixel circuit shown; Fig. 36 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 37 is a working time diagram of the Fig. 36 pixel circuit shown; Fig. 38 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 39 is a working time diagram of the Fig. 38 pixel circuit shown; Fig. 40 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 41 is a working time diagram of the Fig. 40 pixel circuit shown; Fig. 42 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 43 is a working time diagram of the Fig. 42 shown pixel circuit; Fig. 44 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 45 is a working time diagram of the Fig. 44 pixel circuit shown; Fig. 46 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 47 is a working time diagram of the Fig. 46 pixel circuit shown; Fig. 48 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 49 is a working time diagram of the Fig. 48 pixel circuit shown; Fig. 50 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 51 is a working time diagram of the Fig. 50 pixel circuit shown; Fig. 52 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 53 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 54 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; Fig. 55 is a working time diagram of the Fig. 54 shown pixel circuit. DETAILED DESCRIPTION

[0034] In the following, the technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present disclosure, not all of them. Starting from the embodiments in the present disclosure, all other embodiments that can be achieved by those skilled in the art without creative effort are within the scope of the present disclosure.

[0035] The transistors used in all embodiments of the present disclosure may be thin-film transistors or field-effect transistors or other devices with the same properties. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor, with the exception of the control electrode, one electrode is referred to as the first electrode and the other electrode as the second electrode.

[0036] If the transistor is a thin-film transistor or a field-effect transistor, the control electrode may be a gate electrode, the first electrode a drain electrode, and the second electrode a source electrode; or the control electrode may be a gate electrode, the first electrode a source electrode, and the second electrode a drain electrode.

[0037] As in Fig. 1, the pixel circuit described in the present embodiment includes a light-emitting element EL, a driving circuit 11, a first energy storage circuit 12, a first control circuit 13, and a data writing circuit 72;

[0038] A control terminal of the driver circuit 11 is electrically connected to a first node N1, a first terminal of the driver circuit 11 is electrically connected to a power supply voltage terminal ELVDD, and a second terminal of the driver circuit 11 is electrically connected to the light-emitting element EL; the driver circuit 11 is configured to drive the light-emitting element EL under the control of a potential of the control terminal of the driver circuit 11;

[0039] A control terminal of the first control circuit 13 is electrically connected to a first light emission control line EM1, a first terminal of the first control circuit 13 is electrically connected to a first node N1, and a second terminal of the first control circuit 13 is electrically connected to a second node N2; the first control circuit 13 is configured to control the connection between the first node N1 and the second node N2 under the control of a first light emission control signal provided by the first light emission control line EM1;

[0040] A first terminal of the first energy storage circuit 12 is electrically connected to the second node N2, and a second terminal of the first energy storage circuit 12 is electrically connected to the second terminal of the driver circuit 11; the first energy storage circuit 12 is configured to store electrical energy;

[0041] The data write circuit 72 is electrically connected to a first sensing terminal G1, the second node N2, and a data line Da, and is configured to write a data voltage Vdata provided by the data line Da into the second node N2 under the control of a first sensing signal provided by the first sensing terminal G1.

[0042] When the pixel circuit described in the embodiment of the present disclosure is operated after using the threshold voltage compensation in a source-follower manner and the voltage difference between the two terminals of the energy storage circuit 12 does not change under the condition that one terminal of the first energy storage circuit 12 (the first energy storage circuit 12 may include a capacitor) is floating, the threshold voltage compensation is realized.

[0043] The pixel circuit described in at least one embodiment of the present disclosure further comprises a first reference voltage write circuit;

[0044] The first reference voltage writing circuit is electrically connected to a second reset terminal and the first node, and the first reference voltage writing circuit is also electrically connected to a reference voltage terminal or the power supply voltage terminal, is configured to write the reference voltage provided by the reference voltage terminal or a power supply voltage provided by the power supply voltage terminal into the first node under the control of a second reset signal provided by the second reset terminal.

[0045] In a specific implementation, the pixel circuit may further include a first reference voltage writing circuit, and the first reference voltage writing circuit writes a reference voltage or a power supply voltage into the first node under the control of the second reset signal.

[0046] As in Fig. 2, the pixel circuit described in at least one embodiment of the present disclosure comprises, based on at least one embodiment of the Fig. 1 further comprises a first reference voltage writing circuit 21;

[0047] The first reference voltage writing circuit 21 is electrically connected to the second reset terminal R2, the reference voltage terminal VR and the first node N1 and is configured to write the reference voltage Vref provided by the reference voltage terminal VR into the first node N1 under the control of the second reset signal provided at the second reset terminal R2.

[0048] As in Fig. 3, the pixel circuit of at least one embodiment of the present disclosure additionally comprises a first reference voltage write circuit 21 based on at least one embodiment of the pixel circuit shown in Fig. 1 shown pixel circuit;

[0049] The first reference voltage write circuit 21 is electrically connected to the second reset terminal R2, the power supply voltage terminal ELVDD, and the first node N1, and is configured to write the power supply voltage provided by the power supply voltage terminal ELVDD into the first node N1 under the control of the second reset signal provided by the second reset terminal R2.

[0050] Optionally, the second reset terminal and the first scan terminal are the same signal terminal; the pixel circuit further includes a second reference voltage write circuit;

[0051] The second reference voltage writing circuit is electrically connected to the first reset terminal, the reference voltage terminal, and the first node, respectively, and is configured to write the reference voltage to the first node under the control of the first reset signal provided from the first reset terminal.

[0052] As in Fig. 4, in at least one embodiment of the Fig. In the pixel circuit shown in Figure 2, the second reset terminal and the first scanning terminal G1 are one and the same signal terminal; the pixel circuit also includes a second reference voltage write circuit 41;

[0053] The first reference voltage writing circuit 21 is electrically connected to the first sensing terminal G1, the reference voltage terminal VR, and the first node N1, and is configured to write the reference voltage Vref provided by the reference voltage terminal VR into the first node N1 under the control of the second reset signal provided by the second reset terminal R2;

[0054] The second reference voltage writing circuit 41 is electrically connected to the first reset terminal R1, the reference voltage terminal VR, and the first node N1, and is configured to write the reference voltage Vref into the first node N1 under the control of the first reset signal provided from the first reset terminal R1.

[0055] The pixel circuit described in at least one embodiment of the present disclosure further comprises a first light emission control circuit;

[0056] The first light emission control circuit is electrically connected to the second light emission control line, the power supply voltage terminal, and the first terminal of the driver circuit, and is configured to control the connection between the power supply voltage terminal and the first terminal of the driver circuit under the control of the second light emission control signal provided by the second light emission control line.

[0057] As in Fig. 5, the pixel circuit described in at least one embodiment of the present disclosure comprises, based on at least one embodiment of the Fig. 2 further comprises a first light emission control circuit 51;

[0058] The first light emission control circuit 51 is electrically connected to the second light emission control line EM2, the power supply voltage terminal ELVDD, and the first terminal of the driver circuit 11, and is configured to control the connection between the power supply voltage terminal ELVDD and the first terminal of the driver circuit 11 under the control of the second light emission control signal provided from the second light emission control line EM2.

[0059] In at least one embodiment of the present disclosure, the pixel circuit further comprises a second light emission control circuit;

[0060] The second light emission control circuit is electrically connected to a second light emission control line, wherein a second terminal of the driver circuit and a first terminal of the light emitting element are configured to connect the second terminal of the driver circuit and the first terminal of the light emitting element under the control of the second light emission control signal provided by the second light emission control line.

[0061] As in Fig. 6, the pixel circuit comprises at least one embodiment of the Fig. 5 also includes a second light emission control circuit 61;

[0062] The second light emission control circuit 61 is electrically connected to the second light emission control line EM2, the second terminal of the second light emission control circuit 61, and the first terminal of the light emitting element EL, respectively, and is configured to connect the second terminal of the driver circuit 11 and the first terminal of the light emitting element EL under the control of the second light emission control signal provided from the second light emission control line EM2.

[0063] The pixel circuit described in at least one embodiment of the present disclosure further comprises a first initialization circuit;

[0064] The first initialization circuit is electrically connected to the first reset terminal, a first reset voltage terminal, and a second terminal of the driver circuit and configured to write the first reset voltage provided by the first reset voltage terminal to the second terminal of the driver circuit under the control of the first reset signal provided by the first reset terminal;

[0065] The first reset voltage terminal includes an initial voltage terminal, a first voltage terminal, a reference voltage terminal, or a power supply voltage terminal.

[0066] In at least one embodiment of the present disclosure, the first reset voltage terminal may include an initial voltage terminal, a first voltage terminal, a reference voltage terminal, or a power supply voltage terminal, and the first reset voltage may be an initial voltage, a first voltage, a reference voltage, or a power supply voltage, but is not limited thereto. In actual operation, the first reset voltage terminal may include other voltage terminals, and the reset voltage may be other voltage signals according to actual needs.

[0067] In at least one embodiment of the present disclosure, the first voltage terminal may be, but is not limited to, a low voltage terminal.

[0068] Optionally, the data write circuit includes a tenth transistor;

[0069] A gate electrode of the tenth transistor is electrically connected to a first sense terminal, a first electrode of the tenth transistor is electrically connected to the second node, and a second electrode of the tenth transistor is electrically connected to the data line.

[0070] As in Fig. 7, the pixel circuit described in at least one embodiment of the present disclosure comprises, based on at least one embodiment of the Fig. 2 further comprises a first initialization circuit 71;

[0071] The first initialization circuit 71 is electrically connected to the first reset terminal R1, the initial voltage terminal I1, and the second terminal of the driver circuit 11, and is configured to write the initial voltage Vint provided by the initial voltage terminal I1 to the second terminal of the driver circuit 11 under the control of the first reset signal provided by the first reset terminal R1.

[0072] As in Fig. 8, the pixel circuit described in at least one embodiment of the present disclosure comprises, based on at least one embodiment of the Fig. 3 further comprises a first initialization circuit 71;

[0073] The first initialization circuit 71 is electrically connected to the first reset terminal R1, the low voltage terminal ELVSS and the second terminal of the driver circuit 11 and configured to write the low voltage signal provided by the low voltage terminal ELVSS to the second terminal of the driver circuit 11 under the control of the first reset signal provided by the first reset terminal R1.

[0074] As in Fig. 9, the pixel circuit described in at least one embodiment of the present disclosure comprises, based on at least one embodiment of the Fig. 4 further comprises a first initialization circuit 71;

[0075] The first initialization circuit 71 is electrically connected to the first reset terminal R1, the initial voltage terminal I1, and the second terminal of the driver circuit 11, and is configured to write the initial voltage Vint provided by the initial voltage terminal I1 to the second terminal of the driver circuit 11 under the control of the first reset signal provided by the first reset terminal R1.

[0076] As in Fig. 10, the pixel circuit described in at least one embodiment of the present disclosure comprises, based on at least one embodiment of the Fig. 5 further comprises a first initialization circuit 71;

[0077] The first initialization circuit 71 is electrically connected to the first reset terminal R1, the initial voltage terminal I1 and the second terminal of the driver circuit 11 and configured to write the initial voltage Vint provided by the initial voltage terminal I1 to the second terminal of the driver circuit 11 under the control of the first reset signal provided by the first reset terminal R1.

[0078] As in Fig. 11, the pixel circuit described in at least one embodiment of the present disclosure comprises, based on at least one embodiment of the Fig. 6 further comprises a first initialization circuit 71;

[0079] The first initialization circuit 71 is electrically connected to the first reset terminal R1, the initial voltage terminal I1, and the second terminal of the driver circuit 11, and is configured to write the initial voltage Vint provided by the initial voltage terminal I1 to the second terminal of the driver circuit 11 under the control of the first reset signal provided by the first reset terminal R1.

[0080] Optionally, the driver circuit comprises a driver transistor, the first control circuit comprises a first transistor, and the first energy storage circuit comprises a first capacitor;

[0081] A gate electrode of the first transistor is electrically connected to the first light emission control line, a first electrode of the first transistor is electrically connected to the first node, and a second electrode of the first transistor is electrically connected to the second node;

[0082] A gate electrode of the driver transistor is electrically connected to the first node, a first electrode of the driver transistor is electrically connected to the power supply voltage terminal, and a second electrode of the driver transistor is electrically connected to the light-emitting element;

[0083] A first terminal of the first capacitor is electrically connected to the second node, and a second terminal of the first capacitor is electrically connected to a second electrode of the driver transistor.

[0084] Optionally, the first reference voltage write circuit comprises the second transistor;

[0085] A gate electrode of the second transistor is electrically connected to the second reset terminal, a first electrode of the second transistor is electrically connected to the reference voltage terminal, and a second electrode of the second transistor is electrically connected to the first node; or,

[0086] A gate electrode of the second transistor is electrically connected to the second reset terminal, a first electrode of the second transistor is electrically connected to the supply voltage terminal, and a second electrode of the second transistor is electrically connected to the first node;

[0087] Optionally, the second reference voltage writing circuit comprises a third transistor;

[0088] A gate electrode of the third transistor is electrically connected to the first reset terminal, a first electrode of the third transistor is electrically connected to the reference voltage terminal, and a second electrode of the third transistor is electrically connected to the first node.

[0089] Optionally, the first light emission control circuit comprises a fourth transistor;

[0090] A gate electrode of the fourth transistor is electrically connected to the second light emission control line, a first electrode of the fourth transistor is electrically connected to the power supply voltage terminal, and a second electrode of the fourth transistor is electrically connected to the first terminal of the driver circuit;

[0091] The second light emission control circuit includes a fifth transistor;

[0092] A gate electrode of the fifth transistor is electrically connected to the second light emission control line, a first electrode of the fifth transistor is electrically connected to the second terminal of the driver circuit, a second electrode of the fifth transistor is electrically connected to the first terminal of the light emitting element.

[0093] Optionally, the first initialization circuit comprises a sixth transistor;

[0094] A gate electrode of the sixth transistor is electrically connected to the first reset terminal, a first electrode of the sixth transistor is electrically connected to the initial voltage terminal, the first voltage terminal, the reference voltage terminal, or the power supply voltage terminal, and a second electrode of the sixth transistor is electrically connected to the second terminal of the driver circuit.

[0095] As in Fig. 12, the driver circuit comprises at least one embodiment of the Fig. The pixel circuit shown in Figure 7 includes a driver transistor DT, the first control circuit includes a first transistor T1, and the first energy storage circuit includes a first capacitor C1; the light-emitting element is an organic light-emitting diode O1;

[0096] The gate electrode of the first transistor T1 is electrically connected to the first light emission control line EM1, the source electrode of the first transistor T1 is electrically connected to the first node N1, and the drain electrode of the first transistor T1 is electrically connected to the second node N2;

[0097] The gate electrode of the driver transistor DT is electrically connected to the first node N1, the drain electrode of the driver transistor DT is electrically connected to the power supply voltage terminal ELVDD, and the source electrode of the driver transistor DT is electrically connected to the anode of the organic light-emitting diode O1; the cathode of the organic light-emitting diode O1 is electrically connected to the low-voltage terminal ELVSS;

[0098] The first terminal of the first capacitor C1 is electrically connected to the second node N2, and the second terminal of the first capacitor C1 is electrically connected to the source electrode of the driver transistor DT;

[0099] The first reference voltage writing circuit comprises a second transistor T2;

[0100] The gate electrode of the second transistor T2 is electrically connected to the second reset terminal R2, the source electrode of the second transistor T2 is electrically connected to the reference voltage terminal VR, and the drain electrode of the second transistor T2 is electrically connected to the first node N1;

[0101] The first initialization circuit comprises a sixth transistor T6;

[0102] The gate electrode of the sixth transistor T6 is electrically connected to the first reset terminal R1, the source electrode of the sixth transistor T6 is electrically connected to the initial voltage terminal I1, and the drain electrode of the sixth transistor T6 is electrically connected to the source electrode of the driver transistor DT;

[0103] The data write circuit comprises a tenth transistor T10;

[0104] The gate electrode of the tenth transistor T10 is electrically connected to the first sense terminal G1, the source electrode of the tenth transistor T10 is electrically connected to the second node N2, and the drain electrode of the tenth transistor T10 is electrically connected to the data line Da.

[0105] In at least one embodiment of the Fig. In the pixel circuit shown in Figure 12, all transistors are n-type transistors, but not limited to them.

[0106] As in Fig. 13, the display period includes a first phase S1, a second phase S2, a third phase S3 and a fourth phase S4, which are set sequentially when at least one embodiment of the Fig. 12 shown pixel circuit is in operation;

[0107] In the first phase S1, EM1 provides a low voltage signal, R1 provides a high voltage signal, G1 provides a low voltage signal, R2 provides a high voltage signal, T2 is turned on, and T6 is turned on to write the reference voltage Vref provided by VR to the gate electrode of DT, write the initial voltage Vint provided by I1 to the source electrode of DT, reset the gate potential of DT, the anode potential of O1, and the potential of the source electrode of DT;

[0108] In the second phase S2, EM1 provides a low voltage signal, R1 provides a high voltage signal, G1 provides a high voltage signal, R2 provides a high voltage signal, T6, T10 and T2 are all turned on to write the data voltage Vdata provided by the data line Da to the second node N2, write the reference voltage Vref provided by the reference voltage terminal VR to the first node N1 and write the initial voltage Vin provided by the initial voltage terminal I1 to the source electrode of the DT;

[0109] In the third phase S3, EM1 supplies a low-voltage signal, R1 supplies a low-voltage signal, G1 supplies a high-voltage signal, R2 supplies a high-voltage signal, and Da supplies the data voltage Vdata. At this time, T6 is off, T2 is on, T10 is on, and the gate potential of DT is Vref;

[0110] At the beginning of the third phase S3, the DT is turned on to charge C1 and increase the potential of the source electrode of the DT until the potential of the source electrode of the DT reaches Vref-Vth, and the DT is turned off;

[0111] In the fourth phase S4, EM1 supplies a high-voltage signal, T1 and DT are turned on, and the potential of N1 is equal to that of N2. Since N1 is in a floating state, the voltage difference across C1 remains unchanged before and after DT is turned on. At this time, the difference between the potential of the first node and the potential of the source electrode of DT is Vdata-Vref+Vth, the gate-source voltage of DT is Vdata-Vref+Vth, and the current flowing through O1 is K(Vdata-Vref). 2; The above formula shows that since Vref is a fixed voltage, the drain-source current Ids supplied to O1 can be appropriately determined from the data voltage Vdata; the current flowing through O1 has no relationship with the threshold voltage of the driver transistor and the supply voltage provided by ELVDD, and the threshold voltage compensation can be implemented.

[0112] At least one embodiment of the Fig. 12 of the present disclosure, wherein in the second phase S2, both R1 and G1 provide a high voltage signal, T6 is turned on, and T10 is turned on to write the data voltage Vdata provided by the data line Da into the second node N2 and control the potential of the second terminal of C1 to be the initial voltage Vint.

[0113] In at least one embodiment of the present disclosure, in the second phase S2, the first reset signal provided by R1 and the first scan signal provided by G1 are simultaneously the high voltage signal to prevent T6 from being turned on first, so that after the initial voltage Vint provided by I1 is applied to N2, T10 is turned on to apply the data voltage provided by Da to N1. At this time, the potential of N2 will change due to C1, so it cannot be maintained at Vint; and in the embodiment of the present disclosure, in the second phase S2, T6, and T10 are turned on simultaneously, so the above-mentioned problems will not occur.

[0114] Furthermore, in at least one embodiment of the present disclosure, the time for which the first reset signal provided by R1 remains at the high level may be the same as the time for which the first strobe signal provided by G1 remains at the high level, that is, the first strobe signal may be delayed by a predetermined time from the first reset signal, which may reduce the use of a Gate On Array (GOA, a gate driver circuit arranged on the array substrate), and the first reset signal and the first strobe signal are provided simultaneously by a GOA.

[0115] As in Fig. 14, the driver circuit comprises at least one embodiment of the Fig. 9, the pixel circuit includes a driver transistor DT, the first control circuit includes a first transistor T1, and the first energy storage circuit includes a first capacitor C1; the light-emitting element is an organic light-emitting diode O1;

[0116] The gate electrode of the first transistor T1 is electrically connected to the first light emission control line EM1, the source electrode of the first transistor T1 is electrically connected to the first node N1, and the drain electrode of the first transistor T1 is electrically connected to the second node N2;

[0117] The gate electrode of the driver transistor DT is electrically connected to the first node N1, the drain electrode of the driver transistor DT is electrically connected to the power supply voltage terminal ELVDD, and the source electrode of the driver transistor DT is electrically connected to the anode of the organic light-emitting diode O1; the cathode of the organic light-emitting diode O1 is electrically connected to the low-voltage terminal ELVSS;

[0118] The first terminal of the first capacitor C1 is electrically connected to the second node N2, and the second terminal of the first capacitor C1 is electrically connected to the source electrode of the driver transistor DT;

[0119] The first reference voltage writing circuit comprises a second transistor T2;

[0120] The gate electrode of the second transistor T2 is electrically connected to the first sense terminal G1, the source electrode of the second transistor T2 is electrically connected to the reference voltage terminal VR, and the drain electrode of the second transistor T2 is electrically connected to the first node N1;

[0121] The second reference voltage writing circuit comprises a third transistor T3;

[0122] The gate electrode of the third transistor T3 is electrically connected to the first reset terminal R1, the source electrode of the third transistor T3 is electrically connected to the reference voltage terminal VR, and the drain electrode of the third transistor T3 is electrically connected to the first node N1;

[0123] The first initialization circuit comprises a sixth transistor T6;

[0124] The gate electrode of the sixth transistor T6 is electrically connected to the first reset terminal R1, the source electrode of the sixth transistor T6 is electrically connected to the initial voltage terminal I1, and the drain electrode of the sixth transistor T6 is electrically connected to the source electrode of the driver transistor DT;

[0125] The data write circuit comprises a tenth transistor T10;

[0126] The gate electrode of the tenth transistor T10 is electrically connected to the first sense terminal G1, the source electrode of the tenth transistor T10 is electrically connected to the second node N2, and the drain electrode of the tenth transistor T10 is electrically connected to the data line Da.

[0127] In at least one embodiment of the Fig. In the pixel circuit shown in Figure 14, all transistors are n-type transistors, but not limited to them.

[0128] In at least one embodiment of the Fig. 14, the gate electrode of T2 is controlled by the first scanning signal provided by G1, and T3 is controlled by the first reset signal provided by R1, and compared to the pixel circuit shown in Fig. 12 reduces at least one embodiment of the pixel circuit shown in Fig. 14, the pixel circuit shown utilizes a control signal (the second reset signal provided by R2), which can reduce the use of one group of GOAs and requires only three groups of GOAs.

[0129] Fig. 15 is a working time diagram of the Fig. 14 shown pixel circuit.

[0130] If at least one embodiment of the Fig. 14 of the present disclosure,

[0131] In the second phase S2 and the third phase S3, G1 outputs a high voltage signal, T2 and T10 are turned on;

[0132] In the first phase S1 and the second phase S2, R1 outputs a high voltage signal and T3 and T6 are turned on.

[0133] As in Fig. 16, based on at least one embodiment of the Fig. 10 shown pixel circuit,

[0134] The driver circuit comprises a driver transistor DT, the first control circuit comprises a first transistor T1, and the first energy storage circuit comprises a first capacitor C1; the light-emitting element is an organic light-emitting diode O1;

[0135] The gate electrode of the first transistor T1 is electrically connected to the first light emission control line EM1, the source electrode of the first transistor T1 is electrically connected to the first node N1, and the drain electrode of the first transistor T1 is electrically connected to the second node N2;

[0136] The first light emission control circuit comprises a fourth transistor T4;

[0137] The gate electrode of the fourth transistor T4 is electrically connected to the second light emission control line EM2, the source electrode of the fourth transistor T4 is electrically connected to the power supply voltage terminal ELVDD, and the drain electrode of the fourth transistor T4 is electrically connected to the drain electrode of the driver transistor DT;

[0138] The gate electrode of the driver transistor DT is electrically connected to the first node N1, the source electrode of the driver transistor DT is electrically connected to the anode of the organic light-emitting diode O1; the cathode of the organic light-emitting diode O1 is electrically connected to the low-voltage terminal ELVSS;

[0139] The first terminal of the first capacitor C1 is electrically connected to the second node N2, and the second terminal of the first capacitor C1 is electrically connected to the source electrode of the driver transistor DT;

[0140] The first reference voltage writing circuit comprises the second transistor T2;

[0141] The gate electrode of the second transistor T2 is electrically connected to the second reset terminal R2, the source electrode of the second transistor T2 is electrically connected to the reference voltage terminal VR, and the drain electrode of the second transistor T2 is electrically connected to the first node N1;

[0142] The first initialization circuit comprises a sixth transistor T6;

[0143] The gate electrode of the sixth transistor T6 is electrically connected to the first reset terminal R1, the source electrode of the sixth transistor T6 is electrically connected to the initial voltage terminal I1, and the drain electrode of the sixth transistor T6 is electrically connected to the source electrode of the driver transistor DT;

[0144] The data write circuit comprises a tenth transistor T10;

[0145] The gate electrode of the tenth transistor T10 is electrically connected to the first sense terminal G1, the source electrode of the tenth transistor T10 is electrically connected to the second node N2, and the drain electrode of the tenth transistor T10 is electrically connected to the data line Da.

[0146] In at least one embodiment of the Fig. In the pixel circuit shown in Figure 16, all transistors are n-type transistors, but not limited to them.

[0147] Fig. 17 is a working time diagram of the Fig. 16 shown pixel circuit.

[0148] In at least one embodiment of the Fig. 16 of the present disclosure, a fourth transistor T4 is added, and the potential of the second light-emission control signal provided by EM2 is at a low voltage during the period in which the potential of the first reset signal provided by R1 is a high voltage. That is, the second light-emission control signal provided by EM2 is reversed in phase to the first reset signal provided by R1. During the initialization phase of the anode potential of O1, it prevents the formation of a current path between DT and T6. At the same time, Vint can also be used to better reset the anode potential of O1.

[0149] As in Fig. 17, the display period includes the first phase S1, the second phase S2, the third phase S3 and the fourth phase S4, which are set sequentially when at least one embodiment of the Fig. 16 of the present disclosure is in operation;

[0150] In the first phase S1, EM1 provides a low voltage signal, EM2 provides a low voltage signal, R1 provides a high voltage signal, G1 provides a low voltage signal, R2 provides a high voltage signal, T1 and T4 are off, T2 is on and T6 is on to write the reference voltage Vref provided by VR to the gate electrode of DT, write the initial voltage Vint provided by I1 to the source electrode of DT and reset the gate potential of DT, the anode potential of O1 and the source electrode potential of DT;

[0151] In the second phase S2, EM1 provides a low voltage signal, EM2 provides a low voltage signal, R1 provides a high voltage signal, G1 provides a high voltage signal, R2 provides a high voltage signal, T6, T1 and T4 are off, T10 and T2 are all on to write the data voltage Vdata provided by the data line Da to the second node N2, write the reference voltage Vref provided by the reference voltage terminal VR to the first node N1, and write the initial voltage Vin provided by the initial voltage terminal I1 to the source electrode of DT;

[0152] In the third phase S3, EM1 supplies a low-voltage signal, EM2 supplies a high-voltage signal, R1 supplies a low-voltage signal, G1 supplies a high-voltage signal, R2 supplies a high-voltage signal, and Da supplies the data voltage Vdata. At this time, T6 is off and T2 is on, T10 is on, the gate potential of DT is Vref; T4 is on, and the drain of DT is electrically connected to ELVDD.

[0153] At the beginning of the third phase S3, the DT is turned on to charge C1 and increase the potential of the source electrode of the DT until the potential of the source electrode of the DT reaches Vref-Vth, and the DT is turned off;

[0154] In the fourth phase S4, EM1 supplies a high-voltage signal, EM2 supplies a high-voltage signal, T1, T4, and DT are turned on, and the drain electrode of DT is electrically connected to ELVDD, and the potential of N1 is equal to that of N2. Since N1 is in a floating state before and after the DT is turned on, the voltage difference across C1 remains unchanged. At this time, the potential difference between the potential of the first node and the potential of the source electrode of DT is Vdata-Vref+Vth, and the gate-source voltage of DT is Vdata-Vref+Vth, and the current flowing through O1 is K(Vdata-Vref). 2; From the above formula, since Vref is a fixed voltage, the drain-source current Ids provided to O1 can be determined according to the data voltage Vdata; the current flowing through O1 has no relationship with the threshold voltage of the driver transistor and the supply voltage provided by ELVDD, the threshold voltage compensation is implemented.

[0155] As in Fig. 18, the driver circuit comprises at least one embodiment of the Fig. The pixel circuit shown in Figure 11 includes a driver transistor DT, the first control circuit includes a first transistor T1, and the first energy storage circuit includes a first capacitor C1; the light-emitting element is an organic light-emitting diode O1;

[0156] The driver circuit comprises a driver transistor DT, the first control circuit comprises a first transistor T1, and the first energy storage circuit comprises a first capacitor C1; the light-emitting element is an organic light-emitting diode O1;

[0157] The gate electrode of the first transistor T1 is electrically connected to the first light emission control line EM1, the source electrode of the first transistor T1 is electrically connected to the power supply voltage terminal ELVDD, and the drain electrode of the first transistor T1 is electrically connected to the first node N1;

[0158] The first light emission control circuit comprises a fourth transistor T4;

[0159] The gate electrode of the fourth transistor T4 is electrically connected to the second light emission control line EM2, the source electrode of the fourth transistor T4 is electrically connected to the power supply voltage terminal ELVDD, and the drain electrode of the fourth transistor T4 is electrically connected to the drain electrode of the driver transistor DT;

[0160] The gate electrode of the driver transistor DT is electrically connected to the first node N1;

[0161] The first terminal of the first capacitor C1 is electrically connected to the second node N2, and the second terminal of the first capacitor C1 is electrically connected to the source electrode of the driver transistor DT;

[0162] The second light emission control circuit comprises a fifth transistor T5;

[0163] The gate electrode of the fifth transistor T5 is electrically connected to the second light-emitting control line EM2, the source electrode of the fifth transistor T5 is electrically connected to the source electrode of the driver transistor DT, and the drain electrode of the fifth transistor T5 is electrically connected to the anode of the organic light-emitting diode O1; the cathode of the organic light-emitting diode O1 is electrically connected to the low-voltage terminal ELVSS;

[0164] The first reference voltage writing circuit comprises a second transistor T2;

[0165] The gate electrode of the second transistor T2 is electrically connected to the second reset terminal R2, the source electrode of the second transistor T2 is electrically connected to the reference voltage terminal VR, and the drain electrode of the second transistor T2 is electrically connected to the first node N1;

[0166] The first initialization circuit comprises a sixth transistor T6;

[0167] The gate electrode of the sixth transistor T6 is electrically connected to the first reset terminal R1, the source electrode of the sixth transistor T6 is electrically connected to the initial voltage terminal I1, and the drain electrode of the sixth transistor T6 is electrically connected to the source electrode of the driver transistor DT;

[0168] The data write circuit comprises a tenth transistor T10;

[0169] The gate electrode of the tenth transistor T10 is electrically connected to the first sense terminal G1, the source electrode of the tenth transistor T10 is electrically connected to the second node N2, and the drain electrode of the tenth transistor T10 is electrically connected to the data line Da.

[0170] In at least one embodiment of the Fig. In the pixel circuit shown in Figure 18, all transistors are n-type transistors, but not limited to them.

[0171] Fig. 19 is a working time diagram of the Fig. 18 shown pixel circuit.

[0172] Compared to at least one embodiment of the Fig. 16 adds at least one embodiment of the pixel circuit shown in Fig. 18, a fifth transistor T5 is added; and there is an overlapping period between the period in which the potential of the second light-emission control signal provided by EM2 is a high voltage and the period in which the potential of the first reset signal provided by R1 is a high voltage. During this overlapping period, T6, T4, and T5 are all turned on. At this time, Vint can reset the potential of the anode of O1; during the period in which T5 is off, the anode potential of O1 remains at Vint. Even if the source voltage of DT is Vref-Vth during the threshold voltage compensation period, this does not affect the turn-on sequence of the red pixel circuit, the green pixel circuit, and the blue pixel circuit.

[0173] As in Fig. 19, the display period comprises a pre-phase S0, the first phase S1, the second phase S2, the third phase S3 and the fourth phase S4, which are set sequentially when at least one embodiment of the Fig. 18 shown pixel circuit is in operation;

[0174] In the pre-phase S0, EM1 provides a low voltage signal, EM2 provides a high voltage signal, R1 provides a high voltage signal, G1 provides a low voltage signal, R2 provides a high voltage signal, T1 is turned off, T4 is turned on, T6 is turned on, T10 is turned off, T2 is turned on to write the reference voltage Vref provided by VR to the first node N1, control the electrical connection between the drain electrode of DT and ELVDD, and write the initial voltage Vint provided by I1 to the source electrode of DT;

[0175] In the first phase S1, EM1 provides a low voltage signal, EM2 provides a low voltage signal, R1 provides a high voltage signal, G1 provides a low voltage signal, R2 provides a high voltage signal, T1, T4 and T5 are off, T2 is on, T6 is on to write the reference voltage Vref provided by VR to the gate electrode of DT, write the initial voltage Vint provided by I1 to the source electrode of DT and reset the gate potential of DT, the anode potential of O1 and the source electrode potential of DT;

[0176] In the second phase S2, EM1 provides a low voltage signal, EM2 provides a low voltage signal, R1 provides a high voltage signal, G1 provides a high voltage signal, R2 provides a high voltage signal, T6, T1, T4 and T5 are off, T10 and T2 are all on to write the data voltage Vdata provided by the data line Da to the second node N2, write the reference voltage Vref provided by the reference voltage terminal VR to the first node N1, and write the initial voltage Vin provided by the initial voltage terminal I1 to the source electrode of DT;

[0177] In the third phase S3, EM1 supplies a low-voltage signal, EM2 supplies a high-voltage signal, R1 supplies a low-voltage signal, G1 supplies a high-voltage signal, R2 supplies a high-voltage signal, and Da supplies the data voltage Vdata. At this time, T6 is off and T2 is on, T10 is on, the gate potential of DT is Vref; T4 and T5 are on, the drain electrode of DT is electrically connected to ELVDD, and the source electrode of DT is electrically connected to the anode of O1.

[0178] At the beginning of the third phase S3, the DT is turned on to charge C1 and increase the potential of the source electrode of the DT until the potential of the source electrode of the DT reaches Vref-Vth, and the DT is turned off;

[0179] In the fourth phase S4, EM1 supplies a high-voltage signal, EM2 supplies a high-voltage signal, T1, T4, T5, and DT are turned on, the drain electrode of DT is electrically connected to ELVDD, the source electrode of DT is electrically connected to the anode of O1, and the potential of N1 is equal to the potential of N2. Because N1 is in a floating state, the voltage difference across C1 remains unchanged before and after DT is turned on. At this time, the potential difference between the potential of the first node and the potential of the source electrode of DT is Vdata-Vref+Vth, the gate-source voltage of DT is Vdata-Vref+Vth, and the current flowing through O1 is K(Vdata-Vref). 2; From the above formula, since Vref is a fixed voltage, the drain-source current Ids applied to O1 can be appropriately determined by the data voltage Vdata; the current flowing through O1 has no relationship with the threshold voltage of the driver transistor and the power supply voltage provided by ELVDD, and threshold voltage compensation can be performed.

[0180] As in Fig. 20, the driver circuit comprises at least one embodiment of the Fig. The pixel circuit shown in Figure 8 comprises a driver transistor DT, the first control circuit comprises a first transistor T1, and the first energy storage circuit comprises a first capacitor C1; the light-emitting element is an organic light-emitting diode O1;

[0181] The gate electrode of the first transistor T1 is electrically connected to the first light emission control line EM1, the source electrode of the first transistor T1 is electrically connected to the power supply voltage terminal ELVDD, and the drain electrode of the first transistor T1 is electrically connected to the first node N1;

[0182] The first light emission control circuit comprises a fourth transistor T4;

[0183] The gate electrode of the fourth transistor T4 is electrically connected to the second light emission control line EM2, the source electrode of the fourth transistor T4 is electrically connected to the power supply voltage terminal ELVDD, and the drain electrode of the fourth transistor T4 is electrically connected to the drain electrode of the driver transistor DT;

[0184] The gate electrode of the driver transistor DT is electrically connected to the first node N1, the source electrode of the driver transistor DT is electrically connected to the anode of the organic light-emitting diode O1; the cathode of the organic light-emitting diode O1 is electrically connected to the low-voltage terminal ELVSS;

[0185] The first terminal of the first capacitor C1 is electrically connected to the second node N2, and the second terminal of the first capacitor C1 is electrically connected to the source electrode of the driver transistor DT;

[0186] The first reference voltage writing circuit comprises a second transistor T2;

[0187] The gate electrode of the second transistor T2 is electrically connected to the second reset terminal R2, the source electrode of the second transistor T2 is electrically connected to the power supply voltage terminal ELVDD, and the drain electrode of the second transistor T2 is electrically connected to the first node N1;

[0188] The first initialization circuit comprises a sixth transistor T6;

[0189] The gate electrode of the sixth transistor T6 is electrically connected to the first reset terminal R1, the source electrode of the sixth transistor T6 is electrically connected to the low voltage terminal ELVSS, and the drain electrode of the sixth transistor T6 is electrically connected to the source electrode of the driver transistor DT;

[0190] The data write circuit comprises a tenth transistor T10;

[0191] The gate electrode of the tenth transistor T10 is electrically connected to the first sense terminal G1, the source electrode of the tenth transistor T10 is electrically connected to the second node N2, and the drain electrode of the tenth transistor T10 is electrically connected to the data line Da.

[0192] In at least one embodiment of the Fig. In the pixel circuit shown in Figure 20, all transistors are n-type transistors, but not limited to them.

[0193] Fig. 21 is a working time diagram of the Fig. 20 shown pixel circuit.

[0194] In at least one embodiment of the Fig. In the pixel circuit shown in Figure 20, the source electrode of T2 is electrically connected to the power supply voltage terminal ELVDD, and the drain electrode of T6 is electrically connected to the low voltage terminal ELVSS, which can save two additional voltage lines, which is advantageous for the layout design.

[0195] Optionally, the pixel circuit described in at least one embodiment of the present disclosure further comprises a second energy storage circuit and a second initialization circuit;

[0196] A second terminal of the first energy storage circuit is electrically connected to the second terminal of the driver circuit via the second energy storage circuit;

[0197] A first terminal of the second energy storage circuit is electrically connected to a third node, a second terminal of the second energy storage circuit is electrically connected to the second terminal of the driver circuit, and the second energy storage circuit is configured to store electrical energy;

[0198] The second initialization circuit is electrically connected to the scanning terminal, the second terminal of the driver circuit, and the second reset voltage terminal, and is configured to control the connection between the second terminal of the driver circuit and the second reset voltage terminal under the control of the scanning signal provided by the scanning terminal;

[0199] The second reset voltage terminal includes the initial voltage terminal, the first voltage terminal, or the third node;

[0200] The sensing terminal comprises a first or a second sensing terminal.

[0201] In at least one embodiment of the present disclosure, the second reset voltage terminal may include an initial voltage terminal, a first voltage terminal, or a third node, and the second reset voltage provided by the second reset voltage terminal may be, but is not limited to, the initial voltage, the first voltage, or the potential of the third node; in actual operation, the second reset voltage terminal may be other voltage terminals, and the second reset voltage may be other voltage signals according to actual needs.

[0202] Optionally, the pixel circuit described in at least one embodiment of the present disclosure may further comprise a second energy storage circuit, a first reference voltage writing circuit, a data writing circuit, and a first initialization circuit;

[0203] The second node is electrically connected to the first node via the second energy storage circuit;

[0204] The first reference voltage writing circuit is electrically connected to the reset terminal, the reference voltage terminal, and the first node, respectively, and is configured to write the reference voltage provided by the reference voltage terminal into the first node under the control of the reset signal provided by the reset terminal;

[0205] The data write circuit is electrically connected to the first sensing terminal, the second node, and the data line, and configured to write the data voltage provided by the data line to the second node under the control of the first sensing signal provided by the first sensing terminal;

[0206] The first initialization circuit is electrically connected to the reset terminal, the initial voltage terminal and the second terminal of the driver circuit and configured to write the initial voltage provided by the initial voltage terminal to the second terminal of the driver circuit under the control of the reset signal provided by the reset terminal.

[0207] As in Fig. 22, the pixel circuit described in at least one embodiment of the present disclosure comprises, based on the Fig. 1 further comprises a second energy storage circuit 221, a first reference voltage writing circuit 21, a data writing circuit 72 and a first initialization circuit 71;

[0208] The second node N2 is electrically connected to the first node N1 via the second energy storage circuit 221;

[0209] The first reference voltage writing circuit 21 is electrically connected to the reset terminal R0, the reference voltage terminal VR, and the first node N1, and is configured to write the reference voltage Vref provided by the reference voltage terminal VR into the first node N1 under the control of the reset signal provided by the reset terminal R0;

[0210] The data write circuit 72 is electrically connected to the first sensing terminal G1, the second node N2, and the data line Da, and is configured to write the data voltage Vdata provided by the data line Da to the second node N2 under the control of the first sensing signal provided by the first sensing terminal G1;

[0211] The first initialization circuit 71 is electrically connected to the reset terminal R0, the initial voltage terminal I1 and the second terminal of the driver circuit 11 and configured to write the initial voltage Vint provided by the initial voltage terminal I1 to the second terminal of the driver circuit 11 under the control of the reset signal provided by the reset terminal R0.

[0212] Optionally, the first energy storage circuit comprises a first capacitor, the second energy storage circuit comprises a second capacitor, the first control circuit comprises a first transistor, the first reference voltage writing circuit comprises an eighth transistor, the data writing circuit comprises an eleventh transistor, the first initialization circuit comprises a seventh transistor; the driver circuit comprises a driver transistor;

[0213] A gate electrode of the first transistor is electrically connected to the first light emission control line, a first electrode of the first transistor is electrically connected to the first node, and a second electrode of the first transistor is electrically connected to the second node;

[0214] A gate electrode of the driver transistor is electrically connected to the first node, a first electrode of the driver transistor is electrically connected to the power supply voltage terminal, and a second electrode of the driver transistor is electrically connected to the light-emitting element;

[0215] A first terminal of the first capacitor is electrically connected to the second node, and a second terminal of the first capacitor is electrically connected to the second electrode of the driver transistor;

[0216] A first terminal of the second capacitor is electrically connected to the first node, and a second terminal of the second capacitor is electrically connected to the second node;

[0217] A gate electrode of the eighth transistor is electrically connected to the reset terminal, a first electrode of the eighth transistor is electrically connected to the reference voltage terminal, and a second electrode of the eighth transistor is electrically connected to the first node;

[0218] A gate electrode of the eleventh transistor is electrically connected to the first sense terminal, a first electrode of the eleventh transistor is electrically connected to the second node, and a second electrode of the eleventh transistor is electrically connected to the data line;

[0219] A gate electrode of the seventh transistor is electrically connected to the reset terminal, a first electrode of the seventh transistor is electrically connected to the initial voltage terminal, and a second electrode of the seventh transistor is electrically connected to the second terminal of the driver circuit.

[0220] As in Fig. 23, based on at least one embodiment of the Fig. 22, the first energy storage circuit comprises a first capacitor C1, and the second energy storage circuit comprises a second capacitor C2; the first control circuit comprises a first transistor T1; the first reference voltage writing circuit comprises an eighth transistor T8; the data writing circuit comprises an eleventh transistor T11; and the first initialization circuit comprises a seventh transistor T7; the driver circuit comprises a driver transistor DT; the light-emitting element is an organic light-emitting diode O1;

[0221] The gate electrode of the first transistor T1 is electrically connected to the first light emission control line EM1, the source electrode of the first transistor T1 is electrically connected to the gate electrode of the driver transistor DT, and the drain electrode of the first transistor T1 is electrically connected to the second node N2;

[0222] The gate electrode of the driver transistor DT is electrically connected to the first node N1, the drain electrode of the driver transistor DT is electrically connected to the supply voltage terminal ELVDD, the source electrode of the driver transistor DT is electrically connected to the anode of O1; the cathode of O1 is electrically connected to the low-voltage terminal ELVSS;

[0223] The first terminal of the first capacitor C1 is electrically connected to the second node N2, and the second terminal of the first capacitor C1 is electrically connected to the third node N3;

[0224] The first terminal of the second capacitor C2 is electrically connected to the first node N1, and the second terminal of the second capacitor C2 is electrically connected to the second node N2;

[0225] The gate electrode of the eighth transistor T8 is electrically connected to the reset terminal R0, the source electrode of the eighth transistor T8 is electrically connected to the reference voltage terminal VR, and the drain electrode of the eighth transistor T8 is electrically connected to the first node N1;

[0226] The gate electrode of the tenth transistor T10 is electrically connected to the first sense terminal G1, the source electrode of the tenth transistor T10 is electrically connected to the second node N2, and the drain electrode of the tenth transistor T10 is electrically connected to the data line Da;

[0227] The gate electrode of the seventh transistor T7 is electrically connected to the reset terminal R0, the source electrode of the seventh transistor T7 is electrically connected to the initial voltage terminal I1, and the drain electrode of the seventh transistor T7 is electrically connected to the source electrode of the driver transistor DT.

[0228] Fig. 24 is a working time diagram of the Fig. 23 shown pixel circuit.

[0229] As in Fig. 24, the display period includes the first phase S1, the second phase S2, the third phase S3 and the fourth phase S4, which are set sequentially when at least one embodiment of the Fig. 23 of the present disclosure;

[0230] In the first phase S1, EM1 and G1 provide a low voltage signal, R0 provides a high voltage signal, T7 and T8 are both turned on to write the reference voltage Vref provided by VR to the first node N1 and write the initial voltage Vint provided by I1 to the source electrode of DT;

[0231] In the second phase S2, EM1 provides a low voltage signal, R0 and G1 provide a high voltage signal, Da provides a data voltage Vdata, T7, T8 and T10 are all turned on to write the reference voltage Vref provided by VR to the first node N1 and write the initial voltage Vint provided by I1 to the source electrode of DT and write the data voltage Vdata to the second node N2;

[0232] At the beginning of the second phase S2, DT is turned on, and DT compensates the threshold voltage in a source-follower manner, and the source potential of DT continuously increases from Vint until the source potential of DT becomes Vref-Vth. The threshold voltage compensation is completed at this time, and DT is turned off. At this time, the difference between the potential of N2 and the potential of the source electrode of DT is Vdata-(Vref-Vth);

[0233] In the third phase S3, EM1 supplies a low voltage signal, R0 supplies a low voltage signal, G1 supplies a high voltage signal, T10 is turned on, and the data line Da supplies a data voltage to the second node N2;

[0234] In the fourth phase S4, EM1 provides a high voltage signal, R0 and G1 provide a low voltage signal, T1 is turned on to write Vdata to the first node N1, and the gate-source voltage of DT is Vdata-Vref+Vth, the current Ioled flowing through O1 is equal to K(Vdata-Vref) 2 ; K is a current coefficient of DT. Referring to the above equation, the current Ioled supplied by the driver transistor DT to O1 can be determined according to the voltage difference between Vdata and Vref; since Vref is a fixed voltage, Ioled can be determined according to Vdata.

[0235] As in Fig. 25, the pixel circuit described in at least one embodiment of the present disclosure comprises, based on the Fig. 1 further comprises a second energy storage circuit 221 and a second initialization circuit 222;

[0236] The second terminal of the first energy storage circuit 12 is electrically connected to the second terminal of the driver circuit 11 via the second energy storage circuit 221;

[0237] The first terminal of the second energy storage circuit 221 is electrically connected to the third node N3, and the second terminal of the second energy storage circuit 221 is electrically connected to the second terminal of the driver circuit 11;

[0238] The second initialization circuit 222 is electrically connected to the first scanning terminal G1 and the second terminal of the driver circuit 11, and the second initialization circuit 222 is also electrically connected to the initial voltage terminal I1 and configured to write the initial voltage Vint provided by the initial voltage terminal I1 to the second terminal of the driver circuit 11 under the control of the first scanning signal provided by the first scanning terminal G1.

[0239] The pixel circuit described in the present embodiment includes a light-emitting element, a driving circuit, a power storage unit, a first control circuit, a data writing circuit, and a second initialization circuit;

[0240] A control terminal of the driver circuit is electrically connected to the first node, a first terminal of the driver circuit is electrically connected to the power supply voltage terminal, and a second terminal of the driver circuit is electrically connected to the light-emitting element; the driver circuit is configured to drive the light-emitting element under the control of the potential of the control terminal of the driver circuit;

[0241] A control terminal of the first control circuit is electrically connected to the first light emission control line, a first terminal of the first control circuit is electrically connected to the first node, and a second terminal of the first control circuit is electrically connected to the second node; the first control circuit is configured to control the connection of the first node and the second node under the control of the first light emission control signal provided by the first light emission control line;

[0242] The data write circuit is electrically connected to the first sensing terminal, the second node, and the data line, and is configured to write the data voltage provided by the data line to the second node under the control of the first sensing signal provided by the first sensing terminal;

[0243] The second initialization circuit is electrically connected to the scanning terminal, the second terminal of the driver circuit, and the second reset voltage terminal, and is configured to control the second terminal of the driver circuit and the second reset voltage terminal under the control of the scanning signal provided by the scanning terminal;

[0244] The energy storage unit comprises a first energy storage circuit, a second energy storage circuit and a second write circuit;

[0245] The first terminal of the first energy storage circuit is electrically connected to the second node, the second terminal of the first energy storage circuit is electrically connected to the third node, and the first energy storage circuit is configured to store electrical energy;

[0246] The first terminal of the second energy storage circuit is electrically connected to the third node, the second terminal of the second energy storage circuit is electrically connected to the second terminal of the driver circuit, and the second energy storage circuit is configured to store electrical energy;

[0247] The second write circuit is electrically connected to the reset terminal and the third node and configured to control the potential of the third node under the control of the reset signal provided from the reset terminal.

[0248] Optionally, the second reset voltage terminal may comprise an initial voltage terminal, a first voltage terminal, or a third node;

[0249] The sensing terminal comprises a first or a second sensing terminal.

[0250] In a specific implementation, the pixel circuit described in the embodiments of the present disclosure may include a light-emitting element, a driver circuit, a power storage unit, a first control circuit, a data write circuit, and a second initialization circuit. The first control circuit is configured to control to connect the first node and the second node under the control of the first light emission control signal; the data write circuit writes the data voltage provided by the data line to the second node under the control of the first sensing signal; the second initialization circuit controls to connect the second terminal of the driver circuit and the second reset voltage terminal under the control of the sensing signal; the second write circuit is configured to control the potential of the third node under the control of the reset signal.the driver circuit is configured to control the light-emitting element under the control of the potential of the control terminal of the driver circuit;

[0251] As in Fig. 26, the pixel circuit described in the present embodiment includes a light-emitting element EL, a driving circuit 11, a power storage unit, a first control circuit 13, a data writing circuit 72, and a second initialization circuit 222;

[0252] A control terminal of the driver circuit 11 is electrically connected to the first node N1, a first terminal of the driver circuit 11 is electrically connected to the power supply voltage terminal ELVDD, and a second terminal of the driver circuit 11 is electrically connected to the light-emitting element EL; the driver circuit 11 is configured to drive the light-emitting element EL under the control of the potential of the control terminal of the driver circuit;

[0253] A control terminal of the first control circuit 13 is electrically connected to the first light emission control line EM1, a first terminal of the first control circuit 13 is electrically connected to the first node N1, and a second terminal of the first control circuit 13 is electrically connected to the second node N2; the first control circuit 13 is configured to control the connection between the first node N1 and the second node N2 under the control of the first light emission control signal provided by the first light emission control line EM1;

[0254] The data write circuit 72 is electrically connected to the first sensing terminal G1, the second node N2, and the data line Da, and is configured to write the data voltage Vdata provided by the data line Da to the second node N2 under the control of the first sensing signal provided by the first sensing terminal G1;

[0255] The second initialization circuit 222 is electrically connected to the first scanning terminal G1, the second terminal of the driver circuit 11, and the second reset voltage terminal Vf2, and is configured to control to connect the second terminal of the driver circuit 11 and the second reset voltage terminal Vf2 under the control of the scanning signal provided from the first scanning terminal G1;

[0256] The energy storage unit comprises a first energy storage circuit 12, a second energy storage circuit 221 and a second write circuit 232;

[0257] A first terminal of the first energy storage circuit 12 is electrically connected to the second node N2, a second terminal of the first energy storage circuit 12 is electrically connected to the third node N3, and the first energy storage circuit 12 is configured to store electrical energy;

[0258] A first terminal of the second energy storage circuit 221 is electrically connected to the third node N3, a second terminal of the second energy storage circuit 221 is electrically connected to the second terminal of the driver circuit 11, and the second energy storage circuit 221 is configured to store electrical energy;

[0259] The second write circuit 232 is electrically connected to the reset terminal R0 and the third node N3 and configured to control the potential of the third node N3 under the control of the reset signal provided from the reset terminal R0.

[0260] The pixel circuit described in at least one embodiment of the present disclosure may further include a first write circuit;

[0261] The first write circuit is electrically connected to the reset terminal, a write voltage terminal, and a write node, and is configured to write the write voltage provided by the write voltage terminal into the write node under the control of the reset signal provided by the reset terminal; the write node includes a first node or a third node, and the write voltage terminal includes a reference voltage terminal or a power supply voltage terminal.

[0262] In a specific implementation, the pixel circuit may further comprise a first write-in circuit, and the first write-in circuit writes the write-in voltage to the write-in node under the control of the reset signal.

[0263] In at least one embodiment of the present disclosure, the enrollment node may include, but is not limited to, a first node or a third node;

[0264] The write voltage terminal may include a reference voltage terminal or a power supply voltage terminal, and the write voltage may be a reference voltage or a power supply voltage, but is not limited thereto; in actual operation, the write voltage terminal may include other voltage terminals, and the write voltage may be other voltage signals according to actual needs.

[0265] As in Fig. 27, the pixel circuit described in at least one embodiment of the present disclosure may be based on at least one embodiment of the Fig. 26 further comprises a first write circuit 231;

[0266] The first write circuit 231 is electrically connected to the reset terminal R0, the reference voltage terminal VR, and the control terminal of the driver circuit 11, and is configured to write the reference voltage Vref provided by the reference voltage terminal VR to the control terminal of the driver circuit 11 under the control of the reset signal provided by the reset terminal R0; the second write circuit 232 is electrically connected to the reset terminal R0 and the third node N3, and the second write circuit 232 is also electrically connected to the reference voltage terminal VR, and is configured to write the reference voltage Vref provided by the reference voltage terminal VR to the third node under the control of the reset signal provided by the reset terminal R0.

[0267] In at least one embodiment of the present disclosure, the second write circuit may also be electrically connected to the first reset voltage terminal and is configured to write the first reset voltage provided by the first reset voltage terminal to the third node under the control of the reset signal provided by the reset terminal;

[0268] The first reset voltage terminal includes an initial voltage terminal, a first voltage terminal, a reference voltage terminal, or a power supply voltage terminal.

[0269] In at least one embodiment of the present disclosure, the first reset voltage terminal may include an initial voltage terminal, a first voltage terminal, a reference voltage terminal, or a power supply voltage terminal, and the first reset voltage may be an initial voltage, a first voltage, a reference voltage, or a power supply voltage, but is not limited thereto. In actual operation, the first reset voltage terminal may include other voltage terminals, and the reset voltage may be other voltage signals according to actual needs.

[0270] In a particular implementation, the second write circuit may write the first reset voltage to the third node under the control of the reset signal.

[0271] In at least one embodiment of the present disclosure, the second write circuit may also be electrically connected to the control terminal of the driver circuit and is configured to control the connection between the control terminal of the driver circuit and the third node under the control of the reset signal.

[0272] In a specific implementation, the second write circuit may be controlled to connect the control terminal of the driver circuit and the third node under the control of the reset signal.

[0273] As in Fig. 28, the pixel circuit described in at least one embodiment of the present disclosure may be based on at least one embodiment of the Fig. 26 further comprises a first write circuit 231;

[0274] The first write circuit 231 is electrically connected to the reset terminal R0, the reference voltage terminal VR, and the control terminal of the driver circuit 11, and is configured to write the reference voltage Vref provided by the reference voltage terminal VR into the control terminal of the driver circuit 11 under the control of the reset signal provided by the reset terminal R0;

[0275] The second write circuit 232 is electrically connected to the reset terminal R0, the control terminal of the driver circuit 11, and the third node N3, and is configured to control to connect the control terminal of the driver circuit 11 and the third node N3 under the control of the reset signal.

[0276] As in Fig. 29, the pixel circuit described in at least one embodiment of the present disclosure may be based on at least one embodiment of the Fig. 26 further comprises a first write circuit 231;

[0277] The first write circuit 231 is electrically connected to the reset terminal R0, the reference voltage terminal VR, and the third node N3, and is configured to write the reference voltage provided by the reference voltage terminal VR to the third node N3 under the control of the reset signal provided by the reset terminal R0;

[0278] The second write circuit 232 is electrically connected to the reset terminal R0, the third node N3, and the control terminal of the driver circuit 11, and is configured to control to connect the third node and the control terminal of the driver circuit 11 under the control of the reset signal.

[0279] The pixel circuit described in at least one embodiment of the present disclosure may further include a first light emission control circuit;

[0280] The first light emission control circuit is electrically connected to the second light emission control line, the power supply voltage terminal, and the first terminal of the driver circuit, and is configured to control the connection of the power supply voltage terminal and the first terminal of the driver circuit under the control of the second light emission control signal provided by the second light emission control line.

[0281] As in Fig. 30, the pixel circuit described in at least one embodiment of the present disclosure may be based on at least one embodiment of the Fig. 27 further comprises a first light emission control circuit 51;

[0282] The first light emission control circuit 51 is electrically connected to the second light emission control line EM2, the power supply voltage terminal ELVDD, and the first terminal of the driver circuit 11, and is configured to control to connect the power supply voltage terminal ELVDD and the first terminal of the driver circuit 11 under the control of the second light emission control signal provided from the second light emission control line EM2.

[0283] As in Fig. 31, the pixel circuit described in at least one embodiment of the present disclosure may be based on at least one embodiment of the Fig. 28 further comprises a first light emission control circuit 51;

[0284] The first light emission control circuit 51 is electrically connected to the second light emission control line EM2, the power supply voltage terminal ELVDD, and the first terminal of the driver circuit 11, and is configured to control to connect the power supply voltage terminal ELVDD and the first terminal of the driver circuit 11 under the control of the second light emission control signal provided from the second light emission control line EM.

[0285] As in Fig. 32, the pixel circuit described in at least one embodiment of the present disclosure may be based on at least one embodiment of the Fig. 29 further comprises a first light emission control circuit 51;

[0286] The first light emission control circuit 51 is electrically connected to the second light emission control line EM2, the power supply voltage terminal ELVDD, and the first terminal of the driver circuit 11, and is configured to control to connect the power supply voltage terminal ELVDD and the first terminal of the driver circuit 11 under the control of the second light emission control signal provided from the second light emission control line EM.

[0287] As in Fig. 33, the pixel circuit described in at least one embodiment of the present disclosure may be based on at least one embodiment of the Fig. 26 further comprises a first write circuit 231 and a first light emission control circuit 51;

[0288] The first write circuit 231 is electrically connected to the reset terminal R0, the power supply voltage terminal ELVDD, and the control terminal of the driver circuit 11, and is configured to control the connection of the power supply voltage terminal ELVDD and the control terminal of the driver circuit 11 under the control of the reset signal provided from the reset terminal R0;

[0289] The second write circuit 232 is electrically connected to the reset terminal R0, the third node N3, and the initial voltage terminal I1, and is configured to control the initial voltage terminal I1 to write an initial voltage Vint into the third node N3 under the control of the reset signal;

[0290] The first light emission control circuit 51 is electrically connected to the second light emission control line EM2, the power supply voltage terminal ELVDD, and the first terminal of the driver circuit 11, and is configured to control to connect the power supply voltage terminal ELVDD and the first terminal of the driver circuit 11 under the control of the second light emission control signal provided from the second light emission control line EM2.

[0291] Optionally, the first energy storage circuit comprises a first capacitor; the second energy storage circuit comprises a second capacitor, and the second initialization circuit comprises a seventh transistor;

[0292] A gate electrode of the seventh transistor is electrically connected to a first sensing terminal or a second sensing terminal, a first electrode of the seventh transistor is electrically connected to a second reset voltage terminal, and a second electrode of the seventh transistor is electrically connected to the second terminal of the driver circuit;

[0293] A first terminal of the first capacitor is electrically connected to the second node, and a second terminal of the first capacitor is electrically connected to the third node;

[0294] A first terminal of the second capacitor is electrically connected to the third node, and a second terminal of the second capacitor is electrically connected to the second terminal of the driver circuit.

[0295] Optionally, the first write circuit includes an eighth transistor;

[0296] A gate electrode of the eighth transistor is electrically connected to the reset terminal, a first electrode of the eighth transistor is electrically connected to the reference voltage terminal, and a second electrode of the eighth transistor is electrically connected to the control terminal of the driver circuit.

[0297] Optionally, the second write circuit comprises a ninth transistor;

[0298] A gate electrode of the ninth transistor is electrically connected to the reset terminal, a first electrode of the ninth transistor is electrically connected to the first reset voltage terminal, and a second electrode of the ninth transistor is electrically connected to the third node.

[0299] Optionally, the second write circuit comprises a ninth transistor;

[0300] A gate electrode of the ninth transistor is electrically connected to the reset terminal, a first electrode of the ninth transistor is electrically connected to the third node, and a second electrode of the ninth transistor is connected to the control circuit of the driver circuit.

[0301] Optionally, the first light emission control circuit comprises a fourth transistor;

[0302] A gate electrode of the fourth transistor is electrically connected to the second light emission control line, a first electrode of the fourth transistor is electrically connected to the power supply voltage terminal, and a second electrode of the fourth transistor is electrically connected to the first terminal of the driver circuit.

[0303] Optionally, the data write circuit includes a tenth transistor;

[0304] A gate electrode of the tenth transistor is electrically connected to the first sense terminal, a first electrode of the tenth transistor is electrically connected to the second node, and a second electrode of the tenth transistor is electrically connected to the data line.

[0305] As in Fig. 34, the driver circuit comprises at least one embodiment of the Fig. The pixel circuit shown in Figure 27 includes a driver transistor DT, the first control circuit includes a first transistor T1, and the first energy storage circuit includes a first capacitor C1; the light-emitting element is an organic light-emitting diode O1;

[0306] The gate electrode of the first transistor T1 is electrically connected to the first light emission control line EM1, the source electrode of the first transistor T1 is electrically connected to the first node N1, and the drain electrode of the first transistor T1 is electrically connected to the second node N2;

[0307] The gate electrode of the driver transistor DT is electrically connected to the first node N1, the drain electrode of the driver transistor DT is electrically connected to the power supply voltage terminal ELVDD, and the source electrode of the driver transistor DT is electrically connected to the anode of the organic light-emitting diode O1; the cathode of the organic light-emitting diode O1 is electrically connected to the low-voltage terminal ELVSS;

[0308] A first terminal of the first capacitor C1 is electrically connected to the second node N2, and a second terminal of the first capacitor C1 is electrically connected to the third node N3;

[0309] The second energy storage circuit comprises a second capacitor C2, and the second initialization circuit comprises a seventh transistor T7;

[0310] The gate electrode of the seventh transistor T7 is electrically connected to the first sensing terminal G1, the source electrode of the seventh transistor T7 is electrically connected to the initial voltage terminal I1, and the drain electrode of the seventh transistor T7 is electrically connected to the source electrode of the driver transistor DT; the initial voltage terminal I1 is configured to provide the initial voltage Vint;

[0311] The first terminal of the second capacitor C2 is electrically connected to the third node N3, and the second terminal of the second capacitor C2 is electrically connected to the source electrode of the driver transistor DT;

[0312] The first write circuit comprises an eighth transistor T8 and the second write circuit comprises a ninth transistor T9;

[0313] The gate electrode of the eighth transistor T8 is electrically connected to the reset terminal R0, the source electrode of the eighth transistor T8 is electrically connected to the reference voltage terminal VR, and the drain electrode of the eighth transistor T8 is electrically connected to the gate electrode of the driver transistor DT;

[0314] The gate electrode of the ninth transistor T9 is electrically connected to the reset terminal R0, and the drain electrode of the ninth transistor T9 is electrically connected to the third node N3;

[0315] The source electrode of the ninth transistor T9 is electrically connected to the reference voltage terminal VR;

[0316] The data write circuit comprises a tenth transistor T10;

[0317] The gate electrode of the tenth transistor T10 is electrically connected to the first sense terminal G1, the source electrode of the tenth transistor T10 is electrically connected to the second node N2, and the drain electrode of the tenth transistor T10 is electrically connected to the data line Da.

[0318] In at least one embodiment of the Fig. In the pixel circuit shown in Figure 34, all transistors are n-type transistors, but not limited to them.

[0319] As in Fig. 35, the display period may comprise a first phase S1, a second phase S2 and a third phase S3, which are set sequentially when at least one embodiment of the Fig. 34 of the present disclosure;

[0320] In the first phase S1, EM1 provides a low voltage signal, R0 provides a high voltage signal, G1 provides a high voltage signal, Da provides a data voltage Vdata, T8 is turned on to write the reference voltage Vref provided by VR to the gate electrode of DT, and T1 is turned off, T10 is turned on to write the data voltage Vdata to the second node N2, T9 is turned on to write Vref to the third node N3, and T7 is turned on to write Vint to the source electrode of DT;

[0321] In the second phase S2, EM1 provides a low voltage signal, R0 provides a high voltage signal, G1 provides a low voltage signal, T8 is turned on to write Vref to the gate electrode of DT, and T9 is turned on to write Vref to the third node N3;

[0322] At the beginning of the second phase S2, DT is turned on, and DT compensates the threshold voltage in a source-follower manner. The source potential of DT continuously increases from Vint until the source potential of DT becomes Vref-Vth. At this time, the threshold voltage compensation is completed and DT is turned off. At this time, the difference between the potential of N2 and the source electrode potential of DT is Vdata-(Vref-Vth).

[0323] In the third phase S3, EM supplies a high-voltage signal, R0 supplies a low-voltage signal, G1 supplies a low-voltage signal, T1 is turned on, the gate potential of DT is Vdata, and the gate-source voltage of DT is Vdata-Vref+Vth; at this time, the current Ioled flowing through O1 is equal to K (Vdata-Vref) 2; K is the current coefficient of DT. Referring to the above equation, the current Ioled supplied by the driver transistor DT to O1 can be determined from the voltage difference between Vdata and Vref; since Vref is a fixed voltage, Ioled can be determined from Vdata.

[0324] In at least one embodiment of the pixel circuit in Fig. 34 of the present disclosure, two capacitors are connected in series, and a stable potential is applied to the third node between the two capacitors to prevent the change of the signal written to the third node, and the resetting of the anode potential of O1 and the writing of the data voltage to the first capacitor are controlled by the same signal, and the data voltage is written to the gate electrode of the driving transistor by the first light emission control signal to achieve light emission; the writing time of the data voltage is not controlled by the threshold voltage compensation time, thereby realizing high-speed writing; at least one embodiment of the present disclosure needs to use fewer control signals to achieve exactly the same technical effect.

[0325] If at least one embodiment of the Fig. 34 of the present disclosure, in the first phase S1, R0 provides a high voltage signal, G1 provides a high voltage signal, and T10 is turned on to write the data voltage Vdata provided by the data line Da to the second node N2, T9 is turned on to write the reference voltage Vref provided by VR to the third node N3, and T7 is turned on to write the initial voltage Vint provided by I1 to the second terminal of C2.

[0326] As in Fig. 36, the driver circuit comprises at least one embodiment of the Fig. The pixel circuit shown in Figure 28 includes a driver transistor DT, the first control circuit includes a first transistor T1, and the first energy storage circuit includes a first capacitor C1; the light-emitting element is an organic light-emitting diode O1;

[0327] The gate electrode of the first transistor T1 is electrically connected to the first light emission control line EM1, the source electrode of the first transistor T1 is electrically connected to the first node N1, and the drain electrode of the first transistor T1 is electrically connected to the second node N2;

[0328] The gate electrode of the driver transistor DT is electrically connected to the first node N1, the drain electrode of the driver transistor DT is electrically connected to the power supply voltage terminal ELVDD, and the source electrode of the driver transistor DT is electrically connected to the anode of the organic light-emitting diode O1; the cathode of the organic light-emitting diode O1 is electrically connected to the low-voltage terminal ELVSS;

[0329] A first terminal of the first capacitor C1 is electrically connected to the second node N2, and a second terminal of the first capacitor C1 is electrically connected to the third node N3;

[0330] The second energy storage circuit comprises a second capacitor C2; the second initialization circuit comprises a seventh transistor T7;

[0331] The gate electrode of the seventh transistor T7 is electrically connected to the first sensing terminal G1, the source electrode of the seventh transistor T7 is electrically connected to the initial voltage terminal I1, and the drain electrode of the seventh transistor T7 is electrically connected to the source electrode of the driver transistor DT; the initial voltage terminal I1 is configured to provide the initial voltage Vint;

[0332] The first terminal of the second capacitor C2 is electrically connected to the third node N3, and the second terminal of the second capacitor C2 is electrically connected to the source electrode of the driver transistor DT;

[0333] The first write circuit comprises an eighth transistor T8 and the second write circuit comprises a ninth transistor T9;

[0334] The gate electrode of the eighth transistor T8 is electrically connected to the reset terminal R0, the source electrode of the eighth transistor T8 is electrically connected to the reference voltage terminal VR, and the drain electrode of the eighth transistor T8 is electrically connected to the gate electrode of the driver transistor DT;

[0335] The gate electrode of the ninth transistor T9 is electrically connected to the reset terminal R0, the source electrode of the ninth transistor T9 is electrically connected to the third node N3, and the drain electrode of the ninth transistor T9 is electrically connected to the gate electrode of the driver transistor DT;

[0336] The data write circuit comprises a tenth transistor T10;

[0337] The gate electrode of the tenth transistor T10 is electrically connected to the first sense terminal G1, the source electrode of the tenth transistor T10 is electrically connected to the second node N2, and the drain electrode of the tenth transistor T10 is electrically connected to the data line Da.

[0338] In at least one embodiment of the Fig. In the pixel circuit shown in Figure 36, all transistors are n-type transistors, but not limited to them.

[0339] Fig. 37 is a working time diagram of the Fig. 36 shown pixel circuit.

[0340] As in Fig. 37, the display period may comprise a first phase S1, a second phase S2 and a third phase S3, which are set sequentially when at least one embodiment of the Fig. 36 of the present disclosure;

[0341] In the first phase S1, EM1 supplies a low voltage signal, R0 supplies a high voltage signal, G1 supplies a high voltage signal, Da supplies a data voltage Vdata, T8 is turned on to write the reference voltage Vref provided by VR to the gate electrode of DT, and T1 is turned off, T10 is turned on to write the data voltage Vdata to the second node N2, T9 is turned on to control the connection between the first node N1 and the third node N3 so that the potential of the third node N3 is Vref; T7 is turned on to write Vint to the source electrode of DT;

[0342] In the second phase S2, EM1 provides a low voltage signal, R0 provides a high voltage signal, G1 provides a low voltage signal, T8 is turned on to write Vref to the gate electrode of DT, T9 is turned on to control the connection between the first node N1 and the third node N3, so that the potential of the third node N3 is Vref;

[0343] At the beginning of the second phase S2, DT is turned on, and DT compensates the threshold voltage in a source-follower manner. The source potential of DT continuously increases from Vint until the source potential of DT becomes Vref-Vth. At this time, the threshold voltage compensation is completed and DT is turned off. At this time, the difference between the potential of N2 and the source electrode potential of DT is Vdata-(Vref-Vth).

[0344] In the third phase S3, EM supplies a high-voltage signal, R0 supplies a low-voltage signal, G1 supplies a low-voltage signal, T1 is turned on, the gate potential of DT is Vdata, and the gate-source voltage of DT is Vdata-Vref+Vth; at this time, the current Ioled flowing through O1 is equal to K (Vdata-Vref) 2 ; K is the current coefficient of DT. Referring to the above equation, the current Ioled supplied by the driver transistor DT to O1 can be determined from the voltage difference between Vdata and Vref; since Vref is a fixed voltage, Ioled can be determined from Vdata.

[0345] If at least one embodiment of the Fig. 36 of the present disclosure, in the first phase S1, both R0 and G1 provide high voltage signals, and T8 and T9 are both turned on to write the reference voltage Vref provided by VR to the third node N3, T10 and T7 are all turned on to write the data voltage Vdata provided by the data line Da to the second node, and write the initial voltage Vint provided by I1 to the second terminal of C2.

[0346] As in Fig. 38, the driver circuit comprises at least one embodiment of the Fig. The pixel circuit shown in Figure 29 includes a driver transistor DT, the first control circuit includes a first transistor T1, and the first energy storage circuit includes a first capacitor C1; the light-emitting element is an organic light-emitting diode O1;

[0347] The gate electrode of the first transistor T1 is electrically connected to the first light emission control line EM1, the source electrode of the first transistor T1 is electrically connected to the power supply voltage terminal ELVDD, and the drain electrode of the first transistor T1 is electrically connected to the first node N1;

[0348] The gate electrode of the driver transistor DT is electrically connected to the first node N1, the drain electrode of the driver transistor DT is electrically connected to the power supply voltage terminal ELVDD, and the source electrode of the driver transistor DT is electrically connected to the anode of the organic light-emitting diode O1; the cathode of the organic light-emitting diode O1 is electrically connected to the low-voltage terminal ELVSS;

[0349] A first terminal of the first capacitor C1 is electrically connected to the second node N2, and a second terminal of the first capacitor C1 is electrically connected to the third node N3;

[0350] The second energy storage circuit comprises a second capacitor C2; the second initialization circuit comprises a seventh transistor T7;

[0351] The gate electrode of the seventh transistor T7 is electrically connected to the first sensing terminal G1, the source electrode of the seventh transistor T7 is electrically connected to the initial voltage terminal I1, and the drain electrode of the seventh transistor T7 is electrically connected to the source electrode of the driver transistor DT; the initial voltage terminal I1 is configured to provide the initial voltage Vint;

[0352] The first terminal of the second capacitor C2 is electrically connected to the third node N3, and the second terminal of the second capacitor C2 is electrically connected to the source electrode of the driver transistor DT;

[0353] The first write circuit comprises an eighth transistor T8 and the second write circuit comprises a ninth transistor T9;

[0354] The gate electrode of the eighth transistor T8 is electrically connected to the reset terminal R0, the source electrode of the eighth transistor T8 is electrically connected to the reference voltage terminal VR, and the drain electrode of the eighth transistor T8 is electrically connected to the third node N3;

[0355] The gate electrode of the ninth transistor T9 is electrically connected to the reset terminal R0, the source electrode of the ninth transistor T9 is electrically connected to the third node N3, and the drain electrode of the ninth transistor T9 is electrically connected to the gate electrode of the driver transistor DT;

[0356] The data write circuit comprises a tenth transistor T10;

[0357] The gate electrode of the tenth transistor T10 is electrically connected to the first sense terminal G1, the source electrode of the tenth transistor T10 is electrically connected to the second node N2, and the drain electrode of the tenth transistor T10 is electrically connected to the data line Da.

[0358] In at least one embodiment of the Fig. In the pixel circuit shown in Figure 38, all transistors are n-type transistors, but not limited to them.

[0359] Fig. 39 is a working time diagram of the Fig. 38 shown pixel circuit.

[0360] As in Fig. 39, the display period may comprise a first phase S1, a second phase S2 and a third phase S3, which are set sequentially when at least one embodiment of the Fig. 38 of the present disclosure is in operation;

[0361] In the first phase S1, EM1 provides a low voltage signal, R0 provides a high voltage signal, G1 provides a high voltage signal, Da provides a data voltage Vdata, T8 is turned on to write the reference voltage Vref provided by VR to the third node N3, and T1 is turned off, T10 is turned on to write the data voltage Vdata to the second node N2, T9 is turned on to control the connection between the first node N1 and the third node N3 so that the potential of the first node N1 is Vref; T7 is turned on to write Vint to the source electrode of DT;

[0362] In the second phase S2, EM1 provides a low voltage signal, R0 provides a high voltage signal, G1 provides a low voltage signal, T8 is turned on to write Vref to the third node N3, T9 is turned on to control the connection between the first node N1 and the third node N3, so that the potential of the first node N1 is Vref;

[0363] At the beginning of the second phase S2, DT is turned on, and DT compensates the threshold voltage in a source-follower manner. The source potential of DT continuously increases from Vint until the source potential of DT becomes Vref-Vth. At this time, the threshold voltage compensation is completed and DT is turned off. At this time, the difference between the potential of N2 and the source electrode potential of DT is Vdata-(Vref-Vth).

[0364] In the third phase S3, EM supplies a high-voltage signal, R0 supplies a low-voltage signal, G1 supplies a low-voltage signal, T1 is turned on, the gate potential of DT is Vdata, and the gate-source voltage of DT is Vdata-Vref+Vth; at this time, the current Ioled flowing through O1 is equal to K (Vdata-Vref) 2 ; K is the current coefficient of DT. Referring to the above equation, the current Ioled supplied by the driver transistor DT to O1 can be determined from the voltage difference between Vdata and Vref; since Vref is a fixed voltage, Ioled can be determined from Vdata.

[0365] If at least one embodiment of the Fig. 38 of the present disclosure, in the first phase S1, both R0 and G1 provide high voltage signals, and T8 and T9 are both turned on to write the reference voltage Vref provided by VR to the third node N3, T10 and T7 are all turned on to write the data voltage Vdata provided by the data line Da to the second node and write the initial voltage Vint provided by I1 to the second terminal of C2.

[0366] As in Fig. 40, the driver circuit comprises at least one embodiment of the Fig. 30, the pixel circuit includes a driver transistor DT, the first control circuit includes a first transistor T1, and the first energy storage circuit includes a first capacitor C1; the light-emitting element is an organic light-emitting diode O1; the first light-emitting control circuit includes a fourth transistor T4;

[0367] The gate electrode of the first transistor T1 is electrically connected to the first light emission control line EM1, the source electrode of the first transistor T1 is electrically connected to the first node N1, and the drain electrode of the first transistor T1 is electrically connected to the second node N2;

[0368] The gate electrode of the fourth transistor T4 is electrically connected to the second light emission control line EM2, the source electrode of the fourth transistor T4 is electrically connected to the power supply voltage terminal ELVDD, and the drain electrode of the fourth transistor T4 is electrically connected to the drain electrode of the driver transistor DT;

[0369] The gate electrode of the driver transistor DT is electrically connected to the first node N1, the source electrode of the driver transistor DT is electrically connected to the anode of the organic light-emitting diode O1; the cathode of the organic light-emitting diode O1 is electrically connected to the low-voltage terminal ELVSS;

[0370] A first terminal of the first capacitor C1 is electrically connected to the second node N2, and a second terminal of the first capacitor C1 is electrically connected to the third node N3;

[0371] The second energy storage circuit comprises a second capacitor C2, and the second initialization circuit comprises a seventh transistor T7;

[0372] The gate electrode of the seventh transistor T7 is electrically connected to the first sensing terminal G1, the source electrode of the seventh transistor T7 is electrically connected to the initial voltage terminal I1, and the drain electrode of the seventh transistor T7 is electrically connected to the source electrode of the driver transistor DT; the initial voltage terminal I1 is configured to provide the initial voltage Vint;

[0373] The first terminal of the second capacitor C2 is electrically connected to the third node N3, and the second terminal of the second capacitor C2 is electrically connected to the source electrode of the driver transistor DT;

[0374] The first write circuit comprises an eighth transistor T8 and the second write circuit comprises a ninth transistor T9;

[0375] The gate electrode of the eighth transistor T8 is electrically connected to the reset terminal R0, the source electrode of the eighth transistor T8 is electrically connected to the reference voltage terminal VR, and the drain electrode of the eighth transistor T8 is electrically connected to the gate electrode of the driver transistor DT;

[0376] The gate electrode of the ninth transistor T9 is electrically connected to the reset terminal R0, and the drain electrode of the ninth transistor T9 is electrically connected to the third node N3;

[0377] The source electrode of the ninth transistor T9 is electrically connected to the reference voltage terminal VR;

[0378] The data write circuit comprises a tenth transistor T10;

[0379] The gate electrode of the tenth transistor T10 is electrically connected to the first sense terminal G1, the source electrode of the tenth transistor T10 is electrically connected to the second node N2, and the drain electrode of the tenth transistor T10 is electrically connected to the data line Da.

[0380] In at least one embodiment of the Fig. In the pixel circuit shown in Figure 40, all transistors are n-type transistors, but not limited to them.

[0381] Fig. 41 is a working time diagram of the Fig. 40 pixel circuit shown.

[0382] As in Fig. 41, the display period may comprise a first phase S1, a second phase S2 and a third phase S3, which are set sequentially when at least one embodiment of the Fig. 40 of the present disclosure;

[0383] In the first phase S1, EM1 provides a low voltage signal, EM2 provides a low voltage signal, R0 provides a high voltage signal, G1 provides a high voltage signal, Da provides the data voltage Vdata, T4 is off, and T8 is turned on to write the reference voltage Vref provided by VR to the gate electrode of DT, T1 is turned off, T10 is turned on to write the data voltage Vdata to the second node N2, T9 is turned on to write Vref to the third node N3, T7 is turned on to write Vint to the source electrode of DT;

[0384] In the second phase S2, EM1 provides a low voltage signal, EM2 a high voltage signal, R0 a high voltage signal, G1 a low voltage signal, T8 is turned on to write Vref to the gate electrode of DT, T9 is turned on to write Vref to the third node N3; T4 is turned on, and the drain electrode of DT is electrically connected to ELVDD;

[0385] At the beginning of the second phase S2, DT is turned on, and DT compensates the threshold voltage in a source-follower manner. The source potential of DT continuously increases from Vint until the source potential of DT becomes Vref-Vth. At this time, the threshold voltage compensation is completed and DT is turned off. At this time, the difference between the potential of N2 and the source electrode potential of DT is Vdata-(Vref-Vth).

[0386] In the third phase S3, EM1 provides a high voltage signal, EM2 a high voltage signal, R0 a low voltage signal, G1 a low voltage signal, T1 and T4 are turned on, and the drain electrode of DT is electrically connected to ELVDD;

[0387] The gate potential of the DT is Vdata, and the gate-source voltage of the DT is Vdata-Vref+Vth; at this time, the current Ioled flowing through O1 is equal to K(Vdata-Vref) 2 ; where K is the current coefficient of the DT. Referring to the above equation, the current Ioled supplied by the driver transistor DT to O1 can be determined from the voltage difference between Vdata and Vref; since Vref is a fixed voltage, Ioled can be determined from Vdata.

[0388] If at least one embodiment of the Fig. 40 of the present disclosure, in the first phase S1, both R0 and G1 provide high voltage signals, and T9 is turned on to write the reference voltage Vref provided by VR to the third node N3, both T10 and T7 are turned on to write the data voltage Vdata provided by the data line Da to the second node, and write the initial voltage Vint provided by I1 to the second terminal of C2.

[0389] As in Fig. 42, the driver circuit comprises at least one embodiment of the Fig. 31, the pixel circuit includes a driver transistor DT, the first control circuit includes a first transistor T1, and the first energy storage circuit includes a first capacitor C1; the light-emitting element is an organic light-emitting diode O1; the first light-emitting control circuit includes a fourth transistor T4;

[0390] The gate electrode of the first transistor T1 is electrically connected to the first light emission control line EM1, the source electrode of the first transistor T1 is electrically connected to the first node N1, and the drain electrode of the first transistor T1 is electrically connected to the second node N2;

[0391] The gate electrode of the fourth transistor T4 is electrically connected to the second light emission control line EM2, the source electrode of the fourth transistor T4 is electrically connected to the power supply voltage terminal ELVDD, and the drain electrode of the fourth transistor T4 is electrically connected to the drain electrode of the driver transistor DT;

[0392] The gate electrode of the driver transistor DT is electrically connected to the first node N1, the source electrode of the driver transistor DT is electrically connected to the anode of the organic light-emitting diode O1; the cathode of the organic light-emitting diode O1 is electrically connected to the low-voltage terminal ELVSS;

[0393] A first terminal of the first capacitor C1 is electrically connected to the second node N2, and a second terminal of the first capacitor C1 is electrically connected to the third node N3;

[0394] The second energy storage circuit comprises a second capacitor C2; the second initialization circuit comprises a seventh transistor T7;

[0395] The gate electrode of the seventh transistor T7 is electrically connected to the first sensing terminal G1, the source electrode of the seventh transistor T7 is electrically connected to the initial voltage terminal I1, and the drain electrode of the seventh transistor T7 is electrically connected to the source electrode of the driver transistor DT; the initial voltage terminal I1 is configured to provide the initial voltage Vint;

[0396] The first terminal of the second capacitor C2 is electrically connected to the third node N3, and the second terminal of the second capacitor C2 is electrically connected to the source electrode of the driver transistor DT;

[0397] The first write circuit comprises an eighth transistor T8 and the second write circuit comprises a ninth transistor T9;

[0398] The gate electrode of the eighth transistor T8 is electrically connected to the reset terminal R0, the source electrode of the eighth transistor T8 is electrically connected to the reference voltage terminal VR, and the drain electrode of the eighth transistor T8 is electrically connected to the gate electrode of the driver transistor DT;

[0399] The gate electrode of the ninth transistor T9 is electrically connected to the reset terminal R0, the source electrode of the ninth transistor T9 is electrically connected to the third node N3, and the drain electrode of the ninth transistor T9 is electrically connected to the gate electrode of the driver transistor DT;

[0400] The data write circuit comprises a tenth transistor T10;

[0401] The gate electrode of the tenth transistor T10 is electrically connected to the first sense terminal G1, the source electrode of the tenth transistor T10 is electrically connected to the second node N2, and the drain electrode of the tenth transistor T10 is electrically connected to the data line Da.

[0402] In at least one embodiment of the Fig. In the pixel circuit shown in Figure 42, all transistors are n-type transistors, but not limited to them.

[0403] Fig. 43 is a working time diagram of the Fig. 42 shown pixel circuit.

[0404] As in Fig. 43, the display period may comprise a first phase S1, a second phase S2 and a third phase S3, which are set sequentially when at least one embodiment of the Fig. 42 of the present disclosure;

[0405] In the first phase S1, EM1 supplies a low voltage signal, EM2 supplies a low voltage signal, R0 supplies a high voltage signal, G1 supplies a high voltage signal, Da supplies the data voltage Vdata, T8 is turned on to write the reference voltage Vref provided by VR to the gate electrode of the DT, T1 and T4 are turned off, T10 is turned on to write the data voltage Vdata to the second node N2, T9 is turned on to control the connection between the first node N1 and the third node N3 so that the potential of the third node N3 is Vref; T7 is turned on to write Vint to the source electrode of DT;

[0406] In the second phase S2, EM1 provides a low voltage signal, EM2 provides a high voltage signal, R0 provides a high voltage signal, G1 provides a low voltage signal, T4 is turned on, the drain electrode of DT is electrically connected to ELVDD, and T8 is turned on to write Vref to the gate electrode of DT, T9 is turned on to control the connection between the first node N1 and the third node N3, so that the potential of the third node N3 is Vref;

[0407] At the beginning of the second phase S2, DT is turned on, and DT compensates the threshold voltage in a source-follower manner. The source potential of DT continuously increases from Vint until the source potential of DT becomes Vref-Vth. At this time, the threshold voltage compensation is completed and DT is turned off. At this time, the difference between the potential of N2 and the source electrode potential of DT is Vdata-(Vref-Vth).

[0408] In the third phase S3, EM1 and EM2 supply high-voltage signals, R0 supplies low-voltage signals, G1 supplies low-voltage signals, T1 and T4 are turned on, the drain electrode of DT is electrically connected to ELVDD, and the gate potential of DT is Vdata, and the gate-source voltage of DT is Vdata-Vref+Vth; at this time, the current Ioled flowing through O1 is equal to K(Vdata-Vref). 2 ; where K is the current coefficient of DT. Referring to the above equation, the current Ioled supplied by the driver transistor DT to O1 can be determined from the voltage difference between Vdata and Vref; since Vref is a fixed voltage, Ioled can be determined from Vdata.

[0409] As in Fig. 44 based on at least one embodiment of the Fig. As shown in the pixel circuit shown in Figure 32, the driver circuit includes a driver transistor DT, the first control circuit includes a first transistor T1, and the first energy storage circuit includes a first capacitor C1; the light-emitting element is an organic light-emitting diode O1; the first light-emitting control circuit includes a fourth transistor T4;

[0410] The gate electrode of the first transistor T1 is electrically connected to the first light emission control line EM1, the source electrode of the first transistor T1 is electrically connected to the first node N1, and the drain electrode of the first transistor T1 is electrically connected to the second node N2;

[0411] The gate electrode of the fourth transistor T4 is electrically connected to the second light emission control line EM2, the source electrode of the fourth transistor T4 is electrically connected to the power supply voltage terminal ELVDD, and the drain electrode of the fourth transistor T4 is electrically connected to the drain electrode of the driver transistor DT;

[0412] The gate electrode of the driver transistor DT is electrically connected to the first node N1, the source electrode of the driver transistor DT is electrically connected to the anode of the organic light-emitting diode O1; the cathode of the organic light-emitting diode O1 is electrically connected to the low-voltage terminal ELVSS;

[0413] A first terminal of the first capacitor C1 is electrically connected to the second node N2, and a second terminal of the first capacitor C1 is electrically connected to the third node N3;

[0414] The second energy storage circuit comprises a second capacitor C2; the second initialization circuit comprises a seventh transistor T7;

[0415] The gate electrode of the seventh transistor T7 is electrically connected to the first sensing terminal G1, the source electrode of the seventh transistor T7 is electrically connected to the initial voltage terminal I1, and the drain electrode of the seventh transistor T7 is electrically connected to the source electrode of the driver transistor DT; the initial voltage terminal I1 is configured to provide the initial voltage Vint;

[0416] The first terminal of the second capacitor C2 is electrically connected to the third node N3, and the second terminal of the second capacitor C2 is electrically connected to the source electrode of the driver transistor DT;

[0417] The first write circuit comprises an eighth transistor T8 and the second write circuit comprises a ninth transistor T9;

[0418] The gate electrode of the eighth transistor T8 is electrically connected to the reset terminal R0, the source electrode of the eighth transistor T8 is electrically connected to the reference voltage terminal VR, and the drain electrode of the eighth transistor T8 is electrically connected to the third node N3;

[0419] The gate electrode of the ninth transistor T9 is electrically connected to the reset terminal R0, the source electrode of the ninth transistor T9 is electrically connected to the third node N3, and the drain electrode of the ninth transistor T9 is electrically connected to the gate electrode of the driver transistor DT;

[0420] The data write circuit comprises a tenth transistor T10;

[0421] The gate electrode of the tenth transistor T10 is electrically connected to the first sense terminal G1, the source electrode of the tenth transistor T10 is electrically connected to the second node N2, and the drain electrode of the tenth transistor T10 is electrically connected to the data line Da.

[0422] In at least one embodiment of the Fig. In the pixel circuit shown in Figure 44, all transistors are n-type transistors, but not limited to them.

[0423] Fig. 45 is a working time diagram of the Fig. 44 shown pixel circuit.

[0424] As in Fig. 45, the display period may comprise the first phase S1, the second phase S2 and the third phase S3, which are set sequentially when at least one embodiment of the Fig. 44 of the present disclosure is in operation;

[0425] In the first phase S1, EM1 and EM2 provide low voltage signals, R0 provides a high voltage signal, G1 provides a high voltage signal, Da provides the data voltage Vdata, T8 is turned on to write the reference voltage Vref provided by VR to the third node N3, T1 and T4 are turned off, T10 is turned on to write the data voltage Vdata to the second node N2, T9 is turned on to control the connection between the first node N1 and the third node N3 so that the potential of the first node N1 is Vref; T7 is turned on to write Vint to the source electrode of DT;

[0426] In the second phase S2, EM1 provides a low voltage signal, EM2 provides a high voltage signal, R0 provides a high voltage signal, G1 provides a low voltage signal, T8 is turned on to write Vref to the third node N3, T9 is turned on to control the connection between the first node N1 and the third node N3 so that the potential of the first node N1 is Vref; T4 is turned on, and the drain electrode of DT is electrically connected to ELVDD;

[0427] At the beginning of the second phase S2, DT is turned on, and DT compensates the threshold voltage in a source-follower manner. The source potential of DT continuously increases from Vint until the source potential of DT becomes Vref-Vth. At this time, the threshold voltage compensation is completed and DT is turned off. At this time, the difference between the potential of N2 and the source electrode potential of DT is Vdata-(Vref-Vth).

[0428] In the third phase S3, EM1 and EM2 supply high-voltage signals, R0 supplies low-voltage signals, G1 supplies low-voltage signals, T1 and T4 are turned on, the drain electrode of DT is electrically connected to ELVDD, and the gate potential of DT is Vdata, and the gate-source voltage of DT is Vdata-Vref+Vth; at this time, the current Ioled flowing through O1 is equal to K(Vdata-Vref). 2 ; where K is the current coefficient of DT. Referring to the above equation, the current Ioled supplied by the driver transistor DT to O1 can be determined from the voltage difference between Vdata and Vref; since Vref is a fixed voltage, Ioled can be determined from Vdata.

[0429] As in Fig. 46, the driver circuit comprises at least one embodiment of the Fig. 33, the pixel circuit includes a driver transistor DT, the first control circuit includes a first transistor T1, and the first energy storage circuit includes a first capacitor C1; the light-emitting element is an organic light-emitting diode O1; the first light-emitting control circuit includes a fourth transistor T4;

[0430] The gate electrode of the first transistor T1 is electrically connected to the first light emission control line EM1, the source electrode of the first transistor T1 is electrically connected to the power supply voltage terminal ELVDD, and the drain electrode of the first transistor T1 is electrically connected to the first node N1;

[0431] The gate electrode of the fourth transistor T4 is electrically connected to the second light emission control line EM2, the source electrode of the fourth transistor T4 is electrically connected to the power supply voltage terminal ELVDD, and the drain electrode of the fourth transistor T4 is electrically connected to the drain electrode of the driver transistor DT;

[0432] The gate electrode of the driver transistor DT is electrically connected to the first node N1, the drain electrode of the driver transistor DT is electrically connected to the power supply terminal ELVDD, and the source electrode of the driver transistor DT is electrically connected to the anode of the organic light-emitting diode O1; the cathode of the organic light-emitting diode O1 is electrically connected to the low-voltage terminal ELVSS;

[0433] A first terminal of the first capacitor C1 is electrically connected to the second node N2, and a second terminal of the first capacitor C1 is electrically connected to the third node N3;

[0434] The second energy storage circuit comprises a second capacitor C2, and the second initialization circuit comprises a seventh transistor T7;

[0435] The gate electrode of the seventh transistor T7 is electrically connected to the first sensing terminal G1, the source electrode of the seventh transistor T7 is electrically connected to the initial voltage terminal I1, and the drain electrode of the seventh transistor T7 is electrically connected to the source electrode of the driver transistor DT; the initial voltage terminal I1 is configured to provide the initial voltage Vint;

[0436] The first terminal of the second capacitor C2 is electrically connected to the third node N3, and the second terminal of the second capacitor C2 is electrically connected to the source electrode of the driver transistor DT;

[0437] The first write circuit comprises an eighth transistor T8 and the second write circuit comprises a ninth transistor T9;

[0438] The gate electrode of the eighth transistor T8 is electrically connected to the reset terminal R0, the source electrode of the eighth transistor T8 is electrically connected to the power supply voltage terminal ELVDD, and the drain electrode of the eighth transistor T8 is electrically connected to the gate electrode of the driver transistor DT;

[0439] The gate electrode of the ninth transistor T9 is electrically connected to the reset terminal R0, and the drain electrode of the ninth transistor T9 is electrically connected to the third node N3;

[0440] The source electrode of the ninth transistor T9 is electrically connected to the initial voltage terminal I1;

[0441] The data write circuit comprises a tenth transistor T10;

[0442] The gate electrode of the tenth transistor T10 is electrically connected to the first sense terminal G1, the source electrode of the tenth transistor T10 is electrically connected to the second node N2, and the drain electrode of the tenth transistor T10 is electrically connected to the data line Da.

[0443] In at least one embodiment of the Fig. In the pixel circuit shown in Figure 46, all transistors are n-type transistors, but not limited to them.

[0444] Fig. 47 is a working time diagram of the Fig. 46 shown pixel circuit.

[0445] The difference between at least one embodiment of the Fig. 48 and at least one embodiment of the pixel circuit shown in Fig. 46 is that the source electrode of T9 is electrically connected to the low voltage terminal ELVSS and the source electrode of T7 is electrically connected to the low voltage terminal ELVSS.

[0446] Fig. 49 is a working time diagram of the Fig. 48 shown pixel circuit.

[0447] The difference between at least one embodiment of the Fig. 50 and at least one embodiment of the pixel circuit shown in Fig. 46 is that: the gate electrode of the seventh transistor T7 is electrically connected to the second scanning terminal G2.

[0448] As in Fig. 51, if at least one embodiment of the method shown in Fig. 50 of the present disclosure, the display period includes the first phase S1, the second phase S2, the third phase S3, and the fourth phase S4, which are set sequentially;

[0449] In the first phase S1, EM1 and EM2 provide low voltage signals, R0 provides high voltage signals, G2 provides high voltage signals, G1 provides low voltage signals, Da provides data voltage Vdata, and T8 is turned on to write the reference voltage Vref provided by VR to the gate electrode of DT, T1 and T4 are turned off, T10 is turned off, T9 is turned on to write the initial voltage Vint provided by I1 to the third node N3, and T7 is turned on to write Vint to the source electrode of DT;

[0450] In the second phase S2, EM1 provides a low voltage signal, EM2 a high voltage signal, R0 a high voltage signal, G1 a low voltage signal, T8 is turned on to write Vref to the gate electrode of DT, T9 is turned on to write Vref to the third node N3; T4 is turned on, and the drain electrode of DT is electrically connected to ELVDD;

[0451] At the beginning of the second phase S2, the DT is turned on and compensates the threshold voltage according to the source-follower principle. The source potential of the DT continuously increases from Vint until the source potential of the DT reaches Vref-Vth;

[0452] In the third phase S3, EM1 supplies a low-voltage signal, EM2 a high-voltage signal, R0 a high-voltage signal, G2 a low-voltage signal, G1 a high-voltage signal, and T10 is turned on to write the data voltage Vdata to the second node N2; at this time, the difference between the potential of N2 and the potential of the source electrode of DT is Vdata-(Vref-Vth); T4 is turned on, and the drain electrode of DT is electrically connected to ELVDD;

[0453] In the fourth phase S4, EM1 and EM2 supply high-voltage signals, R0 supplies low-voltage signals, G1 supplies low-voltage signals, G2 supplies low-voltage signals, T4 is turned on, and the drain electrode of DT is electrically connected to ELVDD; T1 is turned on, and the gate potential of DT is Vdata, and the gate-source voltage of DT is Vdata-Vref+Vth; at this time, the current Ioled flowing through O1 is equal to K(Vdata-Vref) 2; where K is the current coefficient of DT. Referring to the above equation, the current Ioled supplied by the driver transistor DT to O1 can be determined from the voltage difference between Vdata and Vref; since Vref is a fixed voltage, Ioled can be determined from Vdata.

[0454] The difference between at least one embodiment of the pixel circuit shown in the present disclosure 52 and at least one embodiment of the pixel circuit shown in Fig. 50 of the present disclosure is that the source electrode of T7 is electrically connected to the third node N3 and the source electrode of T3 is not electrically connected to I1.

[0455] As in Fig. 51, if at least one embodiment of the method shown in Fig. 52 of the present disclosure, the display period includes the first phase S1, the second phase S2, the third phase S3, and the fourth phase S4, which are set sequentially;

[0456] In the first phase S1, EM1 and EM2 provide low voltage signals, R0 provides high voltage signals, G2 provides high voltage signals, G1 provides low voltage signals, Da provides data voltage Vdata, and T8 is turned on to write the reference voltage Vref provided by VR to the gate electrode of DT, T1 and T4 are turned off, T10 is turned off, T9 is turned on to write the initial voltage Vint provided by I1 to the third node N3, and T7 is turned on to write Vint to the source electrode of DT;

[0457] In the second phase S2, EM1 provides a low voltage signal, EM2 a high voltage signal, R0 a high voltage signal, G1 a low voltage signal, T8 is turned on to write Vref to the gate electrode of DT, T9 is turned on to write Vref to the third node N3; T4 is turned on, and the drain electrode of DT is electrically connected to ELVDD;

[0458] At the beginning of the second phase S2, the DT is turned on and compensates the threshold voltage according to the source-follower principle. The source potential of the DT continuously increases from Vint until the source potential of the DT reaches Vref-Vth;

[0459] In the third phase S3, EM1 supplies a low-voltage signal, EM2 a high-voltage signal, R0 a high-voltage signal, G2 a low-voltage signal, G1 a high-voltage signal, and T10 is turned on to write the data voltage Vdata to the second node N2; at this time, the difference between the potential of N2 and the potential of the source electrode of DT is Vdata-(Vref-Vth); T4 is turned on, and the drain electrode of DT is electrically connected to ELVDD;

[0460] In the fourth phase S4, EM1 and EM2 supply high-voltage signals, R0 supplies low-voltage signals, G1 supplies low-voltage signals, G2 supplies low-voltage signals, T4 is turned on, and the drain electrode of DT is electrically connected to ELVDD; T1 is turned on, and the gate potential of DT is Vdata, and the gate-source voltage of DT is Vdata-Vref+Vth; at this time, the current Ioled flowing through O1 is equal to K(Vdata-Vref) 2; where K is the current coefficient of DT. Referring to the above equation, the current Ioled supplied by the driver transistor DT to O1 can be determined from the voltage difference between Vdata and Vref; since Vref is a fixed voltage, Ioled can be determined from Vdata.

[0461] The difference between at least one embodiment of the Fig. 53 of the present disclosure and at least one embodiment of the pixel circuit shown in Fig. 50 of the present disclosure is that the source electrode of T7 and the source electrode of T9 are electrically connected to ELVSS, and the source electrode of T7 and the source electrode of T9 are not electrically connected to I1.

[0462] As in Fig. 51, the display period includes the first phase S1, the second phase S2, the third phase S3 and the fourth phase S4, which are set sequentially when at least one embodiment of the Fig. 53 of the present disclosure is in operation;

[0463] In the first phase S1, EM1 and EM2 provide low voltage signals, R0 provides high voltage signals, G2 provides high voltage signals, G1 provides low voltage signals, Da provides data voltage Vdata, and T8 is turned on to write the reference voltage Vref provided by VR to the gate electrode of DT, T1 and T4 are turned off, T10 is turned off, T9 is turned on to write the low voltage signal provided by ELVSS to the third node N3, and T7 is turned on to write the low voltage signal provided by ELVSS to the source electrode of DT;

[0464] In the second phase S2, EM1 provides a low-voltage signal, EM2 a high-voltage signal, R0 a high-voltage signal, G1 a low-voltage signal, T8 is turned on to write Vref to the gate electrode of DT, T9 is turned on to write the low-voltage signal provided by ELVSS to the third node N3; T4 is turned on, and the drain electrode of DT is electrically connected to ELVDD;

[0465] At the beginning of the second phase S2, the DT is turned on and compensates the threshold voltage according to the source-follower principle. The source potential of the DT continuously increases from Vint until the source potential of the DT reaches Vref-Vth;

[0466] In the third phase S3, EM1 supplies a low-voltage signal, EM2 a high-voltage signal, R0 a high-voltage signal, G2 a low-voltage signal, G1 a high-voltage signal, and T10 is turned on to write the data voltage Vdata to the second node N2; at this time, the difference between the potential of N2 and the potential of the source electrode of DT is Vdata-(Vref-Vth); T4 is turned on, and the drain electrode of DT is electrically connected to ELVDD;

[0467] In the fourth phase S4, EM1 and EM2 supply high-voltage signals, R0 supplies low-voltage signals, G1 supplies low-voltage signals, G2 supplies low-voltage signals, T4 is turned on, and the drain electrode of DT is electrically connected to ELVDD; T1 is turned on, and the gate potential of DT is Vdata, and the gate-source voltage of DT is Vdata-Vref+Vth; at this time, the current Ioled flowing through O1 is equal to K(Vdata-Vref) 2; where K is the current coefficient of DT. Referring to the above equation, the current Ioled supplied by the driver transistor DT to O1 can be determined from the voltage difference between Vdata and Vref; since Vref is a fixed voltage, Ioled can be determined from Vdata.

[0468] The difference between at least one embodiment of the Fig. 54 and at least one embodiment of the pixel circuit shown in Fig. 46 is that: the source electrode of T7 is electrically connected to the third node N3 and the source electrode of T7 is not electrically connected to I1.

[0469] As in Fig. 55, the display period may comprise a first phase S1, a second phase S2 and a third phase S3, which are set sequentially when at least one embodiment of the Fig.54 of the present disclosure is in operation;

[0470] In the first phase S1, EM1 and EM2 provide a low voltage signal, R0 provides a high voltage signal, G1 provides a high voltage signal, Da provides a data voltage Vdata, T9 is turned on to write the initial voltage Vint provided by I1 to the third node N3, T1 and T4 are turned off, T10 is turned on to write the data voltage Vdata to the second node N2, T9 is turned on to control the connection between the first node N1 and the third node N3 so that the potential of the first node N1 is Vref; T7 is turned on to write Vint to the source electrode of DT;

[0471] In the second phase S2, EM1 provides a low voltage signal, EM2 provides a high voltage signal, R0 provides a high voltage signal, G1 provides a low voltage signal, T8 is turned on to write Vref to the third node N3, T9 is turned on to control the connection between the first node N1 and the third node N3 so that the potential of the first node N1 is Vref; T4 is turned on, and the drain electrode of DT is electrically connected to ELVDD;

[0472] At the beginning of the second phase S2, DT is turned on, and DT compensates the threshold voltage in a source-follower manner. The source potential of DT continuously increases from Vint until the source potential of DT becomes Vref-Vth. At this time, the threshold voltage compensation is completed and DT is turned off. At this time, the difference between the potential of N2 and the source electrode potential of DT is Vdata-(Vref-Vth).

[0473] In the third phase S3, EM1 and EM2 supply high-voltage signals, R0 supplies low-voltage signals, G1 supplies low-voltage signals, T1 and T4 are turned on, the drain electrode of DT is electrically connected to ELVDD, and the gate potential of DT is Vdata, and the gate-source voltage of DT is Vdata-Vref+Vth; at this time, the current Ioled flowing through O1 is equal to K(Vdata-Vref). 2 ; where K is the current coefficient of DT. Referring to the above equation, the current Ioled supplied by the driver transistor DT to O1 can be determined from the voltage difference between Vdata and Vref; since Vref is a fixed voltage, Ioled can be determined from Vdata.

[0474] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the driving method includes:

[0475] Driving the light-emitting element by the driver circuit under the control of a potential of the control terminal of the driver circuit;

[0476] Controlling the connection between the first node and the second node by the first control circuit under the control of the first light emission control signal provided by the first light emission control line;

[0477] Storing electrical energy in the first energy storage circuit;

[0478] Writing the data voltage provided by the data line into the second node by the data writing circuit under the control of the first scanning signal provided by the first scanning terminal.

[0479] Optionally, the pixel circuit further comprises a first initialization circuit; the display period includes a first phase and a second phase which are set sequentially, and the driving method further comprises:

[0480] In the first phase, the first initialization circuit writes the first reset voltage to the second terminal of the driver circuit;

[0481] In the second phase, the first initialization circuit writes the first reset voltage to the second terminal of the driver circuit; the data write circuit writes the data voltage provided by the data line to the second node under the control of the first strobe signal.

[0482] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the driving method includes:

[0483] Driving the light-emitting element by the driver circuit under the control of the potential of the control terminal of the driver circuit;

[0484] Control by the first control circuit to connect the first node and the second node under the control of the first light emission control signal provided by the first light emission control line;

[0485] Storage of electrical energy by the first energy storage circuit; Storage of electrical energy by the second energy storage circuit;

[0486] Writing the data voltage provided by the data line into the second node by the data writing circuit under the control of the first scanning signal provided by the first scanning terminal;

[0487] Control by the second initialization circuit to connect the second terminal of the driver circuit and the second reset voltage terminal under the control of the scanning signal provided by the scanning terminal;

[0488] Controlling the potential of the third node by the second write circuit under the control of the reset signal provided from the reset terminal.

[0489] Optionally, the pixel circuit further comprises a first write-in circuit; the display period comprises a first phase and a second phase which are set sequentially; the driving method comprises:

[0490] In the first phase, the first write circuit writes the write voltage into the control terminal of the driver circuit, the second initialization circuit controls to connect the second terminal of the driver circuit and the second reset voltage terminal, and the second write circuit writes the first reset voltage into the third node, and the data write circuit writes the data voltage provided by the data line into the second node;

[0491] In the second phase, the first write circuit writes the write voltage to the control terminal of the driver circuit, and the second write circuit writes the first reset voltage to the third node.

[0492] Optionally, the pixel circuit further comprises a first write-in circuit; the display period comprises a first phase and a second phase which are set sequentially; the driving method comprises:

[0493] In the first phase, the first write circuit writes the write voltage into the control terminal of the driver circuit or the third node, and the second initialization circuit controls to connect the second terminal of the driver circuit and the second reset voltage terminal, the second write circuit controls to connect the control terminal of the driver circuit and the third node, and the data write circuit writes the data voltage provided by the data line into the second node;

[0494] In the second phase, the first write circuit writes the write voltage into the control terminal of the driver circuit or the third node, and the second write circuit controls to connect the control terminal of the driver circuit and the third node.

[0495] The display device described in the embodiment of the present disclosure includes the pixel circuit.

[0496] The display device provided by the embodiments of the present disclosure may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook, a digital photo frame, a navigation device, and the like.

[0497] The above descriptions are implementations of the present disclosure. It should be noted that those skilled in the art may make some improvements and modifications without departing from the principle of the present disclosure. These improvements and modifications also fall within the scope of the present disclosure.

Claims

[1] A pixel circuit comprising a light-emitting element, a driver circuit, a first energy storage circuit, a first control circuit and a data writing circuit, wherein a control terminal of the driver circuit is electrically connected to a first node, a first terminal of the driver circuit is electrically connected to a power supply voltage terminal, and a second terminal of the driver circuit is electrically connected to the light-emitting element; the driver circuit is configured to drive the light-emitting element under the control of a potential of the control terminal of the driver circuit; a control terminal of the first control circuit is electrically connected to a first light emission control line, a first terminal of the first control circuit is electrically connected to the first node, and a second terminal of the first control circuit is electrically connected to a second node; the first control circuit is configured to control the connection between the first node and the second node under the control of a first light emission control signal provided by the first light emission control line; a first terminal of the first energy storage circuit is electrically connected to the second node, and a second terminal of the first energy storage circuit is electrically connected to the second terminal of the driver circuit; the first energy storage circuit is configured to store electrical energy; the data write circuit is electrically connected to a first sensing terminal, the second node, and a data line, respectively, and is configured to write a data voltage provided by the data line to the second node under the control of a first sensing signal provided by the first sensing terminal. [2] The pixel circuit according to claim 1, further comprising a first reference voltage writing circuit, wherein the first reference voltage writing circuit is electrically connected to a second reset terminal and the first node, respectively, and the first reference voltage writing circuit is also electrically connected to a reference voltage terminal or the power supply voltage terminal, configured to write a reference voltage provided by the reference voltage terminal or a power supply voltage provided by the power supply voltage terminal into the first node under the control of a second reset signal provided by the second reset terminal. [3] The pixel circuit of claim 2, further comprising a second reference voltage writing circuit, wherein the second reference voltage writing circuit is electrically connected to a first reset terminal, the reference voltage terminal, and the first node, respectively, and is configured to write the reference voltage to the first node under the control of the first reset signal provided by the first reset terminal. [4] The pixel circuit according to claim 2, further comprising a first light emission control circuit, wherein the first light emission control circuit is electrically connected to the second light emission control line, the power supply voltage terminal, and the first terminal of the driver circuit, and is configured to control the connection between the power supply voltage terminal and the first terminal of the driver circuit under the control of the second light emission control signal provided from the second light emission control line. [5] The pixel circuit according to claim 4, further comprising a second light emission control circuit, wherein the second light emission control circuit is electrically connected to the second light emission control line, the second terminal of the driving circuit, and a first terminal of the light emitting element, respectively, and is configured to control the connection between the second terminal of the driving circuit and the first terminal of the light emitting element under the control of the second light emission control signal provided from the second light emission control line. [6] The pixel circuit of claim 1, further comprising a first initialization circuit, wherein the first initialization circuit is electrically connected to a first reset terminal, a first reset voltage terminal, and the second terminal of the driver circuit, and is configured to write a first reset voltage provided by the first reset voltage terminal to the second terminal of the driver circuit under the control of a first reset signal provided by the first reset terminal; the first reset voltage terminal comprises an initial voltage terminal, a first voltage terminal, a reference voltage terminal or the power supply voltage terminal. [7] The pixel circuit of claim 1, wherein the driver circuit comprises a driver transistor, the first control circuit comprises a first transistor, and the first energy storage circuit comprises a first capacitor; a gate electrode of the first transistor is electrically connected to the first light emission control line, a first electrode of the first transistor is electrically connected to the first node, and a second electrode of the first transistor is electrically connected to the second node; a gate electrode of the driver transistor is electrically connected to the first node, a first electrode of the driver transistor is electrically connected to the power supply voltage terminal, and a second electrode of the driver transistor is electrically connected to the light-emitting element; a first terminal of the first capacitor is electrically connected to the second node, and a second terminal of the first capacitor is electrically connected to a second electrode of the driver transistor. [8] The pixel circuit of claim 2, wherein the first reference voltage writing circuit comprises a second transistor; a gate electrode of the second transistor is electrically connected to the second reset terminal, a first electrode of the second transistor is electrically connected to the reference voltage terminal, and a second electrode of the second transistor is electrically connected to the first node; or, the gate electrode of the second transistor is electrically connected to the second reset terminal, the first electrode of the second transistor is electrically connected to the power supply voltage terminal, and the second electrode of the second transistor is electrically connected to the first node. [9] The pixel circuit according to claim 3, wherein the second reference voltage writing circuit comprises a third transistor; a gate electrode of the third transistor is electrically connected to the first reset terminal, a first electrode of the third transistor is electrically connected to the reference voltage terminal, and a second electrode of the third transistor is electrically connected to the first node. [10] The pixel circuit according to claim 5, wherein the first light emission control circuit comprises a fourth transistor; a gate electrode of the fourth transistor is electrically connected to the second light emission control line, a first electrode of the fourth transistor is electrically connected to the power supply voltage terminal, and a second electrode of the fourth transistor is electrically connected to the first terminal of the driver circuit; the second light emission control circuit comprises a fifth transistor; a gate electrode of the fifth transistor is electrically connected to the second light emission control line, a first electrode of the fifth transistor is electrically connected to the second terminal of the driver circuit, a second electrode of the fifth transistor is electrically connected to the first terminal of the light-emitting element. [11] The pixel circuit according to claim 6, wherein the first initialization circuit comprises a sixth transistor; a gate electrode of the sixth transistor is electrically connected to the first reset terminal, a first electrode of the sixth transistor is electrically connected to the initial voltage terminal, the first voltage terminal, the reference voltage terminal, or the power supply voltage terminal, and a second electrode of the sixth transistor is electrically connected to the second terminal of the driver circuit. [12] The pixel circuit of claim 1, further comprising a second energy storage circuit and a second initialization circuit, wherein a second terminal of the first energy storage circuit is electrically connected to the second terminal of the driver circuit via the second energy storage circuit; a first terminal of the second energy storage circuit is electrically connected to a third node, a second terminal of the second energy storage circuit is electrically connected to the second terminal of the driver circuit, and the second energy storage circuit is configured to store electrical energy; the second initialization circuit is electrically connected to a sensing terminal, the second terminal of the driver circuit, and the second reset voltage terminal, and is configured to control the connection between the second terminal of the driver circuit and the second reset voltage terminal under the control of a sensing signal provided by the sensing terminal; the second reset voltage terminal comprises an initial voltage terminal, a first voltage terminal, or a third node; the sensing terminal comprises a first sensing terminal or a second sensing terminal. [13] The pixel circuit according to claim 1, further comprising a second energy storage circuit, a first reference voltage writing circuit, a data writing circuit, and a first initialization circuit, wherein the second node is electrically connected to the first node via the second energy storage circuit; the first reference voltage writing circuit is electrically connected to the reset terminal, the reference voltage terminal, and the first node, respectively, and is configured to write the reference voltage provided by the reference voltage terminal into the first node under the control of the reset signal provided by the reset terminal; the data write circuit is electrically connected to the first sensing terminal, the second node, and the data line, respectively, and is configured to write the data voltage provided by the data line to the second node under the control of the first sensing signal provided by the first sensing terminal; the first initialization circuit is electrically connected to the reset terminal, the initial voltage terminal, and the second terminal of the driver circuit, and is configured to write the initial voltage provided by the initial voltage terminal to the second terminal of the driver circuit under the control of the reset signal provided by the reset terminal. [14] A pixel circuit comprising a light-emitting element, a driver circuit, an energy storage unit, a first control circuit, a data writing circuit and a second initialization circuit, wherein a control terminal of the driver circuit is electrically connected to a first node, a first terminal of the driver circuit is electrically connected to a power supply voltage terminal, and a second terminal of the driver circuit is electrically connected to the light-emitting element; the driver circuit is configured to drive the light-emitting element under the control of a potential of the control terminal of the driver circuit; a control terminal of the first control circuit is electrically connected to a first light emission control line, a first terminal of the first control circuit is electrically connected to the first node, and a second terminal of the first control circuit is electrically connected to a second node; the first control circuit is configured to control the connection between the first node and the second node under the control of a first light emission control signal provided by the first light emission control line; the data write circuit is electrically connected to a first sensing terminal, the second node, and a data line, respectively, and is configured to write a data voltage provided by the data line to the second node under the control of a first sensing signal provided by the first sensing terminal; the second initialization circuit is electrically connected to a sensing terminal, the second terminal of the driver circuit, and a second reset voltage terminal, and is configured to control the connection between the second terminal of the driver circuit and the second reset voltage terminal under the control of a sensing signal provided by the sensing terminal; the energy storage unit comprises a first energy storage circuit, a second energy storage circuit and a second write circuit; a first terminal of the first energy storage circuit is electrically connected to the second node, a second terminal of the first energy storage circuit is electrically connected to the third node, and the first energy storage circuit is configured to store electrical energy; a first terminal of the second energy storage circuit is electrically connected to the third node, a second terminal of the second energy storage circuit is electrically connected to the second terminal of the driver circuit, and the second energy storage circuit is configured to store electrical energy; the second write circuit is electrically connected to a reset terminal and the third node, respectively, and is configured to control a potential of the third node under the control of a reset signal provided from the reset terminal. [15] The pixel circuit of claim 14, wherein the second reset voltage terminal comprises an initial voltage terminal, a first voltage terminal, or a third node; the sensing terminal comprises a first sensing terminal or a second sensing terminal. [16] The pixel circuit of claim 14, further comprising a first write circuit, wherein the first write circuit is electrically connected to the reset terminal, a write voltage terminal, and a write node, respectively, and is configured to write a write voltage provided by the write voltage terminal into the write node under the control of the reset signal provided by the reset terminal; the write-in node comprises the first node or the third node, and the write-in voltage terminal comprises a reference voltage terminal or the power supply voltage terminal. [17] The pixel circuit of claim 16, wherein the second write circuit is further electrically connected to a first reset voltage terminal and configured to write a first reset voltage provided by the first reset voltage terminal to the third node under the control of the reset signal provided by the reset terminal; the first reset voltage terminal comprises the initial voltage terminal, the first voltage terminal, the reference voltage terminal, or the power supply voltage terminal. [18] The pixel circuit of claim 14, wherein the second write-in circuit is further electrically connected to the control terminal of the driver circuit and is configured to control the connection between the control terminal of the driver circuit and the third node under the control of the reset signal. [19] The pixel circuit according to any one of claims 14 to 18, further comprising a first light emission control circuit, wherein the first light emission control circuit is electrically connected to a second light emission control line, the power supply voltage terminal, and the first terminal of the driver circuit, and is each configured to control the connection between the power supply voltage terminal and the first terminal of the driver circuit under the control of a second light emission control signal provided by the second light emission control line. [20] The pixel circuit of claim 14, wherein the first energy storage circuit comprises a first capacitor, the second energy storage circuit comprises a second capacitor, and the second initialization circuit comprises a seventh transistor; a gate electrode of the seventh transistor is electrically connected to a first sense terminal or a second sense terminal, a first electrode of the seventh transistor is electrically connected to a second reset voltage terminal, and a second electrode of the seventh transistor is electrically connected to the second terminal of the driver circuit; a first terminal of the first capacitor is electrically connected to the second node, and a second terminal of the first capacitor is electrically connected to the third node; a first terminal of the second capacitor is electrically connected to the third node and a second terminal of the second capacitor is electrically connected to the second terminal of the driver circuit. [21] The pixel circuit according to claim 16, wherein the first write-in circuit comprises an eighth transistor; a gate electrode of the eighth transistor is electrically connected to the reset terminal, a first electrode of the eighth transistor is electrically connected to the reference voltage terminal, and a second electrode of the eighth transistor is electrically connected to the control terminal of the driver circuit. [22] The pixel circuit of claim 17, wherein the second write-in circuit comprises a ninth transistor; a gate electrode of the ninth transistor is electrically connected to the reset terminal, a first electrode of the ninth transistor is electrically connected to the first reset voltage terminal, and a second electrode of the ninth transistor is electrically connected to the third node. [23] The pixel circuit of claim 18, wherein the second write-in circuit comprises a ninth transistor; a gate electrode of the ninth transistor is electrically connected to the reset terminal, a first electrode of the ninth transistor is electrically connected to the third node, and a second electrode of the ninth transistor is connected to the control circuit of the driver circuit. [24] The pixel circuit according to claim 19, wherein the first light emission control circuit comprises a fourth transistor; a gate electrode of the fourth transistor is electrically connected to the second light emission control line, a first electrode of the fourth transistor is electrically connected to the power supply voltage terminal, and a second electrode of the fourth transistor is electrically connected to the first terminal of the driver circuit. [25] The pixel circuit of claim 14, wherein the data write circuit comprises a tenth transistor; a gate electrode of the tenth transistor is electrically connected to the first sense terminal, a first electrode of the tenth transistor is electrically connected to the second node, and a second electrode of the tenth transistor is electrically connected to the data line; the first control circuit comprises a first transistor; a gate electrode of the first transistor is electrically connected to the first light emission control line, a first electrode of the first transistor is electrically connected to the first node, and a second electrode of the first transistor is electrically connected to the second node. [26] A driving method applied to the pixel circuit according to any one of claims 1 to 13, the driving method comprising: Driving the light-emitting element by the driver circuit under the control of the potential of the control terminal of the driver circuit; Controlling the connection between the first node and the second node by the first control circuit under the control of the first light emission control signal provided by the first light emission control line; Storing electrical energy in the first energy storage circuit; Writing the data voltage provided by the data line into the second node by the data writing circuit under the control of the first scanning signal provided by the first scanning terminal. [27] The driving method according to claim 26, wherein the pixel circuit further comprises a first initialization circuit; the display period comprises a first phase and a second phase which are set sequentially, and the driving method further comprises: in the first phase, writing the first reset voltage into the second terminal of the driver circuit by the first initialization circuit; In the second phase, the first initialization circuit writes the first reset voltage to the second terminal of the driver circuit; the data write circuit writes the data voltage provided by the data line to the second node under the control of the first strobe signal. [28] A driving method applied to the pixel circuit according to any one of claims 14 to 25, the driving method comprising: Driving the light-emitting element by the driver circuit under the control of the potential of the control terminal of the driver circuit; Controlling the connection between the first node and the second node by the first control circuit under the control of the first light emission control signal provided by the first light emission control line; Storing electrical energy in the first energy storage circuit; Storing electrical energy in the second energy storage circuit; Writing the data voltage provided by the data line into the second node by the data writing circuit under the control of the first scanning signal provided by the first scanning terminal; Control by the second initialization circuit to connect the second terminal of the driver circuit and the second reset voltage terminal under the control of the scanning signal provided by the scanning terminal; Controlling the potential of the third node by the second write circuit under the control of the reset signal provided by the reset terminal. [29] The driving method according to claim 28, wherein the pixel circuit further comprises a first write-in circuit; the display period comprises a first phase and a second phase which are set sequentially; the driving method comprises: in the first phase, writing the write voltage into the control terminal of the driver circuit by the first write circuit, controlling the second initialization circuit to connect the second terminal of the driver circuit and the second reset voltage terminal, and writing the first reset voltage into the third node by the second write circuit, and writing the data voltage provided by the data line into the second node by the data write circuit; in the second phase, writing the write voltage into the control terminal of the driver circuit by the first write circuit, and writing the first reset voltage into the third node by the second write circuit. [30] The driving method according to claim 28, wherein the pixel circuit further comprises a first write-in circuit; the display period comprises a first phase and a second phase which are set sequentially; the driving method comprises: in the first phase, writing the write voltage into the control terminal of the driver circuit or the third node by the first write circuit, and controlling the second initialization circuit to connect the second terminal of the driver circuit and the second reset voltage terminal, and controlling the second write circuit to connect the control terminal of the driver circuit and the third node, and writing the data voltage provided by the data line into the second node by the data write circuit; in the second phase, writing the write voltage into the control terminal of the driver circuit or the third node by the first write circuit, and controlling the second write circuit to connect the control terminal of the driver circuit and the third node. [31] A display device comprising the pixel circuit according to any one of claims 1 to 25.

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