Semiconductor device

Abstract

Semiconductor device (100) comprising: a semiconductor substrate (10) having an upper surface (21) and a lower surface (23) having a drift region (18) of a first conductivity type; and a diode section (80) arranged in the semiconductor substrate (10), wherein: the diode section (80) comprises: a base region (14) of a second conductivity type arranged between the drift region (18) and the upper surface (21) of the semiconductor substrate (10); a first lifetime region (204) arranged in the drift region (18) on one side of the lower surface (23) of the semiconductor substrate (10) relative to the base region (14);and a second lifetime region (200) arranged such that it is positioned between first lifetime regions (204) including the first lifetime region (204) in a first direction parallel to the upper surface (21) of the semiconductor substrate (10), and in which a charge carrier lifetime is longer than in the first lifetime region (204), and a width of the second lifetime region (200) in the first direction is greater than a width W (µm) given by expression 1: W = 0.21 × T1 + 3.3 where T1 is a thickness (µm) of the first lifetime region (204) in a second direction perpendicular to the upper surface (21).

Description

BACKGROUND 1. TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device. 2. STATE OF THE ART

[0002] Conventionally, in a semiconductor device having a freewheeling diode (FWD) or the like, there is a known technology for forming lattice defects in the semiconductor substrate to adjust a carrier lifetime (see, for example, Patent Documents 1 and 2). Patent Document 1: Publication of Japanese Patent Application No. 2020-31155 Patent Document 2: Publication of Japanese Patent Application No. 2020-120121 TECHNICAL TASK

[0003] In a semiconductor device, it is preferable to suppress snapback. GENERAL REVELATION

[0004] To solve the problem described above, a first aspect of the present invention provides a semiconductor device. The semiconductor device may include a semiconductor substrate having an upper surface and a lower surface, the semiconductor substrate including a drift region of a first conductivity type. The semiconductor device according to any one of the above aspects may include a diode portion disposed in the semiconductor substrate. In the semiconductor device according to any one of the above aspects, the diode portion may include a base region of a second conductivity type disposed between the drift region and the upper surface of the semiconductor substrate. In the semiconductor device according to any one of the above aspects, the diode portion may have a first lifetime region disposed in the drift region on a lower surface side of the semiconductor substrate relative to the base region.In the semiconductor device according to any one of the above aspects, the diode portion may have a second lifetime region arranged to be located between first lifetime regions including the first lifetime region in a first direction parallel to the upper surface of the semiconductor substrate, and in which a carrier lifetime is longer than in the first lifetime region. In the semiconductor device according to any one of the above aspects, a width of the second lifetime region in the first direction may be larger than a width W (µm) given by Expression 1:. W=0.21×T1+3.3 where T1 is a thickness of the first lifetime region in a second direction perpendicular to the top surface.

[0005] In the semiconductor device according to any one of the above aspects, the width of the second lifetime region in the first direction may be 7 µm or more.

[0006] In the semiconductor device according to any one of the above aspects, the width of the second lifetime region in the first direction may be 12 µm or less.

[0007] In the semiconductor device according to any one of the above aspects, the diode portion may have one or more second lifetime ranges including the second lifetime range. A sum of widths of the one or more second lifetime ranges in the first direction may be 0.1 times or less of a width of the diode portion in the first direction.

[0008] The semiconductor device according to any one of the above aspects may include a transistor portion disposed in the semiconductor substrate and juxtaposed with a diode portion in the first direction.

[0009] In the semiconductor device according to any one of the above aspects, the diode portion and the transistor portion may include a plurality of trench portions spaced apart from each other in the first direction.

[0010] The semiconductor device according to any one of the above aspects may include a transistor portion disposed in the semiconductor substrate and juxtaposed with the diode portion in a third direction parallel to the top surface of the semiconductor substrate and perpendicular to the first direction.

[0011] In the semiconductor device according to any one of the above aspects, the diode portion and the transistor portion may include a plurality of trench portions spaced apart from each other in the third direction.

[0012] In the semiconductor device according to any one of the above aspects, at least some of the trench portions of the diode portion are arranged above the first lifetime region, and a distance between the second lifetime region and the transistor portion in the first direction may be greater than or equal to a distance between a lower end of a trench portion of the trench portions and the first lifetime region in the second direction.

[0013] In the semiconductor device according to any one of the above aspects, the diode portion may have two or more second lifetime regions including the second lifetime region spaced apart from each other in the first direction.

[0014] In the semiconductor device according to any one of the above aspects, the second lifetime region may also be arranged between first lifetime regions including the first lifetime region in a third direction parallel to the upper surface of the semiconductor substrate and perpendicular to the first direction.

[0015] In the semiconductor device according to any one of the above aspects, a width of the second lifetime region in the third direction may be 0.2 times or more of the thickness of the first lifetime region in the second direction.

[0016] In the semiconductor device according to any one of the above aspects, the width of the second lifetime region in the first direction may be greater than or equal to 3% of a diffusion length of electrons in the semiconductor substrate.

[0017] In the semiconductor device according to any one of the above aspects, the thickness of the first lifetime region in the second direction may be 100 µm or less.

[0018] In the semiconductor device according to any one of the above aspects, the width of the second lifetime region in the first direction may be 0.2 times or more of the thickness of the first lifetime region in the second direction perpendicular to the top surface of the semiconductor substrate.

[0019] In the semiconductor device according to any one of the above aspects, the first lifetime region may contain hydrogen. In the semiconductor device according to any one of the above aspects, the first lifetime region may contain helium.

[0020] In the semiconductor device according to any one of the above aspects, the first lifetime region may be arranged in the diode section and the transistor section. A ratio of an area of ​​the second lifetime region 200 enclosed by the first lifetime region to an area of ​​the first lifetime region 204 in the transistor section of the semiconductor device according to any one of the above aspects may be smaller than a ratio of an area of ​​the second lifetime region 200 enclosed by the first lifetime region to an area of ​​the first lifetime region in the diode section.

[0021] In the semiconductor device according to any one of the above aspects, the first lifetime range may be arranged in the diode section and the transistor section. In the semiconductor device according to any one of the above aspects, the second lifetime range may be arranged in the first lifetime range of the diode section. In the semiconductor device according to any one of the above aspects, the second lifetime range may not be arranged in the first lifetime range of the transistor section.

[0022] In the semiconductor device according to any one of the above aspects, each of the plurality of trench portions may extend in one direction at an angle greater than 0 degrees and less than 90 degrees with respect to the first direction on the upper surface of the semiconductor substrate.

[0023] It should be noted that the summary described above does not necessarily describe all necessary features of the embodiments of the present invention. Furthermore, the present invention may also be a sub-combination of the features described above. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates a plan view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. Figure 2 illustrates an enlarged view of an area D in Fig. 1. Fig. 3 illustrates an example of a cross section ee in Fig. 2. Fig. 4 illustrates examples of VI characteristics during forward conduction of a diode section 80 according to a comparative example. Fig. 5 illustrates an arrangement example of a first lifetime region 204 and a second lifetime region 200 in a diode section 80. Fig. 6 illustrates an enlarged cross-sectional view near a second lifetime region 200. Fig. Figure 7 illustrates distribution examples of carrier lifetimes, vacancy densities and chemical helium concentrations on a line ff in Fig. 6. Fig. Figure 8 illustrates distribution examples of charge carrier lifetimes, vacancy densities and chemical helium concentrations on a line gg in Fig. 6. Fig. Figure 9 illustrates distribution examples of charge carrier lifetimes, vacancy densities and chemical helium concentrations on a line hh in Fig. 6. Fig. 10 illustrates another example of an enlarged cross-sectional view near a second lifetime region 200. Fig. 11A shows a distribution diagram of a net doping concentration (A), a distribution diagram of a chemical hydrogen concentration (B), a distribution diagram of a lattice defect density (C), a distribution diagram of a charge carrier lifetime (D), a distribution diagram of a charge carrier mobility (E), and a distribution diagram of a charge carrier concentration (F) along a line hh in a semiconductor device 100 according to the method shown in Fig. 10 shown embodiment. Fig. 11B illustrates another example of an enlarged cross-sectional view near a second lifetime region 200. Fig. 11C shows another example of a distribution diagram of a net doping concentration (A), a distribution diagram of a chemical hydrogen concentration (B), a distribution diagram of a lattice defect density (C), a distribution diagram of a charge carrier lifetime (D), a distribution diagram of a charge carrier mobility (E), and a distribution diagram of a charge carrier concentration (F) along a line hh in a semiconductor device 100 according to the method shown in Fig. 11B shown embodiment. Fig. 11D illustrates another example of an enlarged cross-sectional view near a second lifetime region 200. Fig. Figure 12 illustrates examples of VI characteristics during forward conduction of a diode section 80. Fig. Figure 13 illustrates trade-off characteristics between a forward voltage Vf and a reverse recovery loss Err in a diode section 80. Fig. 14 illustrates a relationship between a width W1 of a second lifetime region 200 and a snapback amount (an SB amount). Fig. 15 illustrates whether snapback has occurred when a thickness T1 of a first lifetime region 204 and a width W1 of a second lifetime region 200 are changed. Fig. 16A illustrates another arrangement example of a first lifetime region 204 and a second lifetime region 200 in a diode section 80. Fig. 16B illustrates another arrangement example of a first lifetime region 204 and a second lifetime region 200 in a diode section 80. Fig. 16C illustrates another arrangement example of a first lifetime region 204 and a second lifetime region 200 in a diode section 80. Fig. 17 illustrates whether a snapback has occurred when the number of second lifetime regions 200 included in a diode section 80 and a width W1 of each of the second lifetime regions 200 are changed. Fig. 18 illustrates an arrangement example of a first lifetime region 204 and a second lifetime region 200 in an XY plane. Fig. 19 illustrates another arrangement example of a first lifetime region 204 and a second lifetime region 200 in an XY plane. Fig. 20 illustrates another arrangement example of a first lifetime region 204 and a second lifetime region 200 in an XY plane. Fig. 21 illustrates another arrangement example of a first lifetime region 204 and a second lifetime region 200 in an XY plane. Fig. 22A illustrates another arrangement example of a first lifetime region 204 and a second lifetime region 200 in an XY plane. Fig. 22B illustrates another arrangement example of a first lifetime region 204 and a second lifetime region 200 in a diode section 80. Fig. 23A illustrates another arrangement example of a first lifetime region 204 and a second lifetime region 200 in an XY plane. Fig. 23B illustrates another arrangement example of a first lifetime region 204 and a second lifetime region 200 in an XY plane. Fig. 24 illustrates another arrangement example of a first lifetime region 204 and a second lifetime region 200 in an XY plane. Fig. 25 illustrates another arrangement example of a first lifetime region 204 and a second lifetime region 200 in an XY plane. Fig. 26 illustrates another arrangement example of a first lifetime region 204 and a second lifetime region 200 in an XY plane. DESCRIPTION OF EXEMPLARY EMBODIMENTS

[0024] In the following, the present invention will be described by means of embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Furthermore, not all combinations of features described in the embodiments are essential to the solution of the invention.

[0025] In this specification, one side in a direction parallel to a depth direction of a semiconductor substrate is referred to as the "upper" side, and another side is referred to as the "lower" side. One of two main surfaces of a substrate, layer, or other member is referred to as an upper surface, and another surface is referred to as a lower surface. The "upper" and "lower" directions are not limited to a direction of gravity or a direction in which a semiconductor device is mounted.

[0026] In this specification, technical aspects may be described using orthogonal coordinate axes of an X-axis, a Y-axis, and a Z-axis. The orthogonal coordinate axes merely specify relative positions of components and do not restrict a specific direction. For example, the Z-axis is not limited to specifying the height direction relative to the ground. Note that a +Z-axis direction and a -Z-axis direction are directions opposite to each other. When the Z-axis direction is described without specifying a positive or negative sign, it means that the direction is parallel to the +Z-axis and the -Z-axis.

[0027] In this specification, orthogonal axes parallel to the upper surface and the lower surface of the semiconductor substrate are referred to as the X-axis and the Y-axis. Furthermore, an axis perpendicular to the upper surface and the lower surface of the semiconductor substrate is referred to as the Z-axis. In this specification, the Z-axis direction may be referred to as the depth direction. Furthermore, in this specification, a direction parallel to the upper surface and the lower surface of the semiconductor substrate may be referred to as a horizontal direction, including an X-axis direction and a Y-axis direction.

[0028] A region from a center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate may be referred to as an upper surface side. Similarly, a region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate may be referred to as a lower surface side.

[0029] In this specification, a case where a term such as "equal" or "the same" is mentioned may include a case where an error is included due to manufacturing variation or the like. The error is, for example, within 10%.

[0030] In this specification, the conductivity type of a doping region in which doping with an impurity has been performed is described as P-type or N-type. In this specification, the impurity may specifically mean either an N-type donor or a P-type acceptor and may be described as a dopant. In this specification, doping means that the donor or acceptor is introduced into the semiconductor substrate and converted into a semiconductor having an N-type conductivity type or a semiconductor having a P-type conductivity type.

[0031] In this specification, a doping concentration means a concentration of the donor or an acceptor concentration in a thermal equilibrium state. In this specification, a net doping concentration means a net concentration obtained by adding the donor concentration, which is defined as a positive ion concentration, to the acceptor concentration, which is defined as a negative ion concentration, taking charge polarities into account. For example, if the donor concentration N D and the acceptor concentration N A the net doping concentration at any position is called N D -N A In this specification, the net doping concentration can be simply described as the doping concentration.

[0032] The donor has a function of supplying electrons to a semiconductor. The acceptor has a function of receiving electrons from the semiconductor. The donor and acceptor are not limited to the impurities themselves. For example, a VOH defect, in which a vacancy (V), oxygen (O), and hydrogen (H) present in the semiconductor are bonded together, acts as the donor that supplies electrons. In the present description, the VOH defect may be referred to as a hydrogen donor.

[0033] In the semiconductor substrate in the present specification, N-type volume donors are distributed throughout. A volume donor is a dopant donor that is substantially uniformly contained in the ingot during the manufacture of the ingot from which the semiconductor substrate is made. The volume donor, in this example, is an element other than hydrogen. The volume donor dopant is, for example, phosphorus, antimony, arsenic, selenium, or sulfur, but is not limited to these. The volume donor, in this example, is phosphorus. The volume donor is also contained in a P-type region. The semiconductor substrate may be a wafer cut from a semiconductor ingot or may be a chip obtained by singulating the wafer. The semiconductor ingot may be manufactured by a Czochralski process (CZ process), a magnetic field-applied Czochralski process (MCZ process), or a float zone process (FZ process).In this example, the ingot is produced using the MCZ process. The oxygen concentration in the substrate produced using the MCZ process is 1 × 10. 17 up to 7 × 10 17 / cm 3 . The concentration of oxygen contained in the substrate produced by the FZ process is 1 × 10 15 up to 5 × 10 16 / cm 3. When the oxygen concentration is higher, hydrogen donors tend to be more easily generated. A chemical concentration of the volume donors distributed throughout the semiconductor substrate can be used as a volume donor concentration, and the volume donor concentration can have a value between 90% and 100% of the chemical concentration. Furthermore, an undoped substrate that does not contain a dopant such as phosphorus can be used as the semiconductor substrate. In this case, a volume donor concentration (D0) of the undoped substrate is, for example, 1 × 1010 / cm3 or more and 5 × 1012 / cm3 or less. The volume donor concentration (D0) of the undoped substrate is preferably 1 × 10 11 / cm 3 or more. The volume donor concentration (D0) of the undoped substrate is preferably 5 × 10 12 / cm 3or less. It should be noted that each concentration in the present invention may have a value at room temperature. For example, a value at 300 K (Kelvin) (about 26.9 degrees C) may be used as the value at room temperature.

[0034] In this specification, designation as P+-type or N+-type means a higher doping concentration than that of P-type or N-type, and designation as P--type or N-type means a lower doping concentration than that of P-type or N-type. Also, in this specification, designation as P++-type or N++-type means a higher doping concentration than that of P+-type or N+-type. In this specification, a system of units is an SI system of units unless otherwise specified. Although a unit of length can be expressed in cm, various calculations can be performed after converting to meters (m).

[0035] A chemical concentration in the present specification refers to an atomic density of an impurity, which is measured independently of an electrical activation state. The chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by capacitance-voltage profiling (CV method). In addition, a carrier concentration measured by spreading resistance profiling (SRP method) can be defined as the net doping concentration. The carrier concentration measured by the CV method or the SRP method can be a value in a thermal equilibrium state. Furthermore, in an N-type region, the donor concentration is sufficiently larger than the acceptor concentration, and thus the carrier concentration in the region can be defined as the donor concentration.Similarly, in a P-type region, the carrier concentration in the region can be defined as the acceptor concentration. In this specification, the doping concentration in the N-type region can be referred to as the donor concentration, and the doping concentration in the P-type region can be referred to as the acceptor concentration.

[0036] When a concentration distribution of donor, acceptor, or net doping has a peak in a region, a value of the peak may be set as the concentration of donor, acceptor, or net doping in the region. In a case where the concentration of donor, acceptor, or net doping is substantially uniform in a region, or the like, an average value of the concentration of donor, acceptor, or net doping in the region may be set as the concentration of donor, acceptor, or net doping. In the present specification, atoms / cm 3 or / cm 3 Used to express a concentration per unit volume. This unit is used for the donor or acceptor concentration, or the chemical concentration in the semiconductor substrate. Atoms may be omitted.

[0037] The carrier concentration measured by the SRP method may be lower than the concentration of the donor or acceptor. In a region where a current flows, when measuring a spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in a crystalline state. The decrease in carrier mobility occurs when carriers are scattered due to a disruption (disturbance) of a crystal structure caused by lattice defects or the like.

[0038] The concentration of the donor or acceptor calculated from the carrier concentration measured by the CV method or the SRP method may be lower than the chemical concentration of an element that serves as the donor or acceptor. For example, in a silicon semiconductor, the donor concentration of phosphorus or arsenic, which serves as a donor, or the acceptor concentration of boron (boron), which serves as an acceptor, is approximately 99% of their chemical concentrations. On the other hand, in a silicon semiconductor, the donor concentration of hydrogen, which serves as a donor, is approximately 0.1% to 10% of the chemical hydrogen concentration.

[0039] Fig. 1 illustrates a plan view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. 1 shows a position where each element is projected onto an upper surface of a semiconductor substrate 10. Fig. 1 shows only some elements of the semiconductor device 100, and illustration of some elements has been omitted.

[0040] The semiconductor device 100 includes the semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed from a semiconductor material. For example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has end faces 162 in a plan view. When referred to simply as the plan view in the present description, this means that the semiconductor substrate 10 is viewed from a top surface side. In this example, the semiconductor substrate 10 has two sets of end faces 162 that are opposite each other in a plan view. Fig. 1, the X-axis and the Y-axis are parallel to any one of the end faces 162. Furthermore, the Z-axis is perpendicular to the upper surface of the semiconductor substrate 10.

[0041] The semiconductor substrate 10 has an active portion 160. The active portion 160 is a region in which a main current flows in a depth direction between the upper surface and a lower surface of the semiconductor substrate 10 when the semiconductor device 100 is operated. An emitter electrode is arranged above the active portion 160, but its illustration has been omitted in Fig. 1. The active portion 160 may refer to a region that overlaps with the emitter electrode in a plan view. Furthermore, a region that is sandwiched between active portions 160 in a plan view may also be included in the active portion 160.

[0042] The active section 160 includes transistor sections 70 that include transistor elements such as an insulated gate bipolar transistor (IGBT). The active section 160 may further include diode sections 80 that include diode elements such as a freewheeling diode (FWD). In the Fig. In the example shown in Figure 1, the transistor sections 70 and the diode sections 80 are arranged alternately along a predetermined arrangement direction (the X-axis direction in this example) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 in this example is a reverse conducting IGBT (RC-IGBT).

[0043] In Fig. 1, a region in which a transistor section 70 is arranged is marked with a symbol "I", and a region in which a diode section 80 is arranged is marked with a symbol "F". In the present description, a direction perpendicular to the arrangement direction in a plan view may be referred to as an extension direction (the Y-axis direction in Fig. 1). The transistor section 70 and the diode section 80 may each have a longitudinal length in the extension direction. In other words, a length of the transistor section 70 in the Y-axis direction is greater than a width in the X-axis direction. Similarly, a length of the diode section 80 in the Y-axis direction is greater than a width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as a longitudinal direction of each trench section described below.

[0044] The diode section 80 has an N+-type cathode region in a region contacting the lower surface of the semiconductor substrate 10. In this specification, a region where the cathode region is disposed is referred to as the diode section 80. In other words, the diode section 80 is a region overlapping with the cathode region in a plan view. On the lower surface of the semiconductor substrate 10, a P+-type collector region may be disposed in a region other than the cathode region. In this specification, the diode section 80 may also have an extension region 81 in which the diode section 80 extends in the Y-axis direction to a gate rotor described below. The collector region is disposed on a lower surface of the extension region 81.

[0045] The transistor section 70 has the P+-type collector region in a region contacting the lower surface of the semiconductor substrate 10. Furthermore, in the transistor section 70, an N-type emitter region, a P-type base region, and a gate structure including a gate line portion and a gate dielectric film are periodically arranged on the upper surface side of the semiconductor substrate 10.

[0046] The semiconductor device 100 may include one or more arrays above the semiconductor substrate 10. In this example, the semiconductor device 100 includes a gate array 164. The semiconductor device 100 may include an array such as an anode array, a cathode array, and a current sense array. Each array is disposed near an end face 162. The proximity of the end face 162 refers, in plan view, to an area between the end face 162 and the emitter electrode. When the semiconductor device 100 is assembled, each array may be connected to an external circuit via a wiring line such as a wire.

[0047] A gate potential is applied to the gate array 164. The gate array 164 is electrically connected to a conductive portion of a gate trench portion of the active portion 160. The semiconductor device 100 includes a gate runner connecting the gate array 164 and the gate trench portion. Fig. 1 the gate runner is hatched with diagonal lines.

[0048] The gate runner in this example includes outer circumferential gate runners 130 and an active-side gate runner 131. The outer circumferential gate runners 130 are arranged between the active portion 160 and the end faces 162 of the semiconductor substrate 10 in a plan view. The outer circumferential gate runners 130 enclose the active portion 160 in this example in a plan view. A region enclosed by the outer circumferential gate runners 130 in a plan view may be the active portion 160. Furthermore, a drain region is formed below the gate runner. The drain region is a P-type region with a higher concentration than the base region described below and is formed to a position deeper than a position of the base region from the top surface of the semiconductor substrate 10. A region enclosed by the drain region in a plan view may be the active portion 160.

[0049] An outer orbiting gate runner 130 is connected to the gate array 164. The outer orbiting gate runners 130 are arranged above the semiconductor substrate 10. The outer orbiting gate runners 130 may be metal wiring lines containing aluminum or the like.

[0050] The active-side gate runner 131 is arranged in the active section 160. Arranging the active-side gate runner 131 in the active section 160 can reduce a variation in the wiring line length from the gate array 164 for each region of the semiconductor substrate 10.

[0051] The outer circumferential gate runners 130 and the active-side gate runner 131 are connected to the gate trench portion of the active section 160. The outer circumferential gate runners 130 and the active-side gate runner 131 are disposed above the semiconductor substrate 10. The outer circumferential gate runners 130 and the active-side gate runner 131 may be wiring lines formed from a semiconductor such as impurity-doped polysilicon.

[0052] The active-side gate rotor 131 may be connected to the outer orbiting gate rotors 130. In this example, the active-side gate rotor 131 is arranged to extend in the X-axis direction to cross the active section 160 substantially at a center in the Y-axis direction from one of the outer orbiting gate rotors 130 that border the active section 160 to another. When the active section 160 is divided by the active-side gate rotor 131, the transistor sections 70 and the diode sections 80 may be arranged alternately in the X-axis direction in each region obtained by the division.

[0053] The semiconductor device 100 may include a temperature measuring section (not shown) that is a PN junction diode formed of polysilicon or the like, and a current measuring section (not shown) that simulates an operation of a transistor section arranged in the active section 160.

[0054] In this example, the semiconductor device 100 includes an edge termination structure portion 90 between the active portion 160 and the end faces 162 in plan view. The edge termination structure portion 90 is arranged between the outer circumferential gate rotors 130 and the end faces 162 in this example. The edge termination structure portion 90 reduces an electric field strength on the upper surface side of the semiconductor substrate 10. The edge termination structure portion 90 may include at least one of a guard ring, a field plate, or a RESURF, which are arranged in a ring shape and enclose the active portion 160.

[0055] Fig. Figure 2 illustrates an enlarged view of an area D in Fig. 1. Region D is a region including a transistor section 70, a diode section 80, and an active-side gate slider 131. A semiconductor device 100 in this example includes gate trench sections 40, dummy trench sections 30, a well region 11, emitter regions 12, base regions 14, and contact regions 15 disposed internally on an upper surface side of a semiconductor substrate 10. A gate trench section 40 and a dummy trench section 30 are each an example of a trench section. Furthermore, the semiconductor device 100 in this example includes an emitter electrode 52 and the active-side gate slider 131 disposed above an upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate slider 131 are disposed separately from each other.

[0056] A dielectric interlayer film is arranged between the emitter electrode 52 and the active-side gate rotor 131 and the upper surface of the semiconductor substrate 10, but the illustration thereof has been omitted in Fig. 2 is omitted. In this example, contact holes 54 are arranged in the dielectric interlayer film, which penetrate the dielectric interlayer film. Fig. 2, each of the contact holes 54 is hatched with diagonal lines.

[0057] The emitter electrode 52 is arranged over the gate trench portions 40, the dummy trench portions 30, the well region 11, the emitter regions 12, the base regions 14, and the contact regions 15. The emitter electrode 52 is in contact with the emitter regions 12, the contact regions 15, and the base regions 14 on the upper surface of the semiconductor substrate 10 via the contact holes 54. Furthermore, the emitter electrode 52 is connected to dummy wiring portions in the dummy trench portions 30 via the contact holes arranged in the interlayer dielectric film. The emitter electrode 52 may be connected to the dummy wiring portions of the dummy trench portions 30 at edges of the dummy trench portions 30 in the Y-axis direction.The dummy wiring portions of the dummy trench portions 30 may not be connected to the emitter electrode 52 and a gate wiring portion and may be controlled to be at a potential different from a potential of the emitter electrode 52 and a potential of the gate wiring portion.

[0058] The active-side gate runner 131 is connected to the gate trench sections 40 via the contact holes arranged in the interlayer dielectric film. The active-side gate runner 131 may be connected to gate line portions of the gate trench sections 40 at edge portions 41 of the gate trench sections 40 in the Y-axis direction. The active-side gate runner 131 is not connected to the dummy line portions in the dummy trench sections 30.

[0059] The emitter electrode 52 is formed of a material containing a metal. Fig. 2 shows a region in which the emitter electrode 52 is arranged. For example, at least a portion of the emitter electrode 52 is formed from aluminum or an aluminum-silicon alloy, for example, a metal alloy such as AlSi or AlSiCu. The emitter electrode 52 may include a barrier metal formed from titanium, a titanium compound, or the like beneath a region formed from aluminum or the like. Furthermore, a plug formed by embedding tungsten or the like to be in contact with the barrier metal and aluminum or the like may be included in a contact hole.

[0060] The drain region 11 is arranged to overlap the active-side gate slider 131. The drain region 11 is arranged to extend with a predetermined width even in a region that does not overlap the active-side gate slider 131. In this example, the drain region 11 is arranged away from the ends of the contact holes 54 in the Y-axis direction on one side of the active-side gate slider 131. The drain region 11 is a region of a second conductivity type with a higher doping concentration than a base region 14. The base region 14 is P--type in this example, and the drain region 11 is P+-type.

[0061] Both the transistor section 70 and the diode section 80 have a plurality of trench sections arranged in an arrangement direction. In the transistor section 70, in this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are arranged alternately along the arrangement direction. In the diode section 80, in this example, a plurality of dummy trench sections 30 are arranged along the arrangement direction. In the diode section 80, in this example, the gate trench section 40 is not arranged.

[0062] The gate trench section 40 may in this example have two straight sections 39 extending along an extension direction perpendicular to the arrangement direction (sections of a trench that are straight along the extension direction), and an edge section 41 connecting the two straight sections 39. The extension direction in Fig. 2 is the Y-axis direction.

[0063] At least a portion of the edge portion 41 is preferably arranged in a curved line shape in a plan view. Connecting end portions of the two straight portions 39 in the Y-axis direction by the edge portion 41 can reduce electric field strengths at the end portions of the straight portions 39.

[0064] In the transistor section 70, the dummy trench section 30 is arranged between respective straight sections 39 of the gate trench section 40. Between the respective straight sections 39, one dummy trench section 30 may be arranged, or a plurality of dummy trench sections 30 may be arranged. The dummy trench section 30 may have a straight shape extending in the extension direction, or it may have straight sections 29 and an edge section 31 similar to the gate trench section 40. The Fig. The semiconductor device 100 shown in Fig. 2 includes both the dummy trench portions 30 having a straight shape, each of which has no edge portion 31, and the dummy trench portions 30 each of which has the edge portion 31.

[0065] A diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The Y-axis end portions of the gate trench portion 40 and the dummy trench portion 30 are arranged in the well region 11 in plan view. In other words, a lower portion in a depth direction of each of the trench portions is covered with the well region 11 at an end portion in the Y-axis direction of each of the trench portions. With this configuration, an electric field strength at the lower portion of each of the trench portions can be reduced.

[0066] A mesa portion is arranged between respective trench portions in the arrangement direction. The mesa portion refers to a region sandwiched between the trench portions in the semiconductor substrate 10. As an example, an upper end of the mesa portion is the upper surface of the semiconductor substrate 10. A depth position of a lower end of the mesa portion is the same as a depth position of a lower end of the trench portion. The mesa portion, in this example, is arranged to extend in the extension direction (Y-axis direction) along the trench on the upper surface of the semiconductor substrate 10. In this example, mesa portions 60 are arranged in the transistor portion 70, and mesa portions 61 are arranged in the diode portion 80. In a case where simply "mesa portion" is mentioned in the present specification, the portion refers to each of a mesa portion 60 and a mesa portion 61.

[0067] Each of the mesa sections has base regions 14. In the mesa section, a region located closest to the active-side gate slider 131 among the base regions 14 exposed on the upper surface of the semiconductor substrate 10 is defined as a base region 14-e. While Fig. While FIG. 2 shows a base region 14-e disposed at one end portion of each of the mesa portions in the spanwise direction, a base region 14-e is also disposed at another end portion of each of the mesa portions. Each of the mesa portions may include an emitter region 12 of a first conductivity type and / or a contact region 15 of the second conductivity type in a region sandwiched between base regions 14-e in plan view. In this example, the emitter region 12 is N+-type, and the contact region 15 is P+-type. The emitter region 12 and the contact region 15 may be disposed between the base region 14 and the top surface of the semiconductor substrate 10 in the depth direction.

[0068] The mesa portion 60 of the transistor portion 70 includes the emitter regions 12 exposed on the top surface of the semiconductor substrate 10. The emitter regions 12 are arranged in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may include the contact regions 15 exposed on the top surface of the semiconductor substrate 10.

[0069] Each of the contact regions 15 and the emitter regions 12 in the mesa section 60 is arranged from one trench section to another trench section in the X-axis direction. For example, the contact regions 15 and the emitter regions 12 in the mesa section 60 are arranged alternately along the extension direction of the trench section (Y-axis direction).

[0070] In another example, the contact regions 15 and the emitter regions 12 of the mesa section 60 may be arranged in a striped pattern along the extension direction of the trench section (Y-axis direction). For example, the emitter regions 12 are arranged in regions in contact with the trench section, and the contact regions 15 are arranged in regions sandwiched between the emitter regions 12.

[0071] The mesa section 61 of the diode section 80 does not have an emitter region 12. The base regions 14 and the contact regions 15 may be arranged on an upper surface of the mesa section 61. In the region sandwiched between the base regions 14-e on the upper surface of the mesa section 61, the contact region 15 may be arranged in contact with each of the base regions 14-e. The base region 14 may be arranged in a region sandwiched between the contact regions 15 on the upper surface of the mesa section 61. The base region 14 may be arranged in the entire region sandwiched between the contact regions 15.

[0072] A contact hole 54 is arranged above each of the mesa sections. The contact hole 54 is arranged in the region sandwiched between the base regions 14-e. In this example, the contact hole 54 is arranged above each of the contact regions 15, the base region 14, and the emitter regions 12. The contact hole 54 is not arranged in regions corresponding to the base region 14-e and the drain region 11. The contact hole 54 may be arranged at a center of the mesa section 60 in the arrangement direction (X-axis direction).

[0073] In the diode section 80, an N+-type cathode region 82 is disposed in a region that directly contacts the lower surface of the semiconductor substrate 10. A P+-type collector region 22 may be disposed on the lower surface of the semiconductor substrate 10 in a region where the cathode region 82 is not located. The cathode region 82 and the collector region 22 are disposed between a lower surface 23 of the semiconductor substrate 10 and a buffer region 20. Fig. 2, a boundary between the cathode region 82 and the collector region 22 is represented by a dotted line.

[0074] The cathode region 82 is located away from the drain region 11 in the Y-axis direction. With this configuration, a distance is ensured between a P-type region (the drain region 11), which has a relatively high doping concentration and is formed to a deep position, and the cathode region 82, so that a breakdown voltage can be improved. In this example, an end portion in the Y-axis direction of the cathode region 82 is located farther from the drain region 11 than an end portion in the Y-axis direction of the contact hole 54. In another example, the end portion in the Y-axis direction of the cathode region 82 may be located between the drain region 11 and the contact hole 54.

[0075] Fig. 3 illustrates an example of a cross section ee in Fig. 2. Cross section ee is an XZ plane passing through emitter regions 12 and a cathode region 82. A semiconductor device 100 in this example includes a semiconductor substrate 10, an interlayer dielectric film 38, an emitter electrode 52, and a collector electrode 24 in cross section.

[0076] The interlayer dielectric film 38 is disposed on an upper surface of the semiconductor substrate 10. The interlayer dielectric film 38 is a film comprising at least one of a dielectric film, such as silicate glass, to which an impurity, such as boron or phosphorus, is added, a thermal oxide film, or another dielectric film. The interlayer dielectric film 38 has the Fig. 2 described contact holes 54.

[0077] The emitter electrode 52 is disposed above the interlayer dielectric film 38. The emitter electrode 52 is in contact with an upper surface 21 of the semiconductor substrate 10 via the contact holes 54 of the interlayer dielectric film 38. The collector electrode 24 is disposed on a lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum. In the present description, a direction in which the emitter electrode 52 is connected to the collector electrode 24 (Z-axis direction) is referred to as a depth direction.

[0078] The semiconductor substrate 10 has an N-type or N-type drift region 18. The drift region 18 is arranged in a transistor section 70 and a diode section 80, respectively.

[0079] In a mesa section 60 of the transistor section 70, an N+-type emitter region 12 and a P-type base region 14 are arranged in sequence from a top surface side 21 of the semiconductor substrate 10. The drift region 18 is arranged below the base region 14. The mesa section 60 may include an N+-type collection region. The collection region is arranged between the base region 14 and the drift region 18. The collection region is an N+-type region with a higher doping concentration than the drift region 18. Disposing the high-concentration collection region between the drift region 18 and the base region 14 can enhance a carrier injection enhancement (IE) effect and reduce an ON voltage. The collection region may be arranged to cover the entire bottom surface of the base region 14 in each mesa section 60. The collection region may also be arranged in each mesa section 61 of the diode section 80.

[0080] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is arranged in contact with a gate trench section 40. The emitter region 12 may be in contact with trench sections on both sides of the mesa section 60. The emitter region 12 has a higher doping concentration than the drift region 18.

[0081] The base region 14 is disposed below the emitter region 12. In this example, the base region 14 is disposed in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on either side of the mesa portion 60.

[0082] The mesa portion 61 of the diode portion 80 has a P-type base region 14 that contacts the top surface 21 of the semiconductor substrate 10. The drift region 18 is located below the base region 14. The base region 14 of the diode portion 80 may be referred to as an anode region 14.

[0083] In the transistor section 70 and the diode section 80, an N+-type buffer region 20 may be disposed below the drift region 18, respectively. A doping concentration in the buffer region 20 is higher than a doping concentration in the drift region 18. The buffer region 20 may have a concentration peak with a higher doping concentration than that in the drift region 18. A doping concentration at the concentration peak refers to a doping concentration at a local maximum of the concentration peak. Furthermore, an average doping concentration value in a region where a doping concentration distribution is substantially flat may be used as the doping concentration in the drift region 18.

[0084] The buffer region 20 may have two or more concentration peaks in the depth direction of the semiconductor substrate 10 (Z-axis direction). The concentration peaks of the buffer region 20 may be located at the same depth position as, for example, a chemical concentration peak of hydrogen (a proton) or phosphorus. The buffer region 20 may serve as a field stop layer that prevents a depletion layer extending from the lower ends of the base regions 14 from reaching a P+-type collector region 22 and the N+-type cathode region 82.

[0085] In transistor section 70, the P+-type collector region 22 is arranged below the buffer region 20. An acceptor concentration in the collector region 22 is higher than an acceptor concentration in the base region 14. The collector region 22 may include an acceptor that is the same as or different from that of the base region 14. The acceptor of the collector region 22 is, for example, boron.

[0086] In the diode section 80, the N+-type cathode region 82 is arranged below the buffer region 20. A donor concentration in the cathode region 82 is higher than a donor concentration in the drift region 18. A donor of the cathode region 82 is, for example, hydrogen or phosphorus. Note that an element serving as a donor and an acceptor in each region is not limited to the example described above. The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may contact the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0087] One or more gate trench sections 40 and one or more dummy trench sections 30 are arranged on the upper surface 21 side of the semiconductor substrate 10. Each of the trench sections is arranged from the upper surface 21 of the semiconductor substrate 10 through the base region 14 to below the base region 14. In a region where the emitter region 12 and / or the contact region 15 and / or the collection region are arranged, each of the trench sections also penetrates an impurity region described above. The configuration of the trench sections penetrating the impurity region is not limited to that produced in the order of forming the impurity region and then forming the trench sections. The configuration of the trench sections penetrating the impurity region also includes a configuration of forming the trench sections and then forming the impurity region between the trench sections.

[0088] As described above, the transistor section 70 includes gate trench sections 40 and dummy trench sections 30. The diode section 80 includes dummy trench sections 30 and does not include a gate trench section 40. A boundary in the X-axis direction between the diode section 80 and the transistor section 70 is, in this example, a boundary between the cathode region 82 and the collector region 22.

[0089] The gate trench portion 40 includes a gate trench disposed on the upper surface 21 of the semiconductor substrate 10, a gate dielectric film 42, and a gate line portion 44. The gate dielectric film 42 covers an inner wall of the gate trench. The gate dielectric film 42 can be formed by oxidizing or nitriding a semiconductor on the inner wall of the gate trench. The gate line portion 44 is disposed further inside the gate trench than the gate dielectric film 42. In other words, the gate dielectric film 42 insulates the gate line portion 44 from the semiconductor substrate 10. The gate line portion 44 is formed of a conductive material such as polysilicon.

[0090] The gate line section 44 may be arranged so that it is longer in the depth direction than the base region 14. The gate trench sections 40 in cross section are covered with the interlayer dielectric film 38 on the upper surface 21 of the semiconductor substrate 10. The gate line section 44 is electrically connected to a gate rotor. When a predetermined gate voltage is applied to the gate line section 44, a channel is formed by an electron inversion layer in a surface layer of the base region 14 at a boundary in contact with the gate trench section 40.

[0091] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in cross section. The dummy trench portion 30 includes a dummy trench disposed on the upper surface 21 of the semiconductor substrate 10, a dummy dielectric film 32, and a gate wiring portion 34. The gate wiring portion 34 is electrically connected to the emitter electrode 52. The dummy dielectric film 32 covers an inner wall of the dummy trench. The gate wiring portion 34 is disposed in the dummy trench and is located further inside than the dummy dielectric film 32. The dummy dielectric film 32 insulates the gate wiring portion 34 from the semiconductor substrate 10. The gate wiring portion 34 may be formed of the same material as the gate wiring portion 44. For example, the gate line section 34 is formed of a conductive material such as polysilicon.The gate line section 34 may have the same length as the gate line section 44 in the depth direction.

[0092] In this example, the gate trench portions 40 and the dummy trench portions 30 are covered with the interlayer dielectric film 38 on the upper surface 21 of the semiconductor substrate 10. Note that lower portions of the dummy trench portion 30 and the gate trench portion 40 may be formed convexly downward in a curved surface shape (a curved line shape in cross section). In the present specification, a depth position of a lower end of the gate trench portion 40 is defined as Zt.

[0093] In this example, the semiconductor device 100 includes a first lifetime range 204 that sets a charge carrier lifetime. In this example, the first lifetime range 204 is a range in which the lifetime of charge carriers is locally short. The charge carriers are electrons or holes. The charge carriers may simply be referred to as carriers. The first lifetime range 204 may be a range in which the charge carrier lifetime has a local minimum value in the depth direction of the semiconductor substrate 10.

[0094] The first lifetime region 204 is arranged on the side of the upper surface 21 of the semiconductor substrate 10. The first lifetime region 204 is arranged in the diode section 80. The first lifetime region 204 can also be arranged in a part of the transistor section 70. In the Fig. 3, the first lifetime region 204 is arranged in a region that is located in the transistor section 70 and that touches the diode section 80.

[0095] The implantation of charged particles such as helium into the semiconductor substrate 10 forms lattice defects 202 near an implantation position. Fig. 3, the lattice defects 202 at the implantation position of the charged particles are schematically indicated by X marks. In an area where many lattice defects 202 remain, the charge carriers are trapped by the lattice defects 202, and thus the lifetime of the charge carriers is shortened. Adjusting the lifetime of the charge carriers can adjust properties such as a turn-off time and a reverse recovery loss in the diode section 80. Implanting charged particles such as helium into the semiconductor substrate 10 forms lattice defects 210 such as vacancies near an implantation position. The lattice defects 202 create recombination centers. The lattice defects 202 may consist mainly of vacancies such as monoatomic vacancies (V) or diatomic vacancies (W), may be dislocations, may be interstitial atoms, or may be transition metals, or the like.For example, atoms adjacent to the vacancies have dangling bonds. In a broad sense, the lattice defects 202 can also include donors and acceptors, but in the present description, the lattice defects 202 that consist primarily of vacancies can be referred to as vacancy-type lattice defects, vacancy-type defects, or simply lattice defects. In the present description, the lattice defects 202 can simply be referred to as recombination centers or lifetime killers as recombination centers that contribute to the recombination of charge carriers. The lifetime killers can be formed by implanting helium ions into the semiconductor substrate 10. In this case, a chemical helium concentration can be used as a density of the lattice defects 202. In this example, a chemical helium concentration can be used as a density of the lattice defects 202.

[0096] On the other hand, disposing the first lifetime region 204 in the diode section 80 in the first lifetime region 204 reduces holes implanted from the anode region 14 and electrons implanted from the cathode region 82 during forward conduction of the diode section 80. This makes it difficult for a potential difference at a PN junction between the anode region 14 and the drift region 18 to become smaller than a built-in potential, and snapback of a forward voltage may occur in a low-current operation region. In particular, disposing the first lifetime region 204 throughout the diode section 80 in the X-axis direction makes it difficult for a hole density and an electron density to increase in a region of the diode section 80 on the upper surface 21 side, and snapback is easy to occur.

[0097] Fig. 4 illustrates examples of VI characteristics during forward conduction of a diode section 80 according to a comparative example. In the diode section 80, a first lifetime region 204 is arranged throughout the X-axis direction in this example. Fig. Figure 4 shows a relationship between a forward current If of the diode section 80 and an anode-cathode voltage Vak. In addition, Fig. 4 VI characteristics in a variety of examples in which carrier lifetimes in the first lifetime range 204 are different. A carrier lifetime in the first lifetime range 204 can be adjusted by adjusting a dose amount of charged particles such as helium to be implanted into a semiconductor substrate 10. A larger dose amount of charged particles such as helium increases a density of lattice defects formed in the semiconductor substrate 10 and reduces the carrier lifetime.

[0098] When the first lifetime region 204 is arranged throughout the diode section 80, reducing the charge carrier lifetime in the first lifetime region 204 may cause a bounce back in a VI characteristic, as shown in Fig. 4. As shown in Fig. As shown in Figure 4, springback is a phenomenon in which an increase in current is suppressed until the voltage Vak reaches a predetermined value in a low-current operating region during forward conduction, and in which the current increases rapidly once the voltage Vak exceeds the predetermined value. In the low-current operating region, it is necessary to increase a majority carrier density (an electron density in this example) so that a potential difference at a PN junction exceeds a built-in potential. To supply the electron density required to exceed the built-in potential, a shorter carrier lifetime requires a higher anode-cathode voltage Vak. When the potential difference at the PN junction exceeds the built-in potential, implantation of minority carriers begins, and a resistance of the diode section 80 decreases as the forward current increases.As a result, the anode-cathode voltage Vak decreases to cause conductivity modulation and snapback occurs in the VI characteristics.

[0099] A VI waveform in a large-current operating region is approximated by a straight line 85. In the present specification, a difference between a voltage V1 at which the current If = 0 is established on the straight line 85 and a peak voltage V2 at snapback (V2 - V1) may be referred to as a snapback amount (an SB amount). In a semiconductor device 100, snapback is suppressed by adjusting a configuration of the first lifetime region 204 in the diode section 80.

[0100] Fig. 5 illustrates an arrangement example of a first lifetime region 204 and a second lifetime region 200 in a diode section 80. Fig. Figure 5 shows an XZ cross-section passing through a portion of the diode section 80 and a portion of a transistor section 70. In Fig. 5, an illustration of an interlayer dielectric film 38, an emitter electrode 52, a collector electrode 24, and the like arranged above and below a semiconductor substrate 10 is omitted. In Fig. 5, a representation of lattice defects 202 is omitted, and hatching for dummy line sections 34 and gate line sections 44 is omitted.

[0101] In this example, the diode section 80 includes first lifetime regions 204 and a second lifetime region 200 in a region on one side of the upper surface 21 of the semiconductor substrate 10. The first lifetime regions 204 are arranged in a drift region 18 on one side of the lower surface 23 of the semiconductor substrate 10 relative to a base region 14. The first lifetime regions 204 may be arranged below lower ends of dummy trench sections 30. The diode section 80 may include a plurality of first lifetime regions 204 arranged apart from each other in the X-axis direction. A width of a first lifetime region 204 in the X-axis direction may be greater than a width of a mesa section sandwiched between two trench sections.

[0102] The second lifetime region 200 is arranged so that it is sandwiched between the first lifetime regions 204 in a first direction (X-axis direction in this example) parallel to a top surface 21 of the semiconductor substrate 10. The first lifetime regions 204 and the second lifetime region 200 are arranged at the same position in a depth direction of the semiconductor substrate 10 (Z-axis direction).

[0103] The second lifetime region 200 is a region with a longer carrier lifetime than a first lifetime region 204. A carrier lifetime in the second lifetime region 200 may, in this example, be the same as a carrier lifetime in the drift region 18. In other words, the second lifetime region 200 may be the drift region 18 that remained without the first lifetime regions 204 being formed. In another example, the carrier lifetime in the second lifetime region 200 may be shorter than the carrier lifetime in the drift region 18.

[0104] A lattice defect density in the second lifetime region 200 is lower than a lattice defect density in the first lifetime region 204. The lattice defect density in the second lifetime region 200 may be the same as a lattice defect density in the drift region 18 or may be higher than a lattice defect density in the drift region 18. A concentration of impurities such as helium in the second lifetime region 200 may be lower than a concentration of impurities such as helium in the first lifetime region 204. The concentration of impurities such as helium in the second lifetime region 200 may be the same as a concentration of impurities in the drift region 18 or may be higher than a concentration of impurities in the drift region 18. The impurities in the concentration of impurities in this example may be impurities that serve as lattice defects that reduce a charge carrier lifetime.For example, the impurities may be atoms other than atoms of the semiconductor substrate 10 or may be interstitial atoms of atoms of the semiconductor substrate 10. Furthermore, the impurities may be n-type or p-type dopants, may be impurities that do not contribute to a conductivity type (e.g., helium, argon), or may be metal atoms (platinum, gold, and the like). Alternatively, the lattice defects that reduce the charge carrier lifetime may be vacancies or interstitial atoms that do not contain impurities.

[0105] The charge carrier lifetime in the second lifetime region 200 is longer than a charge carrier lifetime in the first lifetime region 204, and thus electrons or holes can easily pass through it. As in this example, disposing the second lifetime region 200 in the diode section 80 allows electrons implanted from a cathode region 82 and holes implanted from the anode region 14 to pass through the second lifetime region 200 during forward conduction of the diode section 80. The electrons that have passed through the second lifetime region 200 diffuse in an XY plane and expand above the first lifetime regions 204. The holes that have passed through the second lifetime region 200 diffuse in the XY plane and expand below the first lifetime regions 204.This can improve the electron density and hole density in regions on the upper surface 21 side and the lower surface 23 side relative to the first lifetime region 204, particularly during low-current operation during forward conduction of the diode section 80. As a result, it is possible to cause conductivity modulation without increasing the anode-cathode voltage Vak and suppress snapback. In this example, a second lifetime region 200 is arranged in a diode section 80. The second lifetime region 200 can be arranged at a center of the diode section 80 in the X-axis direction.

[0106] Fig. 6 illustrates an enlarged cross-sectional view near a second lifetime region 200. A width of the second lifetime region 200 in a first direction (in this example, the X-axis direction) is defined as W1. A thickness of a first lifetime region 204 in a second direction (in this example, the Z-axis direction) perpendicular to a top surface 21 of a semiconductor substrate 10 is defined as T1. The width W1 of the second lifetime region 200 is 0.2 times or more the thickness of the first lifetime region 204. If the width W1 of the second lifetime region 200 is too small, electrons or holes are easily trapped by lattice defects 202 in first lifetime regions 204 on both sides of the second lifetime region 200 when the electrons or holes pass through the second lifetime region 200. The lattice defects 202 that trap the electrons or holes may have trap planes.Furthermore, as the thickness T1 of the first lifetime region 204 increases, the electrons or holes passing through the second lifetime region 200 are easily trapped by the lattice defects 202 in the first lifetime regions 204. In contrast, setting the width W1 of a second lifetime region 200 to 0.2 times or more the thickness of the first lifetime region 204 can ensure the amounts of electrons and holes passing through the second lifetime region 200. The width W1 can be 0.25 times or more, 0.3 times or more, 0.4 times or more, 0.5 times or more, one time or more, or twice or more the thickness T1.

[0107] Note, however, that if the second lifetime range 200 is too large, a reverse recovery time of a diode section 80 is longer, and a reverse recovery charge and a reverse recovery loss also increase. In the diode section 80, a total width of the second lifetime range 200 in the X-axis direction is preferably smaller than a total width of the first lifetime range 204. The total width of the second lifetime range 200 in the X-axis direction in the diode section 80 may be less than or equal to 10% or less than or equal to 5% of a width of the diode section 80 in the X-axis direction.

[0108] A diode section 80 may have a second lifetime region 200 or may have a plurality of second lifetime regions 200 arranged apart from each other in the X-axis direction. The width W1 of each of the second lifetime regions 200 may be 7 μm or larger. Increasing the width W1 of the second lifetime region 200 can suppress the electrons or holes from being trapped by the lattice defects 202 in the first lifetime regions 204 on both sides of the second lifetime region 200 when the electrons or holes pass through the second lifetime region 200. The width W1 may be 8 μm or larger, or 9 μm or larger. The width W1 may be 12 μm or smaller. If the width W1 is too large, a turn-off time of the diode section 80 increases, and the reverse recovery loss also increases. The width W1 can be 11 µm or smaller or 10 µm or smaller.

[0109] An interval between trench portions (dummy trench portions 30 in this example) in the X-axis direction is defined as W2. The interval between the trench portions may be an interval between central positions of the trench portions in the X-axis direction. The width W1 of the second lifetime region 200 may be larger than the interval W2 between the trench portions. In other words, the width W1 of the second lifetime region 200 may be larger than a mesa width of a mesa portion sandwiched between two adjacent trench portions in the X-axis direction. The width W1 may be 1.2 times or more, 1.5 times or more, or twice or more the interval W2. The width W1 may be 10 times or less, 5 times or less, or 3 times or less the interval W2.

[0110] Fig. Figure 7 illustrates distribution examples of charge carrier lifetimes, vacancy densities and chemical helium concentrations on a line ff in Fig. 6. Line ff is a straight line parallel to the X-axis direction and passes through two first lifetime regions 204 and a second lifetime region 200. A carrier lifetime in a first lifetime region 204 is defined as τ1, and a carrier lifetime in the second lifetime region 200 is defined as τ2. A minimum carrier lifetime value in the first lifetime region 204 can be used as the carrier lifetime τ1. A maximum carrier lifetime value in the second lifetime region 200 can be used as the carrier lifetime τ2. The carrier lifetime τ2 can be equal to or shorter than a carrier lifetime in a drift region 18. A value at a center of the drift region 18 in the depth direction can be used as the carrier lifetime in the drift region 18, or an average value can be used.

[0111] Positions where the charge carrier lifetime is τa are defined as boundary positions between the first lifetime ranges 204 and the second lifetime range 200. τa is a value greater than or equal to τ1 and less than or equal to τ2. τa can be either equal to τ1 or τ2, or can be a value obtained by multiplying either τ1 or τ2 by a predetermined coefficient. τa can be a value slightly greater than τ1, can be an average value of τ1 and τ2, or can be another value. Positions where the charge carrier lifetime is greater than τ1 can be defined as the boundary positions between the first lifetime ranges 204 and the second lifetime range 200. The charge carrier lifetime τ2 in the second lifetime range 200 may be ten times or more, one hundred times or more, or one thousand times or more the charge carrier lifetime τ1 in the first lifetime range 204.For example, the carrier lifetime τ1 is 100 ns or less, and the carrier lifetime τ2 is 1 µs or greater. τ1 can be 10 ns or less, and τ2 can be 10 µs or greater.

[0112] A vacancy density in the first lifetime region 204 is defined as V1, and a vacancy density in the second lifetime region 200 is defined as V2. A maximum vacancy density value in the first lifetime region 204 can be used as the vacancy density V1. A minimum vacancy density value in the second lifetime region 200 can be used as the vacancy density V2. The vacancy density V2 can be equal to or greater than a vacancy density in the drift region 18. A value at the center of the drift region 18 in the depth direction can be used as the vacancy density in the drift region 18, or an average value can be used.

[0113] Positions where the vacancy density is Va can be defined as the boundary positions between the first lifetime regions 204 and the second lifetime region 200. Va is a value greater than or equal to V2 and less than or equal to V1. Va can be either equal to V1 or V2, or can be a value obtained by multiplying either V1 or V2 by a predetermined coefficient. Va can be a value slightly less than V1, can be an average value of V1 and V2, or can be another value. Positions where the vacancy density is less than V1 can be defined as the boundary positions between the first lifetime regions 204 and the second lifetime region 200.

[0114] A chemical helium concentration in the first lifetime region 204 is defined as H1, and a chemical helium concentration in the second lifetime region 200 is defined as H2. A maximum chemical helium concentration value in the first lifetime region 204 can be used as the chemical helium concentration H1. A minimum chemical helium concentration value in the second lifetime region 200 can be used as the chemical helium concentration H2. The chemical helium concentration H2 can be equal to or greater than a chemical helium concentration in the drift region 18. A value in the center of the drift region 18 in the depth direction can be used as the chemical helium concentration in the drift region 18, or an average value can be used.

[0115] Positions where the chemical helium concentration is Ha can be defined as the boundary positions between the first lifetime ranges 204 and the second lifetime range 200. Ha is a value greater than or equal to H2 and less than or equal to H1. Ha can be either equal to H1 or H2, or can be a value obtained by multiplying either H1 or H2 by a predetermined coefficient. Ha can be a value slightly less than H1, can be an average value of H1 and H2, or can be another value. Positions where the chemical helium concentration is less than H1 can be defined as the boundary positions between the first lifetime ranges 204 and the second lifetime range 200.When lattice defects are formed by implanting charged particles other than helium, the boundary positions between the first lifetime regions 204 and the second lifetime region 200 can be determined based on a chemical concentration of the charged particles.

[0116] Fig. Figure 8 illustrates distribution examples of charge carrier lifetimes, vacancy densities and chemical helium concentrations on a line gg in Fig. 6. Line gg is a straight line that crosses a first lifetime region 204 in the Z-axis direction. In this example, the first lifetime region 204 is enclosed between drift regions 18 in the Z-axis direction. In this example, a charge carrier lifetime, a vacancy density, and a chemical helium concentration in a drift region 18 are τ2, V2, and H2, respectively.

[0117] Positions where the charge carrier lifetime τa can be defined as boundary positions between the first lifetime region 204 and the drift regions 18. The charge carrier lifetime τa is similar to that in the Fig. 7. Positions where the charge carrier lifetime is greater than τ1 can be defined as the boundary positions between the first lifetime region 204 and the drift regions 18. Positions where the vacancy density is Va can be defined as the boundary positions between the first lifetime region 204 and the drift regions 18. The vacancy density Va is similar to that in the Fig. 7. Positions where the vacancy density is less than V1 can be defined as the boundary positions between the first lifetime region 204 and the drift regions 18. Positions where the chemical helium concentration is Ha can be defined as the boundary positions between the first lifetime region 204 and the drift regions 18. The chemical helium concentration Ha is similar to that in the Fig. 7. Positions where the chemical helium concentration is less than H1 can be defined as boundary positions between the first lifetime ranges 204 and the second lifetime range 200. A charge carrier lifetime distribution in the first lifetime range 204 can be a distribution in which the charge carrier lifetime of τ2 decreases in a Gaussian function. A vacancy density distribution in the first lifetime range 204 can be a distribution in which the vacancy density of V2 increases in the Gaussian function. A chemical helium concentration distribution in the first lifetime range 204 can be a distribution in which the chemical helium concentration of H2 increases in the Gaussian function.

[0118] Fig. Figure 9 illustrates distribution examples of charge carrier lifetimes, vacancy densities and chemical helium concentrations on a line hh in Fig. 6. Line hh is a straight line that crosses a first lifetime range 204 in the Z-axis direction. In this example, a second lifetime range 200 is enclosed between drift ranges 18 in the Z-axis direction.

[0119] In this example, a carrier lifetime, a vacancy density, and a chemical helium concentration in each of the first lifetime region 204 and a drift region 18 are τ2, V2, and H2, respectively. In another example, the carrier lifetime in the first lifetime region 204 may be shorter than the carrier lifetime in the drift region 18, as indicated by a dashed line in Fig. 9. The vacancy density in the first lifetime region 204 may be higher than the vacancy density in the drift region 18, as indicated by a dashed line in Fig. 9. The chemical helium concentration in the first lifetime region 204 may be higher than the chemical helium concentration in the drift region 18, as indicated by a dashed line in Fig. 9. A charge carrier lifetime distribution in the second lifetime range 200 may be a distribution in which the charge carrier lifetime of τ2 decreases in a Gaussian function. A vacancy density distribution in the second lifetime range 200 may be a distribution in which the vacancy density of V2 increases in the Gaussian function. A chemical helium concentration distribution in the second lifetime range 200 may be a distribution in which the chemical helium concentration of H2 increases in the Gaussian function.

[0120] Fig. 10 illustrates another example of an enlarged cross-sectional view near a second lifetime region 200. In this example, first lifetime regions 204 are formed by implanting hydrogen ions into a semiconductor substrate 10. The implantation of the hydrogen ions forms lattice defects 202 in a passage region through which the hydrogen ions have passed. The hydrogen ions may be implanted from a top surface 21 of the semiconductor substrate 10. The first lifetime regions 204 may be formed up to the top surface 21 of the semiconductor substrate 10. Except for the first lifetime regions 204, this example has a structure similar in any aspect to that described in the present specification.

[0121] When the first lifetime regions 204 are formed up to the upper surface 21 of the semiconductor substrate 10, a thickness T1 is a distance from a lower end of a first lifetime region 204 to the upper surface 21. As described in the present specification, a width W1 of the second lifetime region 200 can be determined according to the thickness T1. A distance in a depth direction from a depth position of a density peak of the lattice defects 202 to the lower end of the first lifetime region 204 is defined as T1'. 2 × T1' can be used as the thickness T1 of the first lifetime region 204.

[0122] Fig. 11A shows a distribution diagram of a net doping concentration (A), a distribution diagram of a chemical hydrogen concentration (B), a distribution diagram of a lattice defect density (C), a distribution diagram of a carrier lifetime (D), a distribution diagram of a carrier mobility (E), and a distribution diagram of a carrier concentration (F) along a line hh in a semiconductor device 100 according to the method shown in Fig. 10. The horizontal axis in each of the distribution diagrams indicates a position in the depth direction. In this example, hydrogen ions are implanted at a depth position Ps from a top surface 21 to form a first lifetime region 204. In addition, a buffer region 20 has a plurality of doping concentration peaks. Fig. 11A, there is a doping concentration peak at each of the depth positions Pb1 to Pb4 in order from a depth position closer to a bottom surface 23. In addition, a depth position Kb has a bottom surface side lifetime region 19 formed by irradiating charged particles such as helium.

[0123] The distribution diagram (A) shows a distribution of the net doping concentration of electrically activated donors and acceptors. In this example, a peak of a concentration N p due to hydrogen donors at the Ps position. In Fig. 11A, a region having the peak is defined as a high-concentration region 26. The doping concentration in a part of a region on one side of the lower surface 23 relative to the position Ps is a doping concentration N O . The doping concentration N Ocan be a volume donor concentration. Volume donors of a semiconductor substrate 10 can be phosphorus, antimony, or arsenic, and further, volume acceptors (boron, aluminum, indium, or the like) can be present to the extent that the volume donor concentration is not exceeded.

[0124] In the distribution diagram (A), an N-type region having a higher doping concentration than the doping concentration in drift regions 18 is defined as N+type. The doping concentration in at least a part of a drift region 18 between the position Ps and the position Pb4 may be lower than the doping concentration in a drift region 18 on a side of the upper surface 21 relative to the position Ps. The hydrogen ions implanted from the upper surface 21 of the semiconductor substrate 10 pass through the drift region 18 on the side of the upper surface 21. Therefore, the doping concentration in the drift region 18 may be higher than the doping concentration N due to remaining hydrogen donors. O of the semiconductor substrate 10. An average doping concentration value in the drift region 18 on the side of the upper surface 21 may be three times or less of the doping concentration N Oof the semiconductor substrate 10.

[0125] The hydrogen ions are implanted at the positions Pb4, Pb3, Pb2 and Pb1 from the lower surface 23 of the semiconductor substrate 10. Therefore, the doping concentration in a region on the side of the lower surface 23 relative to the position Pb4 can be higher than the doping concentration N O of the semiconductor substrate 10 as a whole. That is, the doping concentration (a donor concentration in this example) in the drift region 18 in a region sandwiched in the depth direction between two hydrogen donor peaks (respective hydrogen donor peaks at position Ps and position Pb4 in this example) is the lowest. The doping concentration (the donor concentration in this example) in the region sandwiched between these two hydrogen donor peaks is the doping concentration N Oof the semiconductor substrate 10, and the doping concentration distribution may be substantially flat. The fact that the doping concentration distribution is substantially flat may be for a case where, in a region with a predetermined percentage with respect to a distance between the Ps position and the Pb4 position, a concentration difference between maximum and minimum doping concentration values ​​is less than or equal to 50% of an average doping concentration value in the region. The predetermined percentage may be any value within a range greater than or equal to 50% and less than or equal to 80% with respect to the distance between the Ps position and the Pb4 position.Due to the hydrogen donors, the doping concentration in regions on the side of the upper surface 21 relative to the position Ps and on the side of the lower surface 23 relative to the position Pb4 can be higher than the doping concentration N. O of the semiconductor substrate 10. It should be noted that a cathode region 82 in this example is formed by implanting and diffusing or electrically activating phosphorus.

[0126] As indicated by a dashed line in Fig. As shown in Figure 11A, an N+-type collection region 16 may be disposed between an anode region 14 and the drift region 18. The collection region 16 may be arranged continuously from one to another of two trench sections adjacent to each other in the X-axis direction in each mesa section.

[0127] The distribution diagram (B) shows a chemical concentration of implanted hydrogen (a chemical hydrogen concentration). Each peak of the chemical hydrogen concentration has a tail on a main surface side from which the hydrogen ions were implanted. In this example, a peak of the chemical hydrogen concentration at the position Ps has a tail S on the upper surface 21 side. That is, in a distribution of the chemical hydrogen concentration in this example, the chemical hydrogen concentration monotonically gradually decreases from the first position Ps to the upper surface 21 on the upper surface 21 side. The tail S may be located above the drift region 18 and the anode region 14.

[0128] The distribution of the chemical hydrogen concentration in this example has tails where the concentration distribution changes more steeply than at the tail S, on the side of the lower surface 23 relative to the position Ps. That is, the distribution of the chemical hydrogen concentration has an asymmetric distribution on the side of the upper surface 21 and the side of the lower surface 23 relative to the position Ps.

[0129] In addition, a peak of the chemical hydrogen concentration at each of the positions Pb4, Pb3, Pb2, and Pb1 has a tail S' on the lower surface 23 side. The peak of the chemical hydrogen concentration at each of the positions Pb4, Pb3, Pb2, and Pb1 has a tail where the concentration distribution changes more steeply than at the tail S' on the upper surface 21 side. That is, the peak of the chemical hydrogen concentration at each of the positions Pb4, Pb3, Pb2, and Pb1 shows an asymmetric distribution on the upper surface 21 side and the lower surface 23 side relative to the position Pb1.

[0130] It should be noted that the chemical hydrogen concentration may have a minimum value between a position closest to the lower surface 23 among positions where hydrogen ions were implanted from the upper surface 21 side (the Ps position in this example) and a position closest to the upper surface 21 among positions where hydrogen ions were implanted from the lower surface 23 side (the Pb4 position in this example). A position where a sum of a diffusion distribution of hydrogen implanted at the Ps position and a diffusion distribution of hydrogen implanted at the Pb4 position is minimum is a position where the chemical hydrogen concentration has the minimum value.Alternatively, the position at which the chemical hydrogen concentration has the minimum value may be in a region sandwiched between two hydrogen donor peaks (the Ps position and the Pb4 position in this example) and having a substantially flat doping concentration distribution in which the doping concentration exceeds the doping concentration N. O of the semiconductor substrate 10. Alternatively, the position at which the chemical hydrogen concentration has the minimum value may be the upper surface 21.

[0131] The distribution diagram (C) shows a lattice defect density after the hydrogen ions have been implanted into the semiconductor substrate 10 and then annealed under a predetermined condition. A position at which the net doping concentration in the high-concentration region 26 is substantially identical to the doping concentration N Oof the semiconductor substrate 10 on the side of the lower surface 23 relative to the position Ps is defined as a position Z0. On the side of the lower surface 23 relative to the position Z0, the lattice defect density can have a sufficiently small value Nr0. The fact that the lattice defect density has the sufficiently small value Nr O is that the lattice defect density has a low value to the extent that a lifetime of charge carriers is not less than τ O which is mentioned below. As an example, assuming that a concentration of vacancies or double vacancies No. O is, at a temperature of 300 K No O 1 × 10 12 atoms / cm 3 or smaller, can be 1 × 10 11 atoms / cm 3 or smaller or can be 1 × 10 10 atoms / cm 3 or smaller. The lattice defect density can be higher than No. O at a position JO a PN junction between the anode region 14 and the drift region 18 or the collection region 16.

[0132] Near the position Ps and in a passage region from the upper surface 21 to the position Ps, lattice defects are formed due to the passage of hydrogen ions. This allows the first lifetime region 204 to be formed. Note, however, that near the position Ps, the lattice defects are terminated by hydrogen, and thus a distribution of the lattice defect density and a distribution of the chemical hydrogen concentration have different shapes. For example, the peak position Ps of the chemical hydrogen concentration does not coincide with a peak position Ks of the lattice defect density. The peak position Ks of the lattice defect density in this example is located on the upper surface 21 side of the semiconductor substrate 10 relative to the peak position Ps of the chemical hydrogen concentration. The lattice defect density may monotonically decrease on the upper surface 21 side relative to the position Ks.The lattice defect density may decrease monotonically more steeply on the side of the lower surface 23 relative to the position Ks than on the side of the upper surface 21.

[0133] Near the peak position Ps of the chemical hydrogen concentration, a large amount of hydrogen terminates dangling bonds such as vacancies and double vacancies. Therefore, the lattice defect density near the peak position Ps of the chemical hydrogen concentration is much smaller than the lattice defect density at the peak position Ks of the lattice defect density. In the present specification, a width of a distribution showing a concentration greater than 1% of a peak concentration is referred to as a full width of 1% or FW1%M. The proximity of the peak position Ps may refer to a region within a full width of 1% region centered on the peak position Ps. The peak position Ks of the lattice defect density may be located at a position shallower than that of the full width of 1% region centered on the peak position Ps.

[0134] Note, however, that a distance D between the peak position Ks of the lattice defect density and the peak position Ps of the chemical hydrogen concentration is determined according to a distance over which hydrogen diffuses in the semiconductor substrate 10 by annealing. The distance D may be 40 μm or smaller, 20 μm or smaller, or 10 μm or smaller. The distance D may be 1 μm or larger, 3 μm or larger, or 5 μm or larger. The distance D may be greater than, equal to, or larger than the full width of 1% of the chemical hydrogen concentration. The distance D may be greater than, equal to, or larger than the full width of 1% of the net doping concentration at the position Ps. In this case, the full width of 1% of the net doping concentration is a width of a peak at 0.01 Np. A range of a value of the distance D may be a combination of any lower limit and any upper limit described above.A lattice defect density distribution can be observed by measuring a density distribution of vacancies and divacancies by a positron annihilation method as an example.

[0135] A depth position at which the lattice defect density from the upper surface 21 to the lower surface 23 is first identical to No. O is defined as Z1. The first lifetime region 204 can be arranged from the upper surface 21 to the position Z1. As shown in Fig. As described in Figure 10, a distance from the top surface 21 to position Z1 may be defined as a thickness T1. In another example, a distance equal to twice a distance T' from position Ks to position Z1 may be used as the thickness T1. The first lifetime region 204 contains hydrogen donors in this example.

[0136] A peak of the lattice defect density (the lifetime region 19 of the lower surface side) may be located between the lower surface 23 and the Pb4 position. In this example, the peak of the lattice defect density (the lifetime region 19 of the lower surface side) is located at the Kb position between the Pb2 position and the Pb1 position. The peak of the lattice defect density at the Kb position mainly includes lattice defects formed when helium ions were implanted between the Pb2 position and the Pb1 position from the lower surface 23. In this example, no peak of the lattice defect density is located at a position other than the Kb position on the lower surface 23 side relative to the Pb4 position.

[0137] For example, hydrogen ions are implanted at positions Pb4, Pb3, Pb2, and Pb1, and the semiconductor substrate 10 is annealed under a first condition. As a result, peaks of the hydrogen chemical concentration distribution are formed at positions Pb4, Pb3, Pb2, and Pb1. Subsequently, hydrogen ions are implanted at position Ps, helium ions are implanted between position Pb2 and position Pb1, and the semiconductor substrate 10 is annealed under a second condition. An annealing temperature of the second condition is lower than that of the first condition. Most of the lattice defects generated by implanting hydrogen ions at positions Pb4, Pb3, Pb2, and Pb1 are terminated by annealing at a relatively high temperature.In contrast, for the lattice defects created by implanting hydrogen ions at the Ps position, the lattice defects at the Ps position are terminated by annealing at a relatively low temperature. On the other hand, a large amount of hydrogen is also present near the Pb1 position, and thus, the lattice defects created by implanting helium ions between the Pb2 and Pb1 positions are also terminated near the Pb1 position, while the lattice defect density exhibits a peak between the Pb2 and Pb1 positions.

[0138] In this example, another peak of the chemical hydrogen concentration is not located on a side from which the hydrogen ions were implanted (the upper surface 21 side in this example) with respect to the peak of the chemical hydrogen concentration at the Ps position. On the other hand, another peak of the chemical hydrogen concentration (the Pb1 position) is located on a side from which the helium ions were implanted (the lower surface 23 side in this example) with respect to the peak of the chemical hydrogen concentration at Pb2. An integrated value of the lattice defect density on the upper surface 21 side relative to the Ps position may be larger than an integrated value of the lattice defect density on the lower surface 23 side relative to the Pb2 position. It should be noted that the lattice defect density at the Kb position can be defined as a chemical helium concentration.

[0139] The distribution diagram (D) shows a carrier lifetime distribution after hydrogen ions are implanted into the semiconductor substrate 10 and then annealed under a predetermined condition. The carrier lifetime distribution has a shape obtained by inverting the vertical axis of the lattice defect density distribution. For example, a position at which a carrier lifetime has a minimum value coincides with the central peak position Ks of the lattice defect density. It should be noted that the carrier lifetime of the semiconductor device 100 has a maximum value τ. O in a range within a range of FW1%M centered on the peak position Ps of the chemical hydrogen concentration. The maximum value τ Omay be for the carrier lifetime in the drift region 18 on the side of the lower surface 23 relative to the peak position Ps of the chemical hydrogen concentration. The carrier lifetime of the semiconductor device 100 may have the maximum value τ O in a range within a range of FW1%M centered on each peak position Ps, Pb4, Pb3, Pb2, and Pb1 of the chemical hydrogen concentration.

[0140] The charge carrier lifetime can have a sufficiently large value τ O on the side of the lower surface 23 relative to the position Z0. The fact that the charge carrier lifetime has the sufficiently large value τ O can be for the charge carrier lifetime in a case where lifetime killers or defects consisting mainly of vacancies or double vacancies are not intentionally introduced into the semiconductor substrate 10. At the temperature of 300 K, τ O10 µs or greater or 30 µs or greater. As an example, τ O 10 µs. The charge carrier lifetime can be less than τ O at position J O of the PN junction between the anode region 14 and the drift region 18 or the collection region 16.

[0141] The distribution diagram (E) shows a distribution of charge carrier mobility after the hydrogen ions have been implanted into the semiconductor substrate 10 and then annealed under a given condition. The charge carrier mobility can have a mobility µ O for a case of an ideal crystal structure on the side of the lower surface 23 relative to the position Z0. The mobility µ O is for example 1360 cm 2 / (Vs) for electrons and 495 cm 2 / (Vs) for holes in a case of silicon at the temperature of 300 K. The mobility of charge carriers can be smaller than µ O at position JO of the PN junction between the anode region 14 and the drift region 18 or the collection region 16.

[0142] A position where the mobility of charge carriers has a minimum value may coincide with the central peak position Ks of the lattice defect density. Furthermore, a position where the mobility of charge carriers has a local minimum value may coincide with the central peak position Kb of the lattice defect density. The mobility of charge carriers of the semiconductor device 100 may reach the maximum value µ O in the range within the range of FW1%M centered on each peak position Ps, Pb4, Pb3, Pb2 and Pb1 of the chemical hydrogen concentration.

[0143] The distribution diagram (F) shows a distribution of a carrier concentration after hydrogen ions are implanted into the semiconductor substrate 10 and then annealed under a predetermined condition. The carrier concentration can be measured by spreading resistance profiling (an SR profiling method) as an example. The SR profiling method converts a spreading resistance into a specific resistance and calculates the carrier concentration from the specific resistance. Assuming that the specific resistance is ρ (Ω cm), the mobility µ (cm 2 / (V·s)), an elementary charge q (C), the charge carrier concentration N ( / cm 3 ), it is expressed as N = 1 / (µqρ).

[0144] The SR profiling method uses a value for a case where the crystalline state of the semiconductor substrate 10 is ideal as the mobility of carriers. However, when damage remains in the semiconductor substrate 10 due to ion implantation, the crystalline state of the semiconductor substrate 10 collapses into a disordered state, and the mobility has actually decreased. Originally, a decreased mobility should be used as the mobility in SR profiling, but it is difficult to measure a value of the decreased mobility. Therefore, in the example shown in the distribution diagram (F), the SR profiling used an ideal value as the mobility. Therefore, the denominator of the expression for the carrier concentration described above increases, and the mobility decreases.In other words, in the distribution diagram (F), the measured carrier concentration has decreased overall in a region through which the hydrogen ions have passed (a region from a lower end of the anode region 14 to the high-concentration region 26 of the semiconductor substrate 10). Note, however, that in the high-concentration region 26 near the projected region Ps of the hydrogen ions, the chemical hydrogen concentration is high, and thus the disorder state is reduced by a hydrogen termination effect, and the mobility approaches a value for the crystalline state. Furthermore, the hydrogen donors are also formed. Therefore, the carrier concentration is higher than the carrier concentration N. O of the semiconductor substrate 10.

[0145] The measured carrier concentration has decreased overall in a region through which the hydrogen ions have passed (a region from the lower end of the anode region 14 to the vicinity of position Ps of the semiconductor substrate 10). It should be noted, however, that in the region on the side of the lower surface 23 relative to position Pb4, the chemical hydrogen concentration is overall high, and thus the carrier concentration is higher than the substrate concentration N. O is.

[0146] In the semiconductor device 100 in this example, the lattice defect density decreases after annealing before and after the peak position Ps of the chemical hydrogen concentration. Therefore, the carrier lifetime near the position Ps where the chemical hydrogen concentration reaches a peak increases and becomes approximately To.

[0147] Furthermore, as an example, the chemical hydrogen concentration at the peak position Pb1 is the highest in the entire semiconductor substrate 10. If a maximum chemical hydrogen concentration value at the peak position Pb1 is 1 × 10 15 atoms / cm 3 or larger, a concentration of hydrogen diffusing on the upper surface 21 side increases. At this time, hydrogen diffuses to the Ps position. As a result, the dangling bonds due to vacancies or double vacancies at the Ps position are terminated not only by hydrogen implanted at Ps from the upper surface 21 side at a maximum concentration, but also by hydrogen moved from the Pb1 position by diffusion. As a result, the lattice defect density near the peak of the doping concentration distribution at the Ps position can be reliably determined to No. Oand the charge carrier lifetime at position Ps can be set to τ0.

[0148] Fig. 11B illustrates another example of an enlarged cross-sectional view near a second lifetime region 200. This example differs from that shown in Fig. 10 is that hydrogen ions are implanted from a side of a lower surface 23 to a side of an upper surface 21 (for example, near an upper surface 21 or lower ends of trench portions) to form first lifetime regions 204. A distance T1 from a lower surface 23 to an end portion of a first lifetime region 204 on the upper surface 21 side may be greater than a value corresponding to half a thickness of a semiconductor substrate 10 in the Z-axis direction. The distance T1 in this example corresponds to a thickness of the first lifetime region 204. Similar to the example shown in Fig. In the example shown in Figure 10, a distance in a depth direction from a depth position of a density peak of lattice defects 202 to an upper end of the first lifetime range 204 is defined as T1'. 2 × T1' can be used as the thickness T1 of the first lifetime range 204.

[0149] Fig. 11C shows another example of a distribution diagram of a net doping concentration (A), a distribution diagram of a chemical hydrogen concentration (B), a distribution diagram of a lattice defect density (C), a distribution diagram of a charge carrier lifetime (D), a distribution diagram of a charge carrier mobility (E), and a distribution diagram of a charge carrier concentration (F) along a line hh in a semiconductor device 100 according to the method shown in Fig. 11B. On a side of the buffer region 20 of a drift region 18, at least one of a doping concentration or a charge carrier concentration may be higher than a volume donor concentration. The side of the buffer region 20 of the drift region 18 refers to the side of the buffer region 20 relative to a center of the drift region 18 in a depth direction. In the embodiment shown in Fig. In the example shown in Fig. 11C, a region in which at least one of the doping concentration or the charge carrier concentration is higher than the volume donor concentration is arranged at a position located in the drift region 18 and in contact with the buffer region 20.

[0150] Fig. 11D illustrates another example of an enlarged cross-sectional view near a second lifetime region 200. This example differs from the Fig. 10 and Fig. 11B is that first lifetime regions 204 are formed continuously from an upper surface 21 to a lower surface 23. The first lifetime regions 204 in this example may be formed by implanting hydrogen ions or helium from the upper surface 21 and passing them through the lower surface 23, or may be formed by implanting hydrogen ions or helium from the lower surface 23 and passing them through the upper surface 21. The first lifetime regions 204 in this example may be formed by irradiating an electron beam. A thickness T1 of a first lifetime region 204 in this example is the same as a thickness of a semiconductor substrate 10. As an example, a width of a region in which a density of lattice defects 202 has a value greater than or equal to a predetermined value may be defined as T1.The specified value for the density of lattice defects 202 can be 1 × 10. 14 / cm 3The predetermined value for the density of lattice defects 202 may be a value for a doping concentration in a drift region 18. As another example, a width of a region in which a carrier concentration is lower than the doping concentration in the drift region 18 by SR profiling may be defined as T1. The doping concentration in the drift region 18 may be a bulk donor concentration, may be a concentration corresponding to a difference between the bulk donor concentration and a bulk acceptor concentration, may have a value obtained by adding the bulk donor concentration and a hydrogen donor concentration, or may have a value obtained by adding the concentration corresponding to the difference between the bulk donor concentration and the volume acceptor concentration and the hydrogen donor concentration.

[0151] Fig. 12 illustrates examples of VI characteristics during forward conduction of a diode section 80. The Fig. 12 shown properties 250 are the same as the properties in the Fig. 4. In the comparative example, no second lifetime region 200 is arranged. Fig. 12 are properties in an example in which a second lifetime region 200 is arranged in a diode section 80, as shown in Fig. 5 to Fig. 9. In the examples of the features 251, a width W1 of the second lifetime region 200 is 8 µm, a thickness T1 of a first lifetime region 204 is 30 µm, and a ratio W1 / T1 is approximately 0.27. A feature 250-1 and a feature 250-1 have the same carrier lifetime in the first lifetime region 204, a feature 250-2 and a feature 250-2 have the same carrier lifetime in the first lifetime region 204, and a feature 250-3 and a feature 250-3 have the same carrier lifetime in the first lifetime region 204. As in Fig. As shown in Figure 12, the arrangement of the second lifetime region 200 is capable of suppressing snapback even when a carrier lifetime is reduced in the first lifetime region 204. This makes it possible to reduce a reverse recovery loss in the diode section 80 while suppressing snapback.

[0152] Fig. 13 illustrates trade-off characteristics between a forward voltage Vf and a reverse recovery loss Err in a diode section 80. Diagrams indicated by circles in Fig. 13 are displayed are properties for a case where a second lifetime region 200 is arranged in a diode section 80, as in Fig. 5 to Fig. 9. Diagrams represented by squares in Fig. 13 are properties for a case where no second lifetime range 200 is arranged. In the examples indicated by black squares, a snapback has occurred.

[0153] As in Fig. As shown in Figure 13, even if the second lifetime region 200 is disposed, it is possible to obtain trade-off characteristics equivalent to those obtained when no second lifetime region 200 is disposed. Furthermore, even in a region where a carrier lifetime is short, disposing the second lifetime region 200 is capable of suppressing the occurrence of snapback.

[0154] Fig. 14 illustrates a relationship between a width W1 of a second lifetime region 200 and a snapback amount (an SB amount). In this example, a second lifetime region 200 is arranged in a diode section 80 as shown in Fig. 5 to Fig. 9. A thickness T1 of a first lifetime region 204 in this example is 30 µm. It can be seen that increasing the width W1 of the second lifetime region 200 reduces the snapback amount. Specifically, when the width W1 of the second lifetime region 200 exceeds 7 µm, the snapback amount decreases significantly, and when the width W1 becomes 11 µm or larger, the snapback amount becomes 0.

[0155] The width W1 of the second lifetime region 200 may be 7 µm or greater. The width W1 may be 8 µm or greater, 10 µm or greater, or 11 µm or greater. A ratio W1 / T1 of the width W1 of the second lifetime region 200 to the thickness T1 of the first lifetime region 204 may be 0.23 or greater, 0.27 or greater, 0.33 or greater, or 0.37 or greater. Furthermore, the width W1 of the first lifetime region may be 12 µm or less. The ratio W1 / T1 may be 0.4 or less.

[0156] Fig. 15 illustrates whether a snapback has occurred when a thickness T1 of a first lifetime range 204 and a width W1 of a second lifetime range 200 are changed. Diagrams indicated by circle marks in Fig. The figures shown in Figure 15 show a boundary example where snapback does not occur. Snapback did not occur in regions 220, 222, and 224, where the width W1 is larger (or the thickness T1 is smaller) than that at the boundary example.

[0157] It should be noted, however, that in the region 222, the thickness T1 of the first lifetime region 204 is large, thus decreasing the IE effect and causing the forward voltage Vf to be too high. In the region 224, the thickness T1 of the first lifetime region 204 is small, thus increasing the IE effect even in a low-current operating region, and causing the forward voltage Vf to be too low. Therefore, it is preferable to set the thickness T1 of the first lifetime region 204 and the width W1 of the second lifetime region 200 within a range of the region 220. The region 220 is a region where the width W1 is greater than a width W (µm) defined by a straight line 230. The straight line 230 is given by Expression 1: W=0.21×T1+3.3

[0158] As described above, if the thickness T1 of the first lifetime region 204 is too large, the IE effect decreases. The thickness T1 may be smaller than a thickness of a drift region 18 in a depth direction (Z-axis direction). In addition, the thickness T1 may be 100 μm or smaller, 60 μm or smaller, or 40 μm or smaller. The thickness T1 is greater than 0. It should be noted, however, that if the thickness T1 is too small, the IE effect also increases in the low-current operating range, and the forward voltage Vf is too low. The thickness T1 may be 10 μm or larger, 15 μm or larger, or 20 μm or larger.

[0159] Fig. 16A illustrates another arrangement example of a first lifetime region 204 and a second lifetime region 200 in a diode section 80. Except for an arrangement of a first lifetime region 204 and a second lifetime region 200, this example has an aspect similar to any aspect described in Fig. 1 to Fig. 15 is described.

[0160] A semiconductor device 100 in this example includes two or more second lifetime regions 200 in a diode section 80. The respective second lifetime regions 200 are spaced apart from each other in a first direction (the X-axis direction in this example). A first lifetime region 204 is arranged between two second lifetime regions 200. A width W1 of each of the second lifetime regions 200 may be the same as the width W1 shown in Fig. 1 to Fig. 15. Providing two or more second lifetime regions 200 can uniform an electron density across the first lifetime regions 204. Electrons can be distributed across and passed through a plurality of second lifetime regions 200.

[0161] It should be noted that in each of the examples given in Fig. 1 to Fig. 16A, a sum of widths W1 of one or more second lifetime regions 200 included in a diode section 80 in the first direction (the X-axis direction in this example) may be 0.1 times or less of a width WD of a diode section 80 in the first direction. If the sum of the widths W1 is too large, a turn-off time of the diode section 80 is longer and a reverse recovery loss increases. The sum of the widths W1 may be 0.05 times or less of the width WD. The sum of the widths W1 may be 0.001 times or more, or 0.01 times or more of the width WD.

[0162] The diode section 80 includes a plurality of trench sections (dummy trench sections 30 in this example) arranged above the first lifetime regions 204. A distance D2 between a second lifetime region 200 and a transistor section 70 in the first direction (the X-axis direction in this example) may be greater than or equal to a distance D1 between a lower end of a trench section (a dummy trench section 30 in this example) and the first lifetime region 204 in a second direction (the Z-axis direction in this example). The trench section may be a dummy trench section 30 that is closest to the transistor section 70 among a plurality of dummy trench sections 30 in the diode section 80. An end portion of the transistor section 70 in the X-axis direction is a boundary portion between a collector region 22 and a cathode region 82.Ensuring the distance D2 can prevent the electrons implanted from the cathode region 82 from extending to the transistor section 70 and can prevent the electrons from escaping to an emitter electrode 52 through an n-type channel formed in a base region 14 of the transistor section 70. The distance D2 can be 1.5 times or more, or twice or more, the distance D1.

[0163] The two or more second lifetime regions 200 may be arranged at regular intervals in the first direction. In another example, an interval W3 between the second lifetime regions 200 may be smaller than the distance D2. This configuration may also increase the distance D2. In this example, the interval W3 between the second lifetime regions 200 is a width of the first lifetime region 204 in the first direction. Each of the second lifetime regions 200 may be arranged at a center of the diode section 80 in the first direction. As a result, electrons or holes are implanted symmetrically with respect to the center of the diode section 80, and a carrier concentration in the diode section 80 will have a substantially uniform distribution.

[0164] Fig. 16B illustrates another arrangement example of a first lifetime region 204 and a second lifetime region 200 in a diode section 80. This example differs from that in Fig. 16A in that first lifetime regions 204 and a second lifetime region 200 are formed on one side of the lower surface 23. The first lifetime regions 204 and the second lifetime region 200 may be formed in a buffer region 20, may be formed in both the buffer region 20 and a cathode region 82, or may be formed in both the buffer region 20 and a collector region 22. Similar to the example shown in Fig. In the example shown in FIG. 11B, a distance in a depth direction from a depth position of a density peak of lattice defects 202 to an upper end of a first lifetime region 204 is defined as T1'. 2 × T1' can be used as a thickness T1 of the first lifetime region 204. As a result, electrons or holes are implanted evenly in a first direction, and snapback can be suppressed.

[0165] Fig. 16C illustrates another arrangement example of a first lifetime region 204 and a second lifetime region 200 in a diode section 80. This example differs from that in Fig. 16B is that first lifetime regions 204 and a second lifetime region 200 are formed on a lower surface 23 side of a drift region 18. A distance T1 from a lower surface 23 to an end portion of a first lifetime region 204 on an upper surface side may be smaller than a value corresponding to half a thickness of a semiconductor substrate 10 in the Z-axis direction. When the first lifetime regions 204 are formed by implanting hydrogen ions or the like from the lower surface 23, the distance T1 corresponds to a thickness of the first lifetime region 204. Similar to the example shown in Fig. In the example shown in FIG. 11B, a distance in a depth direction from a depth position of a density peak of lattice defects 202 to an upper end of the first lifetime range 204 is defined as T1'. 2 × T1' can be used as the thickness T1 of the first lifetime range 204.

[0166] Fig. 17 illustrates whether a snapback has occurred when the number of second lifetime regions 200 included in a diode section 80 and a width W1 of each of the second lifetime regions 200 are changed. Diagrams indicated by circle marks in Fig. 17 show a boundary example where snapback does not occur. Snapback did not occur in a region 240 where the width W1 is larger than that in the boundary example. When a plurality of second lifetime regions 200 are provided, the plurality of second lifetime regions 200 are arranged at regular intervals in a first direction. In this example, a thickness T1 of a first lifetime region 204 is 30 µm.

[0167] If the number of second lifetime ranges is 200 (the number of ranges on the horizontal axis in Fig. 17), there is a tendency that snapback can be suppressed even if the width W1 of a second lifetime region 200 is reduced. Note, however, that even if the number of second lifetime regions 200 is greater than four, the width W1 of the second lifetime region 200 required to prevent snapback has not been reduced.

[0168] The width W1 of a second lifetime region 200 may be 8 µm or greater. The width W1 may be 0.27 times or more the thickness T1 of the first lifetime region 204. Furthermore, even if only one second lifetime region 200 is arranged in a diode section 80, the width W1 of approximately 12 µm is capable of suppressing snapback. The width W1 may be 12 µm or less. The width W1 may be 0.4 times or less the thickness T1 of the first lifetime region 204.

[0169] Fig. 18 illustrates an arrangement example of a first lifetime region 204 and a second lifetime region 200 in an XY plane. First lifetime regions 204 and second lifetime regions 200 in this example are arranged in a stripe pattern with a longitudinal length in a third direction (Y-axis direction in this example) parallel to a top surface 21 of a semiconductor substrate 10 and perpendicular to a first direction (X-axis direction in this example). The first lifetime regions 204 and the second lifetime regions 200 may have the same length as that of a cathode region 82 in the Y-axis direction or may be longer than the cathode region 82.

[0170] In this example, a diode section 80 and a transistor section 70 are arranged side by side in the first direction (X-axis direction). In addition, as shown in Fig. 2 or the like, respective trench portions (gate trench portions 40 and dummy trench portions 30) are spaced apart from each other in the first direction (X-axis direction). In this example, a longitudinal direction of the first lifetime regions 204 and the second lifetime regions 200 is the same as a longitudinal direction of the trench portions. Furthermore, the longitudinal direction of the first lifetime regions 204 and the second lifetime regions 200 is the same as a longitudinal direction of the diode portion 80 (or the cathode region 82).

[0171] Fig. 19 illustrates another arrangement example of a first lifetime region 204 and a second lifetime region 200 in an XY plane. In this example, the Y-axis direction is a first direction, and the X-axis direction is a third direction. In other words, the first lifetime regions 204 and the second lifetime regions 200 in this example are arranged adjacent to each other in the Y-axis direction. The first lifetime regions 204 and the second lifetime regions 200 in this example are arranged in a stripe pattern with a longitudinal length in the X-axis direction (third direction). The first lifetime regions 204 and the second lifetime regions 200 may have the same length as that of a diode portion 80 in the X-axis direction, or may be longer than the diode portion 80.

[0172] In this example, a diode section 80 and a transistor section 70 are arranged side by side in the third direction (X-axis direction). Furthermore, respective trench sections (gate trench sections 40 and dummy trench sections 30) are spaced apart from each other in the third direction (X-axis direction). In this example, a longitudinal direction of the first lifetime regions 204 and the second lifetime regions 200 is orthogonal to a longitudinal direction of the trench sections. Furthermore, the longitudinal direction of the first lifetime regions 204 and the second lifetime regions 200 is orthogonal to a longitudinal direction of the diode section 80 (or a cathode region 82). This arrangement can also reduce a reverse recovery loss of the diode section 80 while suppressing snapback.

[0173] Fig. 20 illustrates another arrangement example of a first lifetime region 204 and a second lifetime region 200 in an XY plane. In this example, a second lifetime region 200 is sandwiched between first lifetime regions 204 in a third direction (the Y-axis direction in this example) parallel to a top surface 21 of a semiconductor substrate 10 and perpendicular to a first direction (the X-axis direction in this example).

[0174] As an example, a plurality of first lifetime regions 204 may be discretely arranged in both the X-axis direction and the Y-axis direction. Fig. In the example shown in Figure 20, the first lifetime regions 204, which are rectangular in plan view, are discretely arranged along both the X-axis direction and the Y-axis direction. The second lifetime region 200, in this example, has a lattice pattern in which a portion extending in the X-axis direction intersects a portion extending in the Y-axis direction in plan view.

[0175] In another example, a plurality of second lifetime regions 200 may be discretely arranged in both the X-axis direction and the Y-axis direction. For example, the second lifetime regions 200, which are rectangular in plan view, may be discretely arranged along both the X-axis direction and the Y-axis direction.

[0176] In this example, a width of the second lifetime range 200 in the Y-axis direction is defined as W2. The width W2 can be a condition similar to that in Fig. 1 to Fig. 19. For example, the width W2 is 0.2 times or more of a thickness T1 of a first lifetime region 204. It should be noted, however, that the width W2 and the width W1 may not be the same. The width W1 and the width W2 may have different values ​​within a range of the values ​​shown in Fig. 1 to Fig. 19 described conditions for the width W1. This configuration can also reduce a reverse recovery loss of a diode section 80 while suppressing snapback.

[0177] Fig. 21 illustrates another arrangement example of a first lifetime region 204 and a second lifetime region 200 in an XY plane. In this example, a first lifetime region 204 is parallel to a top surface 21 of a semiconductor substrate 10 and is arranged between second lifetime regions 200 in both a first direction (the X-axis direction in this example) and a third direction (the Y-axis direction in this example).

[0178] As an example, a plurality of second lifetime regions 200 may be discretely arranged in both the X-axis direction and the Y-axis direction. Fig. In the example shown in Figure 21, second lifetime regions 200, which are rectangular in plan view, are discretely arranged along both the X-axis direction and the Y-axis direction. The first lifetime region 204 in this example has a lattice pattern in which a portion extending in the X-axis direction intersects a portion extending in the Y-axis direction in plan view. This configuration can also reduce reverse recovery loss of a diode section 80 while suppressing snapback.

[0179] A second lifetime region 200 may be arranged in a first lifetime region 204 of the diode section 80. A second lifetime region 200 may or may not be arranged in the first lifetime region 204 of a transistor section 70. The fact that the second lifetime region 200 is arranged in the first lifetime region 204 refers to the fact that the second lifetime region 200 is enclosed by the first lifetime region 204 in a plan view. In the transistor section 70, a ratio of an area S2_t of the second lifetime region 200 enclosed by the first lifetime region 204 to an area S1_t of the first lifetime region 204 is defined as S2_t / S1_t. In the diode section 80, a ratio of an area S2_d of the second lifetime region 200 enclosed by the first lifetime region 204 to an area S1_d of the first lifetime region 204 is defined as S2_d / S1_d.The ratio S2_t / S1_t may be smaller than the ratio S2_d / S1_d. The ratio S2_t / S1_t may be less than or equal to 50%, less than or equal to 20%, or less than or equal to 10% of the ratio S2_d / S1_d. The area S2_t may be 0. When a body diode of the transistor section 70 is energized, a relatively large number of charge carriers are implanted, but the second lifetime region 200 in the first lifetime region 204 of the transistor section 70 becomes small or cannot shorten a lifetime of the charge carriers.

[0180] Fig. Figure 22A illustrates another arrangement example of a first lifetime region 204 and a second lifetime region 200 in an XY plane. This example differs from that shown in Fig. 21 in an arrangement of a plurality of second lifetime regions 200. Apart from that, this example has a structure similar to that in the example shown in Fig. 21 is similar to the example shown.

[0181] In the Fig. 21, the plurality of second lifetime regions 200 are arranged side by side in the X-axis direction and in the Y-axis direction. In the example shown in Fig. In the example shown in Figure 22A, a plurality of second lifetime regions 200 are arranged side by side along two directions different from both the X-axis and the Y-axis. This configuration can also reduce reverse recovery loss of a diode section 80 while suppressing snapback.

[0182] A second lifetime region 200 may be located within a first lifetime region 204 of the diode section 80. A second lifetime region 200 may or may not be located within the first lifetime region 204 of a transistor section 70. This configuration may also reduce the reverse recovery loss of the diode section 80 while suppressing snapback.

[0183] Fig. Figure 22B illustrates another arrangement example of a first lifetime region 204 and a second lifetime region 200 in an XY plane. This example differs from that shown in Fig. 22A in an arrangement of a plurality of second lifetime regions 200. The arrangement of the plurality of second lifetime regions 200 may not be symmetrical and may be random.

[0184] Fig. Figure 23A illustrates another arrangement example of a first lifetime region 204 and a second lifetime region 200 in an XY plane. This example differs from that shown in Fig. 20 in an arrangement of a plurality of first lifetime regions 204. Apart from that, this example has a structure similar to that in the example shown in Fig. 20 is similar to the example shown.

[0185] In the Fig. 20, the plurality of first lifetime regions 204 are arranged side by side in the X-axis direction and in the Y-axis direction. In the example shown in Fig. In the example shown in Figure 23A, a plurality of first lifetime regions 204 are arranged side by side along two directions that differ from both the X-axis and the Y-axis. This configuration can also reduce reverse recovery loss of a diode section 80 while suppressing snapback.

[0186] A second lifetime region 200 in this example has a lattice pattern in which a portion extending in the X-axis direction intersects a portion extending in the Y-axis direction in a plan view. Widths in directions orthogonal to extension directions of the second lifetime region 200 can be used as widths W1 and W2 of the second lifetime region 200. In this example, a width in the X-axis direction of the second lifetime region 200 extending in the Y-axis direction is defined as W1, and a width in the Y-axis direction of the second lifetime region 200 extending in the X-axis direction is defined as W2.

[0187] Fig. Figure 23B illustrates another arrangement example of a first lifetime region 204 and a second lifetime region 200 in an XY plane. This example differs from that shown in Fig. 23A in an arrangement of a plurality of first lifetime regions 204. The arrangement of the plurality of first lifetime regions 204 may not be symmetrical and may be random.

[0188] Fig. 24 illustrates another arrangement example of a first lifetime region 204 and a second lifetime region 200 in an XY plane. In this example, the extension directions of a first lifetime region 204 and a second lifetime region 200 differ from both the X-axis direction and the Y-axis direction. Except for this, this example has a structure similar in any aspect to that described in the present specification.

[0189] In this example, first lifetime regions 204 and second lifetime regions 200 are alternately arranged along a first direction orthogonal to an extension direction of each lifetime region. The first direction, in this example, differs from both the X-axis direction and the Y-axis direction. Trench portions of a transistor portion 70 and a diode portion 80 are arranged to extend in the Y-axis direction (in other words, to have a longitudinal length). Therefore, each of a plurality of trench portions extends in one direction at an angle greater than 0 degrees and less than 90 degrees with respect to the first direction on a top surface 21 of a semiconductor substrate 10. The angle may be 15 degrees or greater, may be 30 degrees or greater, or may be 45 degrees or greater. The angle may be 75 degrees or less, may be 60 degrees or less, or may be 45 degrees or less.This configuration can also reduce a reverse recovery loss of a diode section 80 while suppressing snapback.

[0190] Fig. 25 illustrates another arrangement example of a first lifetime region 204 and a second lifetime region 200 on an XY plane. In this example, first lifetime regions 204, which are annular, and second lifetime regions 200, which are annular, are alternately arranged concentrically. In this example, an X-axis width of a second lifetime region 200 extending in the Y-axis direction is defined as W1, and a Y-axis width of a second lifetime region 200 extending in the X-axis direction is defined as W2.

[0191] A second lifetime region 200 may be arranged within a first lifetime region 204 of a diode section 80. A second lifetime region 200 may or may not be arranged within the first lifetime region 204 of a transistor section 70. This configuration may also reduce reverse recovery loss of the diode section 80 while suppressing snapback.

[0192] Fig. Figure 26 illustrates another arrangement example of a first lifetime region 204 and a second lifetime region 200 in an XY plane. In this example, the Y-axis direction is a first direction, and the X-axis direction is a third direction. In other words, in this example, the first lifetime regions 204 and the second lifetime regions 200 are arranged side by side in the Y-axis direction.

[0193] The first lifetime regions 204 and the second lifetime regions 200 in this example are partially arranged in a stripe pattern with a longitudinal length in the X-axis direction (third direction). Both end portions of the first lifetime regions 204 in this example in the X-axis direction are arranged in a transistor section 70. Both end portions of the second lifetime regions 200 in this example in the X-axis direction are arranged in a diode section 80 or at a boundary between the diode section 80 and the transistor section 70. This arrangement can also reduce a reverse recovery loss of the diode section 80 while suppressing snapback.

[0194] In each of the Fig. 1 to Fig.In the examples described in FIG. 26, the width W1 and the width W2 of the second lifetime region 200 may be greater than or equal to 3% of a diffusion length of charge carriers in the semiconductor substrate 10. The diffusion length of charge carriers in the semiconductor substrate 10 may, for example, be a diffusion length of charge carriers in a region where lifetime control is not performed. The region where lifetime control is not performed may, for example, be the drift region 18, which is neither the first lifetime region 204 nor the second lifetime region 200 among the drift regions 18. The diffusion length of charge carriers may be a diffusion length of electrons, a diffusion length of holes, or a bipolar diffusion length.As described above, when the electrons pass through the second lifetime region 200, the electrons can be bound to the lattice defects 202 in the first lifetime regions 204 on both sides of the second lifetime region 200. It is possible to suppress the electrons from being bound to the lattice defects 202 by setting a ratio of the width W1 and the width W2 of the second lifetime region 200 to the diffusion length of electrons to a ratio greater than or equal to a predetermined ratio.

[0195] A diffusion length of electrons L n is given by expression 2: Ln=(DnTn)0.5 where D n a diffusion coefficient of electrons (cm 2 / s) and τ n is the lifetime of electrons (s). The diffusion coefficient D n is given by expression 3: Dn=(kBTμn) / q where k Ba Boltzmann constant (1.38 × 10 -23 (J / K)), T is a temperature (K), µn is the mobility of electrons (cm 2 / Vs) in the semiconductor substrate 10 and q is an elementary charge (1.60 × 10 -19 (C)). A diffusion length of holes L p is given by expression 4: Lp=(DpTp)0.5 where D p a diffusion coefficient of holes (cm 2 / s) and τ p is the lifetime of electrons (s). The diffusion coefficient D p is given by expression 5: Dp=(kBTμp) / q where µn is the mobility of holes (cm 2 / Vs) in the semiconductor substrate 10. The bipolar diffusion length is given by Expression 6: La=(DaTHL)0.5 where D a a bipolar diffusion coefficient (cm 2 / s) and D a = 2D n D p / (D n + D p ) is produced. τ HLis a high implantation level lifetime (s) and τ HL = τ n + τ p is manufactured. If the semiconductor substrate 10 is a silicon substrate and if the temperature T is -40 degrees C, τ n 1 × 10 -5 (s), µn can be 2600 (cm 2 / Vs), D n can 52.25 (cm 2 / s) and L n can be 230 (µm). If the semiconductor substrate 10 is a silicon substrate and if the temperature T is -40 degrees C, τ p 1 × 10 -5 (s), µ p is 860 (cm 2 / Vs), D p is 17.36 (cm 2 / s) and L p is 126 (µm). If the semiconductor substrate 10 is a silicon substrate and the temperature T is -40 degrees C, τ HL 2 × 10 -5 (s) be, D a can 26.06 (cm 2 / s) and L amay be 228.3 (µm). The width W1 and the width W2 of the second lifetime region 200 may be greater than or equal to 3% or greater than or equal to 4% of the diffusion length of charge carriers in the semiconductor substrate 10.

[0196] While the present invention has been described with reference to the embodiments, the technical scope of the present invention is not limited to the scope described in the above-described embodiments. It is obvious to those skilled in the art that various modifications or improvements can be made to the above-described embodiments. It is obvious from the description of the claims that embodiments provided with such modifications or improvements can also be included within the technical scope of the present invention.

[0197] It should be noted that the operations, procedures, steps, stages, and the like of each process performed by an apparatus, system, program, and method shown in the claims, embodiments, or diagrams can be performed in any order, as long as the order is not indicated by "before," "before," or the like, and as long as the output from a previous process is not used in a subsequent process. Even if the flow of operations is described using terms such as "first" or "next" in the claims, embodiments, or diagrams for convenience, this does not necessarily mean that the process must be performed in that order. LIST OF REFERENCE SYMBOLS

[0198] 10: Semiconductor substrate; 11: Well region; 12: Emitter region; 14: Base region; 15: Contact region; 16: Collector region; 18: Drift region; 19: Bottom surface side lifetime region; 20: Buffer region; 21: Top surface; 22: Collector region; 23: Bottom surface; 24: Collector electrode; 26: High concentration region; 29: Straight portion; 30: Dummy trench portion; 31: Edge portion; 32: Dummy dielectric film; 34: Dummy wiring portion; 38: Interlayer dielectric film; 39: Straight portion; 40: Gate trench portion; 41: Edge portion; 42: Gate dielectric film; 44: Gate wiring portion; 52: Emitter electrode; 54: Contact hole; 60, 61: mesa section; 70: transistor section; 80: diode section; 81: extension region; 82: cathode region; 85: straight line; 90: edge termination structure section; 100: semiconductor device; 130: outer circumferential gate rotor; 131: active-side gate rotor; 160: active section; 162: end face; 164: gate array;200: second lifetime range; 202: lattice defect; 204: first lifetime range; 220, 222, 224: range; 230: straight line; 240: range; 250: property; and 251: property.; QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 202031155

[0002] JP 2020120121

[0002]

Claims

[1] A semiconductor device comprising: a semiconductor substrate having a top surface and a bottom surface, which has a drift region of a first conductivity type; and a diode section arranged in the semiconductor substrate, the diode section comprising: a base region of a second conductivity type disposed between the drift region and the top surface of the semiconductor substrate; a first lifetime region disposed in the drift region on one side of the lower surface of the semiconductor substrate relative to the base region; and a second lifetime region arranged to be located between first lifetime regions including the first lifetime region in a first direction parallel to the upper surface of the semiconductor substrate, and in which a carrier lifetime is longer than in the first lifetime region, and a width of the second lifetime range in the first direction is greater than a width W (µm) given by Expression 1: W=0.21×T1+3.3 where T1 is a thickness (µm) of the first lifetime region in a second direction perpendicular to the top surface. [2] A semiconductor device according to claim 1, wherein the width of the second lifetime range in the first direction is 7 µm or larger. [3] A semiconductor device according to claim 1, wherein the width of the second lifetime range in the first direction is 12 µm or smaller. [4] A semiconductor device according to claim 1, wherein the diode section has one or more second lifetime ranges including the second lifetime range, a sum of widths of the one or more second lifetime regions in the first direction is 0.1 times or less of a width of the diode portion in the first direction. [5] A semiconductor device according to any one of claims 1 to 4, further comprising a transistor section disposed in the semiconductor substrate and juxtaposed with a diode section in the first direction. [6] A semiconductor device according to claim 5, wherein the diode section and the transistor section have a plurality of trench sections spaced apart from each other in the first direction. [7] A semiconductor device according to any one of claims 1 to 4, further comprising a transistor section disposed in the semiconductor substrate and juxtaposed with the diode section in a third direction parallel to the upper surface of the semiconductor substrate and perpendicular to the first direction. [8] A semiconductor device according to claim 7, wherein the diode section and the transistor section have a plurality of trench sections spaced apart from each other in the third direction. [9] A semiconductor device according to claim 6, wherein at least some of the trench portions of the diode portion are arranged above the first lifetime region, and a distance between the second lifetime region and the transistor section in the first direction is greater than or equal to a distance between a lower end of a trench section of the trench sections and the first lifetime region in the second direction. [10] A semiconductor device according to any one of claims 1 to 4, wherein the diode section has two or more second lifetime regions including the second lifetime region spaced apart from each other in the first direction. [11] A semiconductor device according to any one of claims 1 to 4, wherein the second lifetime range is enclosed between first lifetime ranges including the first lifetime range also in a third direction parallel to the upper surface of the semiconductor substrate and perpendicular to the first direction. [12] A semiconductor device according to claim 11, wherein a width of the second lifetime region in the third direction is 0.2 times or more of the thickness of the first lifetime region in the second direction. [13] A semiconductor device according to any one of claims 1 to 4, wherein the width of the second lifetime region in the first direction is greater than or equal to 3% of a diffusion length of charge carriers in the semiconductor substrate. [14] A semiconductor device according to any one of claims 1 to 3, wherein the thickness of the first lifetime region in the second direction is smaller than a thickness of the drift region in the second direction. [15] A semiconductor device according to any one of claims 1 to 4, wherein the width of the second lifetime region in the first direction is 0.2 times or more of the thickness of the first lifetime region in the second direction perpendicular to the top surface of the semiconductor substrate. [16] A semiconductor device according to claim 6, wherein a width of the first lifetime region is greater than a width of a mesa section arranged between the adjacent trench sections. [17] A semiconductor device according to any one of claims 1 to 4, wherein the first lifetime region contains hydrogen. [18] A semiconductor device according to any one of claims 1 to 4, wherein the first lifetime region contains helium. [19] A semiconductor device according to claim 5, wherein the first lifetime range is arranged in the diode section and the transistor section, a ratio of an area of ​​the second lifetime region enclosed by the first lifetime region to an area of ​​the first lifetime region in the transistor section is smaller than a ratio of an area of ​​the second lifetime region enclosed by the first lifetime region to an area of ​​the first lifetime region in the diode section. [20] A semiconductor device according to claim 5, wherein the second lifetime range is arranged in the first lifetime range of the diode section, and the second lifetime range is not arranged in the first lifetime range of the transistor section. [21] A semiconductor device according to any one of claims 1 to 4, wherein each of the plurality of trench portions extends in one direction at an angle greater than 0 degrees and less than 90 degrees with respect to the first direction on the upper surface of the semiconductor substrate.