COMPUTER

Abstract

The aim is to prevent a delay in the display of a line drawing due to a processing delay in a computer without providing an overlay engine in a timing unit. For this purpose, a computer 1 comprises a host processor 12, which generates a line drawing representing lines defined by a sequence of coordinate data, each representing the position of a stylus on a touch surface, and a video signal VS1 representing the generated line drawing; a timing unit 30, which controls the potential of each of a plurality of gate lines GL arranged in a display field 14 based on a video signal VS2; and an MCU 40, which generates a preliminary line drawing SI in parallel with the host processor 12, representing the same lines as those depicted by the line drawing described above.The preliminary line drawing is superimposed onto the video signal VS2, which has not yet been fed to the time control unit 30.

Description

TECHNICAL AREA

[0001] The present invention relates to a computer and in particular to a computer that can prevent a delay in the display of a line drawing. TECHNICAL BACKGROUND

[0002] In computers, such as tablet devices that support stylus input, data such as coordinate data specifying the position of a stylus and stylus pressure values ​​transmitted by the stylus (hereinafter collectively referred to as "stylus data") are fed from a sensor control unit connected to a touch sensor to a host processor. The host processor then processes this data to generate a line drawing representing a line or lines or text, and to display the generated line drawing on a screen.

[0003] Patent document 1 discloses an example of a computer that supports pen input. In the computer described in the document, to avoid a delay in the display of the line drawing due to processing delays within the computer, an overlay engine is provided in a timing control unit that is part of the display, and the coordinate data is transmitted directly from the sensor control unit to this overlay engine. The overlay engine performs processing to generate a preliminary line drawing based on the coordinate data received from the sensor control unit and to update a display frame received from the host processor based on the generated preliminary line drawing.

[0004] Patent document 2 discloses an example of a liquid crystal display device comprising a graphics processing circuit including a scaler in a stage preceding the timing control unit. STATE OF THE ART Patent documents

[0005] Patent Document 1: US Patent No. US 9721365 B Patent Document 2: JP 2008 - 233869 A Outline of the invention; Problem to be solved by the invention

[0006] The technology described in patent document 1 can prevent a delay in the display of the line drawing, but presents a problem in that the overlay engine must be integrated into the timing unit, which is part of the display. Accordingly, there is a need for a technology that can prevent a delay in the display of the line drawing even without providing an overlay engine in the timing unit.

[0007] Therefore, one of the objectives of the present invention is to provide a computer that can prevent a delay in the display of a line drawing even without providing an overlay engine in a timing control unit. MEANS OF SOLVING THE TASK

[0008] A computer according to the present invention is a computer comprising a host processor configured to generate a line drawing representing lines represented by a sequence of coordinate data, each representing a position of a pen on a touch surface, and to generate a video signal representing the generated line drawing; a timing unit configured to control a potential of each of a plurality of gate lines arranged in a display based on the video signal; and a processor for generating a preliminary line drawing, configured to generate, in parallel with the host processor, a preliminary line drawing representing the same lines as the lines represented by the line drawing, wherein the preliminary line drawing is superimposed on the video signal that has not yet been supplied to the timing unit. EFFECTS OF INVENTION

[0009] According to the present invention, a preliminary line drawing, representing the same lines as the line drawing generated by the host processor, is generated in parallel to the host processor and superimposed onto a video signal that has not yet been fed to the timing unit. It is therefore possible to prevent a delay in the display of the line drawing even without providing an overlay engine in the timing unit. BRIEF DESCRIPTION OF THE FIGURES Fig. Figure 1 is a diagram illustrating a configuration of a position detection system 2 comprising a computer 1 according to a first embodiment of the present invention. Fig. Figure 2 is a diagram illustrating an internal configuration of a video board 13 and a display panel 14 according to the first embodiment of the present invention. Fig. Figure 3 is a diagram illustrating a configuration of a position detection system 2 comprising a computer 1 according to a second embodiment of the present invention. Fig. Figure 4 is a diagram illustrating a configuration of a position detection system 2 comprising a computer 1 according to a third embodiment of the present invention. Fig. Figure 5 is a diagram illustrating an internal configuration of a video board 13 and a display panel 14 according to the third embodiment of the present invention. Fig. Figure 6 is a diagram illustrating a configuration of a position detection system 2 comprising a computer 1 according to a fourth embodiment of the present invention. Fig. Figure 7 is a diagram illustrating an internal configuration of a video board 13 and a display panel 14 according to the fourth embodiment of the present invention. Fig. Figure 8 is a diagram illustrating a configuration of a position detection system 2 comprising a computer 1 according to a fifth embodiment of the present invention. Fig. Figure 9 is a diagram illustrating an internal configuration of a video board 13 and a display panel 14 according to the fifth embodiment of the present invention. FORMS OF EXECUTION OF THE INVENTION

[0010] Embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0011] Fig. Figure 1 is a diagram illustrating a configuration of a position detection system 2 comprising a computer 1 according to a first embodiment of the present invention. As shown in Fig. As illustrated in Figure 1, the position detection system 2 includes an electronic pen 3 in addition to the computer 1.

[0012] Computer 1 is a computer, such as a tablet or smartphone, that has a control surface 1a which serves as both a touch surface and a display surface. However, Computer 1 can also be a computer in which a touch control surface or digitizer that supports pen input and a display are provided separately.

[0013] Computer 1 and electronic pen 3 are configured to communicate bidirectionally via an electromagnetic induction (EMR) system. Hereinafter, a signal transmitted from Computer 1 to electronic pen 3 through this communication is referred to as an "uplink signal US," and a signal transmitted from electronic pen 3 to Computer 1 through this communication is referred to as a "pen signal PS."

[0014] The computer 1 includes a sensor 10, a sensor control unit 11, a host processor 12, a video board 13, a display panel 14 and an MCU (microcontroller unit) 40.

[0015] The sensor 10 comprises a plurality of loop coils arranged on the inside of the control panel surface 1a. One end of each loop coil is connected to the sensor control unit 11, and the other end is grounded. The loop coils serve to supply operating power and commands to the electronic pin 3 and to receive the pin signal PS, which is transmitted by the electronic pin 3, by being coupled via electromagnetic induction to a coil in an LC resonant circuit provided inside the electronic pin 3.

[0016] The sensor control unit 11 is an integrated circuit that transmits the uplink signal US via the sensor 10 to the electronic pin 3 and receives the pin signal PS, which is sent by the electronic pin 3 as a reflection signal in response to the uplink signal US. The uplink signal US is a signal for supplying operating power and commands to the electronic pin 3. The uplink signal US is transmitted periodically by the sensor control unit 11. The electronic pin 3 is configured to store energy in a capacitor in the LC resonant circuit while receiving the uplink signal US, and to transmit the pin signal PS using the stored energy when the electronic pin 3 finishes receiving the uplink signal US.

[0017] Each time the sensor control unit 11 transmits the uplink signal US, it performs processing based on the received pen signal PS to derive coordinate data that specifies the position of the electronic pen 3 on the control panel surface 1a. More precisely, the sensor control unit 11 is configured to derive the coordinate data that specifies the position of the electronic pen 3 by deriving a distribution of the received strength of the pen signal PS on the control panel surface 1a based on the received strength of the pen signal PS at the loop coils and deriving the coordinate data of the position corresponding to a peak of the distribution.

[0018] Additionally, the sensor control unit 11 performs processing to obtain a value indicating the pressure exerted on the tip of the electronic pen 3 (hereinafter referred to as the "pen pressure value") by detecting a phase change in the received pen signal PS. More precisely, the capacitor forming the LC resonant circuit of the electronic pen 3 is a variable-capacitance capacitor whose capacitance changes according to the pressure exerted on the tip of the electronic pen 3. As the capacitance of the variable-capacitance capacitor changes, the resonant frequency of the LC resonant circuit changes, and consequently, so does the frequency of the pen signal PS. The sensor control unit 11 detects this change in frequency by sensing the phase change of the pen signal PS and obtains the pen pressure value based on the result of this detection.

[0019] The sensor control unit 11 is configured to sequentially supply the derived coordinate data and the obtained pen pressure values ​​to the host processor 12 and the MCU 40. These data elements supplied by the sensor control unit 11 to the host processor 12 and the MCU 40 can subsequently be collectively referred to as "pen data PD".

[0020] Host processor 12 is a central processing unit of computer 1. Host processor 12 is configured to run various types of applications, including the computer 1's operating system and a drawing application that supports pen input, by reading a program from a storage device not shown and executing the program. The processing performed by host processor 12 includes generating a video signal VS1, which represents a desktop image of computer 1, and feeding the video signal VS1 to video board 13.

[0021] The drawing application is an application with a function for generating a line drawing, representing one or more lines or characters, as represented by the pen data PD supplied by the sensor control unit 11, and for arranging the generated line drawing on the desktop image. A line or character is the trajectory of the pen tip, represented by a sequence of coordinate data obtained while the pen pressure value is greater than 0 (that is, a value indicating that the pen tip of the electronic pen 3 is in contact with the control panel surface 1a). Furthermore, a line drawing is a curve image formed by applying a line width corresponding to the pen pressure value to an approximating curve formed by smoothly connecting the sequence of coordinate data that constitute the line.Examples of approximation curves include Bézier curves, Catmull-Rom curves, and the like. If drawing data (AppD), such as brush size and line color, is also set in the drawing application, then the drawing application is configured to generate the line drawing according to the set drawing data (AppD).

[0022] The video board 13 is a device that converts the video signal VS1, supplied by the host processor 12, into a video signal VS2 corresponding to the display panel 14. More precisely, the video board 13 contains a scaler 20, which is an integrated circuit for adjusting the resolution, frame rate, and color of the video signal VS1 to values ​​that can be supplied to the display panel 14. The video board 13 is configured to supply the display panel 14 with the video signal VS2, which is the video signal VS1 obtained after adjustment by the scaler 20.

[0023] The display panel 14 is a device that displays a video image according to the video signal VS2 on the control panel surface 1a. The type of display panel 14 is not limited to any particular type. For example, the display panel 14 can be a liquid crystal display or an organic EL display. If the display panel 14 is assumed to be a TFT (thin-film transistor) type liquid crystal display, then the display panel 14 contains a plurality of pixels, each having a thin-film transistor T and a liquid crystal element L, a plurality of gate lines GL, a plurality of signal lines SL, and a common ground line GND, as shown in Fig. 1 shown. Of these, in Fig. Figure 1 shows only one pixel, one gate line GL, one signal line SL, and the common ground line GND. The multitude of pixels are arranged in a matrix. Each gate line GL is connected to the gates of several thin-film transistors T arranged along a row. Each signal line SL is connected to the sources of several thin-film transistors T arranged along a column.

[0024] Display panel 14 performs a process to control the individual pixels line by line. More precisely, display panel 14 uses the video signal VS2 to determine the potentials to be applied to the liquid crystal elements L of the respective pixels in a row to be controlled, and applies these potentials to the respective signal lines SL. Then, the potential of the gate line GL of the controlled row is set to high. Thus, the potentials corresponding to the video signal VS2 are applied to the respective liquid crystal elements L of the controlled row, so that an image corresponding to the video signal VS2 is displayed in the controlled row.

[0025] The display panel 14 includes a timing control unit 30. The timing control unit 30 is a circuit that controls the respective potentials of the multitude of gate lines GL based on the video signal VS2. The timing control unit 30 serves to control the timing of the application of the potentials.

[0026] The MCU 40 is a processing circuit (processor for generating a preliminary line image) that, in parallel with the host processor 12, generates a preliminary line image SI, which represents the same lines as the line image generated by the host processor 12, and superimposes the preliminary line image SI onto the video signal VS2, which has not yet been supplied to the timing control unit 30. The MCU 40 is configured to generate the preliminary line image SI based on a sequence of pen data PD supplied by the sensor control unit 11.

[0027] The preliminary line drawing SI can be an image with a completely identical appearance to the line drawing generated by the host processor 12, or it can be an image that does not have a completely identical appearance. In the first case, the MCU 40 receives the drawing data AppD described above from the host processor 12 and generates the preliminary line drawing SI based on the received drawing data AppD. In the latter case, the MCU 40 may receive all or part of the drawing data AppD specified in the drawing application from the host processor 12, or it may receive only some or all of the drawing data AppD. If the MCU 40 receives all or part of the drawing data AppD from the host processor 12, it generates the preliminary line drawing SI based on the received drawing data AppD.If the MCU 40 does not receive the drawing data AppD from the host processor 12, the MCU 40 generates the preliminary line drawing SI based on predetermined settings.

[0028] In the present embodiment, the scaler 20 has the task of actually superimposing the preliminary line pattern SI, which is supplied by the MCU 40, onto the video signal VS2. This will be described below with reference to Fig. 2 described in detail.

[0029] Fig. Figure 2 is a diagram illustrating an internal configuration of the video board 13 and the display panel 14 according to the present embodiment. As shown in Fig. As illustrated in Figure 2, the video board 13 has a video memory 21 in addition to the scaler 20. The scaler 20 has a receiver unit 50, a resolution setting unit 51, a frame rate setting unit 52, a color setting unit 53, a mixer 54, a transmission unit 55, an OSD (on-screen display) memory 60, an OSD control unit 61, a switching unit 62, and a memory control unit 63. Furthermore, the timing control unit 30 has a receiver unit 31 and a gate line control unit 32.

[0030] The receiver unit 50 is a circuit that receives the video signal VS1 output by the host processor 12. The receiver unit 50 writes the received video signal VS1 to the video memory 21. The video memory 21 is a storage unit configured to store a set of frames from at least one screen of the video signal VS1.

[0031] The resolution adjustment unit 51 is a circuit that adjusts the resolution of the video signal VS1 received by the receiver unit 50 according to the resolution of the display panel 14. For example, if the resolution of the video signal VS1 is FHD (1920 × 1080) and the resolution of the display panel 14 is 4K (3840 × 2160), the resolution adjustment unit 51 performs a process to quadruple the resolution of the video signal VS1. The resolution adjustment unit 51 is configured to read the video signal VS1 to be adjusted from the video memory 21 and overwrite the video memory 21 with the video signal VS1 received after the adjustment.

[0032] The frame rate adjustment unit 52 is a circuit that adjusts the frame rate of the video signal VS1, obtained after adjustment by the resolution adjustment unit 51, to the frame rate of the display panel 14. For example, if the frame rate of the video signal VS1 is 60 fps and the frame rate of the display panel 14 is 30 fps, the frame rate adjustment unit 52 performs a process to reduce the frame rate of the video signal VS1 to half. The frame rate adjustment unit 52 is configured to read the video signal VS1 to be adjusted from the video memory 21 and overwrite the video memory 21 with the video signal VS1 obtained after the adjustment.

[0033] The color adjustment unit 53 is a circuit that adapts the color of the video signal VS1, obtained after adjustment by the frame rate adjustment unit 52, to a color scale of the display panel 14. For example, if the color scale of the video signal VS1 is sRGB and the color scale of the display panel 14 is NTSC, the color adjustment unit 53 performs processing in which the color of the video signal VS1 is reconstructed using NTSC. The color adjustment unit 53 also has a function for detecting a video type (e.g., natural image, baseball, animated cartoon, or the like) and performing color correction according to the detected type. The color adjustment unit 53 is configured to read the video signal VS1 to be adjusted from the video memory 21 and to feed the video signal VS1 obtained after adjustment to the mixer 54.

[0034] The OSD memory 60 is a storage unit that stores an image to be superimposed on the video displayed by the video signal VS1 (hereinafter also referred to as the "OSD image"). Furthermore, the OSD control unit 61 is a circuit that generates the OSD image according to a user action and writes the OSD image to the OSD memory 60. In a typical example, the OSD image is an image that is displayed when a user presses a button located on the edge of the display panel 14 to adjust the color and position of the screen. The OSD memory 60 is configured to store an image set equivalent to at least one screen.

[0035] Mixer 54 is a circuit that overlays the OSD image stored in OSD memory 60 onto the video signal VS1 supplied by the color adjustment unit 53. After processing by mixer 54, the OSD image is displayed on top of the video image represented by video signal VS1 (in a front layer).

[0036] The transmission unit 55 is a circuit that supplies the video signal VS2 to the display panel 14 as the video signal VS1 obtained after processing by the mixer 54. More precisely, the transmission unit 55 is configured to input the video signal VS2 line by line into a line buffer and to sequentially transmit the pixels of a line stored in the line buffer to the display panel 14. Furthermore, the transmission unit 55 is configured to transmit a horizontal synchronization signal (HSYNC) at one end of a line and a vertical synchronization signal (VSYNC) at one end of a screen. The horizontal synchronization signal (HSYNC) and the vertical synchronization signal (VSYNC) also form part of the video signal VS2. The receiving unit 31 in the timing control unit 30 is a circuit that receives the video signal VS2 supplied in this way and supplies the video signal VS2 to the gate line control unit 32.The gate line control unit 32 is a circuit that controls the potential of each of the multitude of gate lines GL based on the video signal VS2 supplied by the receiver unit 31.

[0037] The memory control unit 63 is a circuit that writes the preliminary line pattern SI generated by the MCU 40 to the OSD memory 60. The switching unit 62 is located between the memory control unit 63, the OSD control unit 61, and the OSD memory 60. The switching unit 62 connects the memory control unit 63 to the OSD memory 60 when the memory control unit 63 writes the preliminary line pattern SI to the OSD memory 60, and connects the OSD control unit 61 to the OSD memory 60 when the memory control unit 63 does not write the preliminary line pattern SI to the OSD memory 60. Thus, the preliminary line pattern SI is displayed on the video represented by the video signal VS1 in such a way that it takes precedence over the OSD image.

[0038] As described above, according to the present embodiment, the preliminary line pattern SI, representing the same lines as the line pattern generated by the host processor 12, is generated in parallel to the host processor 12 and superimposed onto the video signal that has not yet been fed to the timing unit 30. It is therefore possible to prevent a delay in the display of the line pattern due to a processing delay in the computer 1 (waiting for processing in the host processor 12 or the like) even without providing an overlay engine in the timing unit 30.

[0039] Furthermore, according to the computer 1 of the present embodiment, the preliminary line drawing SI can be superimposed onto the video signal VS2 using the existing mixer 54 and the existing OSD memory 60. It is therefore possible to reduce the circuit size compared to a case in which a dedicated overlay engine and a dedicated buffer are provided, as in patent document 1.

[0040] Fig. Figure 3 is a diagram illustrating a configuration of a position detection system 2 comprising a computer 1 according to a second embodiment of the present invention. As can be seen by comparing Fig. 3 with Fig. As can be seen in Figure 1, the computer 1 according to the present embodiment differs from the computer 1 according to the first embodiment in that the computer 1 according to the present embodiment has an MCU 41 instead of the MCU 40. The computer 1 according to the present embodiment is otherwise identical to the computer 1 according to the first embodiment. Accordingly, the following description focuses on the differences compared to the computer 1 according to the first embodiment.

[0041] The MCU 41 is identical to the MCU 40 according to the first embodiment with respect to the processing of the generation of the preliminary line image SI. However, the MCU 41 differs from the MCU 40 according to the first embodiment in that the MCU 41 itself superimposes the generated preliminary line image SI onto the video signal VS2, which is output by the video board 13, instead of feeding the generated preliminary line image SI to the scaler 20 and causing the scaler 20 to superimpose the generated preliminary line image SI onto the video signal VS2. As described above, the output from the video board 13 is generated pixel by pixel.Thus, the MCU 41 is configured to determine the times at which the respective pixels of the preliminary line image SI are to be superimposed, by referring to the vertical synchronization signal (VSYNC) and the horizontal synchronization signal (HSYNC) described above, and to sequentially superimpose the respective pixels of the preliminary line image SI onto the video signal VS2 at the determined times. A video signal VS3, which corresponds to the video signal VS2 after superimposition, is fed directly from the MCU 41 to the display panel 14. Upon receiving this input, the display panel 14 performs processing to display video images on the control panel surface 1a using the video signal VS3 instead of the video signal VS2.

[0042] As described above, according to the present embodiment, the preliminary line pattern SI, which represents the same lines as the line pattern generated by the host processor 12, is also generated in parallel to the host processor 12 and superimposed onto the video signal that has not yet been fed to the timing unit 30. It is therefore possible to prevent a delay in the display of the line pattern due to a processing delay with the computer 1, even without providing an overlay engine in the timing unit 30.

[0043] Furthermore, according to the computer 1 of the present embodiment, the preliminary line pattern SI can be generated and superimposed without modifying the existing video board 13 and the existing display panel 14. The implementation is therefore simpler than in the case where the timing unit is modified as in patent document 1.

[0044] Fig. Figure 4 is a diagram illustrating a configuration of a position detection system 2 comprising a computer 1 according to a third embodiment of the present invention. As can be seen by comparing Fig. 4 with Fig. As can be seen in Figure 3, the computer 1 according to the present embodiment differs from the computer 1 according to the second embodiment in that the MCU 41 is arranged in a stage preceding the video board 13, and in that the video signal VS1, generated by the host processor 12, is fed to the MCU 41 instead of the video board 13. The computer 1 according to the present embodiment is otherwise identical to the computer 1 according to the second embodiment. Accordingly, the following description focuses on the differences from the computer 1 according to the second embodiment.

[0045] The MCU 41 according to the present embodiment generates the video signal VS2 by superimposing the preliminary line pattern SI, which is generated based on the sequence of pen data PD supplied by the sensor control unit 11, onto the video signal VS1 supplied by the host processor 12. The video board 13 according to the present embodiment has the function of converting the video signal VS2 generated by the MCU 41 into a video signal VS3 corresponding to the display panel 14 and supplying the video signal VS3 obtained by this conversion to the display panel 14.

[0046] Fig. Figure 5 is a diagram illustrating an internal configuration of the video board 13 and the display panel 14 according to the present embodiment. As shown in Fig. As illustrated in Figure 5, the input signal of the video board 13 according to the present embodiment is the video signal VS2, and the output signal of the video board 13 according to the present embodiment is the video signal VS3. Furthermore, the scaler 20 according to the present embodiment does not include either the switching unit 62 or the storage control unit 63. This is because, in the present embodiment, the video signal VS2, onto which the preliminary line pattern SI is already superimposed, is input into the video board 13. Therefore, the scaler 20 does not need to perform the processing of superimposing the preliminary line pattern SI onto the video signal.

[0047] As described above, according to the present embodiment, the preliminary line pattern SI, which represents the same lines as the line pattern generated by the host processor 12, is also generated in parallel to the host processor 12 and superimposed onto the video signal that has not yet been fed to the timing unit 30. It is therefore possible to prevent a delay in the display of the line pattern due to a processing delay in the computer 1, even without providing an overlay engine in the timing unit 30.

[0048] Furthermore, according to the present embodiment, the preliminary line pattern SI can also be generated and superimposed on the computer 1 without modifying the existing video board 13 and the existing display panel 14. The implementation is therefore simpler than in the case where the timing unit is modified as described in patent document 1.

[0049] Fig. Figure 6 is a diagram illustrating a configuration of a position detection system 2 comprising a computer 1 according to a fourth embodiment of the present invention. As can be seen by comparing Fig. 6 with Fig. As can be seen in Figure 1, the computer 1 according to the present embodiment differs from the computer 1 according to the first embodiment in that the computer 1 according to the present embodiment does not have the sensor control unit 11, but instead has an MCU 42 instead of the MCU 40. The computer 1 according to the present embodiment is otherwise identical to the computer 1 according to the first embodiment. Accordingly, the following description focuses on the differences compared to the computer 1 according to the first embodiment.

[0050] The MCU 42 is provided in the scaler 20. The MCU 42 performs the function of the sensor control unit 11 in the first embodiment. As with the MCU 40 in the first embodiment, the MCU 42 also has the function of generating a preliminary line pattern SI in parallel with the host processor 12, which represents the same lines as the line pattern generated by the host processor 12, and superimposing the preliminary line pattern SI onto the video signal VS2, which has not yet been supplied to the timing control unit 30.

[0051] Regarding the first task, the MCU 42, via sensor 10, performs the processing to transmit the uplink signal US to the electronic pin 3 and to receive the pin signal PS, which is sent by the electronic pin 3, as a reflection signal in response to the uplink signal US. Furthermore, the MCU 42 performs processing to derive or obtain the pin data PD from the received pin signal PS and to supply the pin data PD to the host processor 12. The host processor 12 then generates a line drawing based on the supplied pin data PD.

[0052] Fig. Figure 7 is a diagram illustrating an internal configuration of the video board 13 and the display panel 14 according to the present embodiment. As can be seen by comparing Fig. 7 with Fig. As can be seen in Figure 2, the video board 13 according to the present embodiment differs from the video board 13 according to the first embodiment in that the video board 13 according to the present embodiment does not have either the switching unit 62 or the storage control unit 63, and in that the video board 13 according to the present embodiment has an analog-to-digital converter unit 70, an MCU 42, and a mixer 74. The video board 13 according to the present embodiment is otherwise identical to the video board 13 according to the first embodiment. The display panel 14 has the same configuration as the display panel 14 according to the first embodiment.

[0053] The MCU 42 comprises a pen signal processing unit 71, a renderer 72, and an image memory 73. The A / D converter unit 70 is arranged in a stage preceding the pen signal processing unit 71. The A / D converter unit 70 is responsible for converting the pen signal PS, received in each of the loop coils in the sensor 10, into a digital signal and supplying the digital signal to the pen signal processing unit 71.

[0054] As with the sensor control unit 11 in the first embodiment, the pen signal processing unit 71 performs the processing to transmit the uplink signal US via the sensor 10 to the electronic pen 3 and to receive the pen signal PS, which is sent by the electronic pen 3, as a reflection signal in response to the uplink signal US. Furthermore, the pen signal processing unit 71 performs the processing to derive or obtain the pen data PD from the received pen signal PS and to supply the pen data PD to the host processor 12. The host processor 12 generates a line drawing based on the pen data PD thus supplied.

[0055] The pen signal processing unit 71 also supplies the derived or received pen data PD to the renderer 72. In addition to the pen data PD, the drawing data AppD from the host processor 12 is also supplied to the renderer 72. The renderer 72 generates the preliminary line drawing SI based on the pen data PD and the supplied drawing data AppD, and writes the generated preliminary line drawing SI to the image memory 73. As with the OSD memory 60, the image memory 73 is a storage unit configured to store a set of images from at least one screen.

[0056] Mixer 74 is a circuit that overlays the preliminary line pattern SI, stored in the image memory 73, onto the video signal VS1 output by the color adjustment unit 53. After processing by mixer 74, the preliminary line pattern SI is displayed on the video image represented by the video signal VS1 (in a front layer). Mixer 54 is located in a stage downstream of mixer 74. Thus, when an OSD image is to be displayed, the OSD image is shown in a layer in front of the preliminary line pattern SI.

[0057] As described above, according to the present embodiment, the preliminary line pattern SI, which represents the same lines as the line pattern generated by the host processor 12, is also generated in parallel to the host processor 12 and superimposed onto the video signal that has not yet been fed to the timing unit 30. It is therefore possible to prevent a delay in the display of the line pattern due to a processing delay in the computer 1, even without providing an overlay engine in the timing unit 30.

[0058] Furthermore, according to the present embodiment, the OSD image can also be displayed on computer 1 when the preliminary SI line image is displayed. Additionally, the OSD image can be displayed in a plane in front of the preliminary SI line image.

[0059] Furthermore, according to the computer 1 in the present embodiment, the preliminary line pattern SI is superimposed on the video signal VS1 in a stage that is connected downstream of the color adjustment unit 53. Thus, as with the OSD image, the preliminary line pattern SI can be displayed as a kind of CG in a state in which it is not affected by the color correction of the color adjustment unit 53.

[0060] Fig. Figure 8 is a diagram illustrating a configuration of a position detection system 2 comprising a computer 1 according to a fifth embodiment of the present invention. As can be seen by comparing Fig. 8 with Fig. As can be seen in Figure 6, the computer 1 according to the present embodiment differs from the computer 1 according to the first embodiment in that the computer 1 according to the present embodiment has an MCU 43 instead of the MCU 40. Otherwise, the computer 1 according to the present embodiment is identical to the computer 1 according to the first embodiment. Accordingly, the following description focuses on the differences compared to the computer 1 according to the first embodiment.

[0061] As with the MCU 42 described in the fourth embodiment, the MCU 43 is provided in the scaler 20. The MCU 43 has the task of generating a preliminary line pattern SI in parallel with the host processor 12, which represents the same lines as the line pattern generated by the host processor 12, and of superimposing the preliminary line pattern SI onto the video signal VS2, which has not yet been supplied to the timing control unit 30. On the other hand, unlike the MCU 42 described in the fourth embodiment, the MCU 43 does not have the task of the sensor control unit 11.

[0062] Fig. Figure 9 is a diagram illustrating an internal configuration of the video board 13 and the display panel 14 according to the present embodiment. As can be seen by comparing Fig. 9 with Fig.As can be seen in Figure 2, the video board 13 according to the present embodiment differs from the video board 13 according to the first embodiment in that the video board 13 according to the present embodiment does not have either the switching unit 62 or the storage control unit 63, and in that the video board 13 according to the present embodiment has an MCU 43 and a mixer 83. The video board 13 according to the present embodiment is otherwise identical to the video board 13 according to the first embodiment. The display panel 14 has the same configuration as the display panel 14 according to the first embodiment.

[0063] The MCU 43 comprises a calibration processing unit 80, a renderer 81, and an image memory 82. The pen data PD from the sensor control unit 11 is sequentially fed to the calibration processing unit 80. The calibration processing unit 80 is configured to convert the coordinate data contained in the supplied pen data PD into coordinate data based on the coordinate system of the display panel 14 and to supply the pen data PD, including the coordinate data obtained after the conversion, to the renderer 81.

[0064] The functions and operation of the renderer 81, the image memory 82, and the mixer 83 are identical to the functions and operation of the renderer 72, the image memory 73, and the mixer 74 described in the fourth embodiment. Thus, in the present embodiment as well, the preliminary line drawing SI is displayed in a plane in front of the video image represented by the video signal VS1 and behind the OSD image.

[0065] As described above, according to the present embodiment, a preliminary line pattern SI, representing the same lines as the line pattern generated by the host processor 12, is generated in parallel to the host processor 12 and superimposed onto the video signal that has not yet been fed to the timing unit 30. It is therefore possible to prevent a delay in the display of the line pattern due to a processing delay in the computer 1, even without providing an overlay engine in the timing unit 30.

[0066] Furthermore, according to the present embodiment, as in the fourth embodiment, the OSD image can also be displayed on computer 1 when the preliminary SI line image is displayed. Furthermore, the OSD image can be displayed in a plane in front of the preliminary SI line image.

[0067] Furthermore, according to the computer 1 in the present embodiment, as in the fourth embodiment, the preliminary line pattern SI is superimposed on the video signal VS1 in a stage that is connected downstream of the color adjustment unit 53. Thus, as with the OSD image, the preliminary line pattern SI can be displayed as a kind of CG in a state in which it is not affected by the color correction of the color adjustment unit 53.

[0068] Preferred embodiments of the present invention have been described above. However, the present invention is not limited to such embodiments, and the present invention can of course be modified in various ways without departing from the essence of the present invention.

[0069] In the preceding embodiments, an example was described of a case in which the processing from generation to display of the line drawing is completed in computer 1. However, the present invention is also applicable to cases in which, when a remote connection to another computer is established using an online conferencing app or the like, the line drawing generated by the host processor 12 is transmitted to the other computer, and the line drawing is also included in an image transmitted from the other computer to computer 1. That is, an even greater delay than in the case in which the processing from generation to display of the line drawing is completed in computer 1 occurs before the line drawing generated in computer 1 is displayed in the image transmitted from the other computer to computer 1.However, it is possible to prevent a delay in the display of the line drawing even in such a case by displaying the preliminary line drawing in the image that is transferred from the other computer to computer 1 through the processing of the present invention. REFERENCE MARK LIST 1 computer 1a Control panel interface 2 Position detection system 3 Electronic pen 10 Sensor 11 Sensor control unit 12 Host processor 13 Video board 14 Scoreboard 20 scalers 21 video memory 30 Time control unit 31, 50 receiver unit 32 Gate Line Control Unit 51 Resolution setting unit 52 frame rate setting unit 53 Color setting unit 54, 74, 83 mixers 55 transmission unit 60 OSD memory 61 OSD control unit 62 Switching unit 63 Storage control unit 70 AD converter unit 71 Pen signal processing unit 72, 81 Renderer 73, 82 image storage 80 Matching processing unit AppD drawing data GL Gate line GND common grounding conductor L Liquid crystal cell PD Pen Data PS pen signal SI Preliminary Line Sketch SL signal line T thin-film transistor US Uplink Signal VS1 to VS3 video signal QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 9721365 B

[0005] JP 2008 - 233869 A

[0005]

Claims

[1] Computer, comprising: a host processor configured to generate a stroke image representing strokes represented by a sequence of coordinate data each representing a position of a stylus on a touch surface, and to generate a video signal representing the generated stroke image; a timing control unit configured to control a potential of each of a plurality of gate lines arranged in a display based on the video signal; and a processor for generating a preliminary line image, which is arranged to generate, in parallel with the host processor, a preliminary line image representing the same strokes as the strokes represented by the line image, wherein the preliminary line image is superimposed on the video signal which has not yet been supplied to the timing unit. [2] The computer of claim 1, further comprising: a scaler configured to convert the video signal output by the host processor into a signal corresponding to the display and to supply the video signal obtained after the conversion to the timing control unit, the scaler comprising: an on-screen display memory configured to store an on-screen display image to be superimposed on the video signal, and a mixer configured to superimpose the on-screen display image stored in the on-screen display memory onto the video signal, and the processor is configured to generate a preliminary line image and to write the generated preliminary line image into the on-screen display memory. [3] The computer of claim 2, further comprising: a sensor control unit configured to derive the sequence of coordinate data from a pen signal received from the pen and to output the sequence of coordinate data to both the host processor and the processor for generating a preliminary line image, wherein the processor for generating a preliminary line image is configured to generate the preliminary line image based on the sequence of coordinate data supplied by the sensor control unit. [4] The computer of claim 1, further comprising: a scaler configured to convert the video signal output by the host processor into a signal corresponding to the display and to output the video signal obtained after the conversion to the processor for generating a preliminary line image, wherein the processor is configured to generate a preliminary line image, to superimpose the generated preliminary line image onto the video signal output by the scaler, and to supply the video signal obtained after the superimposition to the timing unit. [5] The computer of claim 4, further comprising: a sensor control unit configured to derive the sequence of coordinate data from a pen signal received from the pen and to output the sequence of coordinate data to both the host processor and the processor for generating a preliminary line image, wherein the processor for generating a preliminary line image is configured to generate the preliminary line image based on the sequence of coordinate data supplied by the sensor control unit. [6] The computer of claim 1, further comprising: a scaler configured to convert the video signal output from the host processor into a signal corresponding to the display, superimpose the preliminary line image onto the signal obtained after the conversion, and supply the video signal obtained after the superimposition to the timing control unit. [7] The computer of claim 6, wherein the processor for generating a preliminary line image is arranged to derive the sequence of coordinate data from a pen signal received from the pen, output the derived sequence of coordinate data to the host processor, and generate the preliminary line image from the derived sequence of coordinate data. [8] The computer of claim 6, further comprising: a sensor control unit configured to derive the sequence of coordinate data from a pen signal received from the pen and to output the sequence of coordinate data to both the host processor and the processor for generating a preliminary line image, wherein the processor for generating a preliminary line image is configured to generate the preliminary line image based on the sequence of coordinate data supplied by the sensor control unit.

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