Tunable hybrid broadband LNA architecture

Abstract

Circuits and methods for an LNA that enable selection of a first mode providing high gain with wide output impedance matching and a second mode providing wideband output impedance matching with improved NF and linearity at moderate gain. Some embodiments allow multiple intermediate modes to enable selection of gain versus linearity and NF.One embodiment includes a matching network having an input terminal configured to be connected to an amplified signal terminal of a gain core and an output terminal, the matching network comprising a first inductor connected between the input terminal and a first node, a second inductor connected to the first node, a boosted gain branch connected between the input terminal and the output terminal, and a non-boosting branch connected between the first node and the output terminal, the boosted gain branch being enabled in a first mode and the non-boosting branch being enabled in a second mode.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Patent Application No. 17 / 855,418, filed June 30, 2022, the contents of which are incorporated herein by reference in their entirety. BACKGROUND(1) Technical field

[0002] The invention relates to electronic circuits, in particular to high-frequency amplifier circuits. (2) Background

[0003] Many modern electronic systems contain radio frequency (RF) receivers; examples include mobile phones, personal computers, tablet computers, wireless network components, televisions, cable system set-top boxes, and radar systems. Many RF receivers are connected to RF transmitters in the form of transceivers, which are often quite complex two-way radio devices. In some cases, RF transceivers can transmit and receive on multiple frequencies in multiple frequency bands.

[0004] Amplifiers are a common component in RF transmitters, receivers, and transceivers and are often used to amplify the energy of transmitted RF signals and provide low-noise amplification of received RF signals. For many RF systems, particularly those requiring low power and / or portability (e.g., mobile phones, Wi-Fi-enabled computers, cameras, and other devices), it has become common practice to use complementary metal-oxide-semiconductor (CMOS) for the fabrication of low-cost, low-power integrated circuits (ICs). CMOS devices include bulk CMOS, silicon-on-insulator (SOI) CMOS, and silicon-on-sapphire (SOS) CMOS (SOS is a type of SOI fabrication technology).

[0005] Reception of RF signals in many environments requires a high-quality low-noise amplifier (LNA) as part of a chain of circuits in an RF front-end receiver (RFFE) or transceiver. Key desired properties of an LNA include high gain with low noise, wide bandwidth, good linearity, and good input and output impedance matching. However, generally, not all of these factors can be optimized simultaneously, so trade-offs among these properties must be made during LNA design.

[0006] Five important design parameters for LNAs are gain, noise figure (NF), input-referred third intercept point (IIP3), output reflection coefficient, and input reflection coefficient. NF is a measure of the signal-to-noise ratio (SNR) degradation caused by components in a signal chain, with lower values ​​indicating better performance. IIP3 is a measure of the amplifier's linearity, with higher values ​​indicating better performance. In general, NF requirements are more stringent in high-gain modes than in low-gain modes, while IIP3 has more stringent requirements in low-gain modes than in high-gain modes. The output reflection coefficient is the scattering parameter S 22(or "S-parameter") and is an indication of the output impedance matching, with lower (more negative when evaluated logarithmically) numbers indicating better impedance matching (lower output attenuation). The input reflection coefficient is the S-parameter S 11 and indicates how much energy is reflected back to the antenna, with lower (more negative when evaluated logarithmically) numbers indicating better performance (lower input attenuation).

[0007] The increase in the frequency of RF communication bands and channels, as well as the continuous growth in the number of bands and channels in use, has pushed current LNA architectures to their limits. For example, it is difficult and sometimes impossible to meet the stringent requirements for gain, percentage bandwidth, linearity, and output impedance matching with a conventional LNA architecture for some of the new 5G cellular bands, particularly in the NR bands from 3 to 6 GHz, the upcoming 7-24 GHz bands, and the millimeter wave range (e.g., 24.25 GHz to 52.6 GHz).

[0008] Accordingly, there is a need for an LNA architecture that overcomes the limitations of conventional LNA architectures. SUMMARY

[0009] The present invention includes circuits and methods for an LNA that enable selection of a first operating mode providing high gain with wide output impedance matching with tradeoffs in current, NF, and linearity, and a second operating mode providing broadband output impedance matching with improved NF and linearity at lower current and moderate gain. Some embodiments allow multiple intermediate operating modes to enable selection of gain versus linearity and NF characteristics. The inventive circuits and methods can also be applied to other types of amplifiers, such as power amplifiers.

[0010] An embodiment of the invention includes a tunable hybrid broadband output impedance matching network having an input terminal configured to be connected to an amplified signal terminal of a gain core and an output terminal configured to be connected to a radio frequency (RF) output terminal, the tunable hybrid broadband output impedance matching network comprising: a first inductor connected between the input terminal and a first node; a second inductor connected to the first node and configured to be connected to a power supply; an amplified gain branch connected between the input terminal and the output terminal; and a non-amplified branch connected between the first node and the output terminal;wherein the boosted gain branch is activated in a first operating mode and the non-boosting branch is activated in a second operating mode;

[0011] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the following description. Further features, objects, and advantages of the invention will become apparent from the description and drawings, as well as from the claims. DESCRIPTION OF THE DRAWINGS Fig. Figure 1A is a simplified schematic diagram of a first embodiment of a low-noise amplifier circuit with a tunable hybrid broadband output impedance matching network. Fig. Figure 1B is a schematic diagram of one embodiment of an improved IIM circuit. Fig. Figure 1C is a schematic diagram of one embodiment of an input-matching feedback circuit. Fig. Figure 1D is a simplified schematic diagram of one embodiment of an output matching DeQing circuit. Fig. Figure 1E is a schematic diagram of one embodiment of a selectable degeneration circuit. Fig. Figure 2A is a graph comparing gain as a function of frequency for a modeled implementation of the Fig. LNA circuit shown in Figure 1A. Fig. Figure 2B is a graph comparing the NF as a function of frequency for a modeled implementation of the Fig. LNA circuit shown in Figure 1A. Fig. Figure 2C is a graph comparing input return loss as a function of frequency for a modeled implementation of the Fig. LNA circuit shown in Figure 1A. Fig. 2D is a graph comparing the output return loss as a function of frequency for a modeled implementation of the Fig.LNA circuit shown in Figure 1A. Fig. Figure 3 is a simplified schematic diagram of a second embodiment of a low-noise amplifier circuit with a tunable hybrid broadband output impedance matching network. Fig. Figure 4 is a simplified schematic diagram of a third embodiment of a low-noise amplifier circuit with a tunable hybrid broadband output impedance matching network. Fig. 5 is a plan view of a substrate, which may be, for example, a printed circuit board or a chip module substrate (e.g., a thin-film tile). Fig. 6 shows an exemplary prior art wireless communication environment that includes various wireless communication systems and may include one or more mobile wireless devices. Fig.7 is a block diagram of a transceiver that could be used in a wireless device, such as a cellular phone, and in which an embodiment of the present invention may be advantageously employed to improve performance. Fig. 8 is a process flow diagram showing a method for achieving different gain modes for a high frequency amplifier having an amplifier core with an amplified signal terminal.

[0012] Like reference numbers and designations in the different drawings indicate like elements unless the context requires otherwise. DETAILED DESCRIPTION

[0013] The present invention includes circuits and methods for an LNA that enable selection of a first operating mode providing high gain with wide output impedance matching, with tradeoffs in current, NF, and linearity, and a second operating mode providing broadband output impedance matching with improved NF and linearity at lower current and moderate gain. Some embodiments allow multiple intermediate operating modes to enable selection of gain versus linearity and NF characteristics. The inventive circuits and methods can also be applied to other types of amplifiers, such as power amplifiers. Bandwidth terms

[0014] For the purposes of this disclosure, “narrowband”, “wideband”, and “ultra-wideband” may be characterized as a percentage bandwidth equal to: (stop frequency f STOPminus starting frequency f START ) divided by the center frequency f CENTER a volume or (f STOP - f START ) / f CENTER (expressed in percent), where f CENTER = (f STOP + f( START) ) / 2. TABLE 1 below provides typical guidelines (not strict definitions) for characterizing typical percentage bandwidths. TABLE 1 Nominal band name % bandwidth range narrowband <7,5% Extended narrowband 7,5% ~ 15% Broadband 15% ~ 25% Ultra-broadband > 25%

[0015] TABLE 2 provides examples of common mobile bands and their classification as broadband or ultra-wideband using the guidelines from TABLE 1. TABLE 2 Typical application f START (GHz) f STOP (GHz) f CENTER (GHz) % Bandwidth Broadband (N77) 3,3 4,2 3,75 24,00% Ultra Wideband (NR-U) 5,125 7,125 6,125 32,65% Ultra Wideband (UWB) 6,2 9 7,6 36,84% First embodiment

[0016] Fig.1A is a simplified schematic diagram of a first embodiment of a low-noise amplifier circuit 100 having a tunable hybrid wideband output impedance matching network 102. In the illustrated example, the LNA circuit 100 includes an amplifier core 104 comprising a stack of two series-connected FETs M CS , M CG in a cascode arrangement. An RF IN applied RF input signal can be passed through an input impedance matching circuit (IIM) 106 and connected to the control gate of the common-source FET M CS which can be considered as the input terminal INT of the amplifier core 104.

[0017] The source of the common source FET M CS is usually connected to a reference potential, e.g., circuit ground, via a degeneration circuit 108. Accordingly, the source of the common-source FET M CSbe considered as the degeneration terminal DT of the gain core 104.

[0018] The source of the common gate FET M CG is connected to the drain of the common-source FET M CS The drain of the common-gate FET M CG provides an amplified RF output signal at a terminal AST of the amplifier core 104, which can be considered as an amplified signal terminal.

[0019] A bias circuit 110 is configured to provide a suitable bias voltage CG_V BIAS to the common gate FET M CG and a suitable preload CS_V BIAS to the common-source FET M CS in a known manner. Note that one or both bias voltages CG_V BIAS and CS_V BIAS in some applications can be zero volts (ie no additional voltage), and in some applications CG_V BIASa reference voltage, such as an AC ground. Other common circuit elements that may be included in some applications, such as DC blocking capacitors, are omitted for clarity.

[0020] The tunable hybrid wideband output impedance matching network (“THWOIM network”) 102 has an IN terminal configured to be connected to the amplified signal terminal AST of the amplifier core 104 and an OUT terminal configured to be connected to an RF output terminal RF OUT The amplified output of the amplifier core 104 is connected via the THWOIM network 102 to the RF output terminal RF OUT connected to a typical load in the form of a resistor R L The value of R L is typically 50 ohms in many modern RF circuits.

[0021] The THWOIM network 102 comprises a first inductor L1 connected in series with a second inductor L2 at a node X, wherein the inductor pair L1, L2 is connected to the terminal IN and configured to be connected to a power supply V DD to be connected. The THWOIM network 102 in the example shown comprises two branches.

[0022] A first branch comprises a first DC blocking capacitor C BLK1, which is connected between the amplified signal terminal AST of the amplifier core 104 and a first terminal of a switch S1. A second terminal of the switch S1 is connected to the control gate of a second-stage FET M SF which provides a second amplification stage in the form of a voltage-buffered source-follower circuit. In the example shown, the FET M SF the second stage a conduction channel (drain to source) that is connected between V DDand a third inductor L3, which in turn is connected to a reference potential, e.g., the circuit ground. The source of the second-stage FET M SF is connected via a second DC blocking capacitor C BLK2 connected to a node Y. A switch S2 is connected between node Y and the OUT terminal. A shunt switch S3 is connected between a reference potential, such as circuit ground, and node Y. The switches S1 - S3 can be implemented (for example only) as FETs, in particular MOSFETS.

[0023] A second branch contains a third capacitor C SER , which is connected between the node X and a switch S4. The third capacitor C SERcan be used as part of the output matching network. A switch S5 is connected between switch S4 and the OUT terminal. A shunt switch S6 is connected between a reference potential, such as circuit ground, and a node Z between switches S4 and S5. Switches S4 - S6 can be implemented (for example only) as FETs, particularly MOSFETs.

[0024] To activate the first mode of operation, which can be referred to as high gain or boosted gain mode, the first branch is placed in an active state, in which switches S1, S2, and S6 are closed and switches S3, S4, and S5 are open. The combination of inductors L1 and L2 acts as a load for the inductively degenerate first stage (i.e., gain core 104) of the entire LNA 100. Closing shunt switch S6 provides a path to ground to avoid loading the RF OUToutput by the tapped load of the first stage (i.e., L1+L2, tapped at node X). The AC component of the amplified signal from the amplified signal terminal AST is amplified by the FET M SF the second stage, the AC component of this amplified signal being fed to the RF terminal OUT is provided. Accordingly, the first branch can be selectively activated as a branch with enhanced gain.

[0025] The first operating mode offers high gain due to two gain stages with wide output impedance matching. The disadvantages of this high gain are higher DC current, NF, and linearity compared to the second operating mode.

[0026] To activate the second operating mode, which can be described as high-power, moderate-gain mode, the second branch is set to an active state, in which switches S3, S4, and S5 are set to a CLOSED state and switches S1, S2, and S6 are set to an OPEN state. Closing shunt switch S3 provides a path to ground to avoid loading the RF OUT -Output through the source follower FET of the second stage M SF of the first (high-gain) branch. In this mode, the inductor L1 is located between the drain of the common-gate FET cascode device M CG and the capacitor C SER , and the AC component of the amplified signal from the amplified signal terminal AST is connected without further amplification to the RF terminal OUT Accordingly, the second branch can be selectively activated as a non-reinforcement branch.

[0027] The inductive load L2 extends the output bandwidth of the LNA 100 and provides higher gain compared to a conventional single-stage cascode LNA due to the increased impedance at the drain of the common-gate FET cascode device M CG .

[0028] Inductors L1 and L2 are typically tuned to provide wide output impedance matching in both operating modes, while ensuring that their summation still provides a flat gain response for the high-gain operating mode. For the high-power mode, additional tuning with capacitor C SER can be achieved. Optional circuit elements

[0029] A. Stack of FETs. In some embodiments, to overcome a relatively low breakdown voltage per CMOS FET, multiple common-gate FETs may be arranged in a FET stack 120 between the drain of the lowest common-gate FET M CGand the Amplified Signal terminal AST in series, as shown in Fig. 1A—that is, the gain core 104 may have multiple common-gate FETs connected in series in a cascode configuration. The amplified signal terminal AST would then be located at the drain of the topmost common-gate FET in the gain core 104.

[0030] B. Improved input impedance matching circuit. While for the IIM circuit 106 in the embodiment of Fig. 1A can be used in a number of circuits, it may be useful to use an improved circuit to match the input impedance. Fig. For example, Figure 1B is a schematic diagram of one embodiment of an improved IIM circuit 106. The improved IIM circuit 106 includes a series inductor L SER , which is connected between the RF connector INand the input terminal INT of the amplifier core 104, and a shunt inductor L SH , which is between L SER and a reference potential (e.g. circuit ground). In other embodiments, L SH with L SER on the INT port side of L SER connected and not on the side of the RF IN -connection (note that changing the order of the connections may result in different compromises in input impedance matching bandwidth and noise figure). Both L SER as well as L SH may, as shown, be adjustable components or have fixed values. In embodiments including a degeneration circuit 108, the series shunt inductors L SER , L SH the extended IIM circuit 106 together with the common-source FET M connected to the degeneration circuit 108 CSa dual-terminal bandpass filter that increases the input bandwidth of an LNA circuit 100.

[0031] C. Input Matching Feedback Circuit. Some embodiments may include an input matching (IM) feedback circuit 122. The IM feedback circuit 122 is Fig. 1A as connected between the input terminal INT and the amplified signal terminal AST. More generally, the IM feedback circuit 122 may be connected to a feedback node in the output signal path of the amplifier core 104, which may be the drain of any FET in the amplifier core 104. The choice of the feedback node for connection to the IM feedback circuit 122 may be based, for example, on different desired feedback strengths and different desired input impedances.

[0032] Fig.Figure 1C is a schematic diagram of one embodiment of an input matching feedback circuit 122. The IM feedback circuit 122 includes, in the example shown, a DC blocking capacitor C F1 , which is connected to a switch S F1 connected in series, which in turn is connected to a resistor R F1 connected in series. In some embodiments, C F1 and / or R Fl be adjustable as shown or have fixed values. In other embodiments, the IM feedback circuit 122 may include one or more parallel switches S F11 , ..., S F1n (general S F1x ), which in turn are connected to corresponding parallel resistors R F11 , ..., R F1 (general R F1x are connected in series. With n parallel branches of switches / resistors, the tunability of the resistors R F1x equals 2 n(the total number of switching combinations). Note that the values ​​of the resistors R F1x do not have to be identical. The IM feedback circuit 122 can be activated by opening all feedback switches S F1x be deactivated.

[0033] In other embodiments, the capacitor C F1 , the set of one or more switches S F1x and the set of one or more resistors R F1x be connected in series in any order. In still other embodiments, the switches S F1x be omitted, whereby the set of one or more resistors R F1x is permanently connected between the input terminal INT and a feedback node in the output signal path of the amplifier core 104.

[0034] In different amplification modes, the presence of one or more resistors R F1xin the circuit a reduction in the Q factor of the input impedance matching, thereby increasing the bandwidth of the improved LNA circuit 100 at the expense of gain and NF.

[0035] An advantage of using a variable or multi-stage IM feedback circuit 122 is that multiple resistance values ​​allow for multiple gain modes. For example, LNAs in mobile RF receiving devices may require multiple gain modes depending on the range of input signal strength at the receiver. In addition, by using variable or multi-stage feedback resistors, R F1x the need for an output attenuator (as is common with conventional receiver LNAs) is eliminated.

[0036] Further information regarding IM feedback circuit 122 may be found in U.S. Patent Application No. 17 / 337,227, entitled “Wideband Multi Gain LNA Architecture,” filed June 2, 2021, which is assigned to the assignee of the present invention and is incorporated herein by reference.

[0037] D. Output Matching DeQing Circuit. Some embodiments may include an output matching (OM) DeQing circuit 124. The OM DeQing circuit 124 is shown in Fig. 1A as coupling between the amplified signal terminal AST and the control gate of the common-gate FET M CG, which in turn is connected to AC ground 112 via a blocking capacitor C. The OM deQing circuit 124 serves to lower the transformation Q of the THWOIM network 102. By lowering the transformation Q, the output impedance matching bandwidth of the LNA circuit 100 is expanded. This architecture demonstrates a better gain-to-bandwidth ratio compared to other known circuits in a variety of applications.

[0038] Fig. Figure 1D is a simplified schematic diagram of one embodiment of an output matching DeQing circuit 124. The OM DeQing circuit 124 includes, in the illustrated example, a DC blocking capacitor C F2 , which is connected to a switch S F2 connected in series, which in turn is connected to a resistor R F2 connected in series. In some embodiments, C F2 and / or R F2adjustable, as shown, or have fixed values. In other embodiments, the OM DeQing circuit 124 may include one or more parallel switches S F21 , ..., S F2n (general S F2x ), which in turn are connected to corresponding parallel resistors R F21 , ..., R F2n (general R F2x ) are connected in series. With n parallel switch / resistor branches, the tunability of the resistors R F2x equals 2 n (the total number of switching combinations). Note that the values ​​of the resistors R F2x do not have to be identical. The OM DeQing circuit 124 can be activated by opening all feedback switches S F2x be deactivated.

[0039] In other embodiments, the capacitor C F2 , the set of one or more switches S F2x and the set of one or more resistors R F2xbe connected in series in any order. In still other embodiments, the switches S F2x be omitted, whereby the set of one or more resistors R F2x permanently between the amplified signal terminal AST and the control gate of the common gate FET M CG is switched on.

[0040] In different amplification modes, the presence of one or more resistors R F2x in the circuit, a reduction in the Q factor of the output impedance matching, thereby increasing the bandwidth of the improved LNA circuit 100 at the expense of gain and NF. Switching a single resistor R F2in the circuit or out of the circuit, for example, offers two operating modes, the first mode with a wider bandwidth of output impedance matching and a second mode with a narrower bandwidth of output impedance matching, but with a higher gain than the first mode. As mentioned above, the variable setting of R F2 or activating more than one resistance value creates additional operating modes.

[0041] More precisely, when the switch S F2 CLOSED, R F2 the amplified signal terminal AST with the control gate of the common-gate FET M CG , whereby R F2 parallel to the equivalent resistance R D the circuit of the amplifier core 104. The presence of R F2 in the circuit reduces the impedance Z DRAINof the amplifier core 104, as seen at terminal AST, and reduces the transformation Q of the THWOIM network 102, where Q is approximately equal to the real part of Z DRAIN divided by the load resistance R L or Re(Z DRAIN ) / R L Accordingly, the transformation Q is lowered, thereby expanding the output impedance matching bandwidth of the LNA circuit 100. This architecture demonstrates a better gain-bandwidth trade-off in a variety of applications compared to other known circuits.

[0042] Conversely, if the switch S F2 OPEN is, R F2 with respect to R D in the equivalent circuit is out of order, and the transformation Q of the THWOIM network 102 is not reduced.

[0043] An advantage of using a variable or multi-stage OM DeQing circuit 124 is that multiple resistor values ​​enable multiple gain modes. For example, LNAs in mobile RF receiving devices may require multiple gain modes depending on the range of input signal strength at the receiver. Furthermore, enabling multiple gain modes can be achieved by using variable or multi-stage DeQing resistors R F2x eliminate the need for an output attenuator (common in conventional receiver LNAs).

[0044] E. Circuit for degeneration. The Fig. The degeneration circuit 108 shown in Figure 1A may simply consist of a fixed inductor. However, to increase flexibility, additional elements may be incorporated into the degeneration circuit 108. Fig.For example, Figure 1E is a schematic diagram of one embodiment of an adjustable degeneration circuit 108. The degeneration circuit 108 may include an adjustable degeneration inductor L DEG , e.g. an inductor of an integrated circuit with multiple terminals. An adjustable inductor L DEG can be used to improve linearity in low-gain modes. For example, a smaller value for the inductor L DEG in higher gain modes and a larger value for the inductor L DEG used in lower gain modes. Some embodiments of the degeneration circuit 108 may include a bypass switch S WBP which is parallel to the degeneration inductance L DEG Accordingly, the degeneration circuit 108 of Fig.1E Operating modes selected by suitable control circuits (not shown) where no inductor is present or where a fixed or variable inductance is present. Performance examples

[0045] Fig. Figure 2A is a graph comparing gain as a function of frequency for a modeled implementation of the Fig.1A. Graph line 202a shows the response for the first, or high-gain mode, in which the first branch of the THWOIM network 102 is active. Graph line 204a shows the response for the second, or high-power, moderate-gain mode, in which the second branch of the THWOIM network 102 is active. In this example, the high-gain mode achieves a gain of more than 21 dB over a bandwidth of approximately 900 MHz, while the high-power, moderate-gain mode achieves a gain of approximately 18.5 dB over nearly the same bandwidth.

[0046] Fig. Figure 2B is a graph comparing the NF as a function of frequency for a modeled implementation of the Fig.1A. Plot line 202b shows the response for the high-gain mode, and plot line 204b shows the response for the high-power, moderate-gain mode. In this example, plot line 204b shows better audio performance for the high-power, moderate-gain mode, but the audio of the high-gain mode (about 0.9 to about 1 dB across the entire frequency range) is perfectly adequate for many applications.

[0047] Fig. Figure 2C is a graph comparing input return loss as a function of frequency for a modeled implementation of the Fig.1A. Plot line 202c shows the response for the high-gain mode, and plot line 204c shows the response for the high-power, moderate-gain mode. In this example, plot line 204c shows better input return loss for the high-power, moderate-gain mode, but the input return loss of the high-gain mode is perfectly adequate for many applications.

[0048] Fig. 2D is a graph comparing the output return loss as a function of frequency for a modeled implementation of the Fig.1A. Plot line 202d shows the response for the high-power, moderate-gain mode, and plot line 204d shows the response for the high-power, moderate-gain mode. In this example, plot 202d shows better output return loss for the high-gain mode, but the output return loss of the high-power, moderate-gain mode is perfectly adequate for many applications.

[0049] Note that for all diagrams in the Fig. 2A - D2 the input current I applied to the modeled LNA 100 DD set to 7.5 mA for the high-power, moderate-gain mode compared to 10 mA for the high-gain mode. In other embodiments, I DD be optimized with regard to performance considerations. Second embodiment

[0050] Fig.3 is a simplified schematic diagram of a second embodiment of a low-noise amplifier circuit 300 having a tunable hybrid wideband output impedance matching network 102. The LNA circuit 300 is similar in most aspects to that shown in Fig. 1A and implements the inductors L1 and L2 as an asymmetric T-coil, as indicated by the dots next to L1 and L2 connected by a dotted arrow k. An asymmetric T-coil is an inductive peaking circuit that can expand the bandwidth of an amplifier and accelerate the rise time of the output signal. As is well known, an asymmetric T-coil contains series-connected inductors (corresponding to the discrete inductors L1 and L2) and an inherent bypass capacitance (not shown) between the inductors. Since a T-coil inherently contains bypass capacitance, the value of the capacitor C SERpossibly compared to the value of C SER in the LNA circuit 100 of Fig. 1A can be adjusted.

[0051] The implementation of the asymmetric T-coil in an integrated circuit can be in the form of a spiral inductor structure with three taps, where a first section of the spiral (e.g. from an input tap to a center tap) corresponds to L1 and a second section of the spiral (e.g. from the center tap to an output tap) corresponds to L2.

[0052] One advantage of using an asymmetric T-coil instead of discrete inductors L1 and L2 is that the IC implementation (e.g., as a three-terminal spiral inductor structure) generally saves chip area compared to discrete inductors. Furthermore, in high-gain mode, the mutual inductance of the asymmetric T-coil inductors L1 and L2 also contributes to the total load inductance to the amplifier core 104, so the asymmetric T-coil does not affect the load inductance Q and the gain of the high-gain mode. Third embodiment

[0053] The embodiments of the Fig. 1A and Fig. 3 can benefit from providing adjustable circuit elements for operation in a number of different modes, allowing trade-offs between gain, bandwidth and linearity. Fig.For example, Figure 4 is a simplified schematic diagram of a third embodiment of a low-noise amplifier circuit 400 having a tunable hybrid wideband output impedance matching network 102. The LNA circuit 400 is similar in most aspects to that shown in Fig. 1A and may use any or all of the inductors L1, L2 and / or L3 as adjustable inductors and any or all of the capacitors C BLK1 , C BLK2 and / or C SER as adjustable capacitors. Furthermore, as mentioned above, all or some of the inductors, resistors, and / or capacitors in the IIM circuit 106, the degeneration circuit 108, the IM feedback circuit 122, and / or the OM DeQing circuit 124 may be adjustable. The asymmetric T-coil embodiment of Fig. 3 can be extended in a similar way with adjustable circuit elements.

[0054] In addition to making some or all of the inductors, resistors, and / or capacitors within the LNA circuit 400 adjustable to achieve different operating modes, multiple operating modes can be achieved by selectively opening and closing various switches (including within the degeneration circuit 108, the IM feedback circuit 122, and / or the OM DeQing circuit 124) as desired, thereby allowing further trade-offs between gain, bandwidth, and linearity. Furthermore, multiple operating modes can be achieved by adding switches, such as a bypass switch S BP, connected in parallel with inductor L1, to include or exclude circuit elements in one or more operating modes. Such additional operating modes can be based on the two basic operating modes (high-power, moderate-gain mode and high-gain mode) to improve overall performance across all these operating modes.

[0055] Embodiments of the present invention provide wide-bandwidth input and output impedance matching for a wide bandwidth in all operating modes without band switching, as should now be apparent. Furthermore, the advantages of the present invention can be realized in a single LNA fabricated as an integrated circuit with very little additional chip area compared to conventional LNA designs. Circuit embodiments

[0056] Circuits and devices according to the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be housed in IC packages and / or in modules for ease of handling, manufacturing, and / or improved performance. In particular, IC embodiments of the present invention are often used in modules in which one or more such ICs are combined with other circuit components or blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) in a package.The ICs and / or modules are then typically combined with other components, often on a printed circuit board, to form part of a final product such as a mobile phone, laptop, or electronic tablet, or to form a higher-level module that can be used in a variety of products such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

[0057] As an example of further integration of embodiments of the present invention with other components, Fig.5 is a top view of a substrate 500, which may be, for example, a printed circuit board or a chip module substrate (e.g., a thin-film tile). In the example shown, the substrate 500 includes a plurality of ICs 502a-502d with connection pads 504 that are interconnected by vias and / or traces on and / or within the substrate 500 or on the opposite (rear) surface of the substrate 500 (to avoid confusion, the surface traces are not shown and not all connection pads are labeled). The ICs 502a-502d may include, for example, signal switches, active filters, amplifiers (including one or more LNAs), and other circuits. IC 502b may, for example, include one or more instances of an LNA circuit, such as those shown in the Fig. 1A, Fig. 3 and Fig. 4 circuits shown.

[0058] The substrate 500 may also include one or more passive devices 506 embedded in, formed on, and / or attached to the substrate 500. The passive devices 506, depicted as general rectangles, may include, for example, filters, capacitors, inductors, transmission lines, resistors, planar antenna elements, transducers (including, for example, MEMS-based transducers such as accelerometers, gyroscopes, microphones, pressure sensors, etc.), batteries, etc., connected to other passive devices 506 and / or the individual ICs 502a-502d by conductive traces on or in the substrate 500.

[0059] The front or back surface of substrate 500 can be used as a site for forming other structures. For example, one or more antennas can be formed on or attached to the front or back surface of substrate 500; an example of a front-surface antenna 508 is shown, connected to an IC chip 502b, which may include RF front-end circuitry. Thus, by incorporating one or more antennas on substrate 500, a complete radio device can be created. System aspects

[0060] Embodiments of the present invention are useful in a wide variety of major radio frequency (RF) circuits and systems, such as radio systems (particularly including cellular radio systems), personal computers, tablet computers, wireless network components, televisions, cable system set-top boxes, radar systems (including phased array and vehicle radar systems), and test equipment.

[0061] Radio system use includes wireless radio frequency systems (including base stations, relay stations, and portable transceivers) that use various technologies and protocols, including various types of orthogonal frequency division multiplexing (“OFDM”), quadrature amplitude modulation (“QAM”), code-division multiple access (“CDMA”), time-division multiple access (“TDMA”), wide band code division multiple access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G, and WiFi (e.g., 802.11a, b, g, ac, ax), as well as other radio communication standards and protocols.

[0062] As an example of the use of a wireless RF system, Fig. 6 illustrates an exemplary wireless communication environment 600 that includes various wireless communication systems 602 and 604 and may include one or more mobile wireless devices 606.

[0063] A wireless device 606 may be capable of communicating with multiple wireless communication systems 602, 604 using one or more of the above-mentioned telecommunications protocols. A wireless device 606 may also be capable of communicating with one or more satellites 608, such as navigation satellites (e.g., GPS) and / or telecommunications satellites. The wireless device 606 may be equipped with multiple external and / or internal antennas for operation at different frequencies and / or to provide diversity against harmful path effects such as fading and multipath interference. A wireless device 606 may be a cellular phone, a personal digital assistant (PDA), a wireless-enabled computer or tablet, or other wireless communication unit or device. A wireless device 606 may also be referred to as a mobile station, user equipment, terminal, or other terminology.

[0064] The wireless system 602 may, for example, be a CDMA-based system that includes one or more base station transceivers (BSTs) 610 and at least one central switching center (SC) 612. Each BST 610 provides wireless radio communications for the devices 606 within its coverage area. The SC 612 is connected to one or more BSTs in the wireless system 602 and coordinates and controls these BSTs.

[0065] The wireless system 604 may, for example, be a TDMA-based system that includes one or more transceiver nodes 614 and a network center (NC) 616. Each transceiver node 614 provides wireless radio communication for the devices 606 within its coverage area. The NC 616 connects to one or more transceiver nodes 614 in the wireless system 604 and coordinates and controls these transceiver nodes 614.

[0066] In general, each BST 610 and each transceiver node 614 is a fixed station that provides communication coverage for the wireless devices 606 and may also be referred to as a base station or by other terms. SC 612 and NC 616 are network units that coordinate and control the base stations and may also be referred to by other terms.

[0067] An important aspect of any wireless system lies in the details of how the system's component elements function. Fig.7 is a block diagram of a transceiver 700 that could be used in a wireless device, such as a cellular phone, and which may advantageously incorporate an embodiment of the present invention to improve performance. As illustrated, the transceiver 700 includes a mix of analog RF circuitry for directly transmitting and / or converting signals on an RF signal path, analog non-RF circuitry for operational requirements outside the RF signal path (e.g., for bias voltages and switching signals), and digital circuitry for control and user interface requirements. In this example, a receiver path Rx includes the RF front-end, intermediate frequency (IF) block, back-end, and baseband sections (although the distinction between the sections may be different in some implementations). The various sections and circuit elements illustrated may be packaged on one chip or multiple IC chips.For example, in the example shown, the RF front-end may comprise an RFFE module and a mixing block, which may be housed in (or as part of) different IC chips or modules. The different chips and / or modules may be interconnected by transmission lines T. IN and T OUT (e.g. microstrip, coplanar waveguide or an equivalent structure or circuit), one or both of which may have an impedance of e.g. 50 Ω.

[0068] The receiver path Rx receives the RF signals transmitted over the air via at least one antenna 702 and a switching unit 704, which can be implemented with active switching devices (e.g., field-effect transistors or FETs) and / or with passive devices implementing frequency-domain multiplexing, such as a diplexer or duplexer. An RF filter 706 forwards the desired received RF signals to at least one low-noise amplifier (LNA) 708a, whose output from the RFFE module is connected to at least one LNA 708b in the mixer block (in this example, via the transmission line T IN). The LNA(s) 708b may provide buffering, input matching, and reverse isolation. The output of the LNA(s) 708b is combined in a corresponding mixer 710 with the output of a first local oscillator 712 to generate an IF signal. The IF signal may be amplified by an IF amplifier 714 and subjected to an IF filter 716 before being fed to a demodulator 718, which may be connected to a second local oscillator 720. The demodulated output signal of the demodulator 718 is converted to a digital signal by an analog-to-digital converter 722 and fed to one or more system components 724 (e.g., a video graphics circuit, a sound circuit, storage devices, etc.). The converted digital signal may represent, for example, video or still images, sounds, or symbols such as text or other characters.

[0069] In the example shown, a transmitter path Tx comprises the baseband, back-end, IF block, and RF front-end sections (again, the distinction between the sections may be different in some implementations). Digital data from one or more system components 724 is converted into an analog signal by a digital-to-analog converter 726, the output of which is applied to a modulator 728, which may also be connected to the second local oscillator 720. The modulated output signal of the modulator 728 may be subjected to an IF filter 730 before being amplified by an IF amplifier 732. The output of the IF amplifier 732 is then combined with the output of the first local oscillator 712 in a mixer 734 to generate an RF signal. The RF signal may be amplified by a driver 736, the output of which is applied to a power amplifier (PA) 738 (in this example, via the transmission line T OUT). The amplified RF signal can be connected to an RF filter 740, the output of which is connected to at least one antenna 702 via the switching unit 704.

[0070] The operation of transceiver 700 is controlled in a known manner by a microprocessor 742, which interacts with system control components 744 (e.g., user interfaces, storage devices, application programs, operating system software, power management, etc.). In addition, transceiver 700 generally includes other circuitry, such as bias circuits 746 (which may be distributed throughout transceiver 700 near transistor devices), ESD (electrostatic discharge) protection circuits, test circuitry (not shown), factory programming interfaces (not shown), etc.

[0071] In modern transceivers, there is often more than one receiver path (Rx) and one transmitter path (Tx), for example, to accommodate multiple frequencies and / or signaling modalities. Furthermore, some components of the transceiver 700 may be arranged in a different order (e.g., filters) or omitted, as should be apparent to one skilled in the art. Other components may be (and often are) added, such as (by way of example only) additional filters, impedance matching networks, variable phase shifters / attenuators, power dividers, etc.

[0072] As one skilled in the art will understand, an RF system architecture is advantageously influenced in key ways by the current invention, including the selection of a first operating mode that provides high gain with wide output impedance matching with trade-offs in current, NF, and linearity, and a second operating mode that provides broadband output impedance matching with improved NF and linearity at lower current and moderate gain. These system-level improvements are specifically enabled by the present invention and allow embodiments of the invention to meet stringent customer performance specifications and a range of RF standards. The present invention is therefore critical to embodiments of the Fig. 7 shown overall system. Proceedings

[0073] Fig.8 is a process flow diagram 800 illustrating a method for achieving different gain modes for a radio frequency amplifier having an amplifier core and an amplified signal terminal. The method includes: connecting a first inductor between the amplified signal terminal and a first node (block 802); connecting a second inductor to the first node and configuring the second inductor to be connected to a power supply (block 804); connecting an amplified gain branch between the amplified signal terminal and an output terminal (block 806); connecting a non-amplified branch between the first node and the output terminal (block 808); selectively enabling the amplified gain branch in a first operating mode (block 810); and selectively enabling the non-amplified branch in a second operating mode (block 812).

[0074] Further aspects of the above method may include modifying the circuit components that implement the method as described above and in the Fig. 1A, Fig. 3 and Fig. 4 shown. Technologies and manufacturing options

[0075] In the Fig. 1A, Fig. 3 and Fig. Although the embodiments shown in Figure 4 are LNAs, the circuits and methods according to the invention can also be applied to other types of amplifiers, such as power amplifiers.

[0076] Additional known circuit elements that may be included in some applications, such as DC blocking capacitors, additional impedance matching circuits, and additional filters, are omitted for clarity. It should also be noted that the value of a circuit component described as "adjustable" may be selected from a range of possible value settings and fixed during manufacturing, upon assembly in a circuit module, during factory testing, or in the field (e.g., by blowing or "busting" fuses), or its value may be dynamically varied, tuned, or set programmatically, e.g., in response to other circuitry (e.g., temperature compensation and / or power control circuitry) or in response to generated or received command signals.

[0077] The operating modes of the LNA circuits according to the invention can be adjusted in a known manner by a control circuit (not shown). The circuit can also be connected to the adjustable components to select different component values ​​(e.g., capacitance, resistance, inductance) for different gain states, e.g., to assist input and / or output impedance matching or to vary the gain relative to linearity and / or NF in some operating modes.

[0078] The switches shown in the embodiments of the present invention can be implemented as FETs, in particular MOSFETs. The term "MOSFET" as used in this disclosure encompasses any field-effect transistor (FET) with an insulated gate whose voltage determines the conductivity of the transistor, and includes insulated gates with a metal or metal-like, insulator, and / or semiconductor structure. The terms "metal" or "metal-like" encompass at least one electrically conductive material (such as aluminum, copper, or another metal, or highly doped polysilicon, graphene, or another electrical conductor), "insulator" encompasses at least one insulating material (such as silicon oxide or another dielectric material), and "semiconductor" encompasses at least one semiconductor material.

[0079] The term "radio frequency" (RF), as used in this disclosure, refers to an oscillation rate in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or an alternating voltage or current in a circuit.

[0080] In the figures referred to in this disclosure, the dimensions of the various elements are not to scale; some dimensions have been greatly exaggerated vertically and / or horizontally for clarity or emphasis. Furthermore, references to orientations and directions (e.g., "top," "bottom," "below," "above," "below," "side," "vertical," "horizontal," etc.) are relative to the example drawings and are not necessarily absolute orientations or directions.

[0081] Various embodiments of the invention may be implemented to meet a variety of specifications. Unless otherwise noted above, the selection of appropriate component values ​​is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including, but not limited to, MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including, but not limited to, standard bulk silicon, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies, such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies.However, embodiments of the invention are particularly useful when fabricated using an SOI- or SOS-based process, or processes with similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high-frequency operation (i.e., radio frequencies up to and above 300 GHz). A monolithic IC implementation is particularly useful because parasitic capacitances can generally be kept low through careful design (or at least distributed evenly across all devices so that they can be compensated).

[0082] Depending on the specification and / or implementation technology (e.g., NMOS, PMOS, or CMOS transistor devices, and enhancement- or depletion-mode transistor devices), the voltage levels may be adjusted and / or the voltage and / or logic signal polarities may be reversed. The voltage, current, and energy handling capabilities of the components may be adjusted as needed, e.g., by adjusting the device size, serially stacking components (particularly FETs) to withstand higher voltages, and / or using multiple components in parallel to handle higher currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or to provide additional features without substantially altering the functionality of the disclosed circuits. conclusion

[0083] A number of embodiments of the invention have been described. It should be understood that various changes may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be sequence independent and may therefore be performed in a different order than that described. Furthermore, some of the steps described above may be optional. Various activities described with respect to the above methods may be performed repeatedly, serially, and / or in parallel.

[0084] It should be understood that the foregoing description is illustrative and not limiting, with respect to the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes all possible combinations of one or more of the methods, machines, manufacturing processes, or compositions of matter recited in the following claims. (It should be noted that the parentheses surrounding claim elements are provided to facilitate reference to those elements and do not, in themselves, indicate any particular required order or enumeration of elements; further, these terms may be reused in dependent claims as references to additional elements without being considered to initiate a conflicting sequence of terms.) QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 17 / 855,418

[0001] US 17 / 337,227

[0036]

Claims

[1] A tunable hybrid broadband output impedance matching network having an input terminal configured to be connected to an amplified signal terminal of an amplification core and an output terminal configured to be connected to a radio frequency (RF) output terminal, the tunable hybrid broadband output impedance matching network comprising: (a) a first inductor connected between the input terminal and a first node; (b) a second inductor connected to the first node and configured to be connected to a power supply; (c) an amplified gain branch connected between the input terminal and the output terminal; and (d) a non-amplification branch connected between the first node and the output terminal; wherein the boosted gain branch is enabled in a first operating mode and the non-amplification branch is enabled in a second operating mode. [2] The invention of claim 1, wherein the reinforced reinforcement branch comprises: (a) a first blocking capacitor connected to the input terminal; (b) a third inductor configured to be connected to a reference voltage; (c) a FET having a control gate, a source connected to the third inductor, and a drain configured to be connected to the power supply; (d) a first switch connected between the first blocking capacitor and the control gate of the FET; (e) a second blocking capacitor connected between the source of the FET and a second node; (f) a second switch connected between the second node and the output terminal; and (g) a third switch connected to the second node and configured to be connected to the reference voltage. [3] The invention of claim 1, wherein the non-amplification branch comprises: (a) a first blocking capacitor connected to the first node; (b) a first switch connected between the first blocking capacitor and a second node; (c) a second switch connected between the second node and the output terminal; and (d) a third switch connected to the second node and configured to be connected to the reference voltage. [4] The invention according to claim 1, wherein the first and second inductors are designed as asymmetric T-coils. [5] The invention of claim 1, wherein at least one of the first and second inductors is adjustable. [6] The invention of claim 1, wherein at least one of the first and second inductors is dynamically variable. [7] A tunable hybrid broadband output impedance matching network having an input terminal configured to be connected to an amplified signal terminal of an amplification core and an output terminal configured to be connected to a radio frequency (RF) output terminal, the tunable hybrid broadband output impedance matching network comprising: (a) a first inductor connected between the input terminal and a first node; (b) a second inductor connected to the first node and configured to be connected to a power supply; (c) a first branch connected between the input terminal and the output terminal, the first branch comprising: (1) a first blocking capacitor connected to the input terminal; (2) a third inductor configured to be connected to a reference voltage; (3) a FET having a control gate, a source connected to the third inductor, and a drain configured to be connected to the power supply; (4) a first switch connected between the first blocking capacitor and the control gate of the FET; (5) a second blocking capacitor connected between the source of the FET and a second node; (6) a second switch connected between the second node and the output terminal; and (7) a third switch connected to the second node and configured to be connected to the reference voltage; and (d) a second branch connected between the first node and the output terminal, the second branch comprising: (1) a third blocking capacitor connected to the first node; (2) a fourth switch connected between the third blocking capacitor and a third node; (3) a fifth switch connected between the third node and the output terminal; and (4) a sixth switch connected to the third node and configured to be connected to the reference voltage; wherein the first branch is activated in a first operating mode and the second branch is activated in a second operating mode. [8] The invention according to claim 7, wherein the first and second inductors are designed as asymmetric T-coils. [9] The invention of claim 7, wherein at least one of the first and / or the second inductor is adjustable. [10] The invention of claim 7, wherein at least one of the first and / or the second inductor is dynamically variable. [11] The invention of claim 7, wherein at least one of the third inductor, the first blocking capacitor, the second blocking capacitor and / or the third blocking capacitor is adjustable. [12] The invention of claim 7, wherein at least one of the third inductor, the first blocking capacitor, the second blocking capacitor and / or the third blocking capacitor is dynamically variable. [13] Amplifier comprising: (a) an amplifier core comprising: (1) an amplifier input terminal configured to receive a radio frequency (RF) signal; and (2) an amplified signal port; (b) a tunable hybrid broadband output impedance matching network having a network input terminal connected to the amplified signal terminal of the amplification core and a network output terminal, the tunable hybrid broadband output impedance matching network comprising: (1) a first inductor connected between the input terminal of the network and a first node; (2) a second inductor connected to the first node and configured to be connected to a power supply; (3) an amplified gain branch connected between the mains input terminal and the mains output terminal; (4) a non-boosting branch connected between the first node and the network output terminal; wherein the boosted gain branch is enabled in a first operating mode and the non-boosting branch is enabled in a second operating mode. [14] The invention of claim 13, wherein the enhanced reinforcement branch comprises: (a) a first blocking capacitor connected to the input terminal; (b) a third inductor configured to be connected to a reference voltage; (c) a FET having a control gate, a source connected to the third inductor, and a drain configured to be connected to the power supply; (d) a first switch connected between the first blocking capacitor and the control gate of the FET; (e) a second blocking capacitor connected between the source of the FET and a second node; (f) a second switch connected between the second node and the output terminal; and (g) a third switch connected to the second node and configured to be connected to the reference voltage. [15] The invention of claim 13, wherein the non-amplification branch comprises: (a) a first blocking capacitor connected to the first node; (b) a first switch connected between the first blocking capacitor and a second node; (c) a second switch connected between the second node and the output terminal; and (d) a third switch connected to the second node and configured to be connected to the reference voltage. [16] The invention according to claim 13, wherein the first and second inductors are designed as asymmetric T-coils. [17] The invention of claim 13, wherein at least one of the first and / or the second inductor is adjustable. [18] The invention of claim 13, wherein at least one of the first and / or the second inductor is dynamically variable. [19] The invention of claim 13, wherein the amplifier is a low noise amplifier. [20] The invention of claim 13, wherein the amplifier is implemented as an integrated circuit fabricated in a silicon-on-insulator technology and including MOS devices. [21] The invention of claim 13, wherein the amplifier is implemented as an integrated circuit mounted in a circuit module. [22] The invention of claim 13, wherein the amplifier is implemented as an integrated circuit that is part of a communication device. [23] The invention of claim 13, wherein the amplifier core further includes a feedback node in an output signal path of the amplifier core and further includes an input feedback circuit connected between the amplifier input terminal and the feedback node. [24] The invention of claim 23, wherein the input feedback circuit is selectively switchable between an enabled state and a disabled state. [25] The invention of claim 13, wherein the amplifier core further includes a feedback node in an output signal path of the amplifier core, and further includes an output feedback circuit connected between the feedback node and a gate of an upper common-gate FET within the amplifier core. [26] The invention of claim 25, wherein the output feedback circuit is selectively switchable between an enabled state and a disabled state. [27] The invention of claim 13, wherein the amplifier core further comprises: (a) a common-source FET having a gate connected to the input terminal of the amplifier, a source, and a drain; (b) a stack comprising at least one common-gate FET, each common-gate FET having a gate, a source, and a drain that outputs an amplified version of the received RF signal, wherein the source of one of the at least one common-gate FET is connected to the drain of the common-source FET, and wherein the drain of one of the at least one common-gate FET is connected to the amplified signal terminal for the stack. [28] The invention of claim 13, wherein the amplifier core includes a degeneration terminal and further includes a degeneration circuit connected to the degeneration terminal and configured to be connected to a reference potential, the degeneration circuit including a degeneration inductor. [29] The invention of claim 28, further comprising a bypass switch connected in parallel with the degeneration inductor. [30] The invention of claim 13, further comprising an input impedance matching circuit connected to the amplifier input terminal and configured to receive the RF signal. [31] The invention of claim 30, wherein the input impedance matching circuit comprises a series inductor connected to the input terminal and configured to receive the RF signal and a shunt inductor connected between the series inductor and a reference potential. [32] A method for achieving different amplification modes for a radio frequency amplifier having an amplifier core with an amplified signal terminal, the method comprising: (a) connecting a first inductor between the amplified signal terminal and a first node; (b) connecting a second inductor to the first node and configuring the second inductor to be connected to a power supply; (c) connecting an amplified gain branch between the amplified signal terminal and an output terminal; (d) connecting a non-amplifying branch between the first node and the output terminal; (e) selectively activating the enhanced gain branch in a first operating mode; and (f) selectively activating the non-amplification branch in a second operating mode.

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